AD1861N

a 16-Bit/18-Bit, 16 3 FS PCM Audio DACs AD1851/AD1861 FUNCTIONAL BLOCK DIAGRAM –VS 1 DGND 2 +VL 3 NC 4 CLK 5 LATCH DAC SERIAL INPUT REGISTER IOUT CONTROL LOGIC 16 +VS 15 TRIM 14 MSB ADJ 13 IOUT 12 AGND TE FEATURES 110 dB SNR Fast Settling Permits 163 Oversampling 63 V Output Optional Trim Allows Super-Linear Performance 65 V Operation 16-Pin Plastic DIP and SOIC Packages Pin-Compatible with AD1856 & AD1860 Audio DACs 2s Complement, Serial Input APPLICATIONS High-End Compact Disc Players Digital Audio Amplifiers DAT Recorders and Players Synthesizers and Keyboards LE 6 DATA 7 NC 8 11 AD1851/ AD1861 SJ 10 RF 9 VOUT NC = NO CONNECT The critical specifications of THD+N and signal-to-noise ratio are 100% tested for all devices. LE PRODUCT DESCRIPTION The AD1851/AD1861 operates with ± 5 V power supplies, making it suitable for home use markets. The digital supply, VL, can be separated from the analog supplies, VS and –VS, for reduced digital crosstalk. Separate analog and digital ground pins are also provided. Power dissipation is 100 mW typical. The AD1851/AD1861 is available in either a 16-pin plastic DIP or a 16-pin plastic SOIC package. Both packages incorporate the industry standard pinout found on the AD1856 and AD1860 PCM audio DACs. As a result, the AD1851/AD1861 is a drop-in replacement for designs where ± 5 V supplies have been used with the AD1856/AD1860. Operation is guaranteed over the temperature range of –25°C to +70°C and over the voltage supply range of ± 4.75 V to ± 5.25 V. B SO The AD1851/AD1861 is a monolithic PCM audio DAC. The AD1851 is a 16-bit device, while the AD1861 is an 18-bit device. Each device provides a voltage output amplifier, DAC, serial-to-parallel register and voltage reference. The digital portion of the AD1851/AD1861 is fabricated with CMOS logic elements that are provided by Analog Devices’ 2 µm ABCMOS process. The analog portion of the AD1851/AD1861 is fabricated with bipolar and MOS devices as well as thin-film resistors. O This combination of circuit elements, as well as careful design and layout techniques, results in high performance audio playback. Laser-trimming of the linearity error affords low total harmonic distortion. An optional linearity trim pin is provided to allow residual differential linearity error at midscale to be eliminated. This feature is particularly valuable for low distortion reproductions of low amplitude signals. Output glitch is also small, contributing to the overall high level of performance. The output amplifier achieves fast settling and high slew rates, providing a full ± 3 V signal at load currents up to 8 mA. When used in current output mode, the AD1851/AD1861 provides a ± 1 mA output signal. The output amplifier is short circuit protected and can withstand indefinite shorts to ground. The serial input interface consists of the clock, data and latch enable pins. The serial 2s complement data word is clocked into the DAC, MSB first, by the external clock. The latch enable signal transfers the input word from the internal serial input register to the parallel DAC input register. The AD1851 input clock can support a 12.5 MHz data rate, while the AD1861 input clock can support a 13.5 MHz data rate. This serial input port is compatible with second generation digital filter chips used in consumer audio products. These filters operate at oversampling rates of 23, 43, 83 and 163 sampling frequencies. PRODUCT HIGHLIGHTS l. AD1851 16-bit resolution provides 96 dB dynamic range. AD1861 18-bit resolution provides 108 dB dynamic range. 2. No external components are required. 3. Operates with ± 5 V supplies. 4. Space saving 16-pin SOIC and plastic DIP packages. 5. 100 mW power dissipation. 6. High input clock data rates and 1.5 µs settling time permits 23, 43, 83 and 163 oversampling. 7. ± 3 V or ± 1 mA output capability. 8. THD + Noise and SNR are 100% tested. 9. Pin-compatible with AD1856 & AD1860 PCM audio DACs. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD1851/AD1861–SPECIFICATIONS (T @ +258C and 65 V supplies, unless otherwise noted) A Min DIGITAL INPUTS VIH VIL IIH, VIH = VL IIL, VIL = 0.4 Typ 2.0 Max Units +VL 0.8 1.0 –10 V V µA µA ACCURACY Gain Error Midscale Output Voltage ±1 ± 10 % mV DRIFT (0°C to +70°C) Total Drift Bipolar Zero Drift ± 25 ±4 ppm of FSR/°C ppm of FSR/°C TE SETTLING TIME (To ± 0.0015% of FSR) Voltage Output 6 V Step 1 LSB Step Slew Rate Current Output 1 mA Step 10 Ω to 100 Ω Load 1 kΩ Load µs µs V/µs 350 350 ns ns LE OUTPUT Voltage Output Configuration Bipolar Range Output Current Output Impedance Short Circuit Duration Current Output Configuration Bipolar Range (± 30%) Output Impedance (± 30%) 1.5 1.0 9 ± 3.0 62.88 ±8 63.12 V mA Ω B SO 0.1 Indefinite to Common POWER SUPPLY Voltage +VL and +VS –VS 4.75 –5.25 TEMPERATURE RANGE Specification Operation Storage 0 –25 –60 WARM-UP TIME 1 ± 1.0 1.7 +25 mA kΩ 5.25 –4.75 V V +70 +70 +100 °C °C °C min O Specifications subject to change without notice. –VS 1 DGND 2 +VL 3 NC 4 CLK 5 16-BIT LATCH 16-BIT DAC SERIAL INPUT REGISTER IOUT 16 +VS 15 TRIM 14 MSB ADJ 13 IOUT 12 AGND CONTROL LOGIC –VS 1 DGND 2 +VL 3 NC 4 CLK 5 16-BIT LATCH 16-BIT DAC SERIAL INPUT REGISTER IOUT 16 +VS 15 TRIM 14 MSB ADJ 13 IOUT 12 AGND CONTROL LOGIC LE 6 11 SJ LE 6 11 SJ DATA 7 10 RF DATA 7 10 RF NC 8 NC 8 AD1851 9 VOUT NC = NO CONNECT AD1851 9 VOUT NC = NO CONNECT AD1851 Functional Block Diagram AD1861 Functional Block Diagram –2– REV. A AD1851/AD1861 AD1851 Min Typ Max Units 16 Bits 0.003 0.004 0.004 0.008 % % 0.009 0.009 0.016 0.040 % % 0.9 0.9 1.6 4.0 % % TOTAL HARMONIC DISTORTION + NOISE 0 dB, 990.5 Hz AD1851N-J, R-J AD1851N, R –20 dB, 990.5 Hz AD1851N-J, R-J AD1851N, R –60 dB, 990.5 Hz AD1851N-J, R-J AD1851N, R D-RANGE* (With A-Weight Filter) –60 dB, 990.5 Hz AD1851N, R AD1851N-J, R-J 88 96 SIGNAL-TO-NOISE RATIO 107 MAXIMUM CLOCK INPUT FREQUENCY 12.5 ACCURACY Differential Linearity Error POWER SUPPLY Current +I –I Power Dissipation B SO AD1861 110 Min D-RANGE* (With A-Weight Filter) –60 dB, 990.5 Hz AD1861N, R AD1861N-J, R-J O 88 96 SIGNAL-TO-NOISE RATIO 107 MAXIMUM CLOCK INPUT FREQUENCY 13.5 dB MHz % of FSR 14 Bits 10.0 –10.0 100 13.0 –15.0 mA mA mW Typ Max Units 18 Bits 0.003 0.004 0.004 0.008 % % 0.009 0.009 0.016 0.040 % % 0.9 0.9 1.6 4.0 % % RESOLUTION TOTAL HARMONIC DISTORTION + NOISE 0 dB, 990.5 Hz AD1861N-J, R-J AD1861N, R –20 dB, 990.5 Hz AD1861N-J, R-J AD1861N, R –60 dB, 990.5 Hz AD1861N-J, R-J AD1861N, R dB dB ± 0.001 LE MONOTONICITY TE RESOLUTION dB dB 110 dB MHz ACCURACY Differential Linearity Error ± 0.001 % of FSR MONOTONICITY 15 Bits POWER SUPPLY Current +I –I Power Dissipation 10.0 –10.0 100 *Tested in accordance with EIAJ Test Standard CP-307. Specifications subject to change without notice. REV. A –3– 13.0 –15.0 mA mA mW AD1851/AD1861 ABSOLUTE MAXIMUM RATINGS* PIN DESCRIPTIONS *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Resolution THD + N Package Option* AD1851N AD1851N-J AD1851R AD1851R-J AD1861N AD1861N-J AD1861R AD1861R-J 16 Bits 16 Bits 16 Bits 16 Bits 18 Bits 18 Bits 18 Bits 18 Bits 0.008% 0.004% 0.008% 0.004% 0.008% 0.004% 0.008% 0.004% N-16 N-16 R-16 R-16 N-16 N-16 R-16 R-16 –VS DGND VL NC CLK LE DATA NC VOUT RF SJ AGND IOUT MSB ADJ TRIM VS Analog Negative Power Supply Logic Ground Logic Positive Power Supply No Connection Clock Input Latch Enable Input Serial Data Input No Internal Connection* Voltage Output Feedback Resistor Summing Junction Analog Ground Current Output MSB Adjustment Terminal MSB Trimming Potentiometer Terminal Analog Positive Power Supply *Pin 8 has no internal connection; -V L from AD1856 or AD1860 socket can be safely applied. LE Model 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TE VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.50 V –VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –6.50 V to 0 V Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . –0.3 V to VL AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V Short Circuit . . . . . . . . . . . . . . . . . Indefinite Short to Ground Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec Storage Temperature . . . . . . . . . . . . . . . . . . –60°C to +100°C *N = Plastic DIP Package; R = Small Outline (SOIC) Package. B SO CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are inserted. WARNING! ESD SENSITIVE DEVICE Typical Performance O 175 10 150 1 –60dB THD+N – % PD – mW 125 100 75 0.1 0.01 50 –20dB 25 0dB 2 4 6 8 10 12 0.001 –30 –20 –10 14 CLOCK FREQUENCY – MHz 0 10 20 30 40 50 60 70 80 90 TEMPERATURE – °C Power Dissipation vs. Clock Frequency THD vs. Temperature –4– REV. A AD1851/AD1861 TOTAL HARMONIC DISTORTION RF Total harmonic distortion plus noise (THD+N) is defined as the ratio of the square root of the sum of the squares of the values of the first 19 harmonics and noise to the value of the fundamental input frequency. It is usually expressed in percent (%). REFERENCE AUDIO OUTPUT THD+N is a measure of the magnitude and distribution of linearity error, differential linearity error, quantization error and noise. The distribution of these errors may be different, depending on the amplitude of the output signal. Therefore, to be most useful, THD+N should be specified for both large (0 dB) and small signal amplitudes (–20 dB and –60 dB). INPUT LATCH SERIAL-TO-PARALLEL CONVERSION CLOCK The THD+N figure of an audio DAC represents the amount of undesirable signal produced during reconstruction and playback of an audio waveform. This specification, therefore, provides a direct method to classify and choose an audio DAC for a desired level of performance. TE The AD1851/AD1861 is a complete monolithic PCM audio DAC. No additional external components are required for operation. As shown in Figure 1 above, each chip contains a voltage reference, an output amplifier, a DAC, an input latch and a parallel input register. LE The voltage reference consists of a bandgap circuit and buffer amplifier. This combination of elements produces a reference voltage that is unaffected by changes in temperature and age. The DAC output voltage, which is derived from the reference voltage, is also unaffected by these environmental changes. Midscale error, or bipolar zero error, is the deviation of the actual analog output from the ideal output (0 V) when the 2s complement input code representing half scale is loaded in the input register. B SO The output amplifier uses both MOS and bipolar devices to produce low offset, high slew rate and optimum settling time. When combined with the on-chip feedback resistor, the output op amp converts the output current of the AD1851/AD1861 to a voltage output. D-range distortion is equal to the value of the total harmonic distortion + noise (THD+N) plus 60 dB when a signal level of –60 dB below full scale is reproduced. D-range is tested with a 1 kHz input sine wave. This is measured with a standard Aweight filter as specified by EIAJ Standard CP-307. The DAC uses a combination of segmented decoder and R-2R architecture to achieve consistent linearity and differential linearity. The resistors which form the ladder structure are fabricated with silicon chromium thin film. Laser-trimming of these resistors further reduces linearity error, resulting in low output distortion. SIGNAL-TO-NOISE RATIO The signal-to-noise ratio (SNR) is defined as the ratio of the amplitude of the output when a full-scale output is present to the amplitude of the output with no signal present. This is measured with a standard A-weight filter as specified by EIAJ Standard CP-307. The input register and serial-to-parallel converter are fabricated with CMOS logic gates. These gates allow the achievement of fast switching speeds and low power consumption. This contributes to the overall low power dissipation of the AD1851/ AD1861. O REV. A DATA FUNCTIONAL DESCRIPTION Settling time is the time required for the output of the DAC to reach and remain within a specified error band about its final value, measured from the digital input transition. It is a primary measure of dynamic performance. D-RANGE DISTORTION LE Figure 1. AD1851/AD1861 Functional Block Diagram SETTLING TIME MIDSCALE ERROR IOUT DAC –5– AD1851/AD1861 GROUNDING RECOMMENDATIONS However, three separate voltage supplies are not necessary for good circuit performance. For example, Figure 3 illustrates a system where only a single positive and a single negative supply are available. The AD1851/AD1861 has two ground pins, designated Analog and Digital ground. The analog ground pin is the “high quality” ground reference point for the device. The analog ground pin should be connected to the analog common point in the system. The output load should also be connected to that same point. In this example, the positive logic and positive analog supplies must both be connected to +5 V, while the negative analog supply will be connected to –5 V. Performance would benefit from a measure of isolation between the supplies introduced by using simple low pass filters in the individual power supply leads. Analog Circuit Considerations The digital ground pin returns ground current from the digital logic portions of the AD1851/AD1861 circuitry. This pin should be connected to the digital common point in the system. As illustrated in Figure 2, the analog and digital grounds should be connected together at one point in the system. +5V +5V 3 +VL 16 +VS TE AD1851/AD1861 + 5V +5V 3 16 +VL +VS AGND 1 12 DIGITAL GROUND AGND 1 12 ANALOG GROUND –5V Figure 3. Alternate Recommended Schematic ANALOG GROUND – 5V LE –VS 2 –VS 2 DIGITAL GROUND AD1851/AD1861 DGND DGND Figure 2. Recommended Circuit Schematic OPTIONAL MSB ADJUSTMENT Use of an optional adjustment circuit allows residual differential linearity error around midscale to be eliminated. This error is especially important when low amplitude signals are being reproduced. In those cases, as the signal amplitude decreases, the ratio of the midscale differential linearity error to the signal amplitude increases, thereby increasing THD. B SO POWER SUPPLIES AND DECOUPLING As with most linear circuits, changes in the power supplies will affect the output of the DAC. Analog Devices recommends that well regulated power supplies with less than 1% ripple be incorporated into the design of any system using the AD1851/AD1861. The AD1851/AD1861 has three power supply input pins. The ± VS supplies provide the supply voltages to operate the linear portions of the DAC including the voltage reference, output amplifier and control amplifier. The ± VS supplies are designed to operate at ± 5 V. The +VL supply operates the digital portions of the chip including the input shift register and the input latching circuitry. The +VL supply is designed to operate at +5 V. Therefore, for best performance at low output levels, the optional MSB adjust circuitry shown in Figure 4 may be used to improve performance. The adjustment should be made with a small signal input (–20 dB or –60 dB). O Decoupling capacitors should be used on all power supply pins. Furthermore, good engineering practice suggests that these capacitors be placed as close as possible to the package pins as well as to the common points. The logic supply, +VL, should be decoupled to digital common, while the analog supplies, ± VS, should be decoupled to analog common. TRIM 15 470kΩ 100kΩ 200kΩ –VS 1 14 MSB ADJUST The use of three separate power supplies will reduce feedthrough from the digital portion of the system to the linear portion of the system, thus contributing to improved performance. Figure 4. Optional THD Adjust Circuit –6– REV. A AD1851/AD1861 AD1851 DIGITAL CIRCUIT CONSIDERATIONS AD1851 Input Data AD1861 DIGITAL CIRCUIT CONSIDERATIONS AD1861 Input Data Data is transmitted to the AD1851 in a bit stream composed of 16-bit words with a serial, MSB first format. Three signals must be present to achieve proper operation. They are the Data, Clock and Latch Enable (LE) signals. Input data bits are clocked into the input register on the rising edge of the Clock signal. The LSB is clocked in on the 16th clock pulse. When all data bits are loaded, a low-going Latch Enable pulse updates the DAC input. Figure 5 illustrates the general signal requirements for data transfer to the AD1851. Data is transmitted to the AD1861 in a bit stream composed of 18-bit words with a serial, MSB first format. Three signals must be present to achieve proper operation. They are the Data, Clock and Latch Enable (LE) signals. Input data bits are clocked into the input register on the rising edge of the Clock signal. The LSB is clocked in on the 18th clock pulse. When all data bits are loaded, a low-going Latch Enable pulse updates the DAC input. Figure 7 illustrates the general signal requirements for data transfer to the AD1861. CLOCK CLOCK AAAAAAAAA AAAAAAAAA L S B M S B DATA M S B TE DATA L S B LATCH LATCH Figure 5. Signal Requirements for AD1851 Figure 7. Signal Requirements for AD1861 Figure 6 illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished properly. The input pins of the AD1851 are both TTL and 5 V CMOS compatible. The input requirements illustrated in Figures 5 and 6 are compatible with data outputs provided by popular DSP filter chips used in digital audio playback systems. The AD1851 input clock can run at a 12.5 MHz rate. This clock rate will allow data transfer rates for 23, 43 or 83 or 163 oversampling reconstructions. B SO LE Figure 8 illustrates the specific timing requirements that must be met in order for the data transfer to be accomplished properly. The input pins of the AD1861 are both TTL and 5 V CMOS compatible. The input requirements illustrated in Figures 7 and 8 are compatible with data outputs provided by popular DSP filter chips used in digital audio playback systems. The AD1861 input clock can run at a 13.5 MHz rate. This clock rate will allow data transfer rates for 23, 43 or 83 or 163 oversampling reconstructions. >30ns DATA >30ns DATA >15ns >15ns >15ns >40ns CLOCK >30ns >30ns CLOCK >30ns >15ns >80.0ns O LATCH >40ns >30ns >15ns >74.1ns LATCH >40ns >40ns Figure 6. Timing Relationships of AD1851 Input Signals REV. A >15ns >40ns >40ns Figure 8. Timing Relationships of AD1861 Input Signals –7– AD1851/AD1861 APPLICATIONS Figures 9 through 12 show connection diagrams for the AD1851 and AD1861 and the Yamaha YM3434 and the NPC SM5813AP/APT digital filter chips. CLK +5V CLK OUT LATCH X1 ST 16/18 DLO DATA AD1851 LEFT LOW OUTPUT PASS FILTER BCO WCO DRO DATA LATCH CLK LOW PASS FILTER TE YM3434 OUT AD1851 RIGHT OUTPUT CLK +5V LE Figure 9. AD1851 with Yamaha YM3434 Digital Filter CLK OUT LATCH ST 16/18 DLO DATA AD1861 B SO X1 LEFT OUTPUT LOW PASS FILTER BCO YM3434 WCO DRO DATA LATCH CLK OUT AD1861 LOW PASS FILTER RIGHT OUTPUT O Figure 10. AD1861 with Yamaha YM3434 Digital Filter –8– REV. A AD1851/AD1861 +5V CLK LEFT OUTPUT CLK LATCH X1 COB OW20 DOL DATA OUT LOW PASS FILTER OUT LOW PASS FILTER AD1851 BCKO SM5813AP/APT WCKO DOR DATA OW18 LATCH AD1851 RIGHT OUTPUT TE CLK +5V Figure 11. AD1851 with NPC SM5813AP/APT Digital Filter +5V CLK LEFT OUTPUT LATCH X1 COB OW20 DOL BCKO SM5813AP/APT DATA B SO WCKO OW18 DOR OUT LOW PASS FILTER OUT LOW PASS FILTER LE CLK AD1861 DATA LATCH CLK AD1861 O Figure 12. AD1861 with NPC SM5813AP/APT Digital Filter REV. A –9– RIGHT OUTPUT AD1851/AD1861 OTHER DIGITAL AUDIO COMPONENTS AVAILABLE FROM ANALOG DEVICES 1 DGND 2 +VL 3 NC 4 CLK 5 LE 6 DATA 7 –VL 8 16-BIT LATCH 16-BIT DAC 16 +VS 15 TRIM SERIAL INPUT REGISTER 14 MSB ADJ IOUT 13 IOUT 12 AGND CONTROL LOGIC 11 SJ 10 RF AD1856 9 VOUT TRIM 3 +VL 4 CLK 5 DATA 7 –VL 8 15 14 INPUT AND DIGITAL OFFSET 20-BIT DAC O LE 6 16 VOLTAGE REFERENCE AD1862 +VL 3 NC 4 CLK 5 16 +VS 15 TRIM SERIAL INPUT REGISTER 14 MSB ADJ 13 IOUT IOUT 12 AGND CONTROL LOGIC LE 6 DATA 7 –VL 8 11 SJ 10 RF AD1860 9 VOUT Complete, No External Components Required 0.0025% THD+N 108 dB Signal-to-Noise Ratio 16-Pin DIP or SOIC Package Standard Pinout B SO 2 2 18-BIT DAC AD1860 18-BIT AUDIO DAC Complete, No External Components Required 0.0025% THD Low Cost 16-Pin DIP or SOIC Package Standard Pinout –VS DGND 18-BIT LATCH NC = NO CONNECT AD1856 16-BIT AUDIO DAC 1 1 LE NC = NO CONNECT –VS –VS TE –VS +VS 24 +VS 23 TRIM 3 22 MSB IOUT 4 21 IOUT AGND 5 20 AGND SJ 6 19 SJ RF 7 18 RF VOUT 8 +VL 9 DR 10 2 MSB NR2 ADJ 13 NR1 12 AGND 11 IOUT 10 RF 9 DGND AD1864 –VS 1 TRIM LR 11 CK REFERENCE REFERENCE – + 18-BIT LATCH – + 18-BIT D/A 18-BIT D/A 18-BIT LATCH 12 17 VOUT 16 –VL 15 DL 14 LL 13 DGND NC = NO CONNECT AD1862 20-BIT AUDIO DAC AD1864 DUAL 18-BIT AUDIO DAC 119 dB Signal-to-Noise Ratio 0.0016% THD+N 102 dB D-Range Performance ± 1 dB Gain Linearity 16-Pin DIP Complete, No External Components 0.0025% THD+N 108 dB Signal-to-Noise Ratio Cophased Outputs 24-Pin Package –10– REV. A AD1851/AD1861 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). TE N (Plastic DIP) Package 16 0.299 (7.60) LE R (SOIC Surface Mount) Package 9 0.419 (10.65) 8 B SO 1 PIN 1 0.030 (0.75) 0.050 (1.27) 0.413 (10.50) 0.104 (2.650) 0.012 (0.30) O 0.019 (0.49) REV. A –11– 0.013 (0.32) 0.042 (1.07) –12– PRINTED IN U.S.A. TE LE B SO O C1458–7–10/90