Differential Inputs, 1 MSPS/500 kSPS, Dual
Simultaneous Sampling SAR ADCs
AD4680/AD4681
Data Sheet
FEATURES
GENERAL DESCRIPTION
16-bit ADC family
Dual simultaneous sampling
Fully differential analog inputs
Throughput conversion rate
1 MSPS for AD4680
500 kSPS for AD4681
SNR (typical)
92.5 dB, VREF = 3.3 V external
100 dB with 8× OSR, RES = 1
On-chip oversampling function
Resolution boost function
INL (maximum) 1.5 LSBs
2.5 V internal reference at 10 ppm/°C
High speed serial interface
−40°C to +125°C operation
3 mm × 3 mm, 16-lead LFCSP
Wide common-mode range
Alert function
The AD4680/AD4681 are 16-bit, pin-compatible, dual simultaneous sampling, high speed, low power, successive approximation
register (SAR) analog-to-digital converters (ADCs) that operate
from a 3.0 V to 3.6 V power supply and feature throughput rates
of 1 MSPS for the AD4680 and 500 kSPS for the AD4681. The
analog input type is differential, accepts a wide common-mode
input voltage, and is sampled and converted on the falling edge
of CS. Integrated on-chip oversampling blocks improve dynamic
range and reduce noise at lower bandwidths. A buffered internal
2.5 V reference is included. Alternatively, an external reference
up to 3.3 V can be used.
The conversion process and data acquisition use standard control
inputs, allowing easy interfacing to microprocessors or digital
signal processors (DSPs). The device is compatible with 1.8 V,
2.5 V, and 3.3 V interfaces using a separate logic supply. The
AD4680/AD4681 are available in a 16-lead lead frame chip scale
package (LFCSP) with operation specified from −40°C to +125°C.
COMPANION PRODUCTS
APPLICATIONS
ADC Drivers: ADA4896-2, ADA4940-2, ADA4807-2, LTC6227
Voltage References: ADR4533, ADR4525
Low Dropout Regulators: ADP166, ADP7104, ADP7182
Additional companion products on the AD4680 and AD4681
product pages
Motor control position feedback
Motor control current sense
Sonar
Power quality
Data acquisition systems
Erbium doped fiber amplifier (EDFA) applications
Inphase (I) and quadrature (Q) demodulation
Table 1. Related Products
Input Type
Differential
Pseudo Differential
Single-Ended
16-Bit
AD7380
AD7383
AD7386
14-Bit
AD7381
AD7384
AD7387
12-Bit
AD7388
FUNCTIONAL BLOCK DIAGRAM
3.3V
3.3V
(AINA+ AND AINA– )
VCC
V REF
V REF
R
C1
AINA+
R
C2
AINA–
C1
0V
(AINB+ AND AINB– )
0V
V REF
1µF
OVERSAMPLING
ADC A
SDOA
REFIO
REFCAP
GND
REGCAP
V REF
VLOGIC
R
C1
AINB+
R
C2
AINB–
OSC
REF
CONTROL
LOGIC
LDO
OVERSAMPLING
ADC B
C1
AD4680/AD4681
0V
GND
SCLK
SDI
CS
DIGITAL
CONTROLLER
SDOB/ALERT
23409-001
0V
1µF
Figure 1.
Rev. 0
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AD4680/AD4681
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Oversampling ............................................................................. 18
Applications ...................................................................................... 1
Resolution Boost ........................................................................ 19
General Description ......................................................................... 1
Alert.............................................................................................. 19
Companion Products ....................................................................... 1
Power Modes .............................................................................. 20
Functional Block Diagram .............................................................. 1
Internal and External Reference .............................................. 20
Revision History ............................................................................... 2
Software Reset ............................................................................. 20
Specifications .................................................................................... 3
Diagnostic Self Test.................................................................... 20
Timing Specifications .................................................................. 5
Interface ........................................................................................... 21
Absolute Maximum Ratings ........................................................... 7
Reading Conversion Results ..................................................... 21
Thermal Resistance ...................................................................... 7
Low Latency Readback .............................................................. 22
Electrostatic Discharge (ESD) Ratings ...................................... 7
Reading from Device Registers ................................................ 23
ESD Caution.................................................................................. 7
Writing to Device Registers ...................................................... 23
Pin Configuration and Function Descriptions ............................ 8
CRC .............................................................................................. 23
Typical Performance Characteristics ............................................. 9
Registers ........................................................................................... 25
Terminology .................................................................................... 13
Addressing Registers.................................................................. 25
Theory of Operation ...................................................................... 14
CONFIGURATION1 Register ................................................. 26
Circuit Information ................................................................... 14
CONFIGURATION2 Register ................................................. 27
Converter Operation.................................................................. 14
ALERT Register .......................................................................... 27
Analog Input Structure.............................................................. 14
ALERT_LOW_THRESHOLD Register .................................. 28
ADC Transfer Function ............................................................ 15
ALERT_HIGH_THRESHOLD Register ................................ 28
Applications Information.............................................................. 16
Outline Dimensions ....................................................................... 29
Power Supply .............................................................................. 16
Ordering Guide .......................................................................... 29
Modes of Operation ....................................................................... 18
REVISION HISTORY
10/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 29
Data Sheet
AD4680/AD4681
SPECIFICATIONS
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, reference voltage (VREF) = 2.5 V internal, sampling frequency (fSAMPLE) = 1 MSPS (AD4680)
or 500 kSPS (AD4681), TA = −40°C to +125°C, no oversampling enabled, unless otherwise noted. FS is full scale.
Table 2.
Parameter
RESOLUTION
THROUGHPUT
AD4680
AD4681
DC ACCURACY
No Missing Codes
Differential Nonlinearity (DNL) Error
Integral Nonlinearity (INL) Error
Gain Error
Gain Error Temperature Drift
Gain Error Match
Offset Error
Zero Error Drift
Zero Error Matching
AC ACCURACY
Dynamic Range
Oversampled Dynamic Range
Signal-to-Noise Ratio (SNR)
Test Conditions/Comments
At 25°C, VCC = 3.3 V
Min
16
16
−1.0
−1.5
−0.015
−11
−0.01
−0.2
−0.5
−2
−0.5
Input frequency (fIN) = 1 kHz
VREF = 3.3 V external
Oversampling ratio (OSR) = 4×
VREF = 3.3 V external
91
89.5
OSR = 8×, RES = 1, VREF = 3.3 V external
fIN = 100 kHz
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Signal-to-Noise-and-Distortion (SINAD) Ratio
Channel to Channel Isolation
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Common-Mode Input Range
Analog Input Common-Mode Rejection
Ratio (CMRR)
DC Leakage Current
Input Capacitance
SAMPLING DYNAMICS
Input Bandwidth
fIN = 100 kHz
VREF = 3.3 V external
(AINx+) – (AINx−)
AINx+, AINx−
AINx+, AINx−
90
89
Typ
±0.7
±0.7
±0.002
±1
±0.002
±0.01
±0.5
±0.1
−VREF
−0.1
When in track mode
When in hold mode
0.1
18
5
6
25
2
26
20
Rev. 0 | Page 3 of 29
1
500
MSPS
kSPS
+1.0
+1.5
+0.015
+11
+0.01
+0.2
+0.5
+2
+0.5
Bits
LSB
LSB
% FS
ppm/°C
% FS
mV
mV
μV/°C
mV
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
+VREF
VREF + 0.1
fIN = 500 kHz
Aperture Delay
Aperture Delay Match
Aperture Jitter
Unit
Bits
93.3
91.8
95.2
92.5
91
100
89
112
−113
−104
92.5
91
−110
0.2 to VREF −
0.2
−75
At −0.1 dB
At −3 dB
Max
V
V
V
dB
1
100
μA
pF
pF
MHz
MHz
ns
ps
ps
AD4680/AD4681
Parameter
REFERENCE INPUT AND OUTPUT
VREF Input Voltage Range
VREF Input Current
AD4680
AD4681
VREF Output Voltage
Data Sheet
Test Conditions/Comments
Min
External reference
External reference
1 MSPS
500 kSPS
At 25°C
−40°C to +125°C
2.49
2.498
2.495
VREF Temperature Coefficient
VREF Noise
DIGITAL INPUTS (SCLK, SDI, CS)
Logic Levels
Input Voltage
Low (VIL)
High (VIH)
Input Current
Low (IIL)
High (IIH)
DIGITAL OUTPUTS (SDOA, SDOB/ALERT)
Output Coding
Output Low Voltage (VOL)
Output High Voltage (VOH)
Floating-State Leakage Current
Floating-State Output Capacitance
POWER SUPPLIES
VCC
Normal Mode (Static)
Shutdown Mode
VLOGIC Current (IVLOGIC)
Normal Mode (Operational)
Normal Mode (Static)
Shutdown Mode
POWER DISSIPATION
Total Power (PTOTAL)
VCC Power (PVCC)
Normal Mode
Operational
Static
Shutdown Mode
VLOGIC Power (PVLOGIC)
Normal Mode
Operational
0.26
0.23
2.5
1
7
Max
Unit
3.4
V
0.29
0.26
2.502
2.505
10
mA
mA
V
V
ppm/°C
μV rms
0.2 × VLOGIC
V
V
+1
+1
μA
μA
0.8 × VLOGIC
−1
−1
Sink current (ISINK) = 300 μA
Source current (ISOURCE) = −300 μA
Twos complement
0.4
VLOGIC − 0.3
±1
10
Bits
V
V
μA
pF
3.0
3.2
1.65
3.3
3.3
3.6
3.6
3.6
V
V
V
7.28
4.76
2.3
100
8.4
5.6
2.8
200
mA
mA
mA
μA
884
438
10
10
950
470
200
200
μA
μA
nA
nA
AD4680
AD4681
29.4
18.7
33.7
21.9
mW
mW
AD4680, 1 MSPS
AD4681, 500 kSPS
26.2
17.1
7
330
30.3
20.2
10
720
mW
mW
mW
μW
AD4680, 1 MSPS
AD4681, 500 kSPS
3.2
1.6
33
33
3.4
1.7
720
720
mW
mW
nW
nW
External reference = 3.3 V
VLOGIC
VCC Current (IVCC)
Normal Mode (Operational)
Typ
AD4680, 1 MSPS
AD4681, 500 kSPS
SDOA and SDOB/ALERT at 0x1FFF
AD4680, 1 MSPS
AD4681, 500 kSPS
Static
Shutdown Mode
Rev. 0 | Page 4 of 29
Data Sheet
AD4680/AD4681
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V internal, and TA = −40°C to +125°C, unless otherwise noted.
Table 3.
Parameter
tCYC
tSCLKED
tSCLK
tSCLKH
tSCLKL
tCSH
tQUIET
Min
Typ
Max
Unit
1
2
190
25
10
10
10
μs
μs
ns
ns
ns
ns
ns
500
1500
ns
ns
tSDOEN
tSDOH
tSDOS
tSDOT
tSDIS
tSDIH
tSCLKCS
tCONVERT
tACQUIRE
6
8
ns
ns
ns
6
8
45
ns
ns
ns
ns
ns
ns
ns
2
1
1
0
190
810
1800
ns
ns
tRESET
250
800
ns
ns
tPOWERUP
tREGWRITE
tSTARTUP
tALERTS
tALERTC
5
11
5
5
ms
ms
ms
ms
11
10
200
12
ms
μs
ns
ns
Description
Time between conversions
AD4680
AD4681
CS falling edge to first SCLK falling edge
SCLK period
SCLK high time
SCLK low time
CS pulse width
Interface quiet time prior to conversion
CS low to SDOA and SDOB/ALERT enabled
VLOGIC ≥ 2.25 V
1.65 V ≤ VLOGIC < 2.25 V
SCLK rising edge to SDOA and SDOB/ALERT hold time
SCLK rising edge to SDOA and SDOB/ALERT setup time
VLOGIC ≥ 2.25 V
1.65 V ≤ VLOGIC < 2.25 V
CS rising edge to SDOA and SDOB/ALERT high impedance
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
SCLK rising edge to CS rising edge
Conversion time
Acquire time
AD4680
AD4681
Valid time to start conversion after software reset (see Figure 37)
Valid time to start conversion after soft reset
Valid time to start conversion after hard reset
Supply active to conversion
First conversion allowed
Settled to within 1% with internal reference
Settled to within 1% with external reference
Supply active to register read write access allowed
Exiting shutdown mode to conversion
Settled to within 1% with internal reference
Settled to within 1% with external reference
Time from CS to ALERT indication (see Figure 36)
Time from CS to ALERT clear (see Figure 36)
Rev. 0 | Page 5 of 29
AD4680/AD4681
Data Sheet
Timing Diagrams
tCYC
tSCLKED
tSCLKH
tSCLK
tCSH
tSCLKL
tQUIET
tSCLKCS
CS
SDOA
SDOB/ALERT
TRISTATE
TRISTATE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
tSDOH
DB4
DB3
tSDOS
DB2
DB1
DB0
tSDOEN
SDI
DB 15
DB 14
DB 13
DB12
DB11
DB10
DB9
tSDIS
DB8
DB7
DB6
DB5
DB4
DB3
TRISTATE
TRISTATE
tSDOT
DB2
DB 1
DB 0
23409-002
SCLK
tSDIH
Figure 2. Serial Interface Timing Diagram
tCONVERT
CS
CONVERSION
CONVERSION
ACQUIRE
23409-003
ACQUIRE
tACQUIRE
Figure 3. Internal Conversion Acquire Timing
tPOWERUP
23409-004
VCC
CS
Figure 4. Power-Up Time to Conversion
tREGWRITE
VCC
SDI
23409-005
CS
REG WRITE
Figure 5. Power-Up Time to Register Read Write Access
tSTARTUP
SDI
SHUTDOWN
NORMAL
SHUTDOWN
MODE
NORMAL
MODE
ACCURATE
CONVERSION
23409-006
CS
Figure 6. Shutdown Mode to Normal Mode Timing
tCONVERT0
CS
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
tCONVERT1
tCONVERT2
tCONVERT3
tCONVERT4
Figure 7. Conversion Timing During OS Normal Mode
Rev. 0 | Page 6 of 29
23409-007
INTERNAL
Data Sheet
AD4680/AD4681
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
VCC to Ground (GND)
VLOGIC to GND
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Reference Input and Output (REFIO)
Input to GND
Input Current to Any Pin Except
Supplies
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Pb-Free Soldering Reflow
Temperature
Rating
−0.3 V to +4 V
−0.3 V to +4 V
−0.3 V to VREF + 0.3 V, VCC +
0.3 V, or 4 V (whichever is
smaller)
−0.3 V to VLOGIC + 0.3 V, or
4 V (whichever is smaller)
−0.3 V to VLOGIC + 0.3 V, or
4 V (whichever is smaller)
−0.3 V to VCC + 0.3 V, or
4 V (whichever is smaller)
±10 mA
Thermal performance is directly linked to printed circuit
board (PCB) design and operating environment. Careful
attention to PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 5. Thermal Resistance
Package Type
CP-16-451
1
θJA
55.4
θJC
12.7
Unit
°C/W
Test Condition 1: thermal impedance simulated values are based on
JEDEC 2S2P thermal test board four thermal vias. See JEDEC JESDS1.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
−40°C to +125°C
−65°C to +150°C
150°C
260°C
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Field induced charge device model (FICDM) per
ANSI/ESDA/JEDEC JS-002.
ESD Ratings for AD4680/AD4681
Table 6. AD4680/AD4681, 16-Lead LFCSP
ESD Model
HBM
FICDM
ESD CAUTION
Rev. 0 | Page 7 of 29
Withstand Threshold (V)
±4000
±1250
Class
3A
C3
AD4680/AD4681
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD4680/AD4681
13 SDOA
14 SDOB/ALERT
15 SDI
16 SCLK
TOP VIEW
(Not to Scale)
GND 1
12 CS
11 REFIO
VLOGIC 2
10 GND
REGCAP 3
REFCAP
NOTES
1. EXPOSED PAD. FOR CORRECT OPERATION OF THE DEVICE,
THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
23409-008
AINA+ 8
A INA– 7
AINB+ 6
9
A INB– 5
VCC 4
Figure 8. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1, 10
2
3
Mnemonic
GND
VLOGIC
REGCAP
4
5, 6
7, 8
9
VCC
AINB−, AINB+
AINA−, AINA+
REFCAP
11
REFIO
12
CS
13
SDOA
14
SDOB/ALERT
15
16
SDI
SCLK
EPAD
Description
Ground Reference Point. This pin is the ground reference point for all circuitry on the device.
Logic Interface Supply Voltage, 1.65 V to 3.6 V. Decouple this pin to GND with a 1 μF capacitor.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this pin to GND with a
1 μF capacitor. The voltage at this pin is 1.9 V typical.
Power Supply Input Voltage, 3.0 V to 3.6 V. Decouple this pin to GND using a 1 μF capacitor.
Analog Inputs of ADC B. These analog inputs form a differential pair.
Analog Inputs of ADC A. These analog inputs form a differential pair.
Decoupling Capacitor Pin for Band Gap Reference. Decouple this pin to GND with a 0.1 μF capacitor. The
voltage at this pin is 2.5 V typical.
Reference Input and Output. The on-chip reference of 2.5 V is available as an output on this pin for
external use if the device is configured accordingly. Alternatively, an external reference of 2.5 V to 3.3 V
can be input to this pin. Decoupling is required on this pin for both the internal and external reference
options. A 1 μF capacitor must be applied from this pin to GND.
Chip Select Input. Active low, logic input. This input provides the dual function of initiating conversions on
the AD4680/AD4681 and framing the serial data transfer.
Serial Data Output A. This pin functions as a serial data output pin to access the ADC A or ADC B
conversion results or data from any of the on-chip registers.
Serial Data Output B (SDOB). This pin functions as a serial data output to access the conversion results.
Alert Indication Output (ALERT). This pin operates as an alert going low to indicate that a conversion result
has exceeded a configured threshold.
This pin can operate as a serial data output pin or alert indication output.
Serial Data Input. This input provides the data written to the on-chip control registers.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC.
Exposed Pad. For correct operation of the device, the exposed pad must be connected to ground.
Rev. 0 | Page 8 of 29
Data Sheet
AD4680/AD4681
TYPICAL PERFORMANCE CHARACTERISTICS
VREF = 2.5 V internal, VCC = 3.6 V, VLOGIC = 3.3 V, fIN = 1 kHz, and TA = 25°C, unless otherwise noted.
0
–20
–40
SNR = 91.0dB
THD = –111.05dB
SINAD = 90.97dB
fIN = 1kHz
VREF = 2.5V (INTERNAL)
–20
–40
–60
–80
–100
–120
–80
–100
–120
–140
–140
–160
–160
–180
0
100
200
300
400
500
FREQUENCY (kHz)
–180
0
50
250
–40
–40
MAGNITUDE (dB)
–60
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
23409-110
–180
0
SNR = 92.48dB
THD = –105.66dB
SINAD = 92.29dB
fIN = 1kHz
VREF = 3.3V (EXTERNAL)
–20
0
50
100
150
200
250
FREQUENCY (MHz)
23409-113
SNR = 92.51dB
THD = –105.79dB
SINAD = 92.31dB
fIN = 1kHz
VREF = 3.3V (EXTERNAL)
–20
Figure 13. AD4681 FFT, VREF =3.3 V External
Figure 10. AD4680 FFT, VREF = 3.3 V External
180000
0
SNR = 100.09dB
THD = –106.16dB
SINAD = 99.14dB
fIN = 1kHz
VREF = 3.3V (EXTERNAL)
OSR = 8, RES = 1
–40
140000
–60
–80
–100
–120
120000
100000
60000
–160
20000
–180
0
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
23409-111
40000
50
Figure 11. AD4680 FFT with Oversampling, VREF = 3.3 V External
Rev. 0 | Page 9 of 29
87843
80000
–140
0
159754
160000
NUMBER OF HITS
–20
13074
2101 2
25
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
CODE
Figure 14. DC Histogram Codes at Code Center
6
7
23409-114
MAGNITUDE (dB)
200
0
0
MAGNITUDE (dB)
150
Figure 12. AD4681 FFT, VREF = 2.5 V Internal
Figure 9. AD4680 Fast Fourier Transform (FFT), VREF = 2.5 V Internal
–180
100
FREQUENCY (kHz)
23409-112
MAGNITUDE (dB)
–60
23409-109
MAGNITUDE (dB)
0
SNR = 91.02dB
THD = –111.12dB
SINAD = 90.98dB
fIN = 1kHz
VREF = 2.5V (INTERNAL)
Data Sheet
1.0
0.8
0.8
–0.6
0.6
–0.4
0.4
–0.2
0.2
DNL (LSB)
1.0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
–3200 –2400
–1600
–800
0
800
1600
2400
3200
CODE
–1.0
–3200
–1600
–800
0
800
1600
2400
3200
CODE
Figure 15. INL Error
Figure 18. DNL Error
96
95
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
94
–2400
23409-118
0
23409-115
INL (LSB)
AD4680/AD4681
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
94
93
92
90
91
SNR (dB)
SNR (dB)
92
90
89
88
86
88
84
87
80
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
23409-116
85
–40
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
23409-119
82
86
Figure 19. AD4680 SNR vs. Input Frequency
Figure 16. SNR vs. Temperature
–50
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
–60
THD (dB)
THD (dB)
–70
–80
–90
–100
–25
–10
5
20
35
50
65
80
TEMPERATURE (°C)
95
110
125
Figure 17. THD vs. Temperature
–120
1k
10k
100k
INPUT FREQUENCY (Hz)
Figure 20. AD4680 THD vs. Input Frequency
Rev. 0 | Page 10 of 29
1M
23409-120
–40
23409-117
–110
Data Sheet
96
AD4680/AD4681
–50
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
94
92
–70
90
–80
THD (dB)
88
–90
86
–100
84
10k
100k
1M
INPUT FREQUENCY (Hz)
–120
1k
94
92
92
SINAD (dB)
94
90
88
84
84
100k
1M
INPUT FREQUENCY (Hz)
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
88
86
10k
82
1k
10k
100k
1M
INPUT FREQUENCY (Hz)
Figure 25. AD4681 SINAD vs. Input Frequency
Figure 22. AD4681 SNR vs. Input Frequency
102
12
100
10
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
98
8
SNR (dB)
96
6
94
92
4
90
2
0
88
0
200
400
600
800
THROUGHPUT (kSPS)
Figure 23. Dynamic Current vs. Throughput
1000
86
23409-223
DYNAMIC CURRENT (mA)
1M
90
86
23409-122
SNR (dB)
96
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
82
1k
100k
Figure 24. AD4681 THD vs. Input Frequency
Figure 21. AD4680 SINAD vs. Input Frequency
96
10k
INPUT FREQUENCY (Hz)
23409-225
1k
23409-121
80
23409-224
–110
82
NO
OVERSAMPLING
2
4
OVERSAMPLING RATIO (OSR)
8
23409-226
SINAD (dB)
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
–60
Figure 26. AD4680 SNR vs. Oversampling Ratio, Oversampling Mode
Rev. 0 | Page 11 of 29
AD4680/AD4681
Data Sheet
–40
500
–50
400
–60
350
300
CMRR (dB)
SHUTDOWN CURRENT (µA)
450
250
200
150
–70
–80
–90
100
–100
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
110
100
PSRR (dB)
90
80
70
60
1k
RIPPLE FREQUENCY (Hz)
100k
1M
23409-125
50
1k
1k
1k
100k
RIPPLE FREQUENCY (Hz)
Figure 29. CMRR vs. Ripple Frequency
Figure 27. Shutdown Current vs. Temperature
40
100
–110
100
Figure 28. Power Supply Rejection Ratio (PSRR) vs. Ripple Frequency
Rev. 0 | Page 12 of 29
1M
23409-126
0
–40
23409-123
50
Data Sheet
AD4680/AD4681
TERMINOLOGY
Differential Nonlinearity (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. DNL is often
specified in terms of resolution for which no missing codes are
guaranteed.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the
Nyquist frequency, excluding harmonics and dc. The value for
SNR is expressed in decibels (dB).
Integral Nonlinearity (INL)
INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in dB, between the rms amplitude of the
input signal and the peak spurious signal.
Gain Error
The first transition (from 100 … 000 to 100 … 001) occurs at a
level ½ LSB above nominal negative full scale. The last transition
(from 011 … 110 to 011 … 111) occurs for an analog voltage
1½ LSB below the nominal full scale. The gain error is the
deviation of the difference between the actual level of the last
transition and the actual level of the first transition from the
difference between the ideal levels.
Signal-to-Noise-and-Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value for SINAD is expressed in dB.
Gain Error Drift
The gain error drift is the gain error change due to a temperature
change of 1°C.
Gain Error Matching
Gain error matching is the difference in negative full-scale error
between the input channels and the difference in positive fullscale error between the input channels.
Zero Error
Zero error is the difference between the ideal midscale voltage,
0 V, and the actual voltage producing the midscale output code,
0 LSB.
Zero Error Drift
The zero error drift is the zero error change due to a temperature
change of 1°C.
Zero Error Matching
Zero error matching is the difference in zero error between the
input channels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ratio of the power in the ADC output at the
frequency, f, to the power of a 200 mV p-p sine wave applied to
the common-mode voltage of AINx+ and AINx− of frequency, f.
CMRR is expressed in dB.
CMRR = 10log(PADC_IN/PADC_OUT)
where:
PADC_IN is the common-mode power at the frequency, f, applied
to the AINx+ and AINx− inputs.
PADC_OUT is the power at the frequency, f, in the ADC output.
Aperture Delay
Aperture delay is the measure of the acquisition performance
and is the time between the falling edge of the CS input and
when the input signal is held for a conversion.
Aperture Delay Match
Aperture delay match is the difference of the aperture delay
between ADC A and ADC B.
Aperture Jitter
Aperture jitter is the variation in aperture delay.
Rev. 0 | Page 13 of 29
AD4680/AD4681
Data Sheet
THEORY OF OPERATION
The AD4680/AD4681 are high speed, dual simultaneous sampling,
fully differential 16-bit, SAR ADCs. The AD4680/AD4681
operate from a 3.0 V to 3.6 V power supply and feature
throughput rates of 1 MSPS (AD4680) and 500 kSPS (AD4681).
The AD4680/AD4681 contain two SAR ADCs and a serial
interface with two separate data output pins. The device is
housed in a 16-lead LFCSP, offering the user considerable spacesaving advantages over alternative solutions.
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the AINx+ and AINx− pins must be matched.
Otherwise, the two inputs have different settling times,
resulting in errors.
CAPACITIVE
DAC
Data is accessed from the device via the serial interface. The
interface can operate with one or two serial outputs. The
AD4680/AD4681 have an on-chip, 2.5 V, internal VREF. If an
external reference is desired, the internal reference can be
disabled, and a reference value ranging from 2.5 V to 3.3 V can
be supplied. If the internal reference is used elsewhere in the
system, the reference output must be buffered. The differential
analog input range for the AD4680/AD4681 is the commonmode voltage (VCM) ± VREF/2.
The AD4680/AD4681 feature on-chip oversampling blocks to
improve performance. Rolling average oversampling mode and
power-down options that allow power saving between
conversions are also available. Configuration of the device is
implemented via the standard serial interface (see the Interface
section).
CONVERTER OPERATION
The AD4680/AD4681 have two SAR ADCs, each based around
two capacitive digital-to-analog converters (DACs). Figure 30
and Figure 31 show simplified schematics of one of the ADCs
in acquisition and conversion phases, respectively. The ADC
comprises control logic, an SAR, and two capacitive DACs. In
Figure 30 (the acquisition phase), SW3 is closed, SW1 and SW2
are in Position A, the comparator is held in a balanced
condition, and the sampling capacitor (CS) arrays can acquire
the differential signal on the input.
AINx–
COMPARATOR
CS
B
AINx+
A SW1
A
SW2
B
VREF
CAPACITIVE
DAC
Figure 31. ADC Conversion Phase
ANALOG INPUT STRUCTURE
Figure 32 shows the equivalent circuit of the analog input structure
of the AD4680/AD4681. The four diodes (D) provide ESD
protection for the analog inputs. Ensure that the analog input
signals never exceed the supply rails by more than 300 mV.
Exceeding the limit causes these diodes to become forwardbiased and start conducting into the substrate. These diodes can
conduct up to 10 mA without causing irreversible damage to
the device.
The C1 capacitors in Figure 32 are typically 3 pF and can primarily
be attributed to pin capacitance. The R1 resistors are lumped
components made up of the on resistance of the switches. The
value of these resistors is typically about 200 Ω. The C2 capacitors
are the sampling capacitors of the ADC with a capacitance of
15 pF typically.
VCC
D
CAPACITIVE
DAC
CS
B
AINx+
AINx–
A SW1
A
SW2
CS
AINx+
C1
COMPARATOR
CONTROL
LOGIC
SW3
D
D
AINx–
23409-012
C1
R1 C2
D
23409-014
CAPACITIVE
DAC
R1 C2
VCC
B
VREF
CONTROL
LOGIC
SW3
CS
23409-013
CIRCUIT INFORMATION
Figure 30. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 31), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected when the
conversion begins. The control logic and charge redistribution
Rev. 0 | Page 14 of 29
Figure 32. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
Data Sheet
AD4680/AD4681
ADC TRANSFER FUNCTION
The conversion result is MSB first, twos complement. The LSB
size is (2 × VREF)/2N, where N is the ADC resolution. The ADC
resolution is determined by the resolution of the device chosen,
and if resolution boost mode is enabled. Table 8 outlines the
LSB size expressed in microvolts for different resolutions and
reference voltages options.
011 ... 110
011 ... 101
100 ... 010
100 ... 001
100 ... 000
–FSR
–FSR – 1LSB
–FSR – 0.5LSB
+FSR – 1LSB
+FSR – 1.5LSB
Figure 33. ADC Ideal Transfer Function (FSR = Full-Scale Range)
Table 8. LSB Size
Resolution
(Bits)
16
18
Rev. 0 | Page 15 of 29
2.5 V Reference
(μV)
76.3
19.1
3.3 V Reference
(μV)
100.7
25.2
23409-015
The ideal transfer characteristic for the AD4680/AD4681 is
shown in Figure 33.
011 ... 111
ADC CODE (TWOS COMPLEMENT)
The AD4680/AD4681 can use a 2.5 V to 3.3 V VREF. The
AD4680/AD4681convert the differential voltage of the analog
inputs (AINA+, AINA−, AINB+, and AINB−) into a digital output.
AD4680/AD4681
Data Sheet
APPLICATIONS INFORMATION
Figure 34 shows an example of a typical application circuit for
the AD4680/AD4681. Decouple the VCC, VLOGIC, REGCAP, and
REFIO pins with suitable decoupling capacitors as shown.
The exposed pad is a ground reference point for circuitry on
the device and must be connected to the board ground.
A differential RC filter must be placed on the analog inputs to
ensure optimal performance is achieved. On a typical application,
it is recommended that resistance (R) = 33 Ω, C1 = 68 pF, and
C2 = 330 pF.
The performance of the AD4680/AD4681devices may be
impacted by noise on the digital interface. This impact depends
on the on-board layout and design. Keep a minimal distance
between the digital line and the digital interface, or place a 100 Ω
resistor in series and close to the SDOA pin and SDOB/ALERT
pin to reduce noise from the digital interface coupling of the
AD4680/AD4681.
The two differential channels of the AD4680/AD4681 can
accept an input voltage range from 0 V to VREF, and have a wide
common-mode range that allows the conversion of a variety of
signals. These analog input pins can easily be driven with an
amplifier. Table 9 lists the recommended driver amplifiers that
best fit and add value to the application.
The AD4680 and the AD4681 have a buffered internal 2.5 V
reference that can be accessed via the REFIO pin. The buffered
internal 2.5V reference must use an external buffer like the
ADA4807-2, when connecting it to the external circuitry. Both
devices have an option to use an ultralow noise, high accuracy
voltage reference as an external voltage source, ranging from
2.5 V to 3.3 V, such as the ADR4533 and ADR4525.
POWER SUPPLY
The typical application circuit in Figure 34 can be powered by
a single 5 V (V+) voltage source that supplies the entire signal
chain. The 5 V supply can come from a low noise, CMOS, low
dropout (LDO) regulator (ADP7105). The driver amplifier
supply is supplied by the 5 V (V+) and −2.5 V (V−) derived
from the inverter (ADM660), which then converts the +5 V to
−5 V, then to the ADP7182 low noise voltage regulator to output
the −2.5 V. The two independent supplies of the AD4680/
AD4681, VCC and VLOGIC, that supply the analog circuitry and
digital interface, respectively, can be supplied by a low
quiescent current LDO regulator such as the ADP166. The
ADP166 is a suitable supply with a fixed output voltage range
from 1.2 V to 3.3 V for typical VCC and VLOGIC levels. Decouple
both the VCC supply and the VLOGIC supply separately with a 1 μF
capacitor. Additionally, an internal LDO regulator supplies the
AD4680/AD4681. The on-chip regulator provides a 1.9 V supply
for internal use on the device only. Decouple the REGCAP pin
with a 1 μF capacitor connected to GND.
Power-Up
The AD4680/AD4681 are not easily damaged by power supply
sequencing. VCC and VLOGIC can be applied in any sequence. An
external reference must be applied after VCC and VLOGIC are
applied.
The AD4680/AD4681 require a tPOWERUP time from applying
VCC and VLOGIC until the ADC conversion results are stable.
Applying CS pulses or interfacing with the AD4680/AD4681
prior to the setup time elapsing does not have a negative impact
on ADC operation. Conversion results are not guaranteed to
meet data sheet specifications during this time, however, and
must be ignored.
Table 9. Signal Chain Components
Companion Devices
ADC Driver
External Reference
LDO Regulator
Part Name
ADA4896-2
ADA4940-2
ADA4807-2
LTC6227
ADR4525
ADR4533
ADP166
ADP7104
ADP7182
Description
1 nV/√Hz, rail-to-rail output amplifier
Ultralow power, full differential, low distortion
1 mA, rail-to-rail output amplifier
Low distortion rail-to-rail output op amp
Ultralow noise, high accuracy voltage reference
Ultralow noise, high accuracy voltage reference
Low quiescent, 150 mA, LDO regulator
Low noise, CMOS LDO regulator
Low noise line regulator
Rev. 0 | Page 16 of 29
Typical Application
Precision, low noise, high frequency
Precision, low density, low power
Precision, low power, high frequency
Precision, low noise, high frequency
2.5 V reference voltage
3.3 V reference voltage
3.0 V to 3.6 V supply for VCC and VLOGIC
5 V supply for driver amplifier
−2.5 V supply for driver amplifier
Data Sheet
AD4680/AD4681
V+ = 5V
V+
VCM = REF/2
+
–
REF
+
–
V+
LDO
VREF = 2.5V TO 3.3V
10kΩ
LDO
3.0V TO 3.6V
INVERTER
1.65V TO 3.6V
10kΩ
LDO
1µF
1µF
V+
AINx+
–
+
V– = –2.5V
C1
AINx–
–
+
V–
1µF
C2
V+
VREF
VCM
0V
VLOGIC
AD4680/AD4681
A INA–
V–
VCC
REFIO
A INA+
R
SDI
EXPOSED
PAD
R
C1
SDOA
SDOB/ALERT
100Ω
100Ω
DIGITAL HOST
(MICROPROCESSOR/FPGA)
SCLK
CS
A INB+
A INB–
REGCAP
REFCAP
1µF
GND
0.1µF
Figure 34. Typical Application Circuit
Rev. 0 | Page 17 of 29
23409-016
VREF
VCM
0V
+5V TO –5V
AD4680/AD4681
Data Sheet
MODES OF OPERATION
The AD4680/AD4681 have several on-chip configuration
registers for controlling the operational mode of the device.
The oversampling ratio of the digital filter is controlled using the
oversampling bits, OSR (see Table 10). The output result is
decimated to 16-bit resolution for the AD4680/AD4681. If
additional resolution is required, this resolution can be
achieved by configuring the resolution boost bit, RES, in the
CONFIGURATION1 register. See the Resolution Boost section
for further details.
OVERSAMPLING
Oversampling is a common method used in analog electronics
to improve the accuracy of the ADC result. Multiple samples of
the analog input are captured and averaged to reduce the noise
component from quantization noise and thermal noise (kTC)
of the ADC. The AD4680 and the AD4681 offer an
oversampling function on chip, rolling average oversampling.
In rolling average oversampling mode, all ADC conversions are
controlled and initiated by the falling edge of CS. After a
conversion is complete, the result is loaded into the FIFO. The
FIFO length is 8, regardless of the oversampling ratio set. The
FIFO is filled on the first conversion after a power-on reset, the
first conversion after a software controlled hard or soft reset, or
on the first conversion after the REFSEL bit is toggled. A new
conversion result is shifted into the FIFO on completion of
every ADC conversion, regardless of the status of the OSR bits
and the OS_MODE bit. This conversion allows a seamless
transition from no oversampling to rolling average oversampling,
or different rolling average oversampling ratios without waiting
for the FIFO to fill.
The rolling average oversampling functionality is enabled by
writing a 1 to the OS_MODE bit and a valid nonzero to the
OSR bits, Bits[8:6] in the CONFIGURATION1 register.
Oversampling can be disabled by writing 0 to OS_MODE and a
zero value to the OSR bits of the CONFIGURATION1 register.
Rolling Average Oversampling
Rolling average oversampling mode can be used in applications
where higher output data rates are required and where higher
SNR or dynamic range is desirable. Rolling averaging involves
taking a number of samples, adding the samples together, and
dividing the result by the number of samples taken. This result
is then output from the device. The sample data is not cleared
after the process is completed. The rolling average oversampling
mode uses a first in, first out (FIFO) buffer of the most recent
samples in the averaging calculation, allowing the ADC
throughput rate and output data rate to stay the same.
The number of samples, n, defined by the OSR bits are taken from
the FIFO, added together, and the result is divided by n. The time
between CS falling edges is the cycle time, which can be controlled
by the user, depending on the desired data output rate.
Table 10. Rolling Average Oversampling Performance Overview
AD4680
Oversampling
Ratio
Disabled
2
4
8
AD4681
SNR (dB Typical)
VREF = 2.5 V
VREF = 3.3 V
RES = 0 RES = 1 RES = 0 RES = 1
91
91
92.5
92.5
92
93
93.2
94.5
94
96
94.8
97.2
95.5
98.6
95.9
99.6
SNR (dB Typical)
RES = 0 RES = 1
85
85
84.5
87.7
85
91
85.5
93
Output Data Rate
(kSPS Maximum)
1000
1000
1000
1000
Output Data Rate
(kSPS Maximum)
500
500
500
500
VCC
CS
S1
ACQ
SDI
SDOA
SDOB/ALERT
S2
ACQ
S3
ACQ
S4
ACQ
(FIFO1 +
FIFO2 )/2
1
2
3
4
5
6
7
8
FIFO
S1
–
–
–
–
–
–
–
S1
1
2
3
4
5
6
7
8
ACQ
S6
ACQ
S7
ACQ
...
ENABLE OS = 4
ENABLE OS = 2
DON’T CARE
S5
(FIFO1 +
FIFO2)/2
(FIFO1 +
FIFO2)/2
(FIFO1 + FIFO2 +
FIFO3 + FIFO4)/4
S2
FIFO
S2
S1
–
–
–
–
–
–
1
2
3
4
5
6
7
8
FIFO
S3
S2
S1
–
–
–
–
–
1
2
3
4
5
6
7
8
FIFO
S4
S3
S2
S1
–
–
–
–
1
2
3
4
5
6
7
8
FIFO
S5
S4
S3
S2
S1
–
–
–
Figure 35. Rolling Average Oversampling Operation
Rev. 0 | Page 18 of 29
1
2
3
4
5
6
7
8
FIFO
S6
S5
S4
S3
S2
S1
–
–
1
2
3
4
5
6
7
8
FIFO
S7
S6
S5
S4
S3
S2
S1
–
23409-018
INTERNAL
Data Sheet
AD4680/AD4681
RESOLUTION BOOST
The default conversion result output data size is 16 bits for the
AD4680/AD4681. When the on-chip oversampling function is
enabled, the performance of the ADC can exceed 16 bits. To
accommodate the performance boost achievable, it is possible to
enable an additional two bits of resolution. If the RES bit in the
CONFIGURATION1 register is set to Logic 1 and the AD4680/
AD4681 are in a valid oversampling mode, the conversion
result size is 18 bits. In this mode, 18 SCLK cycles are required
to propagate the data for the AD4680/AD4681.
The ALERT register contains two status bits per ADC, one
corresponding to the high limit, and the other to the low limit.
A logical OR of alert signals for all ADCs creates a common alert
value. This value can be configured to drive out on the ALERT
function of the SDOB/ALERT pin. The SDOB/ALERT pin is
configured as ALERT by configuring the following bits in
CONFIGURATION1 and the CONFIGURATION2:
Set the SDO bit to 1.
Set the ALERT_EN bit to 1.
Set a valid value to the ALERT_HIGH_THRESHOLD
register and the ALERT_LOW_THRESHOLD register.
ALERT
The alert functionality is an out of range indicator and can be
used as an early indicator of an out of bounds conversion
result. An alert event triggers when the conversion result value
register exceeds the alert high limit value in the ALERT_
HIGH_THRESHOLD register or falls below the alert low limit
value in the ALERT_LOW_THRESHOLD register. The
ALERT_HIGH_THRESHOLD register and the ALERT_
LOW_THRESHOLD register are common to all ADCs. When
setting the threshold limits, the alert high threshold must always
be greater than the alert low threshold. Detailed alert
information is accessible in the ALERT register.
tALERTS
The alert indication function is available in both rolling average
oversampling and in nonoversampling modes.
The ALERT function of the SDOB/ALERT pin is updated at the
end of a conversion. The alert indication status bits in the
ALERT register are updated as well and must be read before the
end of the next conversion. The ALERT function of the
SDOB/ALERT pin is cleared with a falling edge of CS. Issuing a
software reset also clears the alert status in the ALERT register.
tALERTC
CS
SDOA
CONV
ACQ
CONV
ACQ
CONV
ACQ
ALERT
EXCEEDS THRESHOLD
Figure 36. Alert Operation
Rev. 0 | Page 19 of 29
CONV
ACQ
23409-219
INTERNAL
AD4680/AD4681
Data Sheet
POWER MODES
INTERNAL AND EXTERNAL REFERENCE
The AD4680/AD4681 have two power modes, normal mode
and shutdown mode. These modes of operation provide flexible
power management options, allowing optimization of the
power dissipation and throughput rate ratio for different
application requirements.
The AD4680/AD4681 have a buffered 2.5 V internal reference
primarily used as a reference voltage for device operation. When
using the buffered internal 2.5 V reference externally via the
REFIO pin, the internal 2.5 V reference must use an external
buffer before connecting to the external circuitry. Alternatively,
if a more accurate reference or higher dynamic range is
required, an external reference can be supplied. An externally
supplied reference can be in the range of 2.5 V to 3.3 V.
Normal Mode
Keep the AD4680/AD4681 in normal mode to achieve the
fastest throughput rate. All blocks within the AD4680/AD4681
remain fully powered at all times, and an ADC conversion can
be initiated by a falling edge of CS, when required. When the
AD4680/AD4681 are not converting, the devices are in static
mode, and power consumption is automatically reduced. Additional current is required to perform a conversion, therefore,
power consumption on the AD4680/AD4681 scales with
throughput.
Shutdown Mode
When slower throughput rates and lower power consumption
are required, use shutdown mode by either powering down the
ADC between each conversion or by performing a series of
conversions at a high throughput rate and then powering down
the ADC for a relatively long duration between these burst
conversions. When the AD4680/AD4681 are in shutdown mode,
all analog circuitry powers down, including the internal reference,
if enabled. The serial interface remains active during shutdown
mode to allow the AD4680/AD4681 to exit shutdown mode.
Reference selection (internal or external) is configured by the
REFSEL bit in the CONFIGURATION1 register. If REFSEL is
set to 0, the internal reference buffer is enabled. If an external
reference is preferred, the REFSEL bit must be set to 1, and an
external reference must be supplied to the REFIO pin.
SOFTWARE RESET
The AD4680/AD4681 have two reset modes, a soft reset and a
hard reset. A reset is initiated by writing to the reset bits in the
CONFIGURATION2 register.
A soft reset maintains the contents of the configurable registers
but refreshes the interface and the ADC blocks. Any internal
state machines are reinitialized, and the oversampling block
and FIFO are flushed. The ALERT register is cleared. The
reference and LDO regulator remain powered.
A hard reset, in addition to the blocks reset by a soft reset,
resets all user registers to the default status, resets the reference
buffer, and resets the internal oscillator block.
tRESET
CS
SDI
To enter shutdown mode, write to the PMODE bit in the
CONFIGURATION1 register. The AD4680/AD4681 shut
down and current consumption reduces.
SOFTWARE RESET
Figure 37. Software Reset Operation
DIAGNOSTIC SELF TEST
To exit shutdown mode and return to normal mode, set the
PMODE bit in the CONFIGURATION1 register to Logic 0. All
register configuration settings remain unchanged entering or
leaving shutdown mode. After exiting shutdown mode, sufficient time must be allowed for the circuitry to turn on before
starting a conversion. If the internal reference is enabled, the
reference must be allowed to settle for accurate conversions to
happen.
The AD4680/AD4681 run a diagnostic self test after a power-on
reset (POR) or after a software hard reset to ensure correct
configuration is loaded into the device.
The result of the self test is displayed in the SETUP_F bit in the
ALERT register. If the SETUP_F bit is set to Logic 1, the diagnostic
self test has failed. If the test fails, perform a software hard reset
to reset the AD4680/AD4681 registers to the default status.
tSTARTUP
SHUTDOWN
NORMAL
SHUTDOWN
MODE
NORMAL
MODE
Figure 38. Shutdown Mode Operation
Rev. 0 | Page 20 of 29
ACCURATE
CONVERSION
23409-020
CS
SDI
23409-136
Program the PMODE bit in the CONFIGURATION1 register to
configure the power modes in the AD4680/AD4681. Set PMODE
to Logic 0 for normal mode and Logic 1 for shutdown mode.
Data Sheet
AD4680/AD4681
INTERFACE
The interface to the AD4680/AD4681 is via a serial interface.
The interface consists of the CS, SCLK, SDOA, SDOB/ALERT,
and SDI pins.
are available on the next SPI access. Then, take the CS signal
low, and the conversion result clocks out on the serial output
pins. The next conversion is also initiated at this point.
The CS signal frames a serial data transfer and initiates an ADC
conversion process. The falling edge of CS puts the track-andhold into hold mode, at which point the analog input is sampled,
and the bus is taken out of three-state.
The conversion result is shifted out of the device as a 16-bit
result for the AD4680/AD4681. The MSB of the conversion result
is shifted out on the CS falling edge. The remaining data is
shifted out of the device under the control of the SCLK input.
The data is shifted out on the rising edge of SCLK, and the data
bits are valid on both the falling edge and the rising edge. After
the final SCLK falling edge, take CS high again to return the SDOA
and SDOB/ALERT pins to a high impedance state.
The SCLK signal synchronizes data in and out of the device via
the SDOA, SDOB, and SDI signals. A minimum of 16 SCLK
cycles are required for a write to or read from a register. The
minimum numbers of SCLK cycles for a conversion read is
dependent on the resolution of the device and the configuration
settings (see Table 11).
The ADC conversion operation is driven internally by an on-board
oscillator and is independent of the SCLK signal.
The AD4680/AD4681 have two serial output signals, SDOA
and SDOB. To achieve the highest throughput of the device,
use both SDOA and SDOB, 2-wire mode, to read the
conversion results. If a reduced throughput is required or
oversampling is used, it is possible to use 1-wire mode, the
SDOA signal only, for reading conversion results.
Programming the SDO bit in the CONFIGURATION2 register
configures 2-wire or 1-wire mode.
The number of SCLK cycles to propagate the conversion results
on the SDOA and SDOB/ALERT pins is dependent on the serial
mode of operation configured and if resolution boost mode is
enabled (see Figure 39 and Table 11 for details). If CRC reading
is enabled, additional SCLK cycles are required to propagate the
CRC information (see the CRC section for more details).
As the CS signal initiates a conversion, as well as framing the
data, any data access must be completed within a single frame.
Table 11. Number of SCLK Cycles, n, Required for Reading
Conversion Results
Interface
Configuration
2-Wire
Configuring the cyclic redundancy check (CRC) operation for
SPI reads or SPI writes alters the operation of the interface.
Consult the relevant CRC Read, CRC Write, and CRC
Polynomial sections to ensure proper operation.
Resolution
Boost Mode
Disabled
Enabled
1-Wire
READING CONVERSION RESULTS
Disabled
The CS signal initiates the conversion process. A high to low
transition on the CS signal initiates a simultaneous conversion
of both ADCs, ADC A and ADC B. The AD4680/AD4681 have
a one-cycle readback latency. Therefore, the conversion results
Enabled
CS
1
SDOA
SDOB/ALERT
2
3
n–2
n–1
n1
CONVERSION RESULT
1CONSULT
TABLE 11 FOR n, THE NUMBER OF SCLK CYCLES REQUIRED
Figure 39. Reading Conversion Result
Rev. 0 | Page 21 of 29
23409-021
SCLK
CRC
Read
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
SCLK
Cycles
16
24
18
26
32
40
36
44
AD4680/AD4681
Data Sheet
Serial 2-Wire Mode
LOW LATENCY READBACK
Configure 2-wire mode by setting the SDO bit to 0 in the
CONFIGURATION1 register. In 2-wire mode, the conversion
result for ADC A is output on the SDOA pin, and the conversion
result for ADC B is output on the SDOB/ALERT pin (see
Figure 40).
The interface on the AD4680/AD4681 has a one-cycle latency,
as shown in Figure 42. For applications that operate at lower
throughput rates, the latency of reading the conversion result
can be reduced. When the conversion time elapses, tCONVERT, a
second CS pulse after the initial CS pulse that initiates the
conversion, can be used to read back the conversion result. This
operation is shown in Figure 42.
Serial 1-Wire Mode
In applications where slower throughput rates are allowed, the
serial interface can be configured to operate in 1-wire mode. In
1-wire mode, the conversion results from ADC A and ADC B
are output on the serial output, SDOA. Additional SCLK cycles
are required to propagate all data. The ADC A data is output
first, followed by the ADC B conversion results (see Figure 41).
S1
S0
S2
S3
SDOA
DON’T CARE
ADC A S0
ADC A S 1
SDOB/ALERT
DON’T CARE
ADC B S0
ADC B S 1
NOP
NOP
NOP
SDI
23409-022
CS
Figure 40. Reading Conversion Results for 2-Wire Mode
S0
S1
S2
S3
SDOA
SDI
DON’T CARE
NOP
ADC A S0 ADC B S 0
NOP
ADC A S 1 ADC B S 1
NOP
23409-023
CS
Figure 41. Read Conversion Results for 1-Wire Mode
CS
SDOA
SDOB/ALERT
CNVn
DON’T CARE
ACQ
RESULTn
CNV n+1
DON’T CARE
ACQ
RESULTn+1
SCLK
TARGET SAMPLE PERIOD
Figure 42. Low Throughput Low Latency
Rev. 0 | Page 22 of 29
23409-024
INTERNAL
Data Sheet
AD4680/AD4681
The CRC read function can be used in 2-wire SPI mode, 1-wire
SPI mode, and resolution boost mode.
READING FROM DEVICE REGISTERS
All registers in the device can be read over the serial interface. A
register read is performed by issuing a register read command
followed by an additional SPI command that can be either a
valid command or no operation command (NOP). The format
for a read command is shown in Table 14. Bit D15 must be set
to 0 to select a read command. Bits[D14:D12] contain the
register address, and the subsequent 12 bits, Bits[D11:D0], are
ignored.
CRC Write
To enable the CRC write function, the CRC_W bit in the
CONFIGURATION1 register must be set to 1. To set the
CRC_W bit to 1 to enable the CRC feature, the request frame
must have a valid CRC appended to the frame.
After the CRC feature is enabled, all register write requests are
ignored unless accompanied by a valid CRC command, requiring a
valid CRC to both enable and disable the CRC write feature.
WRITING TO DEVICE REGISTERS
All read/write registers in the AD4680/AD4681 can be written
to over the serial interface. The length of an SPI write access is
determined by the CRC write function. An SPI access is 16-bit
if CRC write is disabled and is 24-bit when CRC write is
enabled. The format for a write command is shown in Table 14.
Bit D15 must be set to 1 to select a write command.
Bits[D14:D12] contain the register address, and the subsequent
12 bits, Bits[D11:D0], contain the data to be written to the
selected register.
CRC Polynomial
For CRC checksum calculations, the following polynomial is
always used: x8 + x2 + x + 1.
The following is an example of how to generate the checksum
on a conversion read. The 16-bit data conversion result of the
two channels are combined to produce a 32-bit data. The
8 MSBs of the 32-bit data are inverted and then left shifted by
eight bits to create a number ending in eight Logic 0s. The
polynomial is aligned such that the MSB is adjacent to the
leftmost Logic 1 of the data. An exclusive OR (XOR) function is
applied to the data to produce a new, shorter number. The
polynomial is again aligned such that the MSB is adjacent to the
leftmost Logic 1 of the new result, and the procedure is
repeated. This process repeats until the original data is reduced
to a value less than the polynomial, which is the 8-bit
checksum. The polynomial for this example is 100000111.
CRC
The AD4680/AD4681 have CRC checksum modes that can be
used to improve interface robustness by detecting errors in data
transmissions. The CRC feature is independently selectable for
SPI interface reads and SPI interface writes. For example, the
CRC function for SPI writes can be enabled to prevent
unexpected changes to the device configuration but disabled on
SPI reads, therefore maintaining a higher throughput rate. The
CRC feature is controlled by the programming of the CRC_W
and CRC_R bits in the CONFIGURATION1 register.
Let the original data of two channels be 0xAAAA and 0x5555,
that is, 1010 1010 1010 1010 and 0101 0101 0101 0101. The data
of the two channels is appended including eight zeros on the
right, and then becomes 1010 1010 1010 1010 0101 0101 0101
0101 0000 0000.
CRC Read
If enabled, a CRC is appended to the conversion result or
register reads and consists of an 8-bit word. The CRC is
calculated in the conversion result for ADC A and ADC B and
is output on SDOA. A CRC is also calculated and appended to
register read outputs.
S0
S1
Table 12 shows the CRC calculation of 16-bit, 2-channel data
for the AD4680/AD4681. In the final XOR operation, the
reduced data is less than the polynomial. Therefore, the
remainder is the CRC for the assumed data.
S2
S3
S4
NOP
READ REG 1
READ REG 2
NOP
NOP
SDOA
INVALID
RESULT S0
REG 1DATA
REG 2DATA
RESULT S3
SDOB/ALERT
INVALID
RESULT S0
SDI
RESULT S3
Figure 43. Register Read
S1
S0
S2
S3
SDI
SDOA
SDOB/ALERT
NOP
WRITE REG 1
WRITE REG 2
NOP
INVALID
RESULT S0
RESULT S1
RESULT S2
Figure 44. Register Write
Rev. 0 | Page 23 of 29
23409-026
CS
23409-025
CS
AD4680/AD4681
Data Sheet
Table 12. Example CRC Calculation for 2-Channel, 16-Bit Data1
Data
1 0 1 0 1
Process Data 0 1 0 1 0
1 0 0 0
1 0
1 0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X
1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0
1
1
0
0
0
1
1 1 0
1 1 1
1 1 0
1 0 0
1 0
1 0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
1
1
0
0
CRC
X means don’t care.
16 + 8 = 24 BITS
2-WIRE 16-BIT
SDOA
RESULT_A
SDOB/
ALERT
RESULT_B
CRCA,B
16 + 16 + 8 = 40 BITS
1-WIRE 16-BIT
SDOA
RESULT_A
SDOA
RESULT_A
SDOB/
ALERT
RESULT_B
RESULT_B
CRC A,B
16 + 8 = 26 BITS
2-WIRE 18-BIT
CRCA,B
18 + 18 + 8 = 44 BITS
1-WIRE 18-BIT
SDOA
RESULT_A
RESULT_B
CRC A,B
16 + 8 = 24 BITS
REGISTER READ RESULT
SDOA
REGISTER X
CRC REG X
16 + 8 = 24 BITS
REGISTER READ REQUEST
SDI
REGISTER X
CRC REG X
16 + 8 = 24 BITS
REGISTER WRITE
SDI
WRITE REGISTER X
CRC REG X
Figure 45. CRC Operation
Rev. 0 | Page 24 of 29
23409-027
1
0
1
1 0 0 0 0 0
0 0 0 1 1 1
1 0 0 1 1 1 0 0
Data Sheet
AD4680/AD4681
REGISTERS
The AD4680/AD4681 have user programmable on-chip registers for configuring the device. Table 13 shows a complete overview of the
registers available on the AD4680/AD4681. The registers are either read/write (R/W) or read only (R). Any read request to a write only
register is ignored. Any write request to a read only register is ignored. Writes to any other register address are considered an NOP and
are ignored. Any read request to a register address, other than those listed in Table 13, are considered an NOP, and the data transmitted
in the next SPI frame are the conversion results.
Table 13. Register Summary
Hex. No.
0x1
Register Name
CONFIGURATION1
0x2
CONFIGURATION2
0x3
ALERT
0x4
ALERT_LOW_THRESHOLD
0x5
ALERT_HIGH_THRESHOLD
Bits
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
Bit 15
Bit 7
Bit 14
Bit 6
OSR, Bits[1:0]
Bit 13
Bit 5
ADDRESSING
CRC_W
ADDRESSING
Bit 12
Bit 4
Bit 11
Bit 10
Bit 3
Bit 2
RESERVED
ALERT_EN
RES
RESERVED
RESET
RESERVED
CRC_R
ADDRESSING
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
RESERVED
AL_B_HIGH
ADDRESSING
Bit 9
Bit 1
OS_MODE
REFSEL
CRCW_F
AL_B_LOW
RESERVED
AL_A_HIGH
ALERT_LOW, Bits[11:8]
ALERT_LOW, Bits[7:0]
ALERT_HIGH, Bits[11:8]
ALERT_HIGH, Bits[7:0]
ADDRESSING
Bit 8
Bit 0
OSR, Bit 2
PMODE
SDO
Reset
0x0000
R/W
R/W
0x0000
R/W
SETUP_F
0x0000
R
0x0800
R/W
0x07FF
R/W
AL_A_LOW
ADDRESSING REGISTERS
A serial register transfer on the AD4680/AD4681 consists of 16 SCLK cycles. The four MSBs written to the device are decoded to
determine which register is addressed. The four MSBs consist of the register address (REGADDR), Bits[14:12], and the read/write bit
(WR). The register address bits determine which on-chip register is selected. If the addressed register is a valid write register, the
read/write bit determines whether the remaining 12 bits of data on the SDI input are loaded into the addressed register. If the WR bit is
1, the bits load into the register addressed by the register select bits. If the WR bit is 0, the command is seen as a read request. The
addressed register data is available to be read during the next read operation.
Table 14. Addressing Register Format
MSB
D15
WR
D14
D13
D12
REGADDR
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
D0
Data
Table 15. Bit Descriptions for Addressing Registers
Bit
D15
Mnemonic
WR
D14 to D12
REGADDR
D11 to D0
Data
Description
When a 1 is written to this bit, Bits[11:0] of this register are written to the register specified by REGADDR, if it
is a valid address. Alternatively, when a 0 is written, the next data sent out on the SDOA pin is a read from
the designated register if it is a valid address.
When WR = 1, the contents of REGADDR determine the register for selection as outlined in Table 13.
When WR = 0 and REGADDR contains a valid register address, the contents on the requested register are
output on the SDOA pin during the next interface access.
When WR = 0 and REGADDR contains 0x0, 0x6, or 0x7, the contents on the SDI line are ignored. The next
interface access results in the conversion results being read back.
These bits are written into the corresponding register specified by the REGADDR bits when the WR bit is
equal to 1 and the REGADDR bits contain a valid address.
Rev. 0 | Page 25 of 29
AD4680/AD4681
Data Sheet
CONFIGURATION1 REGISTER
Address: 0x1, Reset: 0x0000, Name: CONFIGURATION1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[15:12] ADDRESSING (R/W)
Addressing
[0] PMODE (R/W)
Power-Down Mode.
[11:10] RESERVED
[1] REFSEL (R/W)
Reference Select.
[9] OS_MODE (R/W)
Oversampling Mode.
[2] RES (R/W)
Resolution.
[8:6] OSR (R/W)
Oversampling Ratio.
[3] ALERT_EN (R/W)
Enable Alert Indicator Function.
[5] CRC_W (R/W)
CRC Write.
[4] CRC_R (R/W)
CRC Read.
Table 16. Bit Descriptions for CONFIGURATION1 Register
Bits
[15:12]
Bit Name
ADDRESSING
[11:10]
9
RESERVED
OS_MODE
[8:6]
OSR
5
CRC_W
4
CRC_R
3
ALERT_EN
2
RES
1
REFSEL
0
PMODE
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
Reserved.
Oversampling Mode. Enables the rolling average oversampling mode of the ADC.
0: disable.
1: enable.
Oversampling Ratio. Sets the oversampling ratio for all the ADCs in the rolling average mode.
Rolling average mode supports oversampling ratios of ×2, ×4, and ×8.
000: disabled.
001: 2×.
010: 4×.
011: 8×.
100: disabled.
101: disabled.
110: disabled.
111: disabled.
CRC Write. Controls the CRC functionality for the SDI interface. When setting this bit from a 0
to a 1, the command must be followed by a valid CRC to set this configuration bit. If a valid
CRC is not received, the entire frame is ignored. If the bit is set to 1, it requires a CRC to clear it to 0.
0: no CRC function.
1: CRC function.
CRC Read. Controls the CRC functionality for the SDOA and SDOB/ALERT interface.
0: no CRC function.
1: CRC function.
Enable Alert Indicator Function. This alert function (on the SDOB/ALERT pin) is enabled when
the SDO bit (Register 0x2, Bit 8) = 1. Otherwise, the ALERT_EN bit is ignored.
0: SDOB.
1: ALERT.
Resolution. Sets the size of the conversion result data. If OSR = 0, these bits are ignored, and
the resolution is set to the default resolution.
0: normal resolution.
1: 2-bit higher resolution.
Reference Select. Selects the ADC reference source.
0: selects internal reference.
1: selects external reference.
Power-Down Mode. Sets the power modes.
0: normal mode.
1: shutdown mode.
Rev. 0 | Page 26 of 29
Reset
0x0
Access
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Data Sheet
AD4680/AD4681
CONFIGURATION2 REGISTER
Address: 0x2, Reset: 0x0000, Name: CONFIGURATION2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[15:12] ADDRESSING (R/W)
Addressing
[7:0] RESET (R/W)
Reset
[11:9] RESERVED
[8] SDO (R/W)
SDO
Table 17. Bit Descriptions for CONFIGURATION2 Register
Bits
[15:12]
Bit Name
ADDRESSING
[11:9]
8
RESERVED
SDO
[7:0]
RESET
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
Reserved.
SDO. Conversion results serial data output.
0: 2-wire, conversion data are output on both SDOA and SDOB/ALERT.
1: 1-wire, conversion data are output on SDOA only.
Reset.
Set to 0x3C to perform a soft reset, which refreshes some blocks, and register contents remain
unchanged. Clears the ALERT register and flushes any oversampling stored variables or active
state machine.
Set to 0xFF to perform a hard reset, which resets all possible blocks in the device. Register
contents are set to defaults. All other values are ignored.
Reset
0x0
Access
R/W
0x0
0x0
R
R/W
0x0
R/W
Reset
0x0
Access
R
0x0
0x0
R
R
0x0
R
0x0
R
ALERT REGISTER
Address: 0x3, Reset: 0x0000, Name: ALERT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[15:12] ADDRESSING (R)
Addressing
[0] AL_A_LOW (R)
Alert A Low
[11:10] RESERVED
[1] AL_A_HIGH (R)
Alert A High
[9] CRCW_F (R)
CRC Error
[3:2] RESERVED
[8] SETUP_F (R)
Load Error
[4] AL_B_LOW (R)
Alert B Low
[7:6] RESERVED
[5] AL_B_HIGH (R)
Alert B High
Table 18. Bit Descriptions for ALERT
Bits
[15:12]
Bit Name
ADDRESSING
[11:10]
9
RESERVED
CRCW_F
8
SETUP_F
[7:6]
RESERVED
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers
section for further details.
Reserved.
CRC Error. Indicates that a register write command failed due to a CRC error. This fault bit is
sticky and remains set until the register is read.
0: no CRC error.
1: CRC error.
Load Error. The SETUP_F indicates that the device configuration data did not load correctly on
startup. This bit does not clear on an ALERT register read. A hard reset via the
CONFIGURATION2 register is required to clear this bit and restart the device setup again.
0: no setup error.
1: setup error.
Reserved.
Rev. 0 | Page 27 of 29
AD4680/AD4681
Bits
5
Bit Name
AL_B_HIGH
4
AL_B_LOW
[3:2]
1
RESERVED
AL_A_HIGH
0
AL_A_LOW
Data Sheet
Description
Alert B High. The alert indication high bit indicates if a conversion result for the respective
input channel exceeds the value set in the ALERT_HIGH_THRESHOLD register. This fault bit is
sticky and remains set until the register is read.
1: alert indication.
0: no alert indication.
Alert B Low. The alert indication low bit indicates if a conversion result for the respective input
channel exceeds the value set in the ALERT_LOW_THRESHOLD register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
Reserved.
Alert A High. The alert indication high bit indicates if a conversion result for the respective
input channel exceeds the value set in the ALERT_HIGH_THRESHOLD register. This fault bit is
sticky and remains set until the register is read.
1: alert indication.
0: no alert indication.
Alert A Low. The alert indication low bit indicates if a conversion result for the respective input
channel exceeds the value set in the ALERT_LOW_THRESHOLD register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
Reset
0x0
Access
R
0x0
R
0x0
0x0
R
R
0x0
R
Reset
0x0
Access
R/W
0x800
R/W
Reset
0x0
Access
R/W
0x7FF
R/W
ALERT_LOW_THRESHOLD REGISTER
Address: 0x4, Reset: 0x0800, Name: ALERT_LOW_THRESHOLD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
[15:12] ADDRESSING (R/W)
Addressing
[11:0] ALERT_LOW (R/W)
Alert Low
Table 19. Bit Descriptions for ALERT_LOW_THRESHOLD
Bits
[15:12]
Bit Name
ADDRESSING
[11:0]
ALERT_LOW
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
Alert Low. Bits[11:0] from ALERT_LOW move to the MSBs of the internal ALERT_LOW register,
Bits[15:4]. The remaining Bits[3:0] of the internal register are fixed at 0x0. Sets an alert when
the converter result is below ALERT_LOW_THRESHOLD and the alert is disabled when it is
above ALERT_LOW_THRESHOLD.
ALERT_HIGH_THRESHOLD REGISTER
Address: 0x5, Reset: 0x07FF, Name: ALERT_HIGH_THRESHOLD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
[15:12] ADDRESSING (R/W)
Addressing
[11:0] ALERT_HIGH (R/W)
Alert High
Table 20. Bit Descriptions for ALERT_HIGH_THRESHOLD
Bits
[15:12]
Bit Name
ADDRESSING
[11:0]
ALERT_HIGH
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing
Registers section for further details.
Alert High. Bits[11:0] from ALERT_HIGH move to the MSBs of the internal ALERT_HIGH register,
Bits[15:4]. The remaining Bits[3:0] of the internal register are fixed at 0xF. Sets an alert when
the converter result is above the ALERT_HIGH_THRESHOLD register and the alert is disabled
when the converter result is below the ALERT_HIGH_THRESHOLD register.
Rev. 0 | Page 28 of 29
Data Sheet
AD4680/AD4681
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10
3.00 SQ
2.90
0.30
0.25
0.18
P IN 1
IN D IC AT O R AR E A OP T IO N S
(SEE DETAIL A)
16
13
12
1
0.50
BSC
EXPOSED
ED
PAD
1.10 SQ
1.00
9
TOP VIEW
0.80
0.75
0.70
4
5
8
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.15 REF
SEATING
PLANE
PKG-005000
0.45
0.40
0.35
0.45
*1.20
0.55 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WEED-4
WITH EXCEPTION TO THE EXPOSED PAD
08-29-2018-A
PIN 1
INDICATOR
AREA
Figure 46. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-45)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
AD4680BCPZ-RL
AD4680BCPZ-RL7
AD4681BCPZ-RL
AD4681BCPZ-RL7
EVAL-AD7380FMCZ
1
2
Resolution
16-Bit
16-Bit
16-Bit
16-Bit
Throughput
Rate
1 MSPS
1 MSPS
500 kSPS
500 kSPS
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
AD7380 Evaluation Board
Package
Option
CP-16-45
CP-16-45
CP-16-45
CP-16-45
Marking
Code
CAK
CAK
CAM
CAM
Z = RoHS Compliant Part.
Use the EVAL-AD7380FMCZ to evaluate the AD4680 and AD4681. The EVAL-AD7380FMCZ is compatible with the EVAL-SDP-CH1Z high speed controller board.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D23409-10/20(0)
Rev. 0 | Page 29 of 29
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