Pseudo Differential Input, 1 MSPS/500 kSPS,
Dual, Simultaneous Sampling, 16-Bit, SAR ADCs
AD4682/AD4683
Data Sheet
FEATURES
GENERAL DESCRIPTION
Dual 16-bit ADC family
Dual simultaneous sampling
Pseudo differential analog inputs
Throughput conversion rate
1 MSPS for the AD4682
500 kSPS for the AD4683
SNR (typical)
87.5 dB, VREF = 3.3 V external
93.4 dB with RES = 1 and OSR = ×8
On-chip oversampling function
Alert function
Resolution boost function
INL error (maximum): 2.5 LSBs
2.5 V internal reference
High speed serial interface
−40°C to +125°C operation
3 mm × 3 mm, 16-lead LFCSP
The AD4682 and the AD4683 are a 16-bit, pin-compatible family
of dual, simultaneous sampling, high speed, low power, successive
approximation register (SAR), analog-to-digital converters (ADCs)
that operate from a 3.0 V to 3.6 V power supply and feature
throughput rates up to 1 MSPS for the AD4682 and 500 kSPS
for the AD4683. The analog input type is pseudo differential
and is sampled and converted on the falling edge of CS.
Integrated on-chip oversampling blocks improve dynamic range
and reduce noise at lower bandwidths. A buffered internal 2.5 V
reference is included. Alternatively, an external reference up to
3.3 V can be used.
The conversion process and data acquisition use standard control
inputs that allow simple interfacing to microprocessors or digital
signal processors (DSPs). The devices are compatible with
1.8 V, 2.5 V, and 3.3 V interfaces, using a separate logic supply.
COMPANION PARTS
APPLICATIONS
ADC Drivers: ADA4896-2, ADA4940-2, ADA4807-2, LTC6227
Voltage References: ADR4533 (3.3 V), ADR4525 (2.5 V)
Low Dropout Regulators: ADP166, ADP7104, ADP7182
Additional companion products on the AD4682 and AD4683
product pages
Motor control position feedback
Motor control current sense
Sonar
Power quality
Data acquisition systems
Erbium doped fiber amplifier (EDFA) applications
Inphase (I) and quadrature (Q) demodulation
Table 1. Related Devices in the Family
Input Type
Differential
Pseudo Differential
Single-Ended
16-Bit
AD7380
AD7383
AD7386
14-Bit
AD7381
AD7384
AD7387
12-Bit
AD7388
FUNCTIONAL BLOCK DIAGRAM
3.3V
3.3V
1µF
(AINA+)
1µF
VLOGIC
VCC
VREF
R
0V
C1
AINA+
OVERSAMPLING
ADC A
AINA–
VREF/2
SDOA
REFIO
REFCAP
GND
OSC
REF
CONTROL
LOGIC
(AINB+)
REGCAP
R
0V
VREF/2
C1
DIGITAL
CONTROLLER
AINB+
AINB–
OVERSAMPLING
ADC B
AD4682/AD4683
GND
SDOB/ALERT
23411-001
VREF
LDO
SCLK
SDI
CS
Figure 1.
Rev. 0
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AD4682/AD4683
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Oversampling ............................................................................. 18
Applications ...................................................................................... 1
Resolution Boost ........................................................................ 18
General Description ......................................................................... 1
Alert.............................................................................................. 19
Companion Parts.............................................................................. 1
Power Modes .............................................................................. 19
Functional Block Diagram .............................................................. 1
Internal and External Reference .............................................. 20
Revision History ............................................................................... 2
Software Reset ............................................................................. 20
Specifications .................................................................................... 3
Diagnostic Self Test.................................................................... 20
Timing Specifications .................................................................. 5
Interface ........................................................................................... 21
Absolute Maximum Ratings ........................................................... 7
Reading Conversion Results ..................................................... 21
Thermal Resistance ...................................................................... 7
Low Latency Readback .............................................................. 22
Electrostatic Discharge (ESD) Ratings ...................................... 7
Reading from Device Registers ................................................ 23
ESD Caution.................................................................................. 7
Writing to Device Registers ...................................................... 23
Pin Configuration and Function Descriptions ............................ 8
CRC .............................................................................................. 24
Typical Performance Characteristics ............................................. 9
Registers ........................................................................................... 26
Terminology .................................................................................... 13
Addressing Registers.................................................................. 26
Theory of Operation ...................................................................... 14
CONFIGURATION1 Register ................................................. 27
Circuit Information ................................................................... 14
CONFIGURATION2 Register ................................................. 28
Converter Operation.................................................................. 14
ALERT Register .......................................................................... 28
Analog Input Structure.............................................................. 14
ALERT_LOW_THRESHOLD Register .................................. 29
ADC Transfer Function ............................................................ 15
ALERT_HIGH_THRESHOLD Register ................................ 29
Applications Information.............................................................. 16
Outline Dimensions ....................................................................... 30
Power Supply .............................................................................. 16
Ordering Guide .......................................................................... 30
Modes of Operation ....................................................................... 18
REVISION HISTORY
10/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 30
Data Sheet
AD4682/AD4683
SPECIFICATIONS
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, reference voltage (VREF) = 2.5 V internal, sampling frequency (fSAMPLE) = 1 MSPS for the
AD4682, fSAMPLE = 500 kSPS for the AD4683, TA = −40°C to +125°C, and no oversampling enabled, unless otherwise noted. FS is full scale.
Multifunction pin names may be referenced by their relevant function only.
Table 2.
Parameter
RESOLUTION
THROUGHPUT CONVERSION RATE
AD4682
AD4683
DC ACCURACY
No Missing Codes
Differential Nonlinearity (DNL) Error
Integral Nonlinearity (INL) Error
Gain Error
Gain Error Temperature Drift
Gain Error Match
Offset Error
Offset Temperature Drift
Offset Error Match
AC ACCURACY
Dynamic Range
Oversampled Dynamic Range
Signal-to-Noise Ratio (SNR)
Test Conditions/Comments
−40°C to +125°C
Min
16
16
−1.0
−2.5
−0.06
−3
−0.5
−5
−40°C to +125°C
Input frequency (fIN) = 1 kHz
VREF = 3.3 V external
Oversampling ratio (OSR) = ×4
VREF = 3.3 V external
85
84
OS_MODE = 1, OSR = ×8, RES = 1
fIN = 100 kHz
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Signal-to-Noise-and-Distortion (SINAD)
Channel to Channel Isolation
ANALOG INPUT
Voltage Range
Absolute Input Voltage Range
Common-Mode Input Range
Common-Mode Rejection Ratio (CMRR)
DC Leakage Current
Input Capacitance
SAMPLING DYNAMICS
Input Bandwidth
fIN = 100 kHz
VREF = 3.3 V external
(AINx+) to (AINx−)
AINx+
AINx−
fIN = 500 kHz
When in track mode
When in hold mode
At −0.1 dB
At −3 dB
84.5
83.5
Typ
±0.5
±1
±0.02
±1
0.025
±0.05
±1
0.05
Rev. 0 | Page 3 of 30
Unit
Bits
1
500
MSPS
kSPS
+1.0
+2.5
+0.06
+3
+0.07
+0.5
+5
+0.5
Bits
LSB
LSB
% FS
ppm/°C
% FS
mV
µV/°C
mV
88
86
91.8
87.5
86
93.4
85.3
101
−100
−97
87
85.5
−110
−VREF/2
−0.1
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
+VREF/2
VREF + 0.1
VREF/2 ± 0.075
−70
0.1
18
5
6
25
2
26
20
Aperture Delay
Aperture Delay Match
Aperture Jitter
Max
1
100
V
V
V
dB
µA
pF
pF
MHz
MHz
ns
ps
ps
AD4682/AD4683
Parameter
REFERENCE INPUT AND OUTPUT
VREF Input
Voltage Range
Current
AD4682
AD4683
VREF Output Voltage
VREF Temperature Coefficient
VREF Noise
DIGITAL INPUTS (SCLK, SDI, AND CS)
Logic Levels
Input Voltage
Low (VIL)
High (VIH)
Input Current
Low (IIL)
High (IIH)
DIGITAL OUTPUTS (SDOA AND SDOB/ALERT)
Output Coding
Output Voltage
Low (VOL)
High (VOH)
Floating State
Leakage Current
Output Capacitance
POWER SUPPLIES
VCC
Data Sheet
Test Conditions/Comments
Min
External reference
External reference
1 MSPS
500 kSPS
−40°C to +125°C
2.49
Normal Mode (Static)
Shutdown Mode
VLOGIC Current (IVLOGIC)
Normal Mode (Operational)
Normal Mode (Static)
Shutdown Mode
Power Dissipation
Total Power (PTOTAL) (Operational)
VCC Power (PVCC)
Normal Mode (Operational)
Normal Mode (Static)
Shutdown Mode
VLOGIC Power (PVLOGIC)
Normal Mode (Operational)
0.26
0.23
2.5
5
7
Max
Unit
3.4
V
0.29
0.26
2.505
10
mA
mA
V
ppm/°C
µV rms
0.2 × VLOGIC
V
V
+1
+1
µA
µA
0.8 × VLOGIC
−1
−1
Twos complement
Sink current (ISINK) = 300 µA
Source current (ISOURCE) = −300 µA
Bits
0.4
V
V
±1
µA
pF
3.3
3.3
3.6
3.6
3.6
V
V
V
7.28
4.76
2.3
101
8.4
5.6
2.8
200
mA
mA
mA
µA
884
438
10
10
950
470
200
200
µA
µA
nA
nA
83
107
mW
26.2
17.2
8
365
30.3
20.2
11
720
mW
mW
mW
µW
3.2
1.6
36
36
3.5
1.7
720
720
mW
mW
nW
nW
VLOGIC − 0.3
10
External reference = 3.3 V
VLOGIC
VCC Current (IVCC)
Normal Mode (Operational)
2.495
Typ
AD4682, 1 MSPS
AD4683, 500 kSPS
SDOA and SDOB at 0x1FFF
AD4682, 1 MSPS
AD4683, 500 kSPS
AD4682, 1 MSPS
AD4683, 500 kSPS
SDOA and SDOB at 0x1FFF
AD4682, 1 MSPS
AD4683, 500 kSPS
Normal Mode (Static)
Shutdown Mode
Rev. 0 | Page 4 of 30
3.0
3.2
1.65
Data Sheet
AD4682/AD4683
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V internal, and TA = −40°C to +125°C, unless otherwise noted. See Figure 2 to Figure 5,
Figure 37, Figure 38, and Figure 39 for the timing diagrams. Multifunction pin names may be referenced by their relevant function only.
Table 3.
Parameter
tCYC
tSCLKED
tSCLK
tSCLKH
tSCLKL
tCSH
tQUIET
Min
Typ
Max
Unit
1
2
190
25
10
10
10
µs
µs
ns
ns
ns
ns
ns
500
1500
ns
ns
tSDOEN
tSDOH
tSDOS
tSDOT
tSDIS
tSDIH
tSCLKCS
tCONVERT
tACQUIRE
6
8
ns
ns
ns
6
8
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
1
1
0
190
810
1810
tRESET
250
800
ns
ns
tPOWERUP
tREGWRITE
tSTARTUP
tALERTS
tALERTC
5
11
5
5
ms
ms
ms
ms
11
10
220
12
ms
µs
ns
ns
Description
Time between conversions
AD4682
AD4683
CS falling edge to first SCLK falling edge
SCLK period
SCLK high time
SCLK low time
CS pulse width
Interface quiet time prior to conversion
AD4682
AD4683
CS low to SDOA and SDOB/ALERT enabled
VLOGIC ≥ 2.25 V
1.65 V ≤ VLOGIC < 2.3 V
SCLK rising edge to SDOA and SDOB/ALERT hold time
SCLK rising edge to SDOA and SDOB/ALERT setup time
VLOGIC ≥ 2.25 V
1.65 V ≤ VLOGIC < 2.3 V
CS rising edge to SDOA and SDOB/ALERT high impedance
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
SCLK rising edge to CS rising edge
Conversion time
Acquire time
AD4682
AD4683
Valid time to start conversion after software reset
Valid time to start conversion after soft reset
Valid time to start conversion after hard reset
Supply active to conversion
First conversion allowed
Settled to within 1% with internal reference
Settled to within 1% with external reference
Supply active to register read write access allowed
Exiting shutdown mode to conversion
Settled to within 1% with internal reference
Settled to within 1% with external reference
Time from CS to ALERT indication
Time from CS to ALERT clear
Rev. 0 | Page 5 of 30
AD4682/AD4683
Data Sheet
Timing Diagrams
tCYC
tSCLKED
tSCLKL
tSCLKH
tSCLK
tCSH
tQUIET
tSCLKCS
CS
6
5
4
7
8
9
10
11
12
13
14
15
16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB15
DB14
DB13
DB12
DB10
DB11
tSDIS
DB9
DB8
DB6
DB7
DB4
DB5
DB3
tSDIH
Figure 2. Serial Interface Timing Diagram
tCONVERT
CS
CONVERSION
CONVERSION
ACQUIRE
ACQUIRE
tACQUIRE
Figure 3. Internal Conversion Acquire Timing
tPOWERUP
VCC
CS
TIME TO ACCURATE CONVERSION
Figure 4. Power-Up Time to Conversion
tREGWRITE
VCC
CS
SDI
REG
WRITE
Figure 5. Power-Up Time to Register Read Write Access
Rev. 0 | Page 6 of 30
TRISTATE
tSDOT
tSDOS
tSDOH
tSDOEN
SDI
TRISTATE
DB2
DB1
DB0
23411-002
TRISTATE
3
23411-003
SDOB
TRISTATE
2
23411-004
SDOA
1
23411-005
SCLK
Data Sheet
AD4682/AD4683
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
VCC to GND
VLOGIC to GND
Input Voltage
Analog to GND
Digital to GND
Digital Output Voltage to
GND
REFIO Input to GND
Input Current to Any Pin
Except Supplies
Temperature
Operating Range
Storage Range
Junction
Pb-Free Soldering Reflow
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Rating
−0.3 V to +4 V
−0.3 V to +4 V
−0.3 V to VREF + 0.3 V, VCC + 0.3 V,
or +4 V (whichever is smaller)
−0.3 V to VLOGIC + 0.3 V, or +4 V
(whichever is smaller)
−0.3 V to VLOGIC + 0.3 V, or +4 V
(whichever is smaller)
−0.3 V to VCC + 0.3 V
±10 mA
θJA is the natural convection, junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 5. Thermal Resistance
Package Type
CP-16-451
1
θJA
55.4
θJC
12.7
Unit
°C/W
Test Condition 1: thermal impedance simulated values are based on
JEDEC 2S2P thermal test board four thermal vias. See JEDEC JESDS-51.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
−40°C to +125°C
−65°C to +150°C
150°C
260°C
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Field induced charge device model (FICDM) per ANSI/ESDA/
JEDEC JS-002.
ESD Ratings for AD4682 and AD4683
Table 6. AD4682 and AD4683, 16-Lead LFCSP
ESD Model
HBM
FICDM
ESD CAUTION
Rev. 0 | Page 7 of 30
Withstand Threshold (V)
±4000
±1250
Class
3A
C3
AD4682/AD4683
Data Sheet
13 SDOA
14 SDOB/ALERT
16 SCLK
15 SDI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND 1
REGCAP 3
12 CS
AD4682/
AD4683
TOP VIEW
(Not to Scale)
11 REFIO
10 GND
9
AINA– 7
REFCAP
AINA+ 8
AINB– 5
AINB+ 6
VCC 4
NOTES
1. EXPOSED PAD. FOR PROPER OPERATION OF THE DEVICE,
CONNECT THE EXPOSED PAD TO GROUND.
23411-009
VLOGIC 2
Figure 6. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1, 10
2
3
Mnemonic
GND
VLOGIC
REGCAP
4
5, 6
VCC
AINB−, AINB+
7, 8
AINA−, AINA+
9
REFCAP
11
REFIO
12
CS
13
SDOA
14
SDOB/ALERT
15
16
SDI
SCLK
EPAD
Description
Ground Reference Points. The GND pins are the ground reference points for all circuitry on the device.
Logic Interface Supply Voltage, 1.65 V to 3.6 V. Decouple VLOGIC to GND with a 1 µF capacitor.
Decoupling Capacitor Pin for Voltage Output from the Internal Regulator. Decouple REGCAP to GND with a 1 µF
capacitor. The voltage at REGCAP is 1.9 V typical.
Power Supply Input Voltage, 3.0 V to 3.6 V. Decouple VCC to GND using a 1 µF capacitor.
Analog Inputs of ADC B. The AINB− and AINB+ analog inputs form a pseudo differential pair. AINB− is typically
connected to VREF/2, and the AINB+ voltage range is from 0 V to VREF.
Analog Inputs of ADC A. The AINA− and AINA+ analog inputs form a pseudo differential pair. AINA− is typically
connected to VREF/2, and the AINA+ voltage range is from 0 V to VREF.
Decoupling Capacitor Pin for Band Gap Reference. Decouple REFCAP to GND with a 0.1 µF capacitor. The voltage
at REFCAP is 2.5 V typical.
Reference Input and Output. The on-chip reference of 2.5 V is available as an output on REFIO for external use if
the device is configured accordingly. Alternatively, an external reference of 2.5 V to 3.3 V can be input to REFIO.
Set the REFSEL bit in the CONFIGURATION1 register to 1 when using the external reference, and apply the
REFSEL bit after VCC and VLOGIC. Decoupling is required on REFIO for both the internal and external reference
options. Apply a 1 µF capacitor from REFIO to GND.
Chip Select Input. Active low, logic input. CS provides the dual function of initiating conversions on the AD4682
and the AD4683 and framing the serial data transfer.
Serial Data Output A. SDOA functions as a serial data output pin to access the ADC A or ADC B conversion results
or data from any of the on-chip registers.
Serial Data Output B/Alert Indication Output. The SDOB/ALERT pin can operate as a serial data output pin or an
alert indication output.
SDOB functions as a serial data output pin to access the ADC B conversion results.
ALERT operates as an alert pin going low to indicate that a conversion result exceeded a configured threshold.
When using ALERT, set the SDO bit in the CONFIGURATION2 register to 1, and set the ALERT_EN bit to 1 in the
CONFIGURATION1 register.
Serial Data Input. SDI provides the data written to the on-chip control registers.
Serial Clock Input. SCLK is for data transfers to and from the ADC.
Exposed Pad. For proper operation of the device, connect the exposed pad to ground.
Rev. 0 | Page 8 of 30
Data Sheet
AD4682/AD4683
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
SNR = 87.7dB
THD = –102.82dB
SINAD = 85.6dB
fIN = 1kHz
VREF = 3.3V (EXTERNAL)
–40
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
0
100
200
300
FREQUENCY (kHz)
400
–180
23411-108
–180
500
0
100
Figure 7. AD4682 Fast Fourier Transform (FFT), VREF = 3.3 V External
500
250
0
SNR = 87.28dB
THD = –99.1dB
SINAD = 87dB
fIN = 1kHz
VREF = 3.3V (EXTERNAL)
–20
–40
–40
MAGNITUDE (dB)
–60
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
0
50
100
150
FREQUENCY (kHz)
SNR = 85.68dB
THD = –102.6dB
SINAD = 85.6dB
fIN = 1kHz
VREF = 2.5V (EXTERNAL)
–20
200
250
–180
23411-109
0
100
150
FREQUENCY (kHz)
50
Figure 8. AD4683 FFT, VREF = 3.3 V External
200
Figure 11. AD4683 FFT, VREF = 2.5 V External
120000
0
SNR = 95.1dB
THD = –99.1dB
SINAD = 93.6dB
fIN = 1kHz
VREF = 3.3V (EXTERNAL)
RES = 1, OSR = 8
–20
–40
95992
100000
85602
NUMBR OF HITS
–60
–80
–100
–120
80000
60000
40438
40000
29563
–140
20000
6450
–160
4157
11 370
0
100
200
300
FREQUENCY (kHz)
400
500
0
23411-110
–180
–6
–5
–4
–3
–2
–1
0
1
2
3
210
6
4
5
CODE
Figure 9. AD4682 FFT, Rolling Average Oversampling
Figure 12. DC Histogram at Code Center
Rev. 0 | Page 9 of 30
6
7
23411-113
MAGNITUDE (dB)
400
Figure 10. AD4682 FFT, VREF = 2.5 V Internal
0
MAGNITUDE (dB)
200
300
FREQUENCY (kHz)
23411-111
–60
MAGNITUDE (dB)
MAGNITUDE (dB)
–40
SNR = 85.7dB
THD = –102.82dB
SINAD = 85.6dB
fIN = 1kHz
VREF = 2.5V (INTERNAL)
–20
23411-112
–20
AD4682/AD4683
Data Sheet
1.5
1.0
0.8
1.0
0.6
0.4
DNL (LSB)
INL (LSB)
0.5
0
–0.5
0.2
0
–0.2
–0.4
–0.6
–1.0
8000
16000
24000
32000
–1.0
–32000 –24000 –16000 –8000
Figure 13. Typical INL Error
16000
24000
32000
90
88
87
87
86
86
SINAD (dB)
88
85
84
85
84
83
83
82
82
81
81
10
100
1000
FREQUENCY (kHz)
80
23411-115
1
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
89
1
100
1000
FREQUENCY (kHz)
Figure 14. AD4682 SNR vs. Frequency
–50
10
23411-118
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
89
SNR (dB)
8000
Figure 16. Typical DNL Error
90
80
0
CODE
23411-117
0
CODE
23411-114
–0.8
–1.5
–32000 –24000 –16000 –8000
Figure 17. AD4682 SINAD vs. Frequency
90
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
89
–60
88
87
SNR (dB)
THD (dB)
–70
–80
–90
86
85
84
83
–100
82
–110
10
100
FREQUENCY (kHz)
1000
80
23411-116
1
1
10
100
FREQUENCY (kHz)
Figure 15. AD4682 THD vs. Frequency
Figure 18. AD4683 SNR vs. Frequency
Rev. 0 | Page 10 of 30
1000
23411-119
81
–120
Data Sheet
–50
AD4682/AD4683
90
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
89
–60
88
87
86
SINAD (dB)
THD (dB)
–70
–80
–90
85
84
83
–100
82
–110
10
100
1000
FREQUENCY (kHz)
80
23411-120
1
1
89
1000
FREQUENCY (kHz)
Figure 19. AD4683 THD vs. Frequency
90
100
10
23411-123
81
–120
Figure 22. AD4683 SINAD vs. Frequency
–50
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
–60
88
–70
86
THD (dB)
SNR (dB)
87
85
84
83
–80
–90
–100
82
–110
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–120
–40
23411-121
80
–40
–25
89
5
20
35
50
65
80
95
110
125
110
125
TEMPERATURE (°C)
Figure 23. AD4682 THD vs. Temperature
Figure 20. AD4682 SNR vs. Temperature
90
–10
23411-124
81
–50
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
–60
88
–70
THD (dB)
86
85
–80
–90
84
83
–100
82
–110
80
–40
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
110
125
–120
–40
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
Figure 21. AD4683 SNR vs. Temperature
Figure 24. AD4683 THD vs. Temperature
Rev. 0 | Page 11 of 30
23411-125
81
23411-122
SNR (dB)
87
AD4682/AD4683
Data Sheet
500
IVCC
IVLOGIC
fIN = 1kHz SINE WAVE
DYNAMIC CURRENT (mA)
IVCC SHUTDOWN CURRENT (µA)
450
400
350
300
250
200
150
100
200
400
600
800
1000
THROUGHPUT RATE (kSPS)
0
–40
23411-126
0
20
35
50
65
80
95
110
125
99
IVCC
IVLOGIC
fIN = 1kHz SINEWAVE
97
95
93
8
SNR (dB)
6
4
91
89
87
85
83
2
81
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
79
23411-127
0
–40
EXTERNAL REFERENCE = 3.3V, RES = 1, OS_MODE = 1
INTERNAL REFERENCE = 2.5V, RES = 1, OS_MODE = 1
EXTERNAL REFERENCE = 3.3V, RES = 1, OS_MODE = 1
INTERNAL REFERENCE = 2.5V, RES = 1, OS_MODE = 1
0
2
4
8
OVERSAMPLING RATIO
23411-130
DYNAMIC CURRENT (mA)
5
Figure 28. IVCC Shutdown Current vs. Temperature
12
Figure 29. AD4682 SNR vs. Oversampling Ratio, Rolling Average Oversampling
Figure 26. Dynamic Current vs. Temperature
110
98
100
96
90
94
80
92
SNR (dB)
70
PSRR (dB)
–10
TEMPERATURE (°C)
Figure 25. Dynamic Current vs. Throughput Rate
10
–25
23411-129
50
60
50
90
88
86
40
84
82
20
80
10
0.001
0.01
RIPPLE FREQUENCY (MHz)
0.1
1
78
23411-128
0
0.0001
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Ripple Frequency
EXTERNAL REFERENCE = 3.3V, RES = 0
EXTERNAL REFERENCE = 3.3V, RES = 1
INTERNAL REFERENCE = 2.5V, RES = 0
INTERNAL REFERENCE = 2.5V, RES = 1
0
2
4
OVERSAMPLING RATIO (OSR)
8
23411-131
30
Figure 30. AD4683 SNR vs. Oversampling Ratio, Rolling Average Oversampling
Rev. 0 | Page 12 of 30
Data Sheet
AD4682/AD4683
TERMINOLOGY
Differential Nonlinearity (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. DNL is often specified
in terms of resolution for which no missing codes are guaranteed.
Integral Nonlinearity (INL)
INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line.
Gain Error
The first transition (from 100 … 000 to 100 … 001) occurs at a
level ½ LSB above nominal negative full scale. The last transition
(from 011 … 110 to 011 … 111) occurs for an analog voltage
1½ LSB below the nominal full scale. The gain error is the
deviation of the difference between the actual level of the last
transition and the actual level of the first transition from the
difference between the ideal levels.
Gain Error Temperature Drift
Gain error temperature drift is the gain error change due to a
temperature change of 1°C.
Gain Error Match
Gain error matching is the difference in negative full-scale error
between the input channels and the difference in positive full-scale
error between the input channels.
Offset Error
Offset error is the difference between the ideal midscale voltage,
0 V, and the actual voltage producing the midscale output code,
0 LSB.
Offset Temperature Drift
Offset temperature drift is the zero error change due to a
temperature change of 1°C.
Offset Error Match
Offset error match is the difference in zero error between the
input channels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in dB, between the rms amplitude of the
input signal and the peak spurious signal.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise-and-Distortion (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value for SINAD is expressed in dB.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ratio of the power in the ADC output at the
frequency, f, to the power of a 200 mV p-p sine wave applied to
the common-mode voltage of AINx+ and AINx− of frequency, f.
The value for CMRR is expressed in dB.
CMRR = 10log(PADC_IN/PADC_OUT)
where:
PADC_IN is the common-mode power at the frequency, f, applied
to the AINx+ and AINx− inputs.
PADC_OUT is the power at the frequency, f, in the ADC output.
Aperture Delay
Aperture delay is the measure of the acquisition performance
and is the time between the falling edge of the CS input and
when the input signal is held for a conversion.
Aperture Delay Match
Aperture delay match is the difference of the aperture delay
between ADC A and ADC B.
Aperture Jitter
Aperture jitter is the variation in aperture delay.
Rev. 0 | Page 13 of 30
AD4682/AD4683
Data Sheet
THEORY OF OPERATION
The AD4682 and the AD4683 are high speed, dual, simultaneous
sampling, pseudo differential, 16-bit, SAR ADCs. The AD4682
and the AD4683 operate from a 3.0 V to 3.6 V power supply and
feature throughput rates of 1 MSPS and 500 kSPS, respectively.
The AD4682 and the AD4682 contain two SAR ADCs and a
serial peripheral interface (SPI) with two separate data output
pins. The devices are housed in a 16-lead LFCSP, offering the
user considerable space-saving advantages over alternative
solutions.
Data is accessed from the devices via the SPI. The SPI can
operate with one or two serial outputs. The AD4682 and the
AD4682 have an on-chip 2.5 V internal reference, VREF. If an
external reference is required, disable the internal reference,
supply a reference value that ranges from 2.5 V to 3.3 V, and set
the REFSEL bit in the CONFIGURATION1 register to 1. If the
internal reference is used elsewhere in the system, buffer the
reference output. The pseudo differential analog input range
for the AD4682 and the AD4683 is the common-mode voltage
(VCM) ± VREF/2.
The AD4682 and the AD4683 feature an on-chip oversampling
block to improve performance. Rolling average oversampling
mode and power-down options that allow power saving between
conversions are also available. Configuration of the devices is
implemented via the standard SPI (see the Interface section).
CONVERTER OPERATION
The AD4682 and the AD4683 have two SAR ADCs, each based
around two capacitive digital-to-analog converters (DACs).
Figure 31 and Figure 32 show the simplified schematics of one
of these ADCs in acquisition and conversion phases, respectively.
The ADC comprises the control logic, an SAR, and two capacitive
DACs. In Figure 31 (the acquisition phase), SW3 is closed, SW1
and SW2 are in Position A, the comparator is held in a balanced
condition, and the sampling capacitor (CS) arrays can acquire
the pseudo differential signal on the input.
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion completes. The control logic generates
the ADC output code. The output impedances of the sources
driving the AINx+ and AINx− pins must be matched. Otherwise,
the two inputs have different settling times, which results in errors.
CAPACITIVE
DAC
B
AINx+
AINx–
A SW1
A
SW2
CS
B
VREF
CAPACITIVE
DAC
Figure 32. ADC Conversion Phase
ANALOG INPUT STRUCTURE
Figure 33 shows the equivalent analog input circuit of the AD4682
and the AD4683. The four diodes (D) provide ESD protection
for the analog inputs. Ensure that the analog input signals do
not exceed the supply rails by more than 300 mV. Exceeding the
limit causes these diodes to become forward-biased and start
conducting into the substrate. These diodes can conduct up to
10 mA without causing irreversible damage to the devices.
The C1 capacitors in Figure 33 are typically 3 pF and can primarily
be attributed to pin capacitance. The R1 resistors are lumped
components made up of the on resistance of the switches. The
value of these resistors is typically about 200 Ω. The C2 capacitors
are sampling capacitors of the ADC with a capacitance of 15 pF
typically.
VCC
D
AINx+
C1
AINx–
CS
C2
VCC
AINx–
CONTROL
LOGIC
SW3
C1
CAPACITIVE
DAC
23411-012
B
VREF
R1
D
D
SW2
C2
COMPARATOR
A SW1
A
R1
D
23411-014
AINx+
CONTROL
LOGIC
SW3
CS
CAPACITIVE
DAC
B
COMPARATOR
CS
23411-013
CIRCUIT INFORMATION
Figure 33. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
Figure 31. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 32), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected when the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
Rev. 0 | Page 14 of 30
Data Sheet
AD4682/AD4683
The conversion result is MSB first, twos complement. The LSB
size is VREF/2N, where N is the ADC resolution. The ADC
resolution is determined by the resolution of the device chosen,
and if resolution boost mode is enabled. Table 8 outlines the LSB
size expressed in µV for different resolutions and reference
voltage options.
011...111
011...110
011...101
100...010
100...001
100...000
–FSR
The ideal transfer characteristics for the AD4682 and the
AD4683 are shown in Figure 34.
–FSR + 1LSB
–FSR + 0.5LSB
+FSR – 1LSB
+FSR – 1.5LSB
ANALOG INPUT
23411-015
The AD4682 and the AD4683 can use a typical 2.5 V to 3.3 V VREF.
The AD4682 and the AD4683 convert the differential voltage of
the analog inputs (AINA+, AINA−, AINB+, and AINB−) into a
digital output.
ADC CODE (TWOS COMPLEMENT)
ADC TRANSFER FUNCTION
Figure 34. ADC Ideal Transfer Function (FSR = Full-Scale Range)
Table 8. LSB Size
Resolution (Bits)
16
18
Rev. 0 | Page 15 of 30
2.5 V Reference (µV)
38.1
9.5
3.3 V Reference (µV)
50.3
12.6
AD4682/AD4683
Data Sheet
APPLICATIONS INFORMATION
Figure 35 shows an example of the typical connection diagram
for the AD4682 and the AD4683. Decouple the VCC, VLOGIC,
REGCAP, and REFIO pins with suitable decoupling capacitors
as shown in Figure 35.
The exposed pad is a ground reference point for circuitry on
the devices and must be connected to the PCB ground.
Place a differential RC filter on the analog inputs to ensure
optimal performance is achieved.
The performance of the AD4682 and the AD4683 devices can be
impacted by noise on the digital interface. This impact is
dependent on the on-board layout and design. Keep a minimal
distance between the digital line to the digital interface, or place
a 100 Ω resistor in series and close to the SDOA pin and the
SDOB/ALERT pin to reduce noise from the digital interface
coupling of the AD4682 and the AD4683.
The two pseudo differential ADC channels of the AD4682 and
the AD4683 can accept an input voltage range from 0 V to VREF
on AINA+ and AINB+, and a VREF/2 voltage on AINA− and AINB−.
The AINA+, AINB+, AINA−, and AINB− analog input pins can be
driven with an amplifier. Table 9 lists the recommended driver
amplifiers that best fit and add value to the application. The
AD4682 and the AD4683 have a buffered internal 2.5 V reference
that is accessed via the REFIO pin. The buffered internal 2.5 V
reference must use an external buffer, like the ADA4807-2,
when connecting the reference to the external circuitry. The
AD4682 and the AD4683 have an option to use an ultralow
noise, high accuracy voltage reference as an external voltage
source ranging from 2.5 V to 3.3 V, such as the ADR4533 and
ADR4525.
POWER SUPPLY
The typical application circuit in Figure 35 can be powered by
a single 5 V voltage source (V+) that supplies the entire signal
chain. The 5 V supply can come from a low noise, CMOS low
dropout (LDO) regulator (ADP7105). The driver amplifier supply
is supplied by the +5 V (V+) and −2.5 V negative supply rail (V−),
which is derived from the inverter (ADM660). The inverter
converts the +5 V to −5 V and supplies the voltage to the
ADP7182 low noise voltage regulator to output the −2.5 V. The
two independent supplies of the AD4682 and the AD4683, VCC
and VLOGIC, that supply the analog circuitry and digital interface,
respectively, can be supplied by a low quiescent current LDO
regulator, such as the ADP166. The ADP166 is a suitable supply
with a fixed output voltage range from 1.2 V to 3.3 V for typical
VCC and VLOGIC levels. Decouple both the VCC supply and the
VLOGIC supply separately with a 1 µF capacitor. Additionally, an
internal LDO regulator supplies the AD4682 and the AD4683. The
on-chip regulator provides a 1.9 V supply for internal use on the
device only. Decouple the REGCAP pin with a 1 µF capacitor
connected to GND.
Power-Up
The AD4682 and the AD4683 are not easily damaged by power
supply sequencing. VCC and VLOGIC can be applied in any
sequence. Apply an external reference after VCC and VLOGIC are
applied.
The AD4682 and the AD4683 require a tPOWERUP time from
applying VCC and VLOGIC until the ADC conversion results are
stable. Applying CS pulses or interfacing with the AD4682 and
the AD4683 prior to the setup time elapsing does not have a
negative impact on ADC operation. Conversion results are not
guaranteed to meet data sheet specifications during this time,
however, and must be ignored.
Table 9. Signal Chain Components
Companion Parts
ADC Driver
Part Name
ADA4896-2
ADA4940-2
ADA4807-2
LTC6227
External Reference
ADR4525
ADR4533
ADP166
LDO
Description
1 nV/√Hz, rail-to-rail output amplifier
Ultra low power, full differential, low distortion
1 mA, rail-to-rail output amplifier
1 nV/√Hz, 420 MHz gain bandwidth product (GBW), railto-rail output amplifier
Ultralow noise, high accuracy 2.5 V voltage reference
Ultralow noise, high accuracy 3.3 V voltage reference
Very low quiescent, 150 mA, LDO regulator
Rev. 0 | Page 16 of 30
Typical Application
Precision, low noise, high frequency
Precision, low density, low power
Precision, low power, high frequency
Precision, low noise, high frequency
2.5 V reference voltage
3.3 V reference voltage
3.0 V to 3.6 V supply for VCC and VLOGIC
Data Sheet
AD4682/AD4683
V+ = 5V
V+
VCM = VREF /2
+
–
REF
+
–
V+
LDO
VREF = 2.5V TO 3.3V
10kΩ
LDO
3.0V TO 3.6V
INVERTER
1.65V TO 3.6V
10kΩ
LDO
1µF
1µF
V– = –2.5V
V+
VCC
REFIO
AINA+
–
+
R
C1
AINA+
AD4682/AD4683
V LOGIC
V–
VCM
SDI
EXPOSED
PAD
V+
VREF
VCM
0V
AINB–
–
+
1µF
AINA–
SDOA
SDOB/ALERT
SCLK
R
C1
DIGITAL HOST
(MICROPROCESSOR/
FIELD PROGRAMMABLE GATE ARRAY)
100Ω
CS
AINB+
AINB–
REGCAP
V–
REFCAP
VCM
100Ω
1µF
GND
0.1µF
Figure 35. Typical Application Circuit
Rev. 0 | Page 17 of 30
23411-135
VREF
VCM
0V
5V TO –5V
AD4682/AD4683
Data Sheet
MODES OF OPERATION
The AD4682 and the AD4683 have several on-chip configuration
registers for controlling the operational mode of the device.
Multifunction pin names may be referenced by their relevant
function only.
OVERSAMPLING
Oversampling is a common method used in analog electronics
to improve the accuracy of the ADC result. Multiple samples of
the analog input are captured and averaged to reduce the noise
component from the quantization noise and the thermal noise
(kTC) of the ADC. The AD4682 and the AD4683 offer an
oversampling function on chip, rolling average oversampling.
The rolling average oversampling functionality is enabled by
writing a 1 on the OS_MODE bit, Bit 9, and a valid nonzero
value on the OSR bits, Bits[8:6], in the CONFIGURATION1
register. Oversampling is disabled by writing a 0 on the
OS_MODE bit, Bit 9, and a zero value on the OSR bits, Bits[8:6], of
the CONFIGURATION1 register.
Rolling Average Oversampling
Rolling average oversampling mode can be used in applications
where higher output data rates are required and where higher
SNR or dynamic range is required. Rolling average oversampling
involves taking a number of samples, adding the samples
together, and dividing the result by the number of samples
taken. This result is then output from the AD4682 or the
AD4683. The sample data is not cleared after the process
completes. The rolling average oversampling mode uses a first
in, first out (FIFO) buffer of the most recent samples in the
averaging calculation, allowing the ADC throughput rate and
output data rate to stay the same.
Rolling average oversampling mode is enabled by setting the
OS_MODE bit to Logic 1 and having a valid nonzero value in
the OSR bits. The oversampling ratio of the digital filter is
controlled using the oversampling bits, OSR (see Table 10). The
output result is decimated to 16-bit resolution for the AD4682 and
the AD4683. If additional resolution is required, configure the
resolution boost bit in the CONFIGURATION1 register. See
the Resolution Boost section for further details.
In rolling average oversampling mode, all ADC conversions are
controlled and initiated by the falling edge of CS. After a
conversion is complete, the result is loaded into the FIFO. The
FIFO length is 8, regardless of the oversampling ratio set. The
FIFO is filled on the first conversion after a power-on reset, the
first conversion after a software controlled hard or soft reset, or
the first conversion after the REFSEL bit is toggled. A new
conversion result is shifted into the FIFO on completion of
every ADC conversion, regardless of the status of the OSR bits
and the OS_MODE bit. This conversion allows a seamless
transition from no oversampling to rolling average oversampling
or different rolling average oversampling ratios without waiting
for the FIFO to fill.
The number of samples, n, defined by the OSR bits are taken
from the FIFO, added together, and the result is divided by n.
The time between CS falling edges is the cycle time, which can
be controlled by the user, depending on the required data
output rate.
RESOLUTION BOOST
The default conversion result output data size for the AD4682 and
the AD4683 is 16 bits. When the on-chip oversampling function is
enabled, the performance of the ADC can exceed the 16-bit level.
To accommodate the performance boost achievable, it is possible
to enable an additional two bits of resolution. If the RES bit in
the CONFIGURATION1 register is set to Logic 1, and the
AD4682 and the AD4683 are in a valid oversampling mode, the
conversion result size for the AD4682 and the AD4683 is 18 bits.
In this mode, 18 SCLKs are required to propagate the data.
Table 10. AD4682 Rolling Average Oversampling Performance Overview
OSR, Bits[8:6]
000
001
010
011
Oversampling Ratio
Disabled
2
4
8
SNR (dB Typical)
VREF = 2.5 V
VREF = 3.3 V
RES = 0
RES = 1
RES = 0
RES = 1
85.7
85.7
87.3
87.3
87.6
87.9
88.8
89.3
90.1
90.9
91.3
92.4
92.6
94.0
93.4
95.4
Rev. 0 | Page 18 of 30
Output Data Rate (kSPS Maximum)
1000
1000
1000
1000
Data Sheet
AD4682/AD4683
VCC
tCYC
CS
S1
ACQ
ACQ
S3
ACQ
S4
ACQ
ENABLE OSR = 2
SDI
SDOA
SDOB
S2
1
2
3
4
5
6
7
8
FIFO
S1
S1
S1
S1
S1
S1
S1
S1
1
2
3
4
5
6
7
8
ACQ
S6
ACQ
S7
ACQ
ENABLE OSR = 4
S1
DON’T CARE
S5
FIFO
S2
S1
S1
S1
S1
S1
S1
S1
1
2
3
4
5
6
7
8
(f1 + f2)/2
(f1 + f2)/2
S2
FIFO
S3
S2
S1
S1
S1
S1
S1
S1
1
2
3
4
5
6
7
8
FIFO
S4
S3
S2
S1
S1
S1
S1
S1
1
2
3
4
5
6
7
8
FIFO
S5
S4
S3
S2
S1
S1
S1
S1
(f1 + f2 + f3 + f4)/4
(f1 + f2)/2
1
2
3
4
5
6
7
8
FIFO
S6
S5
S4
S3
S2
S1
S1
S1
1
2
3
4
5
6
7
8
FIFO
S7
S6
S5
S4
S3
S2
S1
S1
23411-018
INTERNAL
Figure 36. Rolling Average Oversampling Mode Configuration
tALERTS
tALERTC
CS
SDOA
INTERNAL
CONV
ACQ
CONV
ACQ
CONV
ACQ
ALERT
EXCEEDS THRESHOLD
CONV
ACQ
23411-019
NO OVERSAMPLING OR
ROLLING AVERAGE
OVERSAMPLING
Figure 37. Alert Operation
ALERT
The alert functionality is an out of range indicator and can be
used as an early indicator of an out of bounds conversion result.
An alert event triggers when the conversion result value register
exceeds the alert high limit value in the ALERT_HIGH_
THRESHOLD register or falls below the alert low limit value in
the ALERT_LOW_THRESHOLD register. The ALERT_HIGH_
THRESHOLD register and ALERT_LOW_THRESHOLD
register are common to all ADCs. When setting the threshold
limits, the alert high threshold must always be greater than the
alert low threshold. Detailed alert information is accessible in
the ALERT register.
The ALERT register contains two status bits per ADC, one
corresponding to the high limit, and the other to the low limit.
A logical OR of alert signals for all ADCs creates a common
alert value. This value can be configured to drive out on the
ALERT function of the SDOB/ALERT pin. The SDOB/ALERT pin
is configured as ALERT by configuring the following bits in the
CONFIGURATION1 and CONFIGURATION2 registers:
•
•
•
Set the SDO bit to 1.
Set the ALERT_EN bit to 1.
Set a valid value to the ALERT_HIGH_THRESHOLD
register and the ALERT_LOW_THRESHOLD register.
The alert indication function is available in rolling average
oversampling and nonoversampling modes.
The ALERT function of the SDOB/ALERT pin is updated at the
end of the conversion. The alert indication status bits in the
ALERT register are updated as well and must be read before the
end of the next conversion. The ALERT function of the
SDOB/ALERT pin is cleared with a falling edge of CS. Issuing a
software reset also clears the alert status in the ALERT register.
POWER MODES
The AD4682 and the AD4683 have two power modes, normal
and shutdown. These modes of operation provide flexible
power management options, allowing optimization of the
power dissipation and throughput rate ratio for different
application requirements.
Program the PMODE bit in the CONFIGURATION1 register
to configure the power modes in the AD4682 and the AD4683.
Set the PMODE bit to Logic 0 for normal mode and Logic 1 for
shutdown mode.
Normal Mode
Keep the AD4682 and the AD4683 in normal mode to achieve
the fastest throughput rate. All blocks within the AD4682 and
the AD4683 remain fully powered at all times, and an ADC
conversion can be initiated by a falling edge of CS, when required.
When the AD4682 and the AD4683 are not converting, the
devices are in static mode and power consumption is automatically
reduced. Additional current is required to perform a conversion.
Therefore, power consumption on the AD4682 and the AD4683
scales with throughput.
Rev. 0 | Page 19 of 30
AD4682/AD4683
Data Sheet
Shutdown Mode
bit is set to 0, the internal reference buffer is enabled. If the
REFSEL bit is set to 1, the internal reference buffer is disabled. If
an external reference is preferred, set the REFSEL bit to 1 and
supply an external reference to the REFIO pin.
When slower throughput rates and lower power consumption
are required, use shutdown mode by either powering down the
ADC between each conversion, or by performing a series of
conversions at a high throughput rate and then powering down
the ADC for a relatively long duration between these burst
conversions. When the AD4682 and the AD4683 are in shutdown
mode, all analog circuitry powers down, including the internal
reference, if enabled. The SPI remains active during shutdown
mode to allow the AD4682 and the AD4683 to exit shutdown
mode.
SOFTWARE RESET
The AD4682 and the AD4683 have two reset modes, a soft reset
and a hard reset. To initiate a reset, write to the reset bits,
Bits[7:0], in the CONFIGURATION2 register.
A soft reset maintains the contents of the configurable registers
but refreshes the interface and the ADC blocks. Any internal
state machines are reinitialized, and the oversampling block
and FIFO are flushed. The ALERT register is then cleared. The
reference and LDO regulator remain powered.
To enter shutdown mode, write to the PMODE bit in the
CONFIGURATION1 register. The AD4682 and the AD4683
shut down, and current consumption reduces.
A hard reset, in addition to the blocks reset by a soft reset, resets all
user registers to default status, resets the reference buffer, and
resets the internal oscillator block.
To exit shutdown mode and return to normal mode, set the
PMODE bit in the CONFIGURATION1 register to Logic 0. All
register configuration settings remain unchanged entering or
exiting shutdown mode. After exiting shutdown mode, allow
sufficient time for the circuitry to turn on before starting a
conversion. If the internal reference is enabled, allow the
reference to settle for accurate conversions to happen.
tRESET
SDI
23411-140
CS
SOFTWARE RESET
INTERNAL AND EXTERNAL REFERENCE
Figure 38. Software Reset Operation
DIAGNOSTIC SELF TEST
The AD4682 and the AD4683 have a buffered 2.5 V internal
reference primarily used as a reference voltage for device operation.
When using the buffered internal 2.5 V reference externally via
the REFIO pin, the reference must use an external buffer before
connecting to the external circuitry. Alternatively, if a more
accurate reference or higher dynamic range is required, an
external reference can be supplied. An externally supplied
reference voltage can range from 2.5 V to 3.3 V.
The AD4682 and the AD4683 run a diagnostic self test after a
power-on reset (POR) or after a software hard reset to ensure
the proper configuration is loaded into the device.
The result of the self test is displayed in the SETUP_F bit in the
ALERT register. If the SETUP_F bit is set to Logic 1, the diagnostic
self test fails. If the self test fails, perform a software hard reset
to reset the AD4682 and the AD4683 registers to the default status.
Reference selection, internal or external, is configured by the
REFSEL bit in the CONFIGURATION1 register. If the REFSEL
tSTARTUP
SDI
SHUTDOWN
NORMAL
SHUTDOWN MODE
NORMAL MODE
Figure 39. Shutdown Mode Operation
Rev. 0 | Page 20 of 30
ACCURATE CONVERSION
23411-020
CS
Data Sheet
AD4682/AD4683
INTERFACE
The interface to the AD4682 and the AD4683 is via an SPI. The
interface consists of the CS, SCLK, SDOA, SDOB/ALERT, and SDI
pins. Multifunction pin names may be referenced by their relevant
function only.
The CS signal frames a serial data transfer and initiates an ADC
conversion process. The falling edge of CS puts the track-andhold into hold mode, at which point the analog input is sampled,
and the bus is taken out of three-state.
The SCLK signal synchronizes data in and out of the devices via
the SDOA, SDOB, and SDI signals. A minimum of 16 SCLKs
are required for a write to or read from a register. The minimum
number of SCLKs for a conversion read is dependent on the
resolution of the devices and the configuration settings (see
Table 11).
The ADC conversion operation is driven internally by an
on-board oscillator and is independent of the SCLK signal.
The AD4682 and the AD4683 have two serial output signals,
SDOA and SDOB. To achieve the highest throughput of the
devices, use both SDOA and SDOB, 2-wire mode, to read
conversion results. If a reduced throughput is required or
oversampling is used, it is possible to use 1-wire mode, SDOA
signal only, for reading conversion results. Programming the
SDO bit in the CONFIGURATION2 register configures 2-wire
mode or 1-wire mode.
Configuring a cyclic redundancy check (CRC) operation for SPI
reads or SPI writes alters the operation of the interface. Consult
the relevant CRC Read, CRC Write, and CRC Polynomial
sections to ensure proper operation.
READING CONVERSION RESULTS
conversion results are available on the next SPI access. Take the
CS signal low, and the conversion result clocks out on the serial
output pins. The next conversion also initiates at this point.
The conversion result shifts out of the device as a 16-bit result
for the AD4682 and the AD4683. The MSB of the conversion
result shifts out on the CS falling edge. The remaining data
shifts out of the device under the control of the SCLK input.
The data shifts out on the rising edge of the SCLK, and the data
bits are valid on both the falling edge and the rising edge. After
the final SCLK falling edge, take CS high again to return the
SDOA and SDOB/ALERT pins to a high impedance state.
The number of SCLK cycles to propagate the conversion results
on the SDOA and SDOB/ALERT pins is dependent on the serial
mode of operation configured and if resolution boost mode is
enabled (see Figure 40 and Table 11 for details). If CRC reading
is enabled, this reading requires additional SCLK pulses to
propagate the CRC information (see the CRC section for more
details).
As the CS signal initiates a conversion and frames the data, any
data access must be completed within a single frame.
Table 11. Number of SCLK Cycles, n, Required for Reading
Conversion Results
Interface
Configuration
2-Wire
Resolution
Boost Mode
Disabled
Enabled
1-Wire
Disabled
The CS signal initiates the conversion process. A high to low
transition on the CS signal initiates a simultaneous conversion
of both ADCs, ADC A and ADC B. The AD4682 and the
AD4683 have a one-cycle readback latency. Therefore, the
Enabled
CS
SDOx
1CONSULT
1
2
3
n1
CONVERSION RESULTS
TABLE 11 FOR VALUES FOR n, THE NUMBER OF SCLK PULSES REQUIRED.
Figure 40. Reading Conversion Results
Rev. 0 | Page 21 of 30
23411-021
SCLK
CRC Read
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
SCLK Cycles
16
24
18
26
32
40
36
44
AD4682/AD4683
Data Sheet
propagate all of the data. The ADC A data is output first,
followed by the ADC B conversion results (see Figure 42).
Serial 2-Wire Mode
Configure 2-wire mode by setting the SDO bit in the
CONFIGURATION1 register to 0. In 2-wire mode, the conversion
result for ADC A is output on the SDOA pin, and the
conversion result for ADC B is output on the SDOB/ALERT pin
(see Figure 41).
LOW LATENCY READBACK
The interface on the AD4682 and the AD4683 has a one cycle
latency, as shown in Figure 43. For applications that operate at
lower throughput rates, the latency of reading the conversion
result can be reduced. When the conversion time elapses, a
second CS pulse after the initial CS pulse that initiates the
conversion can readback the conversion result. This operation
is shown in Figure 43.
Serial 1-Wire Mode
In applications where slower throughput rates are allowed, the
SPI can be configured to operate in 1-wire mode. In 1-wire mode,
the conversion results from ADC A and ADC B are output on
the serial output, SDOA. Additional SCLK cycles are required to
S0
S1
S2
S3
SDOA
DON’T CARE
ADC A S0
ADC A S1
SDOB
DON’T CARE
ADC B S0
ADC B S1
SDI
NOP
23411-022
CS
NOP
NOP
Figure 41. Reading Conversion Results: 2-Wire Mode
S1
S0
S2
S3
CS
DON’T CARE
SDI
ADC A S0
ADC B S0
ADC A S1
NOP
NOP
ADC B S1
23411-023
SDOA
NOP
Figure 42. Reading Conversion Results: 1-Wire Mode
CS
INTERNAL
SDOA
SDOB
CNVn
ACQ
DON'T CARE
RESULTn
CNVn + 1
DON'T CARE
ACQ
RESULTn + 1
TARGET SAMPLE PERIOD
Figure 43. Low Throughput Low Latency
Rev. 0 | Page 22 of 30
23411-024
SCLK
Data Sheet
AD4682/AD4683
READING FROM DEVICE REGISTERS
WRITING TO DEVICE REGISTERS
All of the registers in the AD4682 and the AD4683 can be read
over the SPI. To perform a register read, issue a register read
command followed by an additional SPI command that can be
either a valid command or a no operation (NOP) command.
The format for a read command is shown in Table 14. Set Bit D15
to 0 to select a read command. Bits[D14:D12] contain the
register address, and the subsequent 12 bits, Bits[D11:D0], are
ignored.
All of the read and write registers in the AD4682 and the
AD4683 can be written to over the SPI. The length of an SPI
write access is determined by the CRC write function. An SPI
access is 16 bits if CRC write is disabled and 24 bits when CRC
write is enabled. The format for a write command is shown in
Table 14. Set Bit D15 to 1 to select a write command.
Bits[D14:D12] contain the register address, and the subsequent
12 bits, Bits[D11:D0], contain the data to be written to the
selected register.
S0
S1
S2
S3
S4
CS
NOP
READ REG 1
READ REG 2
SDOA
INVALID
RESULT S0
REG 1DATA
SDOB
INVALID
RESULT S0
NOP
NOP
REG 2DATA
RESULT S3
23411-025
SDI
RESULT S3
Figure 44. Register Read
S0
S1
S2
S3
SDI
SDOA
SDOB
NOP
WRITE REG 1
WRITE REG 2
NOP
INVALID
RESULT S0
RESULT S1
RESULT S2
Figure 45. Register Write
Rev. 0 | Page 23 of 30
23411-026
CS
AD4682/AD4683
Data Sheet
CRC
CRC Polynomial
The AD4682 and the AD4683 have CRC checksum modes that
can improve interface robustness by detecting errors in data
transmissions. The CRC feature is independently selectable for
SPI reads and SPI writes. For example, the CRC function for
SPI writes can be enabled to prevent unexpected changes to the
device configuration but disabled on SPI reads, therefore
maintaining a higher throughput rate. The CRC feature is
controlled by the programming of the CRC_W bit and CRC_R
bits in the CONFIGURATION1 register.
For CRC checksum calculations, the following polynomial is
always used: x8+ x2 + x + 1.
CRC Read
If enabled, a CRC is appended to the conversion result or register
reads and consists of an 8-bit word. The CRC is calculated in
the conversion result for ADC A and ADC B and is output on
SDOA. A CRC is also calculated and appended to register read
outputs.
The CRC read function can be used in 2-wire SPI mode, 1-wire
SPI mode, and resolution boost mode.
CRC Write
To enable the CRC write function, set the CRC_W bit in the
CONFIGURATION1 register to 1. To set the CRC_W bit to 1
to enable the CRC feature, ensure the request frame has a valid
CRC appended to the frame.
After the CRC feature is enabled, all register write requests are
ignored unless the requests are accompanied by a valid CRC
command, requiring a valid CRC to both enable and disable the
CRC write feature.
The following is an example of how to generate the checksum
on a conversion read. The 16-bit data conversion result of the
two channels is combined to produce 32-bit data. The 8 MSBs
of the 32-bit data are inverted and then left shifted by eight bits
to create a number ending in eight logic zeros. The polynomial
is aligned such that its MSB is adjacent to the leftmost Logic 1
of the data. An exclusive OR (XOR) function is applied to the
data to produce a new, shorter number. The polynomial is again
aligned such that its MSB is adjacent to the leftmost Logic 1 of
the new result, and the procedure is repeated. This process repeats
until the original data is reduced to a value less than the
polynomial, which is the 8-bit checksum. For example, this
polynomial is 100000111.
Let the original data of two channels be 0xAAAA and 0x5555,
that is, 1010 1010 1010 1010 and 0101 0101 0101 0101. The data
of the two channels is then appended, including eight zeros on
the right. The data then becomes 1010 1010 1010 1010 0101
0101 0101 0101 0000 0000.
Table 12 shows the CRC calculation of 16-bit two-channel data.
In the final XOR operation, the reduced data is less than the
polynomial. Therefore, the remainder is the CRC for the
assumed data.
Rev. 0 | Page 24 of 30
Data Sheet
AD4682/AD4683
Table 12. Example CRC Calculation for 16-Bit Two-Channel Data
Data
1 0 1 0 1
Process Data 0 1 0 1 0
1 0 0 0
1 0
1 0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X1 X1 X1 X1 X1 X1 X1 X1
1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0
1
1
0
0
0
1
1 1 0
1 1 1
1 1 0
1 0 0
1 0
1 0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
1
0
1
1
1
0
0
CRC
X = don’t care
1
16 + 16 + 8 = 40 BITS
SDOA
CRC A,B
RESULT_A
2-WIRE 16-BIT
SDOB
RESULT_B
16 + 16 + 8 = 40 BITS
1-WIRE 16-BIT
SDOA
RESULT_B
RESULT_A
CRC A,B
18 + 8 = 26 BITS
SDOA
RESULT_A
SDOB
RESULT_B
SDOA
RESULT_A
CRC A,B
2-WIRE 18-BIT
18 + 18 + 8 = 44 BITS
1-WIRE 18-BIT
RESULT_B
CRC A,B
16 + 8 = 24 BITS
REGISTER
READ RESULT
SDOA
REGISTER X
CRC REG X
16 + 8 = 24 BITS
REGISTER
READ REQUEST
SDI
REGISTER X
CRC REG X
SDI
WRITE REGISTER X
CRC REG X
Figure 46. CRC Operation
Rev. 0 | Page 25 of 30
23411-027
16 + 8 = 24 BITS
REGISTER
WRITE
1
1
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
1
1
0
1
1
0
0
AD4682/AD4683
Data Sheet
REGISTERS
The AD4682 and the AD4683 have user programmable on-chip registers for configuring the device.
Table 13 shows a complete overview of the registers available on the AD4682 and the AD4683. The registers are either read and write
(R/W) or read only (R). Any read request to a write only register is ignored, and any write request to a read only register is ignored.
Writes to any other register address are considered an NOP and are ignored. Any read request to a register address, other than those
listed in Table 13, is considered an NOP, and the data transmitted in the next SPI frame are the conversion results.
Table 13. Register Summary
Address
0x1
Register Name
CONFIGURATION1
Bits
[15:8]
[7:0]
0x2
CONFIGURATION2
[15:8]
[7:0]
0x3
Bit 15
Bit 7
OSR[1:0]
0x5
ALERT_LOW_THRESHOLD
ALERT_HIGH_THRESHOLD
Bit 12
Bit 4
Bit 11
Bit 10
Bit 3
Bit 2
RESERVED
ALERT_EN
RES
CRC_R
Bit 9
Bit 1
OS_MODE
REFSEL
Bit 8
Bit 0
OSR[2]
PMODE
Reset
0x0000
R/W
R/W
SDO
0x0000
R/W
0x0000
R
ALERT_LOW[11:8]
0x0800
R/W
ALERT_HIGH[11:8]
0x07FF
R/W
RESERVED
RESET
[15:8]
ALERT
Bit 13
Bit 5
ADDRESSING
CRC_W
ADDRESSING
ADDRESSING
[7:0]
0x4
Bit 14
Bit 6
RESERVED
AL_B_HIGH
[15:8]
[7:0]
ADDRESSING
[15:8]
[7:0]
ADDRESSING
AL_B_LOW
RESERVED
CRCW_F
SETUP_F
RESERVED
AL_A_HIGH
AL_A_LOW
ALERT_LOW[7:0]
ALERT_HIGH[7:0]
ADDRESSING REGISTERS
A serial register transfer on the AD4682 and the AD4683 consists of 16 SCLK cycles. The 4 MSBs written to the AD4682 and the AD4683
are decoded to determine which register is addressed. The 4 MSBs consist of the register address (REGADDR), Bits[D14:D12], and the
read and write bit (WR), Bit D15. The register address bits determine which on-chip register is selected. The WR bit determines if the
remaining 12 bits of data on the SDI input are loaded into the addressed register, if the addressed register is a valid write register. If the WR bit
is 1, the bits load into the register addressed by the register select bits. If the WR bit is 0, the command is seen as a read request. The addressed
register data is available to be read during the next read operation.
Table 14. Addressing Register Format
MSB
D15
WR
D14
D13
D12
REGADDR
D11
D10
D9
D8
D7
D6
D5
DATA
D4
D3
D2
D1
LSB
D0
Table 15. Bit Descriptions for Addressing Registers
Bit
D15
Mnemonic
WR
D14 to D12
REGADDR
D11 to D0
DATA
Description
If a 1 is written to the WR bit, Bits[D11:D0] of this register are written to the register specified by REGADDR, if
the register is a valid address. Alternatively, if a 0 is written, the next data sent out on the SDOA pin is a read
from the designated register, if the register is a valid address.
When WR = 1, the contents of REGADDR determine the register for selection as outlined in Table 13.
When WR = 0 and REGADDR contains a valid register address, the contents on the requested register are
output on the SDOA pin during the next interface access.
When WR = 0 and REGADDR contains 0x0, 0x6, or 0x7, the contents on the SDI line are ignored. The next
interface access results in the conversion results being read back.
The data bits are written into the corresponding register specified by the REGADDR data bits when WR is
equal to 1 and the REGADDR data bits contain a valid address.
Rev. 0 | Page 26 of 30
Data Sheet
AD4682/AD4683
CONFIGURATION1 REGISTER
Address: 0x1, Reset: 0x0000, Name: CONFIGURATION1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:12] ADDRESSING (R/W)
Addressing.
[0] PMODE (R/W)
Shutdown Mode.
[11:10] RESERVED
[1] REFSEL (R/W)
Reference Select.
[9] OS_MODE (R/W)
Oversampling Mode.
[2] RES (R/W)
Resolution.
[8:6] OSR (R/W)
Oversampling Ratio.
[3] ALERT_EN (R/W)
Enable Alert Indicator Function.
[5] CRC_W (R/W)
CRC Write.
[4] CRC_R (R/W)
CRC Read.
Table 16. Bit Descriptions for CONFIGURATION1
Bits
[15:12]
Bit Name
ADDRESSING
[11:10]
9
RESERVED
OS_MODE
[8:6]
OSR
5
CRC_W
4
CRC_R
3
ALERT_EN
2
RES
1
REFSEL
0
PMODE
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers
section for further details.
Reserved.
Oversampling Mode. Enables the rolling average oversampling mode of the ADC.
0: disable.
1: enable.
Oversampling Ratio. Sets the oversampling ratio for all the ADCs in rolling average oversampling
mode. Rolling average oversampling mode supports oversampling ratios of ×2, ×4, and ×8.
000: disabled.
001: ×2.
010: ×4.
011: ×8.
100: disabled.
101: disabled.
110: disabled.
111: disabled.
CRC Write. Controls the CRC functionality for the SDI interface. When setting the CRC_W bit
from a 0 to a 1, follow the command with a valid CRC to set this configuration bit. If a valid
CRC is not received, the entire frame is ignored. If the CRC_W bit is set to 1, the bit requires a
CRC to clear it to 0.
0: no CRC function.
1: CRC function.
CRC Read. Controls the CRC functionality for the SDOA and SDOB/ALERT interface.
0: no CRC function.
1: CRC function.
Enable Alert Indicator Function. This alert function is enabled when the SDO bit = 1.
Otherwise, the ALERT_EN bit is ignored.
0: SDOB.
1: ALERT.
Resolution. Sets the size of the conversion result data. If OSR = 0, the RES bit is ignored, and
the resolution is set to default resolution.
0: normal resolution.
1: 2-bit higher resolution.
Reference Select. Selects the ADC reference source.
0: selects internal reference.
1: selects external reference.
Shutdown Mode. Sets the power modes.
0: normal mode.
1: shutdown mode.
Rev. 0 | Page 27 of 30
Reset
0x0
Access
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
AD4682/AD4683
Data Sheet
CONFIGURATION2 REGISTER
Address: 0x2, Reset: 0x0000, Name: CONFIGURATION2
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:12] ADDRESSING (R/W)
Addressing
[7:0] RESET (R/W)
Reset
[11:9] RESERVED
[8] SDO (R/W)
SDO
Table 17. Bit Descriptions for CONFIGURATION2
Bits
[15:12]
Bit Name
ADDRESSING
[11:9]
8
RESERVED
SDO
[7:0]
RESET
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers
section for further details.
Reserved.
SDO. Conversion results in the serial data output.
0: 2-wire. Conversion data are output on both the SDOA and SDOB/ALERT pins.
1: 1-wire. Conversion data are output on the SDOA pin only.
Reset.
0x3C performs a soft reset that resets some blocks. Register contents remain unchanged.
Clears the ALERT register and flushes any oversampling stored variables or any active state
machines.
0xFF performs a hard reset that resets all possible blocks in the AD4682 or the AD4683.
Register contents are set to defaults. All other values are ignored.
Reset
0x0
Access
R/W
0x0
0x0
R
R/W
0x0
R/W
Reset
0x0
Access
R
0x0
0x0
R
R
0x0
R
0x0
R
ALERT REGISTER
Address: 0x3, Reset: 0x0000, Name: ALERT
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:12] ADDRESSING (R)
Addressing
[0] AL_A_LOW (R)
Alert A Low
[11:10] RESERVED
[1] AL_A_HIGH (R)
Alert A High
[9] CRCW_F (R)
CRC Error
[3:2] RESERVED
[8] SETUP_F (R)
Load Error
[4] AL_B_LOW (R)
Alert B Low
[7:6] RESERVED
[5] AL_B_HIGH (R)
Alert B High
Table 18. Bit Descriptions for ALERT
Bits
[15:12]
Bit Name
ADDRESSING
[11:10]
9
RESERVED
CRCW_F
8
SETUP_F
[7:6]
RESERVED
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers
section for further details.
Reserved.
CRC Error. Indicates that a register write command failed due to a CRC error. This fault bit is
sticky and remains set until the register is read.
0: no CRC error.
1: CRC error.
Load Error. The SETUP_F bit indicates that the device configuration data did not load
properly on startup. The SETUP_F bit does not clear on an ALERT register read. A hard reset
via the CONFIGURATION2 register is required to clear the SETUP_F bit and restart the device
setup again.
0: no setup error.
1: setup error.
Reserved.
Rev. 0 | Page 28 of 30
Data Sheet
Bits
5
Bit Name
AL_B_HIGH
4
AL_B_LOW
[3:2]
1
RESERVED
AL_A_HIGH
0
AL_A_LOW
AD4682/AD4683
Description
Alert B High. The alert indication high bits indicate if a conversion result for the respective
input channel exceeds the value set in the ALERT_HIGH_THRESHOLD register. This fault bit is
sticky and remains set until the register is read.
1: alert indication.
0: no alert indication.
Alert B Low. The alert indication low bits indicate if a conversion result for the respective
input channel exceeds the value set in the ALERT_LOW_THRESHOLD register. This fault bit is
sticky and remains set until the register is read.
1: alert indication.
0: no alert indication.
Reserved.
Alert A High. The alert indication high bits indicate if a conversion result for the respective
input channel exceeds the value set in the ALERT_HIGH_THRESHOLD register. This fault bit is
sticky and remains set until the register is read.
0: no alert indication.
1: alert indication.
Alert A Low. The alert indication low bits indicate if a conversion result for the respective
input channel exceeds the value set in the ALERT_LOW_THRESHOLD register. This fault bit is
sticky and remains set until the register is read.
1: alert indication.
0: no alert indication.
Reset
0x0
Access
R
0x0
R
0x0
0x0
R
R
0x0
R
Reset
0x0
Access
R/W
0x800
R/W
Reset
0x0
Access
R/W
0x7FF
R/W
ALERT_LOW_THRESHOLD REGISTER
Address: 0x4, Reset: 0x0800, Name: ALERT_LOW_THRESHOLD
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[15:12] ADDRESSING (R/W)
Addressing
[11:0] ALERT_LOW (R/W)
Alert Low
Table 19. Bit Descriptions for ALERT_LOW_THRESHOLD
Bits
[15:12]
Bit Name
ADDRESSING
[11:0]
ALERT_LOW
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers
section for further details.
Alert Low. Bits[D11:D0] from ALERT_LOW move to the MSBs of the internal alert low register,
Bits[D15:D4]. The remaining bits, Bits[D3:D0], are fixed at 0x0, which sets an alert when the
converter result is below ALERT_LOW_THRESHOLD and disables when the converter result is
above ALERT_LOW_THRESHOLD.
ALERT_HIGH_THRESHOLD REGISTER
Address: 0x5, Reset: 0x07FF, Name: ALERT_HIGH_THRESHOLD
15 14 13 12
11 10
9
8
7
6
5
4
3
2
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
[15:12] ADDRESSING (R/W)
Addressing
[11:0] ALERT_HIGH (R/W)
Alert High
Table 20. Bit Descriptions for ALERT_HIGH_THRESHOLD
Bits
[15:12]
Bit Name
ADDRESSING
[11:0]
ALERT_HIGH
Description
Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers
section for further details.
Alert High. Bits[D11:D0] from ALERT_HIGH move to the MSBs of the internal alert high
register, Bits[D15:D4]. The remaining bits, Bits[D3:D0], are fixed at 0xF, which sets an alert
when the converter result is above ALERT_HIGH_THRESHOLD and disables when the
converter result is below ALERT_HIGH_THRESHOLD.
Rev. 0 | Page 29 of 30
AD4682/AD4683
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
16
13
12
1
0.50
BSC
EXPOSED
ED
PAD
1.10 SQ
1.00
9
0.45
0.40
0.35
TOP VIEW
0.80
0.75
0.70
PKG-005000
4
5
8
0.55 REF
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.15 REF
SEATING
PLANE
0.45
*1.20
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WEED-4
WITH EXCEPTION TO THE EXPOSED PAD
08-29-2018-A
PIN 1
INDICATOR
AREA
3.10
3.00 SQ
2.90
Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-45)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
AD4682BCPZ-RL
AD4682BCPZ-RL7
AD4683BCPZ-RL
AD4683BCPZ-RL7
EVAL-AD7383FMCZ
1
2
Resolution
16-Bit
16-Bit
16-Bit
16-Bit
Throughput
Rate
1 MSPS
1 MSPS
500 kSPS
500 kSPS
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Z = RoHS Compliant Part.
Use the EVAL-AD7383FMCZ to evaluate the AD4682 and the AD4683.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D23411-10/20(0)
Rev. 0 | Page 30 of 30
Package Description
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
AD7383 Evaluation Board
Package
Option
CP-16-45
CP-16-45
CP-16-45
CP-16-45
Marking Code
CAN
CAN
CAP
CAP
工商网监
湘ICP备2023018690号
