Data Sheet
AD5291/AD5292
256-/1024-Position, Digital Potentiometers with Maximum ±1% R-Tolerance Error
and 20-TP Memory
►
►
►
►
►
►
►
►
►
►
►
FUNCTIONAL BLOCK DIAGRAM
Single-channel, 256-/1024-position resolution
20 kΩ, 50 kΩ, and 100 kΩ nominal resistance
Maximum ±1% nominal resistor tolerance error (resistor performance mode)
20-times programmable wiper memory
Rheostat mode temperature coefficient: 35 ppm/°C
Voltage divider temperature coefficient: 5 ppm/°C
+9 V to +33 V single-supply operation
±9 V to ±16.5 V dual-supply operation
SPI-compatible serial interface
Wiper setting readback
Power-on refreshed from 20-TP memory
APPLICATIONS
►
►
►
►
►
►
►
Mechanical potentiometer replacement
Instrumentation: gain and offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, and time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration
VDD
RESET
POWER-ON
RESET
AD5291/
AD5292
VLOGIC
RDAC
REGISTER
SCLK
SYNC
DATA
SERIAL
INTERFACE
A
W
OTP
MEMORY
BLOCK
DIN
B
SDO
RDY
VSS
EXT_CAP
GND
07674-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
The AD5291/AD5292 are single-channel, 256-/1024-position digital
potentiometers that combine industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package.
These devices are capable of operating across a wide voltage
range, supporting both dual supply operation at ±10.5 V to ±16.5 V
and single supply operation at +21 V to +33 V, while ensuring less
than 1% end-to-end resistor tolerance error and offering 20-time
programmable (20-TP) memory.
The guaranteed industry leading low resistor tolerance error feature
simplifies open-loop applications as well as precision calibration
and tolerance matching applications.
The AD5291/AD5292 device wiper settings are controllable through
the SPI digital interface. Unlimited adjustments are allowed before
programming the resistance value into the 20-TP memory. The
AD5291/AD5292 do not require any external voltage supply to
facilitate fuse blow, and there are 20 opportunities for permanent
programming. During 20-TP activation, a permanent blow fuse
command freezes the wiper position (analogous to placing epoxy
on a mechanical trimmer).
The AD5291/AD5292 are available in a compact 14-lead TSSOP
package. The part is guaranteed to operate over the extended
industrial temperature range of −40°C to +105°C. In this data sheet,
the digital potentiometer and RDAC terms are used interchangeably.
Rev. G
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
AD5291/AD5292
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................1
Specifications........................................................ 3
Electrical Characteristics—AD5291................... 3
Electrical Characteristics—AD5292................... 6
Interface Timing Specifications.......................... 9
Absolute Maximum Ratings ................................ 11
Thermal Resistance..........................................11
ESD Caution.....................................................11
Pin Configuration and Function Descriptions...... 12
Typical Performance Characteristics................... 13
Test Circuits......................................................... 22
Theory of Operation.............................................23
Serial Data Interface.........................................23
Shift Register....................................................23
RDAC Register.................................................25
20-TP Memory..................................................25
Write Protection................................................26
Basic Operation................................................26
20-TP Readback and Spare Memory Status ...26
Shutdown Mode............................................... 27
Resistor Performance Mode.............................27
Reset................................................................ 27
SDO Pin and Daisy-Chain Operation............... 27
RDAC Architecture........................................... 28
Programming the Variable Resistor..................28
Programming the Potentiometer Divider.......... 28
EXT_CAP Capacitor.........................................29
Terminal Voltage Operating Range.................. 29
Applications Information...................................... 30
High Voltage DAC............................................ 30
Programmable Voltage Source with Boosted
Output.............................................................30
High Accuracy DAC..........................................30
Variable Gain Instrumentation Amplifier........... 30
Audio Volume Control.......................................30
Outline Dimensions............................................. 32
Ordering Guide.................................................32
RAB (kΩ) and Resolution Options.....................32
Evaluation Boards............................................ 33
REVISION HISTORY
1/2022—Rev. F to Rev. G
Changes to OTP Store Current Parameter and OTP Read Current Parameter, Table 1.................................3
Changed Electrical Characteristics—AD5291 Section to Electrical Characteristics—AD5292 Section.......... 6
Changes to OTP Store Current Parameter, OTP Read Current Parameter, and Bandwidth Parameter,
Table 4........................................................................................................................................................... 6
Changed Timing Diagrams Section to Shift Register and Timing Diagrams Section.......................................9
Moved Figure 2................................................................................................................................................ 9
Moved Table 11, Table 12, and Table 13........................................................................................................23
Moved Table 14 and Table 15........................................................................................................................ 25
Moved Table 16..............................................................................................................................................26
Moved Table 17..............................................................................................................................................27
Change to Rheostat Operation—1% Resistor Tolerance Section..................................................................28
analog.com
Rev. G | 2 of 33
Data Sheet
AD5291/AD5292
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5291
VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS, −40°C < TA <
+105°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance (R-Perf Mode)3
Nominal Resistor Tolerance (Normal Mode)
Resistance Temperature Coefficient4
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Resolution
Differential Nonlinearity5
Integral Nonlinearity5
Voltage Divider Temperature Coefficient4
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Terminal Voltage Range6
Capacitance A, Capacitance B4
Capacitance W4
Common-Mode Leakage Current4
DIGITAL INPUTS
Input Logic High4
Input Logic Low4
Input Current
Input Capacitance4
DIGITAL OUTPUTS (SDO and RDY)
Output High Voltage4
Output Low Voltage4
Three-State Leakage Current
Output Capacitance4
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Logic Supply Range
Logic Supply Current
OTP Store Current4, 7
OTP Read Current4, 8
Power Dissipation9
Power Supply Rejection Ratio
analog.com
Symbol
N
R-DNL
R-INL
∆RAB/RAB
∆RAB/RAB
(∆RAB/RAB)/∆T × 106
RW
N
DNL
INL
(∆VW/VW)/∆T × 106
VWFSE
VWZSE
VA, VB, VW
CA, CB
CW
ICM
VIH
VIL
IIL
CIL
VOH
VOL
Conditions
RWB, VA = NC
See Table 2, Table 3
Min
8
−1
−1
−1
Code = full scale; See Figure 38
Code= zero scale
Typ1
±0.5
±7
35
60
8
−0.5
−0.5
Code = half scale; See Figure 41
Code = full scale
Code = zero scale
Unit
Bits
LSB
LSB
%
%
ppm/°C
Ω
+1
+1
+1
100
Bits
LSB
LSB
ppm/°C
LSB
LSB
+0.5
+0.5
1.5
−2
0
+0.25
2
f = 1 MHz, measured to GND, code =
half scale
VSS
85
V
pF
f = 1 MHz, measured to GND, code =
half scale
VA = VB = VW
JEDEC compliant
VLOGIC = 2.7 V to 5.5 V
VLOGIC = 2.7 V to 5.5 V
VIN = 0 V or VLOGIC
65
pF
±1
nA
VDD
2.0
0.8
±1
V
V
µA
pF
GND + 0.4 V
+1
V
V
µA
pF
5
RPULL_UP = 2.2 kΩ to VLOGIC
RPULL_UP = 2.2 kΩ to VLOGIC
VLOGIC − 0.4
−1
COL
VDD
VDD/VSS
IDD
ISS
VLOGIC
ILOGIC
IDD_PROG
IDD_FUSE_READ
PDISS
PSRR
Max
5
VSS = 0 V
VDD/VSS = ±16.5 V
VDD/VSS = ±16.5 V
VLOGIC = 5 V; VIH = 5 V or VIL = GND
VIH = 5 V or VIL = GND
VIH = 5 V or VIL = GND
VIH = 5 V or VIL = GND
∆VDD/∆VSS = ±15 V ± 10%
9
±9
−2
2.7
0.1
−0.1
1
25
25
8
33
±16.5
2
5.5
10
110
V
V
µA
µA
V
µA
mA
mA
µW
%/%
Rev. G | 3 of 33
Data Sheet
AD5291/AD5292
SPECIFICATIONS
Table 1.
Parameter
Symbol
Conditions
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
DYNAMIC CHARACTERISTICS5, 10
Bandwidth
Total Harmonic Distortion
VW Settling Time
Resistor Noise Density
BW
THDW
tS
eN_WB
−3 dB, code = half scale
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
VA = 30 V, VB = 0 V, ±0.5 LSB error
band, initial code = zero scale, board
capacitance = 170 pF
Code = full scale, normal mode
Code = full scale, R-Perf mode
Code = half scale, normal mode
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Code = half scale, R-Perf mode
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C, 0 kHz to
200 kHz
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Min
Typ1
Max
Unit
0.103
0.039
0.021
kHz
520
210
105
dB
−93
−101
−106
750
2.5
ns
µs
µs
2.5
7
14
µs
5
9
16
nV/√Hz
10
18
27
1
Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
2
Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at code 0x02 to code 0xFF or between RWA at code 0xFD to code
0x00. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with a wiper
current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.
3
Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably.
4
Guaranteed by design and characterization, not subject to production test.
5
INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables
ground-referenced bipolar signal adjustment.
7
Different from operating current; supply current for fuse program lasts approximately 550 µs.
8
Different from operating current; supply current for fuse read lasts approximately 550 µs.
9
PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
10
All dynamic characteristics use VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
analog.com
Rev. G | 4 of 33
Data Sheet
AD5291/AD5292
SPECIFICATIONS
Resistor Performance Mode Code Range
Table 2.
RAB = 20 kΩ
Resistor Tolerance
per Code
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
|VDD − VSS| = 30 V to 33 V
|VDD − VSS| = 26 V to 30 V
|VDD − VSS| = 22 V to 26 V
|VDD − VSS| = 21 V to 22 V
RWB
RWA
RWB
RWA
RWB
RWA
RWB
RWA
From 0x5A to
0xFF
From 0x23 to
0xFF
From 0x1E to
0xFF
From 0x00 to
0xA5
From 0x00 to
0xDC
From 0x00 to
0xE1
From 0x7D to
0xFF
From 0x2D to
0xFF
From 0x19 to
0xFF
From 0x00 to
0x82
From 0x00 to
0xD2
From 0x00 to
0xE6
From 0x7D to
0xFF
From 0x23 to
0xFF
From 0x17 to
0xFF
From 0x00 to
0x82
From 0x00 to
0xDC
From 0x00 to
0xE8
N/A
N/A
From 0x23 to
0xFF
From 0x17 to
0xFF
From 0x00 to
0xDC
From 0x00 to
0xE8
Table 3.
RAB = 50 kΩ
Resistor Tolerance per
Code
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
analog.com
|VDD − VSS| = 26 V to 33 V
RAB = 100 kΩ
|VDD − VSS| = 21 V to 26 V
|VDD − VSS| = 26 V to 33 V
|VDD − VSS| = 21 V to 26 V
RWB
RWA
RWB
RWA
RWB
RWA
RWB
RWA
From 0x2A to
0xFF
From 0x11 to
0xFF
From 0x0A to
0xFF
From 0x00 to
0xD5
From 0x00 to
0xEE
From 0x00 to
0xF5
From 0x37 to
0xFF
From 0x16 to
0xFF
From 0x0D to
0xFF
From 0x00 to
0xC8
From 0x00 to
0xE9
From 0x00 to
0xF2
From 0x1E to
0xFF
From 0x0A to
0xFF
From 0x07 to
0xFF
From 0x00 to
0xE1
From 0x00 to
0xF5
From 0x00 to
0xF8
From 0x14 to
0xFF
From 0x0A to
0xFF
From 0x07 to
0xFF
From 0x00 to
0xEB
From 0x00 to
0xF5
From 0x00 to
0xF8
Rev. G | 5 of 33
Data Sheet
AD5291/AD5292
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5292
VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS, −40°C < TA <
+105°C, unless otherwise noted.
Table 4.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance (R-Perf Mode)3
Nominal Resistor Tolerance (Normal Mode)4
Resistance Temperature Coefficient
Wiper Resistance
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE
Resolution
Differential Nonlinearity5
Integral Nonlinearity5
Voltage Divider Temperature Coefficient4
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Terminal Voltage Range4
Capacitance A, Capacitance B6
Capacitance W5
Common-Mode Leakage Current4
DIGITAL INPUTS
Input Logic High4
Input Logic Low4
Input Current
Input Capacitance4
DIGITAL OUTPUTS (SDO and RDY)
Output High Voltage4
Output Low Voltage4
Three-State Leakage Current
Output Capacitance4
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
Logic Supply Range
Logic Supply Current
OTP Store Current6, 7
OTP Read Current6, 8
Power Dissipation9
analog.com
Symbol
N
R-DNL
R-INL
R-INL
R-INL
∆RAB/RAB
∆RAB/RAB
(∆RAB/RAB)/∆T × 106
RW
N
DNL
INL
(∆VW/VW)/∆T × 106
VWFSE
VWZSE
VA, VB, VW
CA, CB
CW
ICM
VIH
VIL
IIL
CIL
VOH
VOL
Conditions
Min
RWB, VA = NC
RAB =50 kΩ, 100 kΩ
RAB =20 kΩ , |VDD − VSS| = 26 V to 33 V
RAB =20 kΩ , |VDD − VSS| = 21 V to 26 V
See Table 5 and Table 6
10
−1
−2
−2
−3
−1
Code = full scale; See Figure 38
Code= zero scale
Typ1
±0.5
±7
35
60
10
−1
−1.5
Code = half scale; See Figure 41
Code = full scale
Code = zero scale
100
85
VDD
V
pF
65
pF
±1
nA
0.8
±1
5
V
V
µA
pF
GND + 0.4
+1
V
V
µA
pF
VLOGIC − 0.4
5
VDD/VSS = ±16.5 V
VDD/VSS = ±16.5 V
VLOGIC = 5 V; VIH = 5 V or VIL = GND
VIH = 5 V or VIL = GND
VIH = 5 V or VIL = GND
VIH = 5 V or VIL = GND
Bits
LSB
LSB
ppm/°C
LSB
LSB
+1
8
−1
VSS = 0 V
Bits
LSB
LSB
LSB
LSB
%
%
ppm/°C
Ω
+1
+2
+2
+3
+1
5
COL
VDD
VDD/VSS
IDD
ISS
VLOGIC
ILOGIC
IDD_PROG
IDD_FUSE_READ
PDISS
Unit
+1
+1.5
−8
0
VSS
f = 1 MHz, measured to GND, code = half
scale
f = 1 MHz, measured to GND, code = half
scale
VA = VB = VW
JEDEC compliant
VLOGIC = 2.7 V to 5.5 V
2.0
VLOGIC = 2.7 V to 5.5 V
VIN = 0 V or VLOGIC
RPULL_UP = 2.2 kΩ to VLOGIC
RPULL_UP = 2.2 kΩ to VLOGIC
Max
9
±9
−2
2.7
0.1
−0.1
1
25
25
8
33
±16.5
2
5.5
10
110
V
V
µA
µA
V
µA
mA
mA
µW
Rev. G | 6 of 33
Data Sheet
AD5291/AD5292
SPECIFICATIONS
Table 4.
Parameter
Power Supply Rejection Ratio6
DYNAMIC CHARACTERISTICS5, 10
Bandwidth
Total Harmonic Distortion
VW Settling Time
Resistor Noise Density
Symbol
Conditions
PSSR
∆VDD/∆VSS = ±15 V ± 10%
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
BW
THDW
tS
eN_WB
−3 dB, code = half scale
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
VA = 30 V, VB = 0 V, ±0.5 LSB error
band, initial code = zero scale, board
capacitance = 170 pF
Code = full scale, normal mode
Code = full scale, R-Perf mode
Code = half scale, normal mode
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Code = half scale, R-Perf mode
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C, 0 kHz to
200 kHz
RAB = 20 kΩ
RAB = 50 kΩ
RAB = 100 kΩ
Min
Typ1
Max
Unit
%/%
0.103
0.039
0.021
kHz
520
210
105
dB
−93
−101
−106
750
2.5
ns
µs
µs
2.5
7
14
µs
5
9
16
nV/√Hz
10
18
27
1
Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
2
Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at code 0x00B to code 0x3FF or between RWA at code 0x3F3 to
code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with a
wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.
3
Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably.
4
Guaranteed by design and characterization, not subject to production test.
5
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of
±1 LSB maximum are guaranteed monotonic operating conditions.
6
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables
ground-referenced bipolar signal adjustment.
7
Different from operating current; supply current for fuse program lasts approximately 550 µs.
8
Different from operating current; supply current for fuse read lasts approximately 550 µs.
9
PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC).
10
All dynamic characteristics use VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V.
analog.com
Rev. G | 7 of 33
Data Sheet
AD5291/AD5292
SPECIFICATIONS
Resistor Performance Mode Code Range
Table 5.
RAB = 20 kΩ
Resistor Tolerance per
Code
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
|VDD − VSS| = 30 V to 33 V
|VDD − VSS| = 26 V to 30 V
|VDD − VSS| = 22 V to 26 V
|VDD − VSS| = 21 V to 22 V
RWB
RWA
RWB
RWA
RWB
RWA
RWB
RWA
From 0x15E to
0x3FF
From 0x8C to
0x3FF
From 0x5A to
0x3FF
From 0x000 to
0x2A1
From 0x000 to
0x373
From 0x000 to
0x3A5
From 0x1F4 to
0x3FF
From 0xB4 to
0x3FF
From 0x64 to
0x3FF
From 0x000 to
0x20B
From 0x000 to
0x34B
From 0x000 to
0x39B
From 0x1F4 to
0x3FF
From 0xFA to
0x3FF
From 0x78 to
0x3FF
From 0x000 to
0x20B
From 0x000 to
0x305
From 0x000 to
0x387
N/A
N/A
From 0xFA to
0x3FF
From 0x78 to
0x3FF
From 0x000 to
0x305
From 0x000 to
0x387
Table 6.
RAB = 50 kΩ
Resistor Tolerance per
Code
RWB
1% R-Tolerance
2% R-Tolerance
3% R-Tolerance
analog.com
|VDD − VSS| = 26 V to 33 V
From 0x08C to
0x3FF
From 0X03C to
0x3FF
From 0X028 to
0x3FF
RAB = 100 kΩ
|VDD − VSS| = 21 V to 26 V
|VDD − VSS| = 26 V to 33 V
|VDD − VSS| = 21 V to 26 V
RWA
RWB
RWA
RWB
RWA
RWB
RWA
From 0x000 to
0x35F
From 0x000 to
0x3C3
From 0x000 to
0x3D7
From 0x0B4 to
0x3FF
From 0x050 to
0x3FF
From 0x032 to
0x3FF
From 0x000 to
0x31E
From 0x000 to
0x3AF
From 0x000 to
0x3CD
From 0x04B to
0x3FF
From 0x028 to
0x3FF
From 0x019 to
0x3FF
From 0x000 to
0x3B4
From 0x000 to
0x3D7
From 0x000 to
0x3E6
From 0x064 to
0x3FF
From 0x028 to
0x3FF
From 0x019 to
0x3FF
From 0x000 to
0x39B
From 0x000 to
0x3D7
From 0x000 to
0x3E6
Rev. G | 8 of 33
Data Sheet
AD5291/AD5292
SPECIFICATIONS
INTERFACE TIMING SPECIFICATIONS
VDD/VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, −40°C < TA < +105°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter
Limit1
Unit
Description
t 12
t2
t3
t4
t5
t6
t7
t8
t9
t104
t114
t124
t124
t124
t124
t134
t134
t144
tRESET
tPOWER-UP5
20
10
10
10
5
5
1
4003
14
1
40
2.4
410
8
1.5
450
1.3
450
20
2
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
µs max
ns max
ms max
ms min
ns max
ms max
ns max
ns min
ms max
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore
RDY rising edge to SYNC falling edge
SYNC rising edge to RDY fall time
RDY low time, RDAC register write command execute time (R-Perf mode)
RDY low time, RDAC register write command execute time (normal mode)
RDY low time, memory program execute time
Software/hardware reset
RDY low time, RDAC register readback execute time
RDY low time, memory readback execute time
SCLK rising edge to SDO valid
Minimum RESET pulse width (asynchronous)
Power-on OTP restore time
1
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2
Maximum SCLK frequency is 50 MHz.
3
Refer to t12 and t13 for RDAC register and memory commands operations.
4
RPULL_UP = 2.2 kΩ to VLOGIC, with a capacitance load of 168 pF.
5
Maximum time after VLOGIC is equal to 2.5 V.
Shift Register and Timing Diagrams
0
0
C3
C2
C1
C0
CONTROL BITS
D9
D8
DB0 (LSB)
D7
D6
D5
D4
DATA BITS
D3
D2
D1
D0
07674-003
DB9 (MSB)
Figure 2. Shift Register Content
analog.com
Rev. G | 9 of 33
Data Sheet
AD5291/AD5292
SPECIFICATIONS
t4
SCLK
t2
t7
t1
t9
t3
t8
SYNC
t5
t6
X
X
C3
C2
D7
D6
D2
D1
SDO
D0
t11
t10
RDY
t12
tRESET
RESET
07674-004
DIN
Figure 3. Write Timing Diagram, CPOL = 0, CPHA = 1
Figure 4. Read Timing Diagram, CPOL = 0, CPHA = 1
analog.com
Rev. G | 10 of 33
Data Sheet
AD5291/AD5292
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 8.
Parameter
Rating
VDD to GND
VSS to GND
VLOGIC to GND
VDD to VSS
VA, VB, VW to GND
Digital Input and Output Voltage to GND
EXT_CAP Voltage to GND
IA, IB, IW
Continuous
RAB = 20 kΩ
RAB = 50 kΩ, 100 kΩ
Pulsed1
Frequency > 10 kHz
Frequency ≤ 10 kHz
Operating Temperature Range4
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Package Power Dissipation
−0.3 V to +35 V
+0.3 V to − 25 V
−0.3 V to + 7 V
35 V
VSS − 0.3 V, VDD+ 0.3 V
−0.3 V to VLOGIC + 0.3 V
−0.3 V to +7 V
±3 mA
±2 mA
MCC2/d3
MCC2/√d3
−40°C to +105°C
150°C
−65°C to +150°C
260°C
20 sec to 40 sec
(TJ max − TA)/θJA
1
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance.
2
Maximum continuous current.
3
Pulse duty factor.
4
Includes programming of OTP memory.
analog.com
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
THERMAL RESISTANCE
θJA is defined by JEDEC specification JESD-51 and the value is
dependent on the test board and test environment.
Table 9. Thermal Resistance
Package Type
θJA
θJC
Unit
14-Lead TSSOP
931
20
°C/W
1
JEDEC 2S2P test board, still air (0 m/sec to 1 m/sec airflow).
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Rev. G | 11 of 33
Data Sheet
AD5291/AD5292
RESET 1
14
RDY
13
SDO
12
11
SYNC
SCLK
10
DIN
VDD 6
9
GND
EXT_CAP 7
8
VLOGIC
VSS 2
A 3
W 4
B 5
AD5291/
AD5292
TOP VIEW
Not to Scale
07674-006
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RESET
2
VSS
3
4
5
6
7
8
9
10
A
W
B
VDD
EXT_CAP
VLOGIC
GND
DIN
11
SCLK
12
SYNC
13
SDO
14
RDY
Hardware Reset Pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory default loads midscale until the
first 20-TP wiper memory location is programmed. RESET is activated at the logic high transition. Tie RESET to VLOGIC if not used.
Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF
capacitors.
Terminal A of RDAC. VSS ≤ VA ≤ VDD.
Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
Terminal B of RDAC. VSS ≤ VB ≤ VDD.
Positive Power Supply. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors.
External Capacitor. Connect a 1 µF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V.
Logic Power Supply; 2.7 V to 5.5 V. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors.
Ground Pin, Logic Ground Reference.
Serial Data Input. The AD5291/AD5292 have a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock
input.
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50
MHz.
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift
register and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC
following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write
sequence is ignored by the DAC.
Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data from the shift register in
daisy-chain mode or in readback mode.
Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from the RDAC register or memory.
analog.com
Rev. G | 12 of 33
Data Sheet
AD5291/AD5292
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.6
0.4
0.2
0.2
0
–0.2
–0.4
–0.6
–0.6
–0.8
RAB = 20kΩ
256
384
512
640
768
896
1023
CODE (Decimal)
Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5292)
0.6
–1.0
0
640
768
896
1023
TEMPERATURE = 25°C
0.4
0.3
0.3
DNL (LSB)
0.4
0.2
0.1
0.2
0.1
0
0
–0.1
–0.1
–0.2
20kΩ
50kΩ
100kΩ
–0.2
384
512
640
768
896
1023
–0.3
07674-007
256
+105°C
+25°C
–40°C
CODE (Decimal)
Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5292)
0
256
384
512
640
768
896
1023
Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
1.0
20kΩ
50kΩ
100kΩ
RAB = 20kΩ
0.8
0.6
0.6
0.4
0.4
INL (LSB)
0.8
0.2
128
CODE (Decimal)
1.0
TEMPERATURE = 25°C
0.2
0
0
–0.2
–0.2
–0.4
–0.4
128
256
384
512
640
CODE (Decimal)
768
–0.6
896
1023
07674-010
0
+105°C
+25°C
–40°C
Figure 8. R-INL in Normal Mode vs. Code vs. Temperature (AD5292)
analog.com
0
128
256
384
512
640
CODE (Decimal)
768
896
1023
07674-216
INL (LSB)
512
0.6
0.5
–0.6
384
Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
0.5
128
256
CODE (Decimal)
RAB = 20kΩ
0
128
07674-211
128
07674-106
0
07674-215
–0.8
DNL (LSB)
0
–0.2
–0.4
–0.3
TEMPERATURE = 25°C
0.6
0.4
–1.0
20kΩ
50kΩ
100kΩ
0.8
INL (LSB)
INL (LSB)
1.0
–40°C
+25°C
+105°C
0.8
Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
Rev. G | 13 of 33
Data Sheet
AD5291/AD5292
TYPICAL PERFORMANCE CHARACTERISTICS
0.15
20kΩ
50kΩ
100kΩ
0.10
0.05
0.05
DNL (LSB)
0.10
–0.05
–0.05
–0.10
–0.15
–0.15
128
256
+105°C
+25°C
–40°C
0
384
512
640
768
896
1023
CODE (Decimal)
Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature (AD5292)
–0.20
128
256
384
512
0.5
0.2
INL (LSB)
0.6
–0.2
–1.0
–0.6
128
256
384
512
640
768
896
1023
CODE (Decimal)
–0.8
07674-014
0
+105°C
+25°C
TEMPERATURE = 25°C
20kΩ
50kΩ
100kΩ
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
0.6
0.6
TEMPERATURE = 25°C
RAB = 20kΩ
0.5
0.5
0.4
0.4
0.3
0.3
DNL (LSB)
0.2
0.1
0.2
0.1
0
0
–0.1
–0.1
20kΩ
50kΩ
100kΩ
–0.2
128
256
384
512
640
768
896
1023
CODE (Decimal)
Figure 14. DNL in R-Perf Mode vs. Code vs. Temperature (AD5292)
analog.com
07674-015
0
+105°C
+25°C
–40°C
–0.3
0
128
256
384
512
640
CODE (Decimal)
768
896
1023
07674-203
DNL (LSB)
1023
Figure 16. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
Figure 13. INL in R-Perf Mode vs. Code vs. Temperature (AD5292)
–0.2
896
0
–0.5
–40°C
768
Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
RAB = 20kΩ
0
640
CODE (Decimal)
1.0
–1.5
0
0.8
1.5
INL (LSB)
0
–0.10
–0.20
TEMPERATURE = 25°C
07674-207
0
07674-011
DNL (LSB)
RAB = 20kΩ
07674-213
0.15
Figure 17. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292)
Rev. G | 14 of 33
Data Sheet
AD5291/AD5292
TYPICAL PERFORMANCE CHARACTERISTICS
0.6
0.4
0.2
0.2
INL (LSB)
0.4
0
–0.2
–0.4
–0.4
–0.6
–0.6
0
128
256
384
512
640
768
896
1023
CODE (Decimal)
–0.8
640
768
896
1023
20kΩ
50kΩ
100kΩ
DNL (LSB)
–0.04
–0.10
–0.08
–0.15
–0.12
256
384
512
640
768
896
1023
Figure 19. DNL in Normal Mode vs. Code vs. Temperature (AD5292)
0.30
0
0.30
0.20
0.20
0.15
0.15
0.10
0.10
INL (LSB)
0.25
0
–0.05
–0.10
96
128
160
192
224
255
07674-008
64
CODE (Decimal)
Figure 20. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5291)
analog.com
640
768
896
1023
20kΩ
50kΩ
100kΩ
TEMPERATURE = 25°C
–0.15
RAB = 20kΩ
32
512
0
–0.10
0
384
0.05
–0.05
–0.15
256
Figure 22. DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
0.25
0.05
128
CODE (Decimal)
+105°C
+25°C
–40°C
–0.16
–0.20
0
32
64
96
128
160
CODE (Decimal)
192
224
255
07674-218
128
07674-205
TEMPERATURE = 25°C
RAB = 20kΩ
0
07674-019
DNL (LSB)
512
0
CODE (Decimal)
INL (LSB)
384
0.04
–0.05
–0.20
256
0.08
0
–0.20
128
CODE (Decimal)
–40°C
+25°C
+105°C
0.05
0
Figure 21. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292)
Figure 18. INL in Normal Mode vs. Code vs. Temperature (AD5292)
0.10
TEMPERATURE = 25°C
0
–0.2
–0.8
20kΩ
50kΩ
100kΩ
0.6
07674-018
INL (LSB)
0.8
–40°C
+25°C
+105°C
RAB = 20kΩ
07674-209
0.8
Figure 23. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
Rev. G | 15 of 33
Data Sheet
AD5291/AD5292
TYPICAL PERFORMANCE CHARACTERISTICS
0.14
RAB = 20kΩ
TEMPERATURE = 25°C
0.12
0.12
0.10
0.10
0.08
0.08
0.06
0.06
0.04
0.02
0.02
0
0
–0.02
–0.02
–0.04
20kΩ
50kΩ
100kΩ
–0.04
0
32
64
+105°C
+25°C
–40°C
96
128
160
192
224
255
CODE (Decimal)
Figure 24. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5291)
0.25
0
32
0.20
0.15
0.15
INL (LSB)
0.20
0.05
96
128
160
192
224
255
Figure 27. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
0.25
0.10
64
CODE (Decimal)
+105°C
+25°C
–40°C
–0.06
07674-009
–0.06
INL (LSB)
0.04
07674-212
DNL (LSB)
DNL (LSB)
0.14
20kΩ
50kΩ
100kΩ
TEMPERATURE = 25°C
0.10
0.05
0
0
–0.05
–0.05
0
32
64
96
128
160
192
224
255
CODE (Decimal)
Figure 25. R-INL in Normal Mode vs. Code vs. Temperature (AD5291)
0.03
0.02
0.02
0.01
0.01
0
0
–0.01
–0.02
–0.03
32
64
96
128
160
192
224
255
Figure 28. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
+105°C
+25°C
–40°C
0
CODE (Decimal)
DNL (LSB)
DNL (LSB)
0.03
–0.10
07674-012
–0.10
07674-217
RAB = 20kΩ
20kΩ
50kΩ
100kΩ
TEMPERATURE = 25°C
–0.01
–0.02
–0.03
–0.04
–0.04
0
32
64
96
128
160
CODE (Decimal)
192
224
255
Figure 26. R-DNL in Normal Mode vs. Code vs. Temperature (AD5291)
analog.com
–0.05
0
32
64
96
128
160
CODE (Decimal)
192
224
255
07674-214
–0.05
07674-013
RAB = 20kΩ
Figure 29. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
Rev. G | 16 of 33
Data Sheet
AD5291/AD5292
TYPICAL PERFORMANCE CHARACTERISTICS
0.25
0.15
0.15
0.10
0.10
0.05
0.05
INL (LSB)
0.20
0
–0.05
–0.10
–0.15
–0.15
32
64
96
128
160
192
224
255
CODE (Decimal)
0.08
0.08
0.06
0.06
DNL (LSB)
0.10
0.04
0.02
0
–0.02
96
128
160
192
224
255
CODE (Decimal)
Figure 31. DNL in R-Perf Mode vs. Code vs. Temperature (AD5291)
0.20
–0.06
0.10
0.05
0.05
INL (LSB)
0.10
0
–0.10
–0.10
–0.15
–0.15
96
128
160
CODE (Decimal)
192
224
256
07674-020
–0.05
64
Figure 32. INL in Normal Mode vs. Code vs. Temperature (AD5291)
analog.com
32
64
96
128
160
192
224
255
20kΩ
50kΩ
100kΩ
TEMPERATURE = 25°C
0
–0.05
32
0
0.20
0.15
0
255
Figure 34. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
0.15
–0.20
224
CODE (Decimal)
+105°C
+25°C
–40°C
192
20kΩ
50kΩ
100kΩ
–0.04
RAB = 20kΩ
64
160
0.02
0
32
128
0.04
–0.02
07674-017
DNL (LSB)
0.10
0
96
TEMPERATURE = 25°C
0.12
–0.06
64
0.14
0.12
–0.04
32
CODE (Decimal)
+105°C
+25°C
–40°C
0
Figure 33. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291)
Figure 30. INL in R-Perf Mode vs. Code vs. Temperature (AD5291)
0.14
–0.25
07674-204
0
20kΩ
50kΩ
100kΩ
–0.20
RAB = 20kΩ
–0.20
0
32
64
96
128
160
CODE (Decimal)
192
224
255
07674-210
–0.25
INL (LSB)
0
–0.05
–0.10
–0.20
TEMPERATURE = 25°C
07674-208
+105°C
+25°C
–40°C
0.20
07674-016
INL (LSB)
0.25
Figure 35. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291)
Rev. G | 17 of 33
Data Sheet
AD5291/AD5292
TYPICAL PERFORMANCE CHARACTERISTICS
0.03
+105°C
+25°C
–40°C
TEMPERATURE = 25°C
0.02
0.02
0.01
0.01
0
0
DNL (LSB)
–0.01
–0.02
–0.04
RAB = 20kΩ
32
64
96
128
160
192
224
255
CODE (Decimal)
Figure 36. DNL in Normal Mode vs. Code vs. Temperature (AD5291)
450
250
200
150
IDD
128
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
224
255
VDD = ±15V
0.16
0.14
0.12
0.1
0.08
0.06
0.04
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
DIGITAL INPUT VOLTAGE (V)
700
700
POTENTIOMETER MODE TEMPCO (ppm/°C)
VDD = 30V,
VSS= 0V
600
20kΩ
50kΩ
100kΩ
500
400
300
200
100
768
192
1023 AD5292
255 AD5291
Figure 38. Rheostat Mode Tempco ΔRWB/ΔT vs. Code
07674-024
512
128
CODE (Decimal)
4.5
5.0
VDD = 30V
VSS= 0V
20kΩ
50kΩ
100kΩ
600
500
400
300
200
100
0
256
64
4.0
Figure 40. Supply Current ILOGIC vs. Digital Input Voltage
Figure 37. Supply Current (IDD, ISS, ILOGIC) vs. Temperature
analog.com
192
07674-031
ISS
07674-022
–50
–40 –30 –20 –10 0
0
0
160
0.02
0
RHEOSTAT MODE TEMPCO (ppm/°C)
96
0.20
300
50
64
0.18
ILOGIC
100
32
Figure 39. DNL in Normal Mode vs. Code vs. Temperature (AD5291)
SUPPLY CURRENT I LOGIC (mA)
350
0
CODE (Decimal)
VDD/VSS = ±15V
VLOGIC = +5V
400
SUPPLY CURRENT (nA)
–0.05
07674-021
0
20kΩ
50kΩ
100kΩ
07674-206
–0.04
0
–0.02
–0.03
–0.03
–0.05
–0.01
0
0
256
64
512
128
CODE (Decimal)
768
192
1023 AD5292
255 AD5291
07674-023
DNL (LSB)
0.03
Figure 41. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code
Rev. G | 18 of 33
Data Sheet
AD5291/AD5292
TYPICAL PERFORMANCE CHARACTERISTICS
0
0x200 (0x80)
–10
0x100 (0x40)
0x080 (0x20)
–20 0x040 (0x10)
0x040 (0x10)
–25
0x020 ( 0x08)
–30
–30
0x010 (0x04)
–40 0x008 (0x02)
0x010 (0x04)
0x004 (0x01)
0x008 (0x02)
–50
0x004 (0x01)
–60 0x001
–40
0x002
–50
10
0x002
0x001
100
1k
10k
100k
1M
FREQUENCY (Hz)
–70
10
07674-025
–45
0x020 ( 0x08)
0
–10
–10 0x100 (0x40)
0x080 (0x20)
–20
10k
100k
1M
Figure 45. 100 kΩ Gain vs. Frequency vs. Code
AD5292 (AD5291)
0x200 (0x80)
1k
FREQUENCY (Hz)
Figure 42. 20 kΩ Gain vs. Frequency vs. Code
0
100
07674-201
–20
GAIN (dB)
0x080 (0x20)
–35
100kΩ
20kΩ
50kΩ
–20
0x040 (0x10)
PSRR (dB)
GAIN (dB)
AD5292 (AD5291)
0x200 (0x80)
–10 0x100 (0x40)
–15
GAIN (dB)
0
AD5292 (AD5291)
–5
0x020 ( 0x08)
–30
0x010 (0x04)
–40
0x008 (0x02)
–30
–40
–50
0x004 (0x01)
–50
–60
1k
10k
100k
FREQUENCY (Hz)
1M
–70
100
–15
0
VDD/VSS = ±15V
CODE = HALF SCALE
VIN = 1V rms
Noise BW = 22kHz
20kΩ
50kΩ
100kΩ
–40
–60
–75
–60
–80
–100
–90
–120
1k
10k
FREQUENCY (Hz)
Figure 44. THD + Noise vs. Frequency
100k
07674-027
–105
analog.com
1M
VDD/VSS = ±15V,
CODE = HALF SCALE
fIN = 1kHz
NOISE BW = 22kHz
20kΩ
50kΩ
100kΩ
–20
–45
–120
100
100k
Figure 46. Power Supply Rejection Ratio vs. Frequency
THD + N (dB)
THD + N (dB)
–30
10k
FREQUENCY (Hz)
Figure 43. 50 kΩ Gain vs. Frequency vs. Code
0
1k
07674-026
100
–140
0.001
0.01
0.1
1
10
AMPLITUDE (V rms)
07674-220
–60
10
0x001
07674-200
0x002
Figure 47. THD + Noise vs. Amplitude
Rev. G | 19 of 33
Data Sheet
AD5291/AD5292
TYPICAL PERFORMANCE CHARACTERISTICS
800,000
8
50k – 150pF
50k – 250pF
100k – 0pF
100k – 75pF
100k – 150pF
100k – 250pF
700,000
BANDWIDTH (Hz)
VDD/VSS = 30V/0V
VA = VDD
VB = VSS
7
600,000
500,000
400,000
300,000
200,000
6
5
4
20kΩ
3
50kΩ
2
100kΩ
1
100,000
0
0
8
16
32
64
16
32
CODE (Decimal)
8
128
256
512 AD5292
128 AD5291
64
0
07674-222
0
0
0
256
64
768
192
1023 AD5292
255 AD5291
Figure 51. Theoretical Maximum Current vs. Code
35
1.2
30
1.0
VDD/VSS = ±15V
VLOGIC = +5V
VA = VDD
VB = VSS
0.8
25
20kΩ
50kΩ
100kΩ
0.6
20
VOLTAGE (V)
SUPPLY CURRENT I DD (mA)
Figure 48. Bandwidth vs. Code vs Net Capacitance
512
128
CODE (Decimal)
07674-029
20k – 0pF
20k – 75pF
20k – 150pF
20k – 250pF
50k – 0pF
50k – 75pF
900,000
THEORETICAL IWB_MAX (mA)
1,000,000
15
10
0.4
0.2
0
–0.2
5
–0.4
0
0
0.2
0.4
0.6
TIME (ms)
0.8
1.0
1.2
–0.8
–2
0
24
15
10
SYNC
16
8
0
–8
Figure 50. 20 kΩ Large-Signal Settling Time from Code Zero Scale
–40
–0.5
0
5
10
15
20
25
TIME (µs)
30
35
40
45
07674-032
15
13
12
11
9
–24
–32
07674-033
TIME (µs)
10
8
7
6
5
4
3
2
1
0
0
14
20kΩ
50kΩ
100kΩ
20kΩ
50kΩ
100kΩ
VWB, CODE: HALF-SCALE,
NORMAL MODE
VWB, CODE: HALF-SCALE,
R-PERF MODE
–1
14
–16
5
–2
12
16
VWB, CODE: FULL SCALE,
R-PERF MODE
VOLTAGE (μV)
VOLTAGE (V)
10
VDD/VSS = ±15V
VA = VDD
VB = VSS
CODE = HALF CODE
32
VDD/VSS = 30V/0V
VLOGIC = 5V
VA = VDD
VB = VSS
25
analog.com
8
40
VWB, CODE: FULL SCALE,
NORMAL MODE
–5
6
Figure 52. Maximum Transition Glitch
30
20
4
TIME (µs)
Figure 49. IDD Waveform While Blowing/Reading Fuse
35
2
07674-035
–0.2
07674-034
–0.6
–5
–0.4
Figure 53. Digital Feedthrough
Rev. G | 20 of 33
Data Sheet
AD5291/AD5292
TYPICAL PERFORMANCE CHARACTERISTICS
NUMBER OF CODES (AD5291)
62.5
3
2
1
8.6
TIME (ms)
200
37.5
150
25.0
100
12.5
50
20.0
8
VDD/VSS = ±15V
VLOGIC = +5V
NUMBER OF CODES (AD5291)
17.5
6
3
2
Figure 55. VEXT_CAP Waveform While Writing Fuse
analog.com
07674-037
17.2
16.0
14.8
13.6
12.4
TIME (ms)
11.2
8.8
10.0
7.6
6.4
5.2
4.0
2.8
1.6
0.4
–2.0
–2
–0.8
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
0
Figure 56. Code Range > 1% R-Tolerance Error vs. Temperature
Figure 54. VEXT_CAP Waveform While Reading Fuse or Calibration
VOLTAGE (V)
50.0
0
–40 –30 –20 –10 0
07674-036
8.0
6.8
7.4
6.2
5.6
5.0
4.4
3.2
3.8
2.6
2.0
1.4
0.8
0.2
–1.0
–1
–0.4
0
250
VA = VDD
VB = VSS
TEMPERATURE = 25°C
20kΩ
50kΩ
100kΩ
80
70
15.0
60
12.5
50
10.0
40
7.5
30
5.0
20
2.5
10
0
21
0
26
30
33
VOLTAGE V DD/VSS
NUMBER OF CODES (AD5292)
VOLTAGE (V)
4
20kΩ
50kΩ
100kΩ
NUMBER OF CODES (AD5292)
5
300
VDD/VSS = ±15V
07674-056
75.0
VDD/VSS = ±15V
VLOGIC = +5V
07674-219
6
Figure 57. Code Range > 1% R-Tolerance Error vs. Voltage
Rev. G | 21 of 33
Data Sheet
AD5291/AD5292
TEST CIRCUITS
Figure 58 to Figure 63 define the test conditions used in the Specifications section.
VA
IW
VDD
A
V+ ~
V+ = VDD ± 10%
ΔVMS
PSRR (dB) = 20 log ΔV
DD
W
B
B
07674-041
NC = NO CONNECT
2.5V
W
B
VMS
+15V
CODE = 0x00
W
B
+
IWB
–
RW =
–15V
–15V
NC
RWB=
VOUT
Figure 62. Gain vs. Frequency
Figure 59. Potentiometer Divider Nonlinearity Error(INL, DNL)
DUT
OP42
B
07674-042
V+
W
DUT
OFFSET
GND
V+ = VDD
1LSB = V+/2N
+15V
A
VIN
DUT
ΔVMS%
ΔVDD%
Figure 61. Power Supply Sensitivity (PSS, PSRR)
Figure 58. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL,
R-DNL)
A
PSS (%/%) =
VMS
VMS
07674-047
DUT
A
W
07674-044
NC
0.1V
IWB
RWB
GND
GND
2
0.1V
VDD
DUT
A
VSS GND
B
ICM
W
+15V
–15V
NC
+15V
Figure 60. Wiper Resistance
analog.com
GND
–15V
NC = NO CONNECT
07674-048
VSS TO VDD
07674-043
GND
A = NC
Figure 63. Common-Mode Leakage Current
Rev. G | 22 of 33
Data Sheet
AD5291/AD5292
THEORY OF OPERATION
The AD5291/AD5292 digital potentiometers are designed to operate as true variable resistors for analog signals that remain within
the terminal voltage range of VSS < VTERM < VDD. The patented
±1% resistor tolerance feature helps to minimize the total RDAC
resistance error, which reduces the overall system error by offering
better absolute matching and improved open-loop performance.
The digital potentiometer wiper position is determined by the RDAC
register contents. The RDAC register acts as a scratchpad register, allowing as many value changes as necessary to place the
potentiometer wiper in the correct position. The RDAC register
can be programmed with any position setting using the standard
SPI interface by loading the 16-bit data-word. Once a desirable
position is found, this value can be stored in a 20-TP memory
register. Thereafter, the wiper position is always restored to that
position for subsequent power-up. The storing of 20-TP data takes
approximately 6 ms; during this time, the shift register is locked,
preventing any changes from taking place. The RDY pin identifies
the completion of this 20-TP storage.
SHIFT REGISTER
The AD5291/AD5292 shift register is 16 bits wide (see Figure 2).
The 16-bit input word consists of two zeros, followed by four control
bits, and 10 RDAC data bits. For the AD5291, the lower two RDAC
data bits are don’t cares if the RDAC register is read from or
written to. Data is loaded MSB first (Bit DB15). The four control bits
determine the function of the software command (see Table 11).
Figure 3 shows a timing diagram of a typical AD5291 and AD5292
write sequence.
The write sequence begins by bringing the SYNC line low. The
SYNC pin must be held low until the complete data-word is loaded
from the DIN pin. When SYNC returns high, the serial data-word
is decoded according to the commands in Table 11. The command
bits (Cx) control the operation of the digital potentiometer. The
data bits (Dx) are the values that are loaded into the decoded
register. The AD5291/AD5292 have an internal counter that counts
a multiple of 16 bits (a frame) for proper operation. For example,
AD5291/AD5292 work with a 32-bit word but does not work properly with a 31-bit or 33-bit word. The AD5291/AD5292 do not require
a continuous SCLK, when SYNC is high, and all serial interface
pins should be operated at close to the VLOGIC supply rails to
minimize power consumption in the digital input buffers.
SERIAL DATA INTERFACE
The AD5291/AD5292 contain a serial interface (SYNC, SCLK, DIN
and SDO) that is compatible with SPI interface standards, as
well as most DSPs. The part allows writing of data via the serial
interface to every register.
Table 11. Command Operation Truth Table
Command
Bits[DB13:DB10]
Command
DB15
DB14
Data Bits[DB9:DB0]1
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Operation
NOP command: do nothing.
Write contents of serial data to RDAC.
Read RDAC wiper setting from the
SDO output in the next frame.
Store wiper setting: store RDAC
setting to 20-TP memory.
Reset: refresh RDAC with 20-TP
stored value.
Read contents of 20-TP memory, or
status of 20-TP memory, from the SDO
output in the next frame.
Write contents of serial data to control
register.
Read control register from the SDO
output in the next frame.
Software shutdown.
D0 = 0 (normal mode).
D0 = 1 (device placed in shutdown
mode).
0
1
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
X
D9
X
X
D8
X
X
D7
X
X
D6
X
X
D5
X
X
D4
X
X
D3
X
X
D2
X
X
D12
X
X
D02
X
3
0
0
0
0
1
1
X
X
X
X
X
X
X
X
X
X
4
0
0
0
1
0
0
X
X
X
X
X
X
X
X
X
X
5
0
0
0
1
0
1
X
X
X
X
X
D4
D3
D2
D1
D0
6
0
0
0
1
1
0
X
X
X
X
X
X
D3
D2
D1
D0
7
0
0
0
1
1
1
X
X
X
X
X
X
X
X
X
X
8
0
0
1
0
0
0
X
X
X
X
X
X
X
X
X
D0
1
X = don’t care.
2
In the AD5291, this bit is a don’t care.
analog.com
Rev. G | 23 of 33
Data Sheet
AD5291/AD5292
THEORY OF OPERATION
Table 12. Control Register Bit Map1
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
X
X
X
X
X
C3
C2
C1
C0
1
X = don’t care.
Table 13. Control Register Function
Bit Name
Description
C0
20-TP program enable
0 = 20-TP program disabled (default)
1 = enable device for 20-TP program
RDAC register write protect
0 = wiper position frozen to value in memory (default)1
1 = allow update of wiper position through digital Interface
Calibration enable
0 = resistor performance mode enabled (default)
1 = normal mode enabled
20-TP memory program success
0 = fuse program command unsuccessful (default)
1 = fuse program command successful
C1
C2
C3
1
Wiper position frozen to value last programmed in 20-TP memory. Wiper is frozen to midscale if 20-TP memory has not been previously programmed.
analog.com
Rev. G | 24 of 33
Data Sheet
AD5291/AD5292
THEORY OF OPERATION
RDAC REGISTER
The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded
with all zeros, the wiper is connected to Terminal B of the variable
resistor. The RDAC register is a standard logic register; there is no
restriction on the number of changes allowed.
20-TP MEMORY
Once a desirable wiper position is found, the contents of the RDAC
register can be saved into a 20-TP memory register (see Table
14). Thereafter, the wiper position is always set at that position for
any future on-off-on power supply sequence. The AD5291/AD5292
have an array of 20 one-time programmable (OTP) memory regis-
ters. When the desired word is programmed to 20-TP memory,
the device automatically verifies that the program command was
successful. The verification process includes margin testing. Bit
C3 of the control register can be polled to verify that the fuse
program command was successful. Programming data to 20-TP
memory consumes approximately 25 mA for 550 µs and takes
approximately 8 ms to complete. During this time, the shift register
is locked, preventing any changes from taking place. The RDY
pin can be used to monitor the completion of the 20-TP memory
program and verification. No change in supply voltage is required
to program the 20-TP memory. However, a 1 µF capacitor on the
EXT_CAP pin is required (see Figure 68). Prior to 20-TP activation,
the AD5291/AD5292 preset to midscale on power-up.
Table 14. Write and Read to RDAC and 20-TP Memory
DIN
SDO
Action
0x1803
0x0500
0x0800
0x0C00
0xXXXX
0x1803
0x0500
0x0100
0x1C00
0x0000
0x0C00
0x000X
Enable update of wiper position and 20-TP memory contents through digital interface.
Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position.
Prepare data read from the RDAC register.
Stores RDAC register content into 20-TP memory. The 16-bit word appears out of SDO, where the last 10 bits contain the contents of the
RDAC register (0x100).
Prepare data read from the control register.
NOP Instruction 0 sends 16-bit word out of SDO, where the last four bits contain the contents of the control register. If Bit C3 = 1, the fuse
program command is successful.
Table 15. Memory Map of Command 5
Data Bits[DB9:DB0]1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Register Contents
X
X
X
X
X
…
X
X
X
X
X
X
X
X
X
X
…
X
X
X
X
X
X
X
X
X
X
…
X
X
X
X
X
X
X
X
X
X
…
X
X
X
X
X
X
X
X
X
X
…
X
X
X
X
X
0
0
0
0
0
…
0
0
1
1
1
0
0
0
0
0
…
1
1
0
0
0
0
0
0
0
1
…
0
1
0
1
1
0
0
1
1
0
…
0
1
1
0
0
0
1
0
1
0
…
1
0
1
0
1
1st programmed wiper location (0x00)
2nd programmed wiper location (0x01)
3rd programmed wiper location (0x02)
4th programmed wiper location (0x03)
5th programmed wiper location (0x04)
…
10th programmed wiper location (0x09)
15th programmed wiper location (0x0E)
20th programmed wiper location (0x13)
Programmed memory status (thermometer encoded)2 (0x14)
Programmed memory status (thermometer encoded)2(0x15)
1
X = don’t care.
2
Allows the user to calculate the remaining spare memory locations.
analog.com
Rev. G | 25 of 33
Data Sheet
AD5291/AD5292
THEORY OF OPERATION
WRITE PROTECTION
On power-up, the shift register write commands for both the RDAC
register and the 20-TP memory register are disabled. The RDAC
write protect bit, C1 of the control register (see Table 12 and Table
13), is set to 0 by default. This disables any change of the RDAC
register content regardless of the software commands, except that
the RDAC register can be refreshed from the 20-TP memory using
the software reset command (Command 4) or through hardware
by the RESET pin. To enable programming of the variable resistor
wiper position (programming the RDAC register), the write protect
bit, C1 of the control register, must first be programmed. This is
accomplished by loading the shift register with Command 6 (see
Table 11). To enable programming of the 20-TP memory block bit,
C0 of the control register (set to 0 by default) must first be set to 1.
BASIC OPERATION
The basic mode of setting the variable resistor wiper position
(programming the RDAC register) is accomplished by loading the
shift register with Command 1 (see Table 11) and the desired wiper
position data. When the desired wiper position is determined, the
user can load the shift register with Command 3 (see Table 11),
which stores the wiper position data in the 20-TP memory register.
After 6 ms, the wiper position is permanently stored in the 20-TP
memory. The RDY pin can be used to monitor the completion of this
20-TP program. Table 14 provides a programming example, listing
the sequence of serial data input (DIN) words with the serial data
output appearing at the SDO pin in hexadecimal format.
20-TP READBACK AND SPARE MEMORY
STATUS
It is possible to read back the contents of any of the 20-TP memory
registers through SDO by using Command 5 (see Table 11). The
lower five LSB bits (D0 to D4) of the data byte select which memory
location is to be read back (see Table 15). Data from the selected
memory location are clocked out of the SDO pin during the next
SPI operation, where the last 10 bits contain the contents of the
specified memory location.
It is also possible to calculate the address of the most recently
programmed memory location by reading back the contents of
read-only Memory Address 0x14 and Memory Address 0x15 using
Command 5. The data bytes read back from Memory Address
0x014 and Memory Address 0x015 are thermometer encoded versions of the address of the last programmed memory location.
For the example outlined in Table 16, the address of the last
programmed location is calculated as
(Number of Bits = 1 in Memory Address 0x14) + (Number of Bits =
1 in Memory Address 0x15) − 1 = 10 + 8 − 1 = 17 (0x10)
If no memory location has been programmed, then the address
generated is −1.
Table 16. Example 20-TP Memory Readback
DIN
SDO
Action
0x1414
0x1415
0xXXXX
0x03FF
0x0000
0x1410
0x0000
0x00FF
0x0000
0xXXXX
Prepares data read from Memory Address 0x14.
Prepares data read from Memory Address 0x15. Sends 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Address
0x14.
NOP Command 0 sends 16-bit word out of SDO, where last 10-bits contain the contents of Memory Address 0x15.
Prepares data read from memory location 0x10.
NOP Instruction 0 sends 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Address 0x10 (17).
analog.com
Rev. G | 26 of 33
Data Sheet
AD5291/AD5292
THEORY OF OPERATION
SHUTDOWN MODE
The AD5291/AD5292 can be placed in shutdown mode by executing the software shutdown command, Command 8 (see Table 11),
and setting the LSB, D0, to 1. This feature places the RDAC in a
special state in which Terminal A is open-circuited, and Wiper W
is connected to Terminal B. The contents of the RDAC register are
unchanged by entering shutdown mode. However, all commands
listed in Table 11 are supported while in shutdown mode. Execute
Command 8 (see Table 11), and set the LSB, D0, to 0 to exit
shutdown mode.
RESISTOR PERFORMANCE MODE
This mode activates a new, patented 1% end-to-end resistor tolerance that ensures a ±1% resistor tolerance on each code, that is,
code = half scale, RWB = 10 kΩ ± 100 Ω. See Table 2 (AD5291)
or Table 5 (AD5292) to check which codes achieve ±1% resistor
tolerance. The resistor performance mode is activated by programming Bit C2 of the control register (see Table 12 and Table 13). The
typical settling time is shown in Figure 50.
RESET
A low-to-high transition of the hardware RESET pin loads the
RDAC register with the contents of the most recently programmed
20-TP memory location. The AD5291/AD5292 can also be reset
through software by executing Command 4 (see Table 11). If no
20-TP memory location is programmed, then the RDAC register
loads with midscale upon reset. The control register is restored with
default bits; see Table 13.
control register using Command 2, Command 5 and Command
7, respectively (see Table 11) or the SDO pin can be used in
daisy-chain mode. Data is clocked out of SDO on the rising edge
of SCLK. The SDO pin contains an open-drain N-channel FET that
requires a pull-up resistor if this pin is used. To place the pin in
high impedance and minimize the power dissipation when the pin
is used, the 0x8001 data word followed by Command 0 should
be sent to the part. Table 17 provides a sample listing for the
sequence of the serial data input (DIN). Daisy chaining minimizes
the number of port pins required from the controlling IC. As shown
in Figure 64, users need to tie the SDO pin of one package to
the DIN pin of the next package. Users may need to increase
the clock period, because the pull-up resistor and the capacitive
loading at the SDO-to-DIN interface may require additional time
delay between subsequent devices.
When two AD5291 and AD5292 devices are daisy-chained, 32 bits
of data are required. The first 16 bits go to U2, and the second 16
bits go to U1. Hold the SYNC pin low until all 32 bits are clocked
into their respective shift registers. The SYNC pin is then pulled
high to complete the operation.
Keep the SYNC pin low until all 32 bits are clocked into their
respective serial registers. The SYNC pin is then pulled high to
complete the operation.
VLOGIC
AD5291/
AD5292
MOSI
MICROCONTROLLER
SCLK
SS
DIN
SYNC
U1
SDO
SCLK
RP
2.2kΩ
AD5291/
AD5292
DIN
SYNC
U2
SDO
SCLK
The serial data output pin (SDO) serves two purposes: it can be
used to read the contents of the wiper setting, 50-TP values and
07674-050
SDO PIN AND DAISY-CHAIN OPERATION
Figure 64. Daisy-Chain Configuration Using SDO
Table 17. Minimize Power Dissipation at SDO Pin
DIN1
SDO1
Action
0xXXXX
0x8001
0x0000
0xXXXX
0xXXXX
High impedance
Last user command sent to the digipot
Prepares the SDO pin to be placed in high impedance mode
The SDO pin is placed in high impedance
1
X is don’t care.
analog.com
Rev. G | 27 of 33
Data Sheet
AD5291/AD5292
THEORY OF OPERATION
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices has patented the
RDAC segmentation architecture for all the digital potentiometers.
In particular, the AD5291/AD5292 employ a three-stage segmentation approach, as shown in Figure 65. The AD5291/AD5292 wiper
switches are designed with the transmission gate CMOS topology
and with the gate voltages derived from VDD and VSS.
A
RM
SW
RM
RW
W
RM
RL
AD5292: RWA D =
RM
RL
07674-051
B
Figure 65. Simplified RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—1% Resistor Tolerance
The AD5291/AD5292 operate in rheostat mode when only two
terminals are used as a variable resistor. The unused terminal can
be left floating or tied to the W terminal, as shown in Figure 66.
B
W
B
Figure 66. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B, RAB, is
available in 20 kΩ, 50 kΩ, and 100 kΩ, and 256 or 1024 tap points
accessed by the wiper terminal. The 8-/10-bit data in the RDAC
latch is decoded to select one of the 256/1024 possible wiper
settings. The AD5291/AD5292 contain an internal ±1% resistor
performance mode that can be disabled or enabled (this is enabled
by default), by programming Bit C2 of the control register (see
Table 12 and Table 13). The digitally programmed output resistance
between the W terminal and the A terminal, RWA, and between
the W terminal and B terminal, RWB, is internally calibrated to
give a maximum of ±1% absolute resistance error across a wide
code range. As a result, the general equations for determining the
digitally programmed output resistance between the W terminal and
B terminal are
analog.com
× RAB
(2)
256 − D
256
× RAB
1024 − D
1024
(3)
× RAB
(4)
where:
D is the decimal equivalent of the binary code loaded in the 8-/
10‑bit RDAC register.
RAB is the end-to-end resistance.
In the zero-scale condition, a finite total wiper resistance of 60 Ω
is present. Regardless of which setting the part is operating in,
take care to limit the current between Terminal A and Terminal B,
between Terminal W and Terminal A, and between Terminal W and
Terminal B, to the maximum continuous current of ±3 mA or to
the pulse current specified in Table 8. Otherwise, degradation or
possible destruction of the internal resistors may occur.
PROGRAMMING THE POTENTIOMETER
DIVIDER
A
W
B
D
1024
(1)
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at the
wiper to B and at the wiper to A that is proportional to the input
voltage at A to B, as shown in Figure 67. Unlike the polarity of VDD
to GND, which must be positive, voltage across A to B, W to A, and
W to B can be at either polarity.
VIN
A
W
B
VOUT
07674-053
A
W
07674-052
A
× RAB
where:
D is the decimal equivalent of the binary code loaded in the
8-/10-bit RDAC register.
RAB is the end-to-end resistance.
AD5291: RWA D =
RW
8-/10-BIT
ADDRESS
DECODER
AD5292: RWB D =
D
256
Similar to the mechanical potentiometer, the resistance of the
RDAC between the W terminal and the A terminal also produces
a digitally controlled complementary resistance, RWA. RWA is also
calibrated to give a maximum of 1% absolute resistance error.
RWA starts at the maximum resistance value and decreases as the
data loaded into the latch increases. The general equations for this
operation are
RL
RL
AD5291: RWB D =
Figure 67. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for simplicity, connecting the A terminal to 30 V and the B terminal to ground produces
an output voltage at the Wiper W to Terminal B ranging from 0
V to 1 LSB less than 30 V. Each LSB of voltage is equal to
the voltage applied across Terminal A and Terminal B, divided by
the 256/1024 positions of the potentiometer divider. The general
Rev. G | 28 of 33
Data Sheet
AD5291/AD5292
THEORY OF OPERATION
equations defining the output voltage at VW with respect to ground
for any valid input voltage applied to Terminal A and Terminal B are
AD5292: VW D =
D
256
× VA +
D
1024
256 − D
256
× VA +
× VB
1024 − D
1024
× VB
(5)
(6)
If using the AD5291/AD5292 in voltage divider mode as shown
in Figure 67, then the ±1% resistor tolerance calibration feature
reduces the error when matching with discrete resistors. However,
it is recommended to disable the internal ±1% resistor tolerance
calibration feature by programming Bit C2 of the control register
(see Table 12 and Table 13) to optimize wiper position update rate.
In this configuration, the RDAC is ratiometric and resistor tolerance
error does not affect performance.
Operation of the digital potentiometer in the voltage divider mode
results in a more accurate operation over temperature. Unlike the
rheostat mode, the output voltage is dependent mainly on the ratio
of the internal resistors, RWA and RWB, and not the absolute values.
Therefore, the temperature drift reduces to 5 ppm/°C.
EXT_CAP CAPACITOR
A 1 µF capacitor to GND must be connected to the EXT_CAP pin
(see Figure 68) on power-up and throughout the operation of the
AD5291/AD5292.
AD5291/
AD5292
EXT_CAP
C1
1µF
OTP
MEMORY
BLOCK
07674-054
GND
Figure 68. Hardware Setup for EXT_CAP Pin
TERMINAL VOLTAGE OPERATING RANGE
The positive VDD and negative VSS power supplies of the AD5291/
AD5292 define the boundary conditions for proper 3-terminal digital
analog.com
VDD
A
W
B
VSS
07674-055
AD5291: VW D =
potentiometer operation. Supply signals present on Terminal A,
Terminal B, and Terminal W that exceed VDD or VSS are clamped by
the internal forward-biased diodes (see Figure 69).
Figure 69. Maximum Terminal Voltages Set by VDD and VSS
The ground pins of the AD5291/AD5292 devices are primarily
used as a digital ground reference. To minimize the digital ground
bounce, the AD5291/AD5292 ground terminals should be joined
remotely to the common ground. The digital input control signals
to the AD5291/AD5292 must be referenced to the device ground
pin (GND), and satisfy the logic level defined in the Specifications
section.
Power-Up Sequence
To ensure that the AD5291/AD5292 power up correctly, a 1 µF
capacitor must be connected to the EXT_CAP pin. Because there
are diodes to limit the voltage compliance at Terminal A, Terminal
B, and Terminal W (see Figure 69), it is important to power VDD
and VSS first before applying any voltage to Terminal A, Terminal B,
and Terminal W. Otherwise, the diode is forward-biased such that
VDD and VSS are powered up unintentionally. The ideal power-up
sequence is GND, VSS, VLOGIC and VDD, the digital inputs, and then
VA, VB, and VW. The order of powering up VA, VB, VW, and the
digital inputs is not important as long as they are powered after
VDD, VSS, and VLOGIC.
Regardless of the power-up sequence and the ramp rates of the
power supplies, after VLOGIC is powered, the power-on preset
activates, restoring the 20-TP memory value to the RDAC register.
Rev. G | 29 of 33
Data Sheet
AD5291/AD5292
APPLICATIONS INFORMATION
HIGH VOLTAGE DAC
VDD
U1
The AD5292 can be configured as a high voltage DAC, with output
voltage as high as 33 V. The circuit is shown in Figure 70. The
output is
× 1.2 V × 1 +
where D is the decimal code from 0 to 1023.
R2
R1
U1B
AD8512
VOUT
07674-153
R2
R3
ADG1207
Figure 70. High Voltage DAC
+VIN4
VSS
Figure 73. Data Acquisition System
The gain can be calculated by using Equation 9.
VOUT
CC
U2
SIGNAL
G(D) = 1 +
RBIAS
IL
Figure 71. Programmable Boosted Voltage Source
In this circuit, the inverting input of the op amp forces VOUT to be
equal to the wiper voltage set by the digital potentiometer. The load
current is then delivered by the supply via the N-channel FET (U3).
The N-Channel FET power handling must be adequate to dissipate
(VIN − VOUT) × IL power. This circuit can source a maximum of 100
mA with a 33 V supply.
HIGH ACCURACY DAC
It is possible to configure the AD5292 as a high accuracy DAC
by optimizing the resolution of the device over a specific reduced
voltage range. This is achieved by placing external resistors on
either side of the RDAC, as shown in Figure 72. The improved
±1% R-Tolerance specification greatly reduces error associated
with matching to discrete resistors.
VOUT(D) =
analog.com
R3 + (D 1024 × RAB) × VDD
R1 + ((1024 − D) 1024) × RAB + R3
49.4 kΩ
D/1024 × RAB
(9)
AUDIO VOLUME CONTROL
LD
07674-155
OP184
VOUT
AD8221
–VIN4
U3 2N7002
VIN
U1
AD5292
–VIN1
For applications that require high current adjustments such as a
laser diode or tunable laser, a boosted voltage source can be
considered; see Figure 71.
AD5292
VDD
+VIN1
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
B
VOUT
07674-156
20kΩ
B
W
V+
OP1177
The AD8221 in conjunction with the AD5291/AD5292 and the
ADG1207, as shown in Figure 73, make an excellent instrumentation amplifier for use in data acquisition systems. The data acquisition system’s low distortion and low noise enable it to condition
signals in front of a variety of ADCs.
AD5292
V–
A
±1%
Figure 72. Optimizing Resolution
U2
U1A
AD8512
R1
VDD
U2
VARIABLE GAIN INSTRUMENTATION
AMPLIFIER
V+
ADR512
B
(7)
VDD
D1
R2
20kΩ
V–
VDD
RBIAS
AD5292
07674-154
D
1024
VOUT D =
R1
(8)
The excellent THD performance and high voltage capability make
the AD5291/AD5292 ideal for a digital volume control as an audio
attenuator or gain amplifier. A typical problem in these systems
is that a large step change in the volume level at any arbitrary
time can lead to an abrupt discontinuity of the audio signal causing
an audible zipper noise. To prevent this, a zero-crossing window
detector can be inserted to the SYNC line to delay the device
update until the audio signal crosses the window. Because the input
signal can operate on top of any dc level rather than absolute zero
volt level, zero-crossing in this case means the signal is ac-coupled,
and the dc offset level is the signal zero reference point.
The configuration to reduce zipper noise is shown in Figure 74,
and the results of using this configuration is shown in Figure 75.
The input is ac-coupled by C1 and attenuated down before feeding
into the window comparator formed by U2, U3, and U4B. U6 is
used to establish the signal zero reference. The upper limit of the
comparator is set above its offset and, therefore, the output pulses
high whenever the input falls between 2.502 V and 2.497 V (or
0.005 V window) in this example. This output is AND’ed with the
SYNC signal such that the AD5291/AD5292 updates whenever
the signal crosses the window. To avoid a constant update of the
device, the SYNC signal should be programmed as two pulses,
rather than as one.
Rev. G | 30 of 33
Data Sheet
AD5291/AD5292
APPLICATIONS INFORMATION
In Figure 75, the lower trace shows that the volume level changes
from a quarter-scale to full-scale when a signal change occurs near
the zero-crossing window.
V+
+15V
U1A
1/2
AD8676
100kΩ
VCC
+3.3V
0V ±14V
V–
–15V
R1
100kΩ
±0.1%
R4
90.9kΩ ±0.1%
+1.657V
0.0133V
R2
806Ω
±0.1%
+3.3V
VCC
ADCMP371
GND
R6
27.4kΩ
±0.1%
R7
33.2kΩ
±0.1%
V–
+3.3V
U4
+1.643V
V+
AD8541
AD5292
SERIAL
INTERFACE
U5A
1/2
7408
+3.3V
U2
+1.81V
A
U3
+1.645V
±1.4V
R5
9.09kΩ ±0.1%
+3.3V
VDD
+15V
U6
U1B
2/2
VOUT
AD8676
SYNC
VCC
ADCMP371
GND
B
SYNC
R3
100kΩ
±0.1%
W
RAB
20kΩ
U4B
2/2
7408
VSS
–15V
07674-157
C1
VIN 100nF
Figure 74. Audio Volume Control with Zipper Noise Reduction
T
1
2
CH1 500mV BW CH2 500mV
B
W
M20µs A CH2
T 50.0%
210mV
07674-158
CHANNEL 1
FREQ = 20.25kHz
1.03V p-p
Figure 75. Zipper Noise Detector
analog.com
Rev. G | 31 of 33
Data Sheet
AD5291/AD5292
OUTLINE DIMENSIONS
Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Updated: November 10, 2021
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package
Option
AD5291BRUZ-100
AD5291BRUZ-100-RL7
AD5291BRUZ-20
AD5291BRUZ-20-RL7
AD5291BRUZ-50
AD5292BRUZ-100
AD5292BRUZ-100-RL7
AD5292BRUZ-20
AD5292BRUZ-20-RL7
AD5292BRUZ-50
AD5292BRUZ-50-RL7
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
14-Lead TSSOP
Tube, 96
Reel, 1000
Tube, 96
Reel, 1000
Tube, 96
Tube, 96
Reel, 1000
Tube, 96
Reel, 1000
Tube, 96
Reel, 1000
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
RU-14
1
Z = RoHS Compliant Part.
RAB (KΩ) AND RESOLUTION OPTIONS
Model1
RAB (kΩ)
Resolution
AD5291BRUZ-100
AD5291BRUZ-100-RL7
AD5291BRUZ-20
AD5291BRUZ-20-RL7
AD5291BRUZ-50
AD5292BRUZ-100
AD5292BRUZ-100-RL7
AD5292BRUZ-20
AD5292BRUZ-20-RL7
AD5292BRUZ-50
AD5292BRUZ-50-RL7
100
100
20
20
50
100
100
20
20
50
50
256
256
256
256
256
1024
1024
1024
1024
1024
1024
1
Z = RoHS Compliant Part.
analog.com
Rev. G | 32 of 33
Data Sheet
AD5291/AD5292
OUTLINE DIMENSIONS
EVALUATION BOARDS
Model1, 2
Description
EVAL−AD5292DBZ
Evaluation Board
1
Z = RoHS Compliant Part.
2
The EVAL−AD5292DBZ is also used to test the AD5291.
©2009-2022 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. G | 33 of 33
工商网监
湘ICP备2023018690号
