2.5 V to 5.5 V, 120 μA, 2-Wire Interface,
Voltage-Output 8-/10-/12-Bit DACs
AD5301/AD5311/AD5321
Data Sheet
FEATURES
GENERAL DESCRIPTION
AD5301: buffered voltage output 8-bit DAC
AD5311: buffered voltage output 10-bit DAC
AD5321: buffered voltage output 12-bit DAC
6-lead SOT-23 and 8-lead MSOP packages
Micropower operation: 120 μA at 3 V
2-wire (I2C-compatible) serial interface
Data readback capability
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 50 nA at 3 V
Reference derived from power supply
Power-on reset to 0 V
On-chip rail-to-rail output buffer amplifier
3 power-down functions
The AD5301/AD5311/AD53211 are single 8-/10-/12-bit, buffered, voltage-output DACs that operate from a single 2.5 V to
5.5 V supply, consuming 120 μA at 3 V. The on-chip output
amplifier allows rail-to-rail output swing with a slew rate of
0.7 V/μs. It uses a 2-wire (I2C-compatible) serial interface that
operates at clock rates up to 400 kHz. Multiple devices can share
the same bus.
APPLICATIONS
The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
devices incorporate a power-on reset circuit, which ensures that
the DAC output powers up to 0 V and remains there until a
valid write takes place. The devices contain a power-down
feature that reduces the current consumption of the device to
50 nA at 3 V and provides software-selectable output loads
while in power-down mode.
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
The low power consumption in normal operation makes these
DACs ideally suited to portable battery-operated equipment. The
power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V,
reducing to 1 μW in all power-down modes.
FUNCTIONAL BLOCK DIAGRAM
VDD
AD5301/AD5311/AD5321
SCL
REF
SDA
INTERFACE
LOGIC
DAC
REGISTER
8-/10-/12-BIT
DAC
BUFFER
VOUT
A0
A1*
POWER-DOWN
LOGIC
GND
*AVAILABLE ON 8-LEAD VERSION ONLY
PD*
00927-001
RESISTOR
NETWORK
POWER-ON
RESET
Figure 1.
1
Protected by U.S. Patent No. 5684481.
Rev. C
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AD5301/AD5311/AD5321
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Amplifier........................................................................ 13
Applications ....................................................................................... 1
Power-On Reset .......................................................................... 13
General Description ......................................................................... 1
Serial Interface ................................................................................ 14
Functional Block Diagram .............................................................. 1
2-Wire Serial Bus ........................................................................ 14
Revision History ............................................................................... 2
Input Shift Register .................................................................... 14
Specifications..................................................................................... 3
Write Operation.......................................................................... 15
AC Characteristics........................................................................ 5
Read Operation........................................................................... 16
Timing Characteristics ................................................................ 5
Power-Down Modes .................................................................. 17
Absolute Maximum Ratings............................................................ 6
Applications Notes ......................................................................... 18
ESD Caution .................................................................................. 6
Using the REF193/REF195 as a Power Supply ........................ 18
Pin Configurations and Function Descriptions ........................... 7
Bipolar Operation Using the AD5301/ AD5311/AD5321 .... 18
Terminology ...................................................................................... 8
Multiple Devices on One Bus ................................................... 18
Typical Performance Characteristics ............................................. 9
CMOS Driven SCL and SDA Lines.......................................... 18
Theory of Operation ...................................................................... 13
Power Supply Decoupling ......................................................... 19
Digital-to-Analog ....................................................................... 13
Outline Dimensions ....................................................................... 20
Resistor String ............................................................................. 13
Ordering Guide .......................................................................... 21
REVISION HISTORY
6/2016—Rev. B to Rev. C
Changes to Figure 33 and Figure 34 ............................................. 16
Changes to Ordering Guide .......................................................... 22
3/2007—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Table 4 ............................................................................ 6
Changes to Figure 4 Caption ........................................................... 7
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
11/2003—Rev. 0 to Rev. A
Changes to Ordering Guide ............................................................ 4
Updated Outline Dimensions ....................................................... 15
7/1999—Revision 0: Initial Version
Rev. C | Page 2 of 24
Data Sheet
AD5301/AD5311/AD5321
SPECIFICATIONS
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
2
Min
B Version 1
Typ
Max
Unit
Test Conditions/Comments
8
±0.15
±0.02
±1
±0.25
Bits
LSB
LSB
Guaranteed monotonic by design over all codes.
10
±0.5
±0.05
±4
±0.5
Bits
LSB
LSB
Guaranteed monotonic by design over all codes.
DC PERFORMANCE 3, 4
AD5301
Resolution
Relative Accuracy
Differential Nonlinearity
AD5311
Resolution
Relative Accuracy
Differential Nonlinearity
AD5321
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Full-Scale Error
Gain Error
Zero-Code Error Drift 5
Gain Error Drift5
12
±2
±0.3
5
±0.15
±0.15
–20
−5
OUTPUT CHARACTERISTICS5
Minimum Output Voltage
0.001
V
Maximum Output Voltage
VDD − 0.001
V
DC Output Impedance
Short-Circuit Current
1
50
20
2.5
6
Ω
mA
mA
μs
μs
Power-Up Time
LOGIC INPUTS (A0, A1, PD)5
Input Current
Input Low Voltage, VIL
Input High Voltage, VIH
μA
V
V
V
V
V
V
pF
VDD + 0.3
+0.3 × VDD
±1
V
V
μA
V
pF
ns
3
0.7 × VDD
−0.3
Bits
LSB
LSB
mV
% of FSR
% of FSR
μV/°C
ppm of
FSR/°C
±1
0.8
0.6
0.5
2.4
2.1
2.0
Pin Capacitance
LOGIC INPUTS (SCL, SDA)5
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIN
Input Hysteresis, VHYST
Input Capacitance, CIN
Glitch Rejection 6
±16
±0.8
20
±1.25
±1
0.05 × VDD
6
50
Rev. C | Page 3 of 24
Guaranteed monotonic by design over all codes.
All zeros loaded to DAC, see Figure 12.
All ones loaded to DAC, see Figure 12.
This is a measure of the minimum drive capability of the
output amplifier.
This is a measure of the maximum drive capability of the
output amplifier.
VDD = 5 V.
VDD = 3 V.
Coming out of power-down mode. VDD = 5 V.
Coming out of power-down mode. VDD = 3 V.
VDD = 5 V ± 10%.
VDD = 3 V ± 10%.
VDD = 2.5 V.
VDD = 5 V ± 10%.
VDD = 3 V ± 10%.
VDD = 2.5 V.
VIN = 0 V to VDD.
Pulse width of spike suppressed.
AD5301/AD5311/AD5321
Parameter
2
Min
Data Sheet
B Version 1
Typ
Max
Unit
Test Conditions/Comments
0.4
0.6
±1
V
V
μA
ISINK = 3 mA.
ISINK = 6 mA.
LOGIC OUTPUT (SDA)5
Output Low Voltage, VOL
Three-State Leakage
Current
Three-State Output
Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
6
2.5
pF
5.5
V
150
120
250
220
μA
μA
IDD specification is valid for all DAC codes.
DAC active and excluding load current.
VIH = VDD and VIL = GND.
VIH = VDD and VIL = GND.
0.2
0.05
1
1
μA
μA
VIH = VDD and VIL = GND.
VIH = VDD and VIL = GND.
Temperature range is as follows: B Version: −40°C to +105°C.
See the Terminology section.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); and AD5321 (Code 112 to 4000).
5
Guaranteed by design and characterization, not production tested.
6
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
1
2
Rev. C | Page 4 of 24
Data Sheet
AD5301/AD5311/AD5321
AC CHARACTERISTICS1
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
3
Parameter
Output Voltage Settling Time
AD5301
AD5311
AD5321
Slew Rate
Major-Code Change Glitch Impulse
Digital Feedthrough
B Version2
Min
Typ
Max
Unit
6
7
8
0.7
12
0.3
μs
μs
μs
V/μs
nV-s
nV-s
8
9
10
Test Conditions/Comments
VDD = 5 V
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 to 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
1 LSB change around major carry
1
See the Terminology section.
Temperature range for the B Version is as follows: –40°C to +105°C.
3
Guaranteed by design and characterization, not production tested.
2
TIMING CHARACTERISTICS1
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter2
fSCL
t1
t2
t3
t4
t5
t63
t7
t8
t9
t10
t11
Cb
Limit at TMIN,
TMAX, B Version
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
300
20 + 0.1Cb5
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns max
ns min
pF max
Test Conditions/Comments
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tSU,STA, setup time for repeated start
tSU,STO, stop condition setup time
tBUF, bus free time between a stop condition and a start condition
tR, rise time of both SCL and SDA when receiving4
May be CMOS driven
tF, fall time of SDA when receiving4
tF, fall time of both SCL and SDA when transmitting4
Capacitive load for each bus line
1
See Figure 2.
Guaranteed by design and characterization, not production tested.
A master device must provide a hold time of at least 300 ns for the SDA signal (refer to the VIH MIN of the SCL signal) in order to bridge the undefined region of the
falling edge of the SCL.
4
tR and tF measured between 0.3 VDD and 0.7 VDD.
5
Cb is the total capacitance of one bus line in picofarads.
2
3
SDA
t9
t3
t11
t10
t4
SCL
t6
t2
t5
START
CONDITION
t1
t7
REPEATED
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. C | Page 5 of 24
t8
STOP
CONDITION
00927-002
t4
AD5301/AD5311/AD5321
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4.
Parameter
VDD to GND
SCL, SDA to GND
PD, A1, A0 to GND
VOUT to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature (TJ max)
SOT-23 Package
Power Dissipation
θJA Thermal Impedance
MSOP Package
Power Dissipation
θJA Thermal Impedance
Lead Temperature
Soldering
1
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
ESD CAUTION
−40°C to +105°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
229.6°C/W
(TJ max – TA)/θJA
206°C/W
JEDEC Industry Standard
J-STD-020
Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. C | Page 6 of 24
Data Sheet
AD5301/AD5311/AD5321
A0 2
A1 3
VOUT 4
AD5301/
AD5311/
AD5321
TOP VIEW
(Not to Scale)
8
GND
7
SDA
6
SCL
5
PD
00927-004
VDD 1
GND
1
SDA
2
SCL 3
Figure 3. 8-Lead MSOP (RM-8) Pin Configuration
AD5301/
AD5311/
AD5321
TOP VIEW
(Not to Scale)
6
VDD
5
A0
4
VOUT
00927-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. 6-Lead SOT-23 (RJ-6) Pin Configuration
Table 5. Pin Function Descriptions
MSOP
1
Pin No.
SOT-23
6
Mnemonic
VDD
2
3
4
5
5
Not applicable
4
Not applicable
A0
A1
VOUT
PD
6
3
SCL
7
2
SDA
8
1
GND
Description
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be
decoupled with a 10 μF in parallel with a 0.1 μF capacitor to GND.
Address Input. Sets the least significant bit of the 7-bit slave address.
Address Input. Sets the second least significant bit of the 7-bit slave address.
Buffered Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software
power-down option. The DAC output goes three-state and the current consumption of the part
drops to 50 nA at 3 V (200 nA at 5 V).
Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input
shift register. Clock rates of up to 400 kbps can be accommodated in the I2C-compatible interface.
SCL may be CMOS/TTL driven.
Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input
shift register during the write cycle and to read back one or two bytes of data (one byte for the
AD5301, two bytes for the AD5311/AD5321) during the read cycle. It is a bidirectional open-drain
data line that should be pulled to the supply with an external pull-up resistor. If not used in
readback mode, SDA may be CMOS/TTL driven.
Ground Reference Point for All Circuitry on the Device.
Rev. C | Page 7 of 24
AD5301/AD5311/AD5321
Data Sheet
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL vs. code plots can be seen in Figure 5 to
Figure 7.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures monotonicity. These DACs are guaranteed monotonic by design over all
codes. Typical DNL vs. code plots can be seen in Figure 8 to
Figure 10.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x00) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error of the AD5301/AD5311/
AD5321 is always positive because the output of the DAC
cannot go below 0 V, due to a combination of the offset errors
in the DAC and output amplifier. It is expressed in millivolts
(see Figure 12).
Full-Scale Error (FSR)
Full-scale error is a measure of the output error when full
scale is loaded to the DAC register. Ideally, the output should
be VDD – 1 LSB. Full-scale error is expressed in percent of FSR.
A plot can be seen in Figure 12.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic from
the ideal expressed as a percentage of the full-scale range.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Major Code Transition Glitch Energy
Major code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC register
changes state. It is normally specified as the area of the glitch in
nV-s and is measured when the digital code is changed by 1 LSB
at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00
to 011 . . . 11).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to. It
is specified in nV-s and is measured with a full-scale change on
the digital input pins, that is, from all 0s to all 1s and vice versa.
Rev. C | Page 8 of 24
Data Sheet
AD5301/AD5311/AD5321
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.3
TA = 25°C
VDD = 5V
TA = 25°C
VDD = 5V
0.2
DNL ERROR (LSB)
INL ERROR (LSB)
0.5
0
0.1
0
–0.1
–0.5
0
50
100
150
200
255
CODE
–0.3
00927-005
0
0.6
TA = 25°C
VDD = 5V
0.4
1
0.2
DNL ERROR (LSB)
INL ERROR (LSB)
150
200
255
Figure 8. AD5301 Typical DNL Plot
2
0
–1
–2
TA = 25°C
VDD = 5V
0
–0.2
–0.4
0
200
400
600
800
1023
CODE
–0.6
00927-006
–3
100
CODE
Figure 5. AD5301 Typical INL Plot
3
50
0
400
600
800
1023
CODE
Figure 6. AD5311 Typical INL Plot
3
200
00927-009
–1.0
00927-008
–0.2
Figure 9. AD5311 Typical DNL Plot
1.0
TA = 25°C
VDD = 5V
TA = 25°C
VDD = 5V
2
DNL ERROR (LSB)
0
–4
0
–0.5
–12
0
1000
2000
CODE
3000
4095
–1.0
Figure 7. AD5321 Typical INL Plot
0
1000
2000
CODE
3000
Figure 10. AD5321 Typical DNL Plot
Rev. C | Page 9 of 24
4095
00927-010
–8
00927-007
INL ERROR (LSB)
0.5
1
AD5301/AD5311/AD5321
Data Sheet
1.00
5
VDD = 5V
0.75
5V SOURCE
4
0.50
MAX INL
MAX DNL
VOUT (V)
ERROR (LSB)
0.25
0
–0.25
3
3V SOURCE
2
3V SINK
MIN DNL
–0.50
5V SINK
MIN INL
1
0
40
80
120
TEMPERATURE (°C)
–0
00927-011
–1.00
–40
0
3
12
15
Figure 14. Source and Sink Current Capability
10
200
VDD = 5V
180
6
TA= 25°C
160
ZERO CODE
4
140
2
120
IDD (µA)
0
–2
–4
VDD
= 5V
V
DD = 5V
100
VDD = 3V
80
60
FULL SCALE
–6
40
–8
20
–20
0
20
40
60
80
0
00927-012
–10
–40
100
TEMPERATURE (°C)
ZERO SCALE
FULL SCALE
CODE
Figure 12. Zero-Code Error and Full-Scale Error vs. Temperature
00927-015
ERROR (mV)
9
I (mA)
Figure 11. AD5301 INL Error and DNL Error vs. Temperature
8
6
00927-014
–0.75
Figure 15. Supply Current vs. Code
200
150
FREQUENCY (Hz)
VDD = 3V
VDD = 5V
IDD (µA)
–40°C
100
+105°C
+25°C
100
120
140
160
190
IDD (µA)
200
0
2.7
00927-013
80
Figure 13. IDD Histogram with VDD = 3 V and VDD = 5 V
3.2
3.7
4.2
VDD (V)
4.7
Figure 16. Supply Current vs. Supply Voltage
Rev. C | Page 10 of 24
5.2
00927-016
50
Data Sheet
AD5301/AD5311/AD5321
1.0
VDD = 5V
TA = 25°C
LOAD = 2kΩ AND
200pF TO GND
0.8
IDD (µA)
0.6
0.4
VOUT
1
+25°C
–40°C
0.2
3.7
4.2
VDD (V)
4.7
5.2
CH1 1V, TIME BASE = 5µs/DIV
Figure 17. Power-Down Current vs. Supply Voltage
00927-019
+105°C
3.2
00927-017
0
2.7
Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Charge)
300
TA = 25°C
TA = 25°C
250
VDD
VDD = 5V
INCREASING
DECREASING
150
100
VDD = 3V
CH1
50
0
0
1.0
2.0
3.0
VLOGIC (V)
4.0
5.0
00927-018
CH2
Figure 18. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage
Increasing and Decreasing
Rev. C | Page 11 of 24
VOUT
CH1 1V, CH2 1V, TIME BASE = 20µs/DIV
Figure 20. Power-On Reset to 0 V
00927-020
IDD (µA)
200
AD5301/AD5311/AD5321
Data Sheet
2.440
TA = 25°C
VDD = 5V
2.445
VOUT (V)
VOUT
CH1
2.450
CH2
00927-021
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
2.455
1ns/DIV
Figure 21. Exiting Power-Down to Midscale
Figure 23. Digital Feedthrough
2.50
VOUT (V)
2.49
2.47
1µs/DIV
00927-022
2.48
Figure 22. Major-Code Transition
Rev. C | Page 12 of 24
00927-023
CLK
Data Sheet
AD5301/AD5311/AD5321
THEORY OF OPERATION
The AD5301/AD5311/AD5321 are single resistor-string DACs
fabricated on a CMOS process with resolutions of 8/10/12 bits,
respectively. Data is written via a 2-wire serial interface. The
devices operate from single supplies of 2.5 V to 5.5 V and the
output buffer amplifiers provide rail-to-rail output swing with
a slew rate of 0.7 V/μs. The power supply (VDD) acts as the
reference to the DAC. The AD5301/AD5311/AD5321 have
three programmable power-down modes, in which the DAC
can be turned off completely with a high impedance output,
or the output can be pulled low by an on-chip resistor (see the
Power-Down Modes section).
RESISTOR STRING
The resistor string section is shown in Figure 25. It is simply
a string of resistors, each with a value of R. The digital code
loaded to the DAC register determines at what node on the
string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches
connecting the string to the amplifier. Because it is a string
of resistors, it is guaranteed monotonic over all codes.
R
R
DIGITAL-TO-ANALOG
The architecture of the DAC channel consists of a resistor string
DAC followed by an output buffer amplifier. The voltage at the
VDD pin provides the reference voltage for the DAC. Figure 24
shows a block diagram of the DAC architecture. Since the input
coding to the DAC is straight binary, the ideal output voltage is
given by
VOUT
V DD D
R
00927-025
R
Figure 25. Resistor String
OUTPUT AMPLIFIER
2N
where:
N = DAC resolution.
D = decimal equivalent of the binary code that is loaded to the
DAC register:
0–255 for AD5301 (8 bits)
0–1023 for AD5311 (10 bits)
0–4095 for AD5321 (12 bits).
RESISTOR
STRING
POWER-ON RESET
OUTPUT BUFFER
AMPLIFIER
VOUT
REF(–)
GND
Figure 24. DAC Channel Architecture
The AD5301/AD5311/AD5321 are provided with a power-on
reset function, ensuring that they power up in a defined state.
00927-024
REF(+)
The output buffer amplifier is capable of generating output voltages to within 1 mV from either rail, which gives an output range
of 0.001 V to VDD − 0.001 V. It is capable of driving a load of
2 kΩ to GND and VDD, in parallel with 500 pF to GND. The
source and sink capabilities of the output amplifier can be seen
in Figure 14.
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at 8 bits) of 6 μs with the output unloaded.
VDD
DAC
REGISTER
TO OUTPUT
AMPLIFIER
R
The DAC register is filled with zeros and remains so until a
valid write sequence is made to the device. This is particularly
useful in applications where it is important to know the state
of the DAC output while the device is powering up.
Rev. C | Page 13 of 24
AD5301/AD5311/AD5321
Data Sheet
SERIAL INTERFACE
SCL is high. In write mode, the master pulls the SDA line
high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for
the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the 10th
clock pulse and then high during the 10th clock pulse to
establish a stop condition.
2-WIRE SERIAL BUS
2
The AD5301/AD5311/AD5321 are controlled via an I Ccompatible serial bus. The DACs are connected to this bus
as slave devices (no clock is generated by the AD5301/AD5311/
AD5321 DACs).
The AD5301/AD5311/AD5321 has a 7-bit slave address. In
the case of the 6-lead device, the six MSBs are 000110 and the
LSB is determined by the state of the A0 pin. In the case of the
8-lead device, the five MSBs are 00011 and the two LSBs are
determined by the state of the A0 and A1 pins. A1 and A0
allow the user to use up to four of these DACs on one bus.
In the case of the AD5301/AD5311/AD5321, a write operation
contains two bytes whereas a read operation may contain one or
two bytes. See Figure 29 to Figure 34 for a graphical explanation
of the serial interface.
A repeated write function gives the user flexibility to update the
DAC output a number of times after addressing the device only
once. During the write cycle, each multiple of two data bytes
updates the DAC output. For example, after the DAC acknowledges its address byte, and receives two data bytes; the DAC
output updates after the two data bytes, if another two data
bytes are written to the DAC while it is still the addressed slave
device. These data bytes also cause an output update. A repeat
read of the DAC is also allowed.
The 2-wire serial bus protocol operates as follows:
4.
The input shift register is 16 bits wide. Figure 26, Figure 27,
and Figure 28 illustrate the contents of the input shift register
for each device. Data is loaded into the device as a 16-bit word
under the control of a serial clock input, SCL. The timing
diagram for this operation is shown in Figure 2. The 16-bit
word consists of four control bits followed by 8/10/12 bits of
data, depending on the device type. MSB (Bit 15) is loaded first.
The first two bits are don’t cares. The next two are control bits
that control the mode of operation of the device (normal mode
or any one of three power-down modes). See the Power-Down
Modes section for a complete description. The remaining bits
are left justified DAC data bits, starting with the MSB and
ending with the LSB.
DB15 (MSB)
X
X
DB0 (LSB)
PD1 PD0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
DATA BITS
00927-026
3.
INPUT SHIFT REGISTER
Figure 26. AD5301 Input Shift Register Contents
DB15 (MSB)
X
X
DB0 (LSB)
PD1 PD0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
DATA BITS
00927-037
2.
The master initiates data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte that consists of the 7-bit slave address
followed by an R/W bit (this bit determines whether data
is read from or written to the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master reads
from the slave device. However, if the R/W bit is low, the
master writes to the slave device.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL.
When all data bits have been read or written, a stop condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line while
Figure 27. AD5311 Input Shift Register Contents
DB15 (MSB)
X
X
DB0 (LSB)
PD1 PD0
D11
D10
D9
D8
D7
D6
D5
D4
D3
DATA BITS
Figure 28. AD5321 Input Shift Register Contents
Rev. C | Page 14 of 24
D2
D1
D0
00927-038
1.
Data Sheet
AD5301/AD5311/AD5321
SDA low. This address byte is followed by the 16-bit word in the
form of two control bytes. The write operations for the three
DACs are shown in Figure 29 to Figure 31.
WRITE OPERATION
When writing to the AD5301/AD5311/AD5321 DACs, the
user must begin with an address byte, after which the DAC
acknowledges that it is prepared to receive data by pulling
SCL
SDA
0
0
START
COND
BY
MASTER
0
1
1
A1*
A0
X
R/W
X
ACK
BY
AD5301
ADDRESS BYTE
PD1
PD0
D7
D6
D5
D4
ACK
BY
AD5301
MOST SIGNIFICANT CONTROL BYTE
SCL
D3
D2
D1
D0
X
X
X
X
ACK
BY
AD5301
LEAST SIGNIFICANT CONTROL BYTE
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
STOP
COND
BY
MASTER
00927-027
SDA
Figure 29. AD5301 Write Sequence
SCL
SDA
0
0
START
COND
BY
MASTER
0
1
1
A1*
A0
X
R/W
X
ACK
BY
AD5311
ADDRESS BYTE
PD1
PD0
D9
D8
D7
D6
ACK
BY
AD5311
MOST SIGNIFICANT CONTROL BYTE
SCL
D5
D4
D3
D2
D1
D0
X
X
ACK
BY
AD5311
LEAST SIGNIFICANT CONTROL BYTE
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
STOP
COND
BY
MASTER
00927-028
SDA
Figure 30. AD5311 Write Sequence
SCL
SDA
0
0
START
COND
BY
MASTER
0
1
1
A1*
A0
X
R/W
X
ACK
BY
AD5321
ADDRESS BYTE
PD1
PD0
D11
D10
MOST SIGNIFICANT CONTROL BYTE
D9
D8
ACK
BY
AD5321
SCL
D7
D6
D5
D4
D3
D2
D1
LEAST SIGNIFICANT CONTROL BYTE
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
D0
ACK
BY
AD5321
STOP
COND
BY
MASTER
Figure 31. AD5321 Write Sequence
Rev. C | Page 15 of 24
00927-029
SDA
AD5301/AD5311/AD5321
Data Sheet
the eight data bits in the DAC register. However, in the case
of the AD5311 and AD5321, the readback consists of two bytes
that contain both the data and the power-down mode bits. The
read operations for the three DACs are shown in Figure 32 to
Figure 34.
READ OPERATION
When reading data back from the AD5301/AD5311/AD5321
DACs, the user must begin with an address byte after which
the DAC acknowledges that it is prepared to transmit data by
pulling SDA low. There are two different read operations. In the
case of the AD5301, the readback is a single byte that consists of
SCL
0
0
START
COND
BY
MASTER
0
1
A1*
1
A0
R/W
D7
D6
D5
ACK
BY
AD5301
ADDRESS BYTE
D4
D3
D2
D1
D0
NO ACK
BY
MASTER
DATA BYTE
STOP
COND
BY
MASTER
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
Figure 32. AD5301 Readback Sequence
SCL
SDA
0
0
0
START
COND
BY
MASTER
1
1
A1*
A0
R/W
X
X
ACK
BY
AD5311
ADDRESS BYTE
PD1
PD0
D9
D8
D7
D6
ACK
BY
MASTER
MOST SIGNIFICANT BYTE
SCL
D4
D3
D2
D1
D0
X
X
NO ACK
BY
MASTER
LEAST SIGNIFICANT CONTROL BYTE
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
STOP
COND
BY
MASTER
00927-031
D5
SDA
Figure 33. AD5311 Readback Sequence
SCL
SDA
0
0
START
COND
BY
MASTER
0
1
1
A1*
A0
X
R/W
X
ACK
BY
AD5321
ADDRESS BYTE
PD1
PD0
D11
MOST SIGNIFICANT BYTE
D10
D9
D8
ACK BY
MASTER
SCL
D7
D6
D5
D4
D3
D2
D1
D0
NO ACK
BY
MASTER
LEAST SIGNIFICANT BYTE
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
STOP
COND
BY
MASTER
Figure 34. AD5321 Readback Sequence
Rev. C | Page 16 of 24
00927-032
SDA
00927-030
SDA
Data Sheet
AD5301/AD5311/AD5321
POWER-DOWN MODES
The AD5301/AD5311/AD5321 have very low power consumption, dissipating typically 0.36 mW with a 3 V supply and 0.75 mW
with a 5 V supply. Power consumption can be further reduced
when the DAC is not in use by putting it into one of three
power-down modes, which are selected by Bit 13 and Bit 12 (PD1
and PD0) of the control word. Table 6 shows how the state of
the bits corresponds to the mode of operation of the DAC.
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the device is known
while the device is in power-down mode and provides a defined
input condition for whatever is connected to the output of the
DAC amplifier. There are three different options. The output is
connected internally to GND through a 1 kΩ resistor, a 100 kΩ
resistor, or it is left three-stated. Resistor tolerance = ±20%.
The output stage is illustrated in Figure 35.
AMPLIFIER
Table 6. PD1 and PD0 Operating Modes
PD0
0
1
0
1
Operating Mode
Normal operation
Power-down (1 kΩ load to GND)
Power-down (100 kΩ load to GND)
Power-down (three-state output)
VOUT
POWER-DOWN
CIRCUITRY
The software power-down modes programmed by PD1 and
PD0 may be overridden by the PD pin on the 8-lead version.
Taking this pin low puts the DAC into three-state power-down
mode. If PD is not used, tie it high.
When both bits are set to 0, the DAC works normally with its
normal power consumption of 150 μA at 5 V, while for the three
power-down modes, the supply current falls to 200 nA at 5 V
(50 nA at 3 V). Not only does the supply current drop, but the
RESISTOR
NETWORK
00927-033
PD1
0
0
1
1
REGISTER
STRING DAC
Figure 35. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
DAC register are unchanged when in power-down. The time to
exit power-down is typically 2.5 μs for VDD = 5 V and 6 μs when
VDD = 3 V (see Figure 21).
Rev. C | Page 17 of 24
AD5301/AD5311/AD5321
Data Sheet
APPLICATIONS NOTES
R2
10kΩ
USING THE REF193/REF195 AS A POWER SUPPLY
Because the supply current required by the AD5301/AD5311/
AD5321 is extremely low, the user has an alternative option to
employ a REF195 voltage reference (for 5 V) or a REF193 voltage
reference (for 3 V) to supply the required voltage to the device
(see Figure 36).
REF195
R1
10kΩ
±5V
+5V
AD820/
OP295
AD5301/
AD5311/
AD5321
VDD
5V
10µF
150µA TYP
+5V
–5V
VOUT
0.1µF
AD5301/
AD5311/
AD5321
VOUT = 0V TO 5V
2-WIRE SERIAL
INTERFACE
00927-034
2-WIRE SDA
SERIAL
INTERFACE SCL
00927-035
VDD
Figure 37. Bipolar Operation with the AD5301/AD5311/AD5321
The output voltage for any input code can be calculated as
Figure 36. REF195 as Power Supply to AD5301/AD5311/AD5321
This is especially useful if the power supply is quite noisy or if
the system supply voltages are at some value other than 5 V or
3 V (for example, 15 V). The REF193/REF195 output a steady
supply voltage for the AD5301/AD5311/AD5321. If the low
dropout REF195 is used, it needs to supply a current of 150 μA
to the AD5301/AD5311/AD5321. This is with no load on the
output of the DAC. When the DAC output is loaded, the REF195
also needs to supply the current to the load.
The total current required (with a 2 kΩ load on the DAC output
and full scale loaded to the DAC) is
150 μA + (5 V/2 kΩ) = 2.65 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 5.3 ppm (26.5 μV) for the 2.65 mA
current drawn from it. This corresponds to a 0.00136 LSB error.
BIPOLAR OPERATION USING THE AD5301/
AD5311/AD5321
The AD5301/AD5311/AD5321 has been designed for singlesupply operation, but a bipolar output range is also possible
using the circuit in Figure 37. The circuit below gives an output
voltage range of ±5 V. Rail-to-rail operation at the amplifier
output is achievable using an AD820 or an OP295 as the output
amplifier.
VOUT = ((VDD × (D/2N) × R1 + R2)/R1) − VDD × (R2/R1))
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
With VDD = 5 V, R1 = R2 = 10 kΩ,
VOUT = (10 × D/2N) − 5 V
MULTIPLE DEVICES ON ONE BUS
Figure 38 shows four AD5301 devices on the same serial bus.
Each has a different slave address since the state of their A0
and A1 pins is different. This allows each DAC to be written to
or read from independently. The master device output bus line
drivers are open-drain, pull-downs in a fully I2C-compatible
interface.
CMOS DRIVEN SCL AND SDA LINES
For single or multisupply systems where the minimum SCL
swing requirements allow it, a CMOS SCL driver may be used,
and the SCL pull-up resistor can be removed, making the SCL
bus line fully CMOS compatible. This reduces power consumption in both the SCL driver and receiver devices. The SDA line
remains open-drain, I2C compatible.
Further changes, in the SDA line driver, may be made to make
the system more CMOS compatible and save more power. As
the SDA line is bidirectional, it cannot be made fully CMOS
compatible. A switched pull-up resistor can be combined with
a CMOS device with an open-circuit (three-state) input such
that the CMOS SDA driver is enabled during write cycles and
I2C mode is enabled during shared cycles, that is, readback,
acknowledge bit cycles, start conditions, and stop conditions.
Rev. C | Page 18 of 24
Data Sheet
AD5301/AD5311/AD5321
POWER SUPPLY DECOUPLING
ground at high frequencies. The power supply lines of the
AD5301/AD5311/AD5321 should use as large a trace as
possible to provide low impedance paths. A ground line routed
between the SDA and SCL lines helps reduce crosstalk between
them. This is not required on a multilayer board as there is a
ground plane layer, but separating the lines helps.
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The AD5301/AD5311/AD5321
should be decoupled to GND with 10 μF in parallel with a 0.1 μF
capacitor, located as close to the package as possible. The 10 μF
capacitor should be the tantalum bead type, while a ceramic
0.1 μF capacitor provides a sufficient low impedance path to
5V
RP
RP
SDA
MASTER
SCL
SCL
VOUT
A0
AD5301
VDD
SDA
A1
SCL
VOUT
A0
VDD
SDA
A1
SCL
VOUT
A0
AD5301
AD5301
Figure 38. Multiple AD5301 Devices on One Bus
Rev. C | Page 19 of 24
SDA
A1
SCL
VOUT
A0
AD5301
00927-036
VDD
SDA
A1
AD5301/AD5311/AD5321
Data Sheet
OUTLINE DIMENSIONS
2.90 BSC
6
5
4
1
2
3
2.80 BSC
1.60 BSC
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.50
0.30
0.15 MAX
0.22
0.08
10°
4°
0°
SEATING
PLANE
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 39. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5
5.15
4.90
4.65
4
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 40. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. C | Page 20 of 24
0.80
0.60
0.40
Data Sheet
AD5301/AD5311/AD5321
ORDERING GUIDE
Model 1
AD5301BRMZ
AD5301BRMZ-REEL7
AD5301BRTZ-500RL7
AD5301BRTZ-REEL7
AD5311BRMZ
AD5311BRMZ-REEL
AD5311BRMZ-REEL7
AD5311BRTZ-500RL7
AD5311BRTZ-REEL7
AD5321BRM
AD5321BRM-REEL7
AD5321BRMZ
AD5321BRMZ-REEL
AD5321BRMZ-REEL7
AD5321BRTZ-500RL7
AD5321BRTZ-REEL7
1
Temperature Range
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
Package Description
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
6-Lead Small Outline Transistor Package [SOT-23]
6-Lead Small Outline Transistor Package [SOT-23]
Z = RoHS Compliant Part.
Rev. C | Page 21 of 24
Package Option
RM-8
RM-8
RJ-6
RJ-6
RM-8
RM-8
RM-8
RJ-6
RJ-6
RM-8
RM-8
RM-8
RM-8
RM-8
RJ-6
RJ-6
Branding
D8B
D8B
D8B
D8B
D9B
D9B
D9B
D9B
D9B
DAB
DAB
DAB
DAB
DAB
DAB
DAB
AD5301/AD5311/AD5321
Data Sheet
NOTES
Rev. C | Page 22 of 24
Data Sheet
AD5301/AD5311/AD5321
NOTES
Rev. C | Page 23 of 24
AD5301/AD5311/AD5321
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©1999–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00927-0-6/16(C)
Rev. C | Page 24 of 24
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