AD5384BBCZ-5REEL7

40-Channel, 3 V/5 V, Single-Supply, Serial, 14-Bit denseDAC® AD5384 Data Sheet FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic Relative accuracy (INL): ±4 LSB maximum On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: −40°C to +85°C Rail-to-rail output amplifier Power-down Package type: 100-ball CSP_BGA User interfaces Serial (SPI-/QSPI™-/MICROWIRE®-/DSP-compatible, featuring data readback) I2C-compatible Channel monitor Simultaneous output update via LDAC Clear function to user programmable code Amplifier boost mode to optimize slew rate User programmable offset and gain adjust Toggle mode enables square wave generation Thermal monitor APPLICATIONS Variable optical attenuators (VOAs) Level settings (automatic test equipment [ATE]) Optical micro-electromechanical systems (MEMS) control systems Instrumentation FUNCTIONAL BLOCK DIAGRAM DVDDx DGND AVDDx AGNDx DAC_GNDx REF_GND REF_OUT/REF_IN SIGNAL_GNDx PD SYNC/AD0 AD5384 1.25V/2.5V REFERENCE DCEN/AD1 14 INPUT 14 REG 0 14 SDO DIN/SDA SCLK/SCL SPI/I2C 14 INTERFACE CONTROL LOGIC STATE MACHINE + CONTROL LOGIC 14 DAC 14 REG 0 DAC 0 VOUT0 m REG 0 R c REG 0 R 14 INPUT 14 REG 1 14 14 14 DAC 14 REG 1 DAC 1 VOUT1 VOUT2 m REG 1 R c REG 1 VOUT3 R VOUT4 14 14 14 BUSY 14 DAC 14 REG 6 VOUT5 DAC 6 VOUT6 m REG 6 R c REG 6 R CLR 14 VOUT0……VOUT38 INPUT 14 REG 7 14 39-TO-1 MUX 14 14 DAC 14 REG 7 DAC 7 VOUT7 VOUT8 m REG 7 R c REG 7 R ×5 VOUT39/MON_OUT VOUT38 LDAC 04652-001 RESET POWER-ON RESET INPUT 14 REG 6 Figure 1. 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Technical Support www.analog.com AD5384 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Reset Function ............................................................................ 23 Integrated Functions ........................................................................ 1 Asynchronous Clear Function.................................................. 23 Applications ....................................................................................... 1 BUSY and LDAC Functions...................................................... 23 Functional Block Diagram .............................................................. 1 Power-On Reset .......................................................................... 23 Revision History ............................................................................... 2 Power-Down Feature ................................................................. 23 General Description ......................................................................... 3 Power Supply Sequencing ......................................................... 23 Specifications..................................................................................... 4 Interfaces.......................................................................................... 24 AC Characteristics........................................................................ 6 DSP-, SPI-, Microwire-Compatible Serial Interface .............. 24 Timing Characteristics ................................................................ 7 I2C Serial Interface ..................................................................... 26 Absolute Maximum Ratings.......................................................... 10 Applications Information .............................................................. 29 ESD Caution ................................................................................ 10 Power Supply Decoupling ......................................................... 29 Pin Configuration and Function Descriptions ........................... 11 Power Supply Sequencing ......................................................... 29 Typical Performance Characteristics ........................................... 15 Monitor Function ....................................................................... 30 Terminology .................................................................................... 18 Toggle Mode Function............................................................... 30 Functional Description .................................................................. 19 Thermal Monitor Function ....................................................... 31 DAC Architecture—General ..................................................... 19 AD5384 in a MEMS-Based Optical Switch ............................ 31 Data Decoding ............................................................................ 19 Optical Attenuators .................................................................... 32 On-Chip Special Function Registers (SFR) ............................ 20 Outline Dimensions ....................................................................... 33 SFR Commands .......................................................................... 20 Ordering Guide .......................................................................... 33 Hardware Functions ....................................................................... 23 REVISION HISTORY 6/14—Rev. B to Rev. C Changed 100-Lead Package to 100-Ball Package ...... Throughout Added Power Supply Sequencing Section and Figure 30 through Figure 33; Renumbered Sequentially ........................................... 29 1/14—Rev. A to Rev. B Updated Format .................................................................. Universal Changed DVDD to DVDDX, AVDD to AVDDx, AGND to AGNDX, VOUT to VOUTX, REFIN TO REF_IN, REFOUT to REF_OUT, SCLK to SCLK/SCL, DAC GND to DAC_GND, SIGNAL GND to SIGNAL_GND, REFGND to REF_GND, SYNC/AD 0 to SYNC/AD0, DCEN/AD 1 to DCEN/AD1, DIN to DIN/SDA ........................................................... Throughout Changes to Title and Features Section ........................................... 1 Deleted Table 1 and Table 2; Renumbered Sequentially ............. 3 Changes to Table 1 ............................................................................ 4 Changed AVDD = 2.7 V to 3.6 V to AVDD = 4.5 V to 5.5 V, AC Characteristics Section .............................................................. 6 Changes to Table 2 ............................................................................ 6 Deleted AD5384-3 Specifications Section and Table 5 ............... 7 Changes to Serial Interface Section and Table 3 ........................... 7 Deleted AC Characteristics Section and Table 6 .......................... 9 Change to I2C Serial Interface Section ........................................... 9 Changes to Absolute Maximum Ratings Section and Table 5 ....... 10 Changes to Table 6 .......................................................................... 11 Changes to Figure 9, Figure 10, and Figure 12 ........................... 15 Changes to Figure 14, Figure 15, Figure 16, and Figure 18....... 16 Deleted Table 11 ............................................................................. 15 Changes to Terminology Section ................................................. 18 Deleted Figure 11; Renumbered Sequentially ............................ 18 Changes to Soft Reset Section....................................................... 20 Changes to Control Register Contents ........................................ 21 Deleted Figure 23............................................................................ 20 Changes to Table 14 ....................................................................... 22 Changes to Reset Function Section, Asynchronous Clear Function Section, and Power-On Reset Section ........................ 23 Added Power Supply Sequencing Section................................... 23 Deleted Microprocessor Interfacing Section, AD5384 to MC68HC11 Section, Figure 32, AD5384 to PIC16C6x/7x Section, Figure 33, AD5384 to 8051 Section, Figure 34, AD5384 to ADSP-2101/ADSP-2103 Section, and Figure 35 ................... 31 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 32 10/04—Rev. 0 to Rev. A Changes to Table 19 ....................................................................... 24 Changes to Ordering Guide .......................................................... 35 7/04—Revision 0: Initial Version Rev. C | Page 2 of 33 Data Sheet AD5384 GENERAL DESCRIPTION The AD5384 is a complete single-supply, 40-channel, 14-bit digital-to-analog converter (DAC) available in a 100-ball CSP_BGA package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5384 includes an internal 1.25 V/2.5 V, 10 ppm/°C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier boost mode that allows the amplifier slew rate to be optimized. The AD5384 contains a serial interface compatible with SPI, QSPI, MICROWIRE, and DSP interface standards with interface speeds in excess of 30 MHz and an I2C-compatible interface supporting 400 kHz data transfer rate. An input register followed by a DAC register provides double buffering, allowing the DAC outputs to be updated independently or simultaneously, using the LDAC input. Each channel has a programmable gain and offset adjust register letting the user fully calibrate any DAC channel. Power consumption is typically 0.25 mA per channel with boost mode off. Rev. C | Page 3 of 33 AD5384 Data Sheet SPECIFICATIONS AVDDx = 4.5 V to 5.5 V; DVDDx = 2.7 V to 5.5 V, AGNDx = DGND = 0 V; external REF_IN = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. The AD5384 is calibrated using an external 2.5 V reference. Temperature range−40°C to +85°C. Table 1. Parameter ACCURACY Resolution Relative Accuracy 1 (INL) Differential Nonlinearity (DNL) Min –1 ±4 +2 Bits LSB LSB ±5 ±0.05 ±0.06 2 1 2.5 ±1 VDD/2 1 mV mV µV/°C % FSR % FSR ppm FSR/°C LSB V 1 MΩ µA V 2.495 2.505 V 1.22 1.28 ±10 ±15 V ppm ppm Ω AVDD 40 ±1 V mA mA 200 1000 0.6 pF pF Ω Reference Temperature Coefficient2 Output Impedance OUTPUT CHARACTERISTICS2 Output Voltage Range1 Short-Circuit Current Load Current Capacitive Load Stability RL = ∞ RL = 5 kΩ DC Output Impedance MONITOR PIN Output Impedance Three-State Leakage Current LOGIC INPUTS (EXCEPT SDA, SCL)2 Input High Voltage, VIH Input Low Voltage, VIL DVDDx > 3.6 V DVDDx ≤ 3.6 V Input Current Pin Capacitance Unit 4 ±4 Gain Temperature Coefficient 2 DC Crosstalk2 REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage Output Voltage Max 14 Zero-Scale Error Offset Error Offset Error Temperature Coefficient Gain Error DC Input Impedance Input Current Reference Range Reference Output 3 Typ 800 0 1 100 Test Conditions/Comments ±1 LSB typical Guaranteed monotonic by design over temperature Measured at Code 32 in the linear region At 25°C TMIN to TMAX ±1% for specified performance, AVDDx = 2 × REF_IN + 50 mV Typically 100 MΩ Typically ±30 nA Enabled via CR10 in the AD5384 control register (CR12) and selects the output voltage At ambient, CR12 = 1, optimized for 2.5 V operation CR12 = 0 Temperature range: 25°C to 85°C Temperature range: −40°C to +85°C kΩ nA DVDDx = 2.7 V to 5.5 V 2 V 0.8 0.6 ±10 10 Rev. C | Page 4 of 33 V V µA pF Total for all pins; TA = TMIN to TMAX Data Sheet Parameter LOGIC INPUTS (SDA, SCL ONLY) Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIN Input Hysteresis, VHYST Input Capacitance, CIN Glitch Rejection AD5384 Min Typ Max 0.7 × DVDDx 0.3 × DVDDx ±1 0.05 × DVDDx 8 50 LOGIC OUTPUTS (BUSY, SDO)2 Output Low Voltage, VOL Test Conditions/Comments V V µA V pF ns SMBus-compatible at DVDDx < 3.6 V SMBus-compatible at DVDDx < 3.6 V Input filtering suppresses noise spikes of less than 50 ns V max V max V min V min µA pF DVDDx = 5 V ± 10%, sinking 200 µA DVDDx = 2.7 V to 3.6 V, sinking 200 µA DVDDx = 5 V ± 10%, sourcing 200 µA DVDDx = 2.7 V to 3.6 V, sourcing 200 µA SDO only SDO only 0.4 0.6 ±1 V V µA pF ISINK = 3 mA ISINK = 6 mA 5.5 5.5 V V 0.375 dB mA/channel 0.475 mA/channel DIDD AIDD (Power-Down) DIDD (Power-Down) 1 20 20 mA µA µA Power Dissipation 80 mW Output High Voltage, VOH 0.4 0.4 Unit DVDDx – 1 DVDDx – 0.5 High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)2 Output Low Voltage, VOL ±1 5 Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDDx DVDDx Power Supply Sensitivity2 ΔMidscale/ΔΑVDDx AIDD 8 4.5 2.7 −85 Outputs unloaded, boost off; 0.25 mA per channel typical Outputs unloaded, boost on; 0.325 mA per channel typical VIH = DVDDx, VIL = DGND Typically 100 nA Typically 1 µA Outputs unloaded, boost off, AVDDx = DVDDx = 5 V Accuracy guaranteed from VOUT = 10 mV to AVDD− 50 mV. Guaranteed by characterization, not production tested. 3 Default on the AD5384 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5384 control register; operating the AD5384 with a 1.25 V reference leads to degraded accuracy specifications. 1 2 Rev. C | Page 5 of 33 AD5384 Data Sheet AC CHARACTERISTICS AVDDx = 4.5 V to 5.5 V; DVDDx = 2.7 V to 5.5 V; AGNDx = DGND = 0 V. Guaranteed by design and characterization, not production tested. Table 2. Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Min Typ Max 3 Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk 1.5 2.5 12 15 100 1 µs µs V/µs V/µs nV-sec mV dB nV-sec Digital Crosstalk 0.8 nV-sec Digital Feedthrough Output Noise 0.1 Hz to 10 Hz 0.1 15 40 nV-sec µV p-p µV p-p 150 100 nV/√Hz nV/√Hz 8 Slew Rate 1 Output Noise Spectral Density At 1 kHz At 10 kHz 1 Unit Program the slew rate via the current boost control bit (CR11). Rev. C | Page 6 of 33 Test Conditions/Comments Boost mode off, CR11 = 0, 1/4 scale to 3/4 scale change settling to ±1 LSB Boost mode off, CR11 = 0 Boost mode off, CR11 = 0 Boost mode off, CR11 = 0 Boost mode on, CR11 = 1 See the Terminology section See the Terminology section Effect of input bus activity on DAC output under test External reference, midscale loaded to DAC Internal reference, midscale loaded to DAC Data Sheet AD5384 TIMING CHARACTERISTICS Serial Interface DVDDx = 2.7 V to 5.5 V; AVDDx = 4.5 V to 5.5 V; AGNDx = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. The AD5384 must remain powered up when part of a multidevice system with a common I2C bus. Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDDx) and are timed from a voltage level of 1.2 V. See Figure 2, Figure 3, Figure 4, and Figure 5. Table 3. Parameter t1 t2 t3 t4 t5 1 t61 t7 t7A t8 t9 t101 t11 t121 t13 t14 t15 t16 t17 t18 t19 t20 2 t212 t222 t23 2 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs ns ns ns ns 36 670 20 20 100 0 100 2000 3 20 40 30 5 8 20 Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th SCLK falling edge to SYNC falling edge Minimum SYNC low time Minimum SYNC high time Minimum SYNC high time in readback mode Data setup time Data hold time 24th SCLK falling edge to BUSY falling edge BUSY pulse width low (single channel update) 24th SCLK falling edge to LDAC falling edge LDAC pulse width low BUSY rising edge to DAC output response time BUSY rising edge to LDAC falling edge LDAC falling edge to DAC output response time DAC output settling time boost mode off CLR pulse width low CLR pulse activation time SCLK rising edge to SDO valid SCLK falling edge to SYNC rising edge SYNC rising edge to SCLK rising edge SYNC rising edge to LDAC falling edge Standalone mode only. Daisy-chain mode only. 200µA IOL VOH (MIN) OR VOL (MAX) TO OUTPUT PIN CL 50pF 200µA IOH Figure 2. Load Circuit for Digital Output Timing Rev. C | Page 7 of 33 04652-003 1 Min 33 13 13 13 13 33 10 140 5 4.5 AD5384 Data Sheet t1 1 SCLK 2 24 t3 t4 t2 24 t5 t6 SYNC t7 t 8 t9 DB0 DIN DB23 t10 BUSY t11 t13 t12 t17 LDAC1 t14 VOUT1 t15 t13 LDAC2 t16 t17 VOUT2 t18 CLR 1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE AFTER BUSY 04652-004 VOUT t19 Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 48 24 t7A SYNC DB23 DIN DB0 DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ DB0 04652-005 DB23 SDO SELECTED REGISTER DATA CLOCKED OUT UNDEFINED Figure 4. Serial Interface Timing Diagram (Data Readback Mode) t1 SCLK 24 t3 t7 SYNC 48 t22 t2 t21 t4 t8 t9 DIN DB23 DB0 DB23 INPUT WORD FOR DAC N DB0 INPUT WORD FOR DAC N + 1 t20 UNDEFINED DB0 t13 INPUT WORD FOR DAC N t23 LDAC Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode) Rev. C | Page 8 of 33 04652-006 DB23 SDO Data Sheet AD5384 I2C Serial Interface DVDDx = 2.7 V to 5.5 V; AVDDx = 4.5 V to 5.5 V; AGNDx = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 6. Limit at TMIN, TMAX. Table 4. Parameter fSCL t1 t2 t3 t4 t5 t61 Min Typ Max 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 t7 t8 t9 t10 300 0 t11 300 0 300 20 + 0.1Cb2 Cb 400 Unit kHz μs μs μs μs ns μs μs μs μs μs ns ns ns ns ns ns pF Description SCL clock frequency SCL cycle time SCL high time, tHIGH SCL low time, tLOW Start/repeated start condition hold time, tHD, STA Data setup time, tSU,DAT Data hold time, tHD,DAT Data hold time, tHD,DAT Setup time for repeated start, tSU,STA Stop condition setup time, tSU, STO Bus free time between a stop and a start condition, tBUF Rise time of SCL and SDA when receiving, tR Rise time of SCL and SDA when receiving (CMOS-compatible), tR Fall time of SDA when transmitting, tF Fall time of SDA when receiving (CMOS-compatible), tF Fall time of SCL and SDA when receiving, tF Fall time of SCL and SDA when transmitting, tF Capacitive load for each bus line 1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of the SCL falling edge. 2 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDDx and 0.7 DVDDx. SDA t9 t3 t10 t11 t4 SCL t4 t6 t2 t5 t1 t8 START CONDITION REPEATED START CONDITION Figure 6. I2C-Compatible Serial Interface Timing Diagram Rev. C | Page 9 of 33 STOP CONDITION 04652-007 t7 AD5384 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) latch-up. Table 5. Parameter AVDDx to AGNDx DVDDx to DGND Digital Inputs to DGND SDA/SCL to DGND Digital Outputs to DGND REF_IN/REF_OUT to AGNDx AGNDx to DGND VOUTx to AGNDx Analog Inputs to AGND Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature (TJ max) 100-Ball CSP_BGA Package θJA Thermal Impedance Reflow Soldering Peak Temperature ESD Human Body Model (HBM) Field-Induced Charged Device Model (FICDM) Rating –0.3 V to +7 V –0.3 V to +7 V –0.3 V to DVDDx + 0.3 V –0.3 V to + 7 V –0.3 V to DVDDx + 0.3 V –0.3 V to AVDDx + 0.3 V –0.3 V to +0.3 V –0.3 V to AVDDx + 0.3 V –0.3 V to AVDDx + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION –40°C to +85°C –65°C to +150°C 150°C 40°C/W 230°C 6.5 kV 1.6 kV Rev. C | Page 10 of 33 Data Sheet AD5384 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 2 3 4 5 6 7 8 9 10 11 12 A A B B C C D D E E F F TOP VIEW G G H H J J K K L L M M 1 2 3 4 5 6 7 8 9 10 11 12 04652-008 1 Figure 7. Pin Configuration Table 6. Pin Function Descriptions Pin No. A1, A12, B2, B11, C11, K11, L2, L11, M1, M12 A2 Mnemonic NC Description No Connect. Do not connect to these pins. VOUT24 A3 CLR A4 SYNC/AD0 A5 SCLK/SCL A6, B6, D6 A7, B3, B7, D7 A8 DVDD1 to DVDD3 DGND PD A9 DCEN/AD1 Buffered Analog Output. The analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. The output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated with the data in the CLR code register. BUSY is low for a duration of 35 µs while all channels are being updated with the CLR code. Multifunction Pin. In serial interface mode, the SYNC pin is the frame synchronization input signal for the serial clocks before the address register is updated. In I2C mode, AD0 acts as a hardware address pin used in conjunction with AD1 to determine the software address for the device on the I2C bus. Multifunction Pin. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. SCLK operates at clock speeds up to 30 MHz. In I2C mode, the SCL pin clocks data into the device. The data transfer rate in I2C mode is compatible with both 100 kHz and 400 kHz operating modes. Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. Decouple these pins with 0.1 µF ceramic and 10 µF tantalum capacitors to DGND. Ground for All Digital Circuitry. Power-Down (Level Sensitive, Active High). Use PD to place the device in low power mode, where AIDD reduces to 2 µA and DIDD to 20 µA. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down. Multifunction Pin. In SPI mode, the DCEN pin acts to enable the daisy-chain function. In I2C mode, the AD1 pin acts as a hardware address pin. Daisy-Chain Select Input (Level Sensitive, Active High). When DCEN is high, this pin is used in conjunction with the SPI/I2C pin set high to enable the SPI serial interface in daisy-chain mode. In I2C mode, the AD1 pin acts as a hardware address pin used in conjunction with AD0 to determine the software address for this device on the I2C bus. Rev. C | Page 11 of 33 AD5384 Data Sheet Pin No. A10 Mnemonic LDAC A11 BUSY B1 VOUT25 B4 DIN/SDA B5 SDO B8 SPI/I2C B9 RESET B10 VOUT22 B12, C1 VOUT23, VOUT26 C2, D2 SIGNAL_GND4 C12, D1 VOUT21, VOUT27 D4, E4 DAC_GND4 D5 AGND4 D8 AGND3 D9, E9 DAC_GND3 D11 VOUT20 D12, E1 AVDD3, AVDD4 E2, F2 SIGNAL_GND1 Description Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC registers, and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored, and the DAC registers are updated when BUSY goes inactive. However, any events on LDAC during power-on reset or at RESET are ignored. Digital CMOS Output. BUSY goes low during internal calculations of the data (×2) loaded to the DAC data register. During this time, the user can continue writing new data to the ×1, c, and m registers, but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also goes low during power-on reset, and when the BUSY pin is low. During this time, the interface is disabled, and any events on LDAC are ignored. A CLR operation also brings BUSY low. Buffered Analog Output. The analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. The output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. In serial interface mode, DIN acts as the serial data input. Data must be valid on the falling edge of SCLK. In I2C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output. Serial Data Output in Serial Interface Mode. Three-state CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of SCLK. Serial Interface Mode Select. This is a multifunction pin. When this pin is high, SPI mode is selected. When this pin is low, I2C is selected. Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power-on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the ×1, m, c, and ×2 registers to their default power-on values. This sequence typically takes 270 µs. The falling edge of RESET initiates the RESET process, and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled, and all LDAC pulses are ignored. When BUSY returns high, the device resumes normal operation, and the status of the RESET pin is ignored until the next falling edge is detected. Buffered Analog Output. The analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. The output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Buffered Analog Outputs. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GNDx pins are connected together internally and must be connected to the AGND plane as close as possible to the AD5384. Buffered Analog Outputs. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Each Group of Eight Channels Contains a DAC_GNDx Pin. This is the ground reference point for the internal 14-bit DAC. Connect these pins to the AGND plane. Analog Ground Reference Point. Each group of eight channels contains an AGND pin. Connect all AGND pins externally to the AGND plane. Analog Ground Reference Point. Each group of eight channels contains an AGND pin. Connect all AGND pins externally to the AGND plane. Each Group of Eight Channels Contains a DAC_GNDx Pin. This is the ground reference point for the internal 14-bit DAC. Connect these pins to the AGND plane. Buffered Analog Output. The analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. The output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Analog Supply Pins. Each group of eight channels has a separate AVDDx pin. Short these pins internally and decouple them with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating range is 4.5 V to 5.5 V. Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GNDx pins are connected together internally and must be connected to the AGND plane as close as possible to the AD5384. Rev. C | Page 12 of 33 Data Sheet AD5384 Pin No. E11, E12 Mnemonic VOUT17, VOUT19 F1 F4, G4 REF_GND DAC_GND1 F9, G9 SIGNAL_GND3 F11, F12, G1, G2, G11 VOUT16, VOUT18, VOUT28, VOUT29, VOUT15 AVDD2 G12 H1 REF_OUT/ REF_IN H2 VOUT31 H4, J4 DAC_GND5 H9, J9 SIGNAL_GND2 H11, H12 VOUT13, VOUT14 J1 AVDD1 J2 VOUT30 J5 AGND1 J6, J7 DAC_GND2 J8 AGND2 J11, J12, K1, K2, K12, L1 L3, L4 VOUT12, VOUT11, VOUT0, VOUT1, VOUT10, VOUT2 SIGNAL_GND5 L5 AGND5 Description Buffered Analog Outputs. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Ground Reference Point for the Internal Reference. Each Group of Eight Channels Contains a DAC_GNDx Pin. This is the ground reference point for the internal 14-bit DAC. Connect these pins to the AGND plane. Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GNDx pins are connected together internally and must be connected to the AGND plane as close as possible to the AD5384. Buffered Analog Outputs. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Analog Supply Pin. Each group of eight channels has a separate AVDDx pin. Short these pins internally and decouple them with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating range is 4.5 V to 5.5 V. Common REF_OUT/REF_IN pin. The default for this pin is a reference input (REF_IN). When the internal reference is selected, this pin is the reference output (REF_OUT). If the application requires an external reference, apply it to this pin. The control register enables/disables the internal reference. Buffered Analog Output. The analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. The output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Each Group of Eight Channels Contains a DAC_GNDx Pin. This is the ground reference point for the internal 14-bit DAC. Connect these pins to the AGND plane. Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GNDx pins are connected together internally and must be connected to the AGND plane as close as possible to the AD5384. Buffered Analog Outputs. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Analog Supply Pin. Each group of eight channels has a separate AVDDx pin. Short these pins internally and decouple them with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating range is 4.5 V to 5.5 V. Buffered Analog Output. The analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. The output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Analog Ground Reference Point. Each group of eight channels contains an AGND pin. Connect all AGND pins externally to the AGND plane. Each Group of Eight Channels Contains a DAC_GNDx Pin. This is the ground reference point for the internal 14-bit DAC. Connect these pins to the AGND plane. Analog Ground Reference Point. Each group of eight channels contains an AGND pin. Connect all AGND pins externally to the AGND plane. Buffered Analog Outputs. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GNDx pins are connected together internally and must be connected to the AGND plane as close as possible to the AD5384. Analog Ground Reference Point. Each group of eight channels contains an AGND pin. Connect all AGND pins externally to the AGND plane. Rev. C | Page 13 of 33 AD5384 Pin No. L6, L7, L8, L9, L10, L12, M2, M3, M4 M5 M6, M7, M8, M9 M10 M11 Data Sheet Mnemonic VOUT6, VOUT32, VOUT34, VOUT36, VOUT38, VOUT9, VOUT3, VOUT4, VOUT5 AVDD5 VOUT7, VOUT33, VOUT35, VOUT37 VOUT39/ MON_OUT VOUT8 Description Buffered Analog Outputs. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Analog Supply Pin. Each group of eight channels has a separate AVDDx pin. Short these pins internally and decouple them with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating range is 4.5 V to 5.5 V. Buffered Analog Outputs. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. This pin has a dual function. It acts as a buffered output for Channel 39 in default mode. However, when the monitor function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to multiplex one of Channel 0 to Channel 38 to the MON_OUT pin. The MON_OUT pin output impedance typically is 500 Ω, and it is intended to drive a high input impedance like that exhibited by the successive approximation register (SAR) analog-to-digital converter (ADC) inputs. Buffered Analog Output. The analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. The output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω. Rev. C | Page 14 of 33 Data Sheet AD5384 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 35 30 0.5 25 FREQUENCY 1.0 0 –0.5 20 15 –1.0 10 –1.5 5 –2.0 0 4096 8192 INPUT CODE 12288 16384 0 –5.0 –4.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 4.0 5.0 –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5 REFERENCE DRIFT (ppm/°C) 04652-009 INL ERROR (LSB) 40 AVDDx = DVDDx = 5.5V VREF = 2.5V TA = 25°C 04652-012 2.0 Figure 11. REF_OUT Temperature Coefficient Figure 8. Typical INL Error Plot 2.510 LDAC 2.500 VOUTx 2.995 2 4 6 8 10 12 TIME (μs) Figure 9. Glitch Impulse Figure 12. Slew Rate with Boost On AVDDx = 5.5V VREF = 2.5V TA = 25°C 14 12 PERCENTAGE OF UNITS (%) LDAC VOUTx AVDDx = DVDDx = 5V VREF = 2.5V TA = 25°C 10 8 6 4 2 8 Figure 10. Slew Rate with Boost Off 9 10 AIDD (mA) Figure 13. Histogram with Boost Off Rev. C | Page 15 of 33 11 04652-014 0 04652-010 2.990 04652-013 AVDDx = DVDDx = 5V VREF = 2.5V TA = 25°C 04652-011 VOLTAGE (V) 2.505 AD5384 Data Sheet 14 DVDDx = 5.5V VIH = DVDDx VIL = DGND TA = 25°C 10 12 NUMBER OF UNITS 8 6 4 10 8 6 4 2 2 0.6 0.7 0.8 DIDD (mA) 0.9 1.0 0 –2 –1 0 1 INL ERROR DISTRIBUTION (LSB) Figure 14. DIDD Histogram 04652-018 0.5 04652-015 0 2 Figure 17. INL Distribution BUSY PD VOUTx 04652-016 AVDDx = DVDDx = 5V VREF = 2.5V TA = 25°C Figure 15. Exiting Soft Power-Down 04652-019 VOUTx AVDDx = DVDDx = 5V VREF = 2.5V TA = 25°C Figure 18. Exiting Hardware Power-Down 6 AV DDx = DV DDx = 5V VREF = 2.5V T = 25°C FULL-SCALE 5 AVDDx = DVDDx = 5V VREF = 2.5V TA = 25°C 3/4 SCALE 4 VOUT (V) VDD VOUTx MIDSCALE 3 2 1/4 SCALE 1 ZERO-SCALE 04652-017 0 –1 –40 –20 –10 –5 –2 0 2 CURRENT (mA) 5 10 20 Figure 19. Output Amplifier Source and Sink Capability Figure 16. Power-Up Transient Rev. C | Page 16 of 33 40 04652-020 NUMBER OF UNITS AVDDx = 5.5V REF_IN = 2.5V TA = 25°C Data Sheet AD5384 0.20 2.456 AVDDx = 5V VREF = 2.5V TA = 25°C 0.15 2.454 ERROR AT ZERO SINKING CURRENT 0.05 AMPLITUDE (V) 0 –0.05 2.452 2.451 (VDD – VOUTx) AT FULL-SCALE SOURCING CURRENT 0 0.25 0.50 0.75 1.00 1.25 ISOURCE /ISINK (mA) 1.50 1.75 2.00 04652-021 –0.20 AVDDx = 5V TA = 25°C REF_OUT DECOUPLED WITH 100nF CAPACITOR 500 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550 Figure 22. Adjacent Channel DAC to DAC Crosstalk Figure 20. Headroom at Rail vs. ISOURCE/ISINK 600 2.449 AVDDx = DVDDx = 5V TA = 25°C DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE Y AXIS = 5µV/DIV X AXIS = 100ms/DIV 400 300 REF_OUT = 2.5V 200 0 100 REF_OUT = 1.25V 1k 10k FREQUENCY (Hz) 100k 04652-022 100 Figure 21. REF_OUT Noise Spectral Density Figure 23. 0.1 Hz to 10 Hz Noise Plot Rev. C | Page 17 of 33 04652-024 2.450 –0.15 OUTPUT NOISE (nV/ Hz) 2.453 04652-025 ERROR VOLTAGE (V) 0.10 –0.10 AVDDx = DVDDx = 5V VREF = 2.5V TA = 25°C 14ns/SAMPLE NUMBER 2.455 AD5384 Data Sheet TERMINOLOGY Relative Accuracy Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error, and is expressed in LSB. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Zero-Scale Error Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. Ideally, with all 0s loaded to the DAC and m = all 1s, c = 2n – 1. VOUT (ZERO-SCALE) = 0 V Zero-scale error is a measure of the difference between VOUT (actual) and VOUT (ideal), expressed in mV. It is mainly due to offsets in the output amplifier. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) in the linear region of the transfer function, expressed in mV. Offset error is measured on the AD5384-5 with Code 32 loaded into the DAC register. Gain Error Gain Error is specified in the linear region of the output range between VOUT = 10 mV and VOUT = AVDDx – 50 mV. It is the deviation in slope of the DAC transfer characteristic from the ideal and is expressed in % FSR with the DAC output unloaded. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC at midscale, in response to a full-scale code (all 0s to all 1s, and vice versa) and output change of all other DACs. It is expressed in LSB. DC Output Impedance DC output impedance is the effective output source resistance. It is dominated by package lead resistance. Output Voltage Settling Time The output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change, and is measured from the BUSY rising edge. Digital-to-Analog Glitch Energy The digital-to-analog glitch energy is the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-sec. It is measured by toggling the DAC register data between 0x1FFF and 0x2000. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC due to both the digital change and the subsequent analog output change at another DAC. The victim channel is loaded with midscale. DAC-to-DAC crosstalk is specified in nV-sec. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter. It is specified in nV-sec. Digital Feedthrough When the device is not selected, high frequency logic activity on the device digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough. Output Noise Spectral Density Output noise spectral density is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hertz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/√Hz in a 1 Hz bandwidth at 10 kHz. Rev. C | Page 18 of 33 Data Sheet AD5384 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The AD5384 is a complete single-supply, 40-channel, voltage output DAC offering 14-bit resolution, available in a 100-ball CSP_BGA package. It features two serial interfaces, SPI and I2C. This family includes an internal 1.25 V/2.5 V, 10 ppm/°C that drives the buffered reference inputs. Alternatively, an external reference can drive these inputs. Reference selection is via a bit in the control register. Internal/external reference selection is via the CR10 bit in the control register, and the CR12 bit in the control register selects the reference magnitude if the internal reference is selected. All channels have an on-chip output amplifier with rail-to-rail output capable of driving 5 kΩ in parallel with a 200 pF load. The architecture of a single DAC channel consists of a 14-bit resistor string DAC followed by an output buffer amplifier operating at a gain of 2. This resistor string architecture guarantees DAC monotonicity. The 14-bit binary digital code loaded to the DAC register determines at which node on the string the voltage is tapped off before being fed to the output amplifier. Each channel on these devices contains independent offset and gain control registers allowing the user to digitally trim offset and gain. These registers let the user calibrate out errors in the complete signal chain, including the DAC, using the internal m and c registers that hold the correction factors. All channels are double buffered, allowing synchronous updating of all channels using the LDAC pin. Figure 24 shows a block diagram of a single channel on the AD5384. The following represents the digital input transfer function for each DAC: x2 = [(m + 2)/ 2n × x1] + (c – 2n – 1) where: x2 is the data-word loaded to the resistor-string DAC. x1 is the 14-bit data-word written to the DAC input register. m is the gain coefficient (default is 0x3FFE on the AD5384). The gain coefficient is written to the 13 most significant bits (DB13 to DB1) and the LSB (DB0) is 0. n is the DAC resolution (n = 14 for AD5384). c is the14-bit offset coefficient (default is 0x2000). VREF (+) AVDDx ×1 INPUT REG m REG ×2 14-BIT DAC c REG VOUTx R AGND Figure 24. Single-Channel Architecture VOUT = 2 × VREF × x2/2n where: x2 is the data-word loaded to the resistor string DAC. VREF is the internal reference voltage or the reference voltage externally applied to the DAC REF_OUT/REF_IN pin. For specified performance, an external reference voltage of 2.5 V is recommended. DATA DECODING The AD5384 contains a 14-bit data bus, DB13 to DB0. Depending on the value of REG1 and REG0 outlined in Table 7, this data is loaded into the addressed DAC input register(s), offset (c) register(s), or gain (m) register(s). Table 8, Table 9, and Table 10 outline the contents of the format data, offset (c), and gain (m) registers. Table 7. Register Selection REG1 1 1 0 0 REG0 1 0 1 0 Register Selected Input data register (×1) Offset register (c) Gain register (m) Special function registers (SFRs) Table 8. DAC Data Format (REG1 = 1, REG0 = 1) 11 11 10 10 01 00 00 DB13 to DB0 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 1111 1110 0001 0000 1111 0001 0000 DAC Output (V) 2 VREF × (16383/16384) 2 VREF × (16382/16384) 2 VREF × (8193/16384) 2 VREF × (8192/16384) 2 VREF × (8191/16384) 2 VREF × (1/16384) 0 Table 9. Offset Data Format (REG1 = 1, REG0 = 0) 11 11 10 10 01 00 00 1111 1111 0000 0000 1111 0000 0000 DB13 to DB0 1111 1111 1111 1110 0000 0001 0000 0000 1111 1111 0000 0001 0000 0000 Offset (LSB) +8191 +8190 +1 0 –1 –8191 –8192 Table 10. Gain Data Format (REG1 = 0, REG0 = 1) R 04652-026 INPUT DATA The following represents the complete transfer function for these devices: 11 10 01 00 00 Rev. C | Page 19 of 33 1111 1111 1111 1111 0000 DB13 to DB0 1111 1111 1111 1111 0000 1110 1110 1110 1110 0000 Gain Factor 1 0.75 0.5 0.25 0 AD5384 Data Sheet ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) Soft CLR The AD5384 contains a number of special function registers (SFRs), as outlined in Table 11. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0. REG1 = REG0 = 0, A5 to A0 = 000010, and DB13 to DB0 = don’t care. Table 11. SFR Register Functions (REG1 = 0, REG0 = 0) R/W A5 A4 A3 A2 A1 A0 Function X 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 No operation (NOP) Write CLR code Soft CLR Soft power-down Soft power-up Control register write Control register read Monitor channel Software reset SFR COMMANDS NOP (No Operation) REG1 = REG0 = 0, and A5 to A0 = 000000. Executing this instruction performs the CLR, which is functionally the same as that provided by the external CLR pin. The DAC outputs are loaded with the data in the CLR code register. It takes 35 µs to execute fully the SOFT CLR, as indicated by the BUSY low time. Soft Power-Down REG1 = REG0 = 0, A5 to A0 = 001000, and DB13 to DB0 = don’t care. Executing this instruction performs a global power-down that puts all channels in low power mode, reducing the analog supply current to 2 µA maximum, and the digital current to 20 µA maximum. In power-down mode, the output amplifier can be configured as a high impedance output or can provide a 100 kΩ load to ground. The contents of all internal registers are retained in power-down mode. While in power-down mode, no registers can be written to. Performs no operation but is useful in serial readback mode to clock out data on DOUT for diagnostic purposes. BUSY pulses low during an NOP operation. Soft Power-Up Write CLR Code This instruction powers up the output amplifiers and the internal reference. The time to exit power-down is 8 µs. The hardware power-down and software functions are internally combined in a digital OR function. REG1 = REG0 = 0, A5 to A0 = 000001, and DB13 to DB0 = contains the CLR data. Bringing the CLR line low, or exercising the soft clear function, loads the contents of the DAC registers, with the data contained in the user configurable CLR register, and sets VOUT0 to VOUT39, accordingly. This is very useful for setting up a specific output voltage in a clear condition. It is also beneficial for calibration purposes; the user can load full scale or zero scale to the clear code register and then issue a hardware or software clear to load this code to all DACs, removing the need for individual writes to each DAC. Default at power-up is all 0s. REG1 = REG0 = 0, A5 to A0 = 001001, and DB13 to DB0 = don’t care. Software Reset REG1 = REG0 = 0, A5 to A0 = 001111, and DB13 to DB0 = don’t care. This instruction implements a software reset. All internal registers reset to their default values, which correspond to m at full scale and c at zero. The contents of the DAC registers clear, setting all analog outputs to 0 V. The soft reset activation time is 135 µs. Only perform a soft reset when the AD5384 is not in power-down mode. Rev. C | Page 20 of 33 Data Sheet AD5384 Table 12. Control Register Contents MSB CR13 CR12 CR11 CR10 CR9 CR8 CR7 Control Register Write/Read REG1 = REG0 = 0, A5 to A0 = 001100, and R/W status determines if the operation is a write (R/W = 0) or a read (R/W = 1). The DB13 to DB0 bits contain the control register data. Control Register Contents CR13: power-down status. This bit configures the output amplifier state in power-down mode This bit is configured as follows: • For CR13 = 1, the amplifier output is high impedance (default at power-up). • For CR13 = 0, the amplifier output is 100 kΩ to ground. CR12: REF select. This bit selects the operating internal reference for the AD5384. CR12 is programmed as follows: • • For CR12 = 1, the internal reference is 2.5 V, which is the recommended operating reference. For CR12 = 0, the internal reference is 1.25 V. CR11: current boost control. This bit boosts the current in the output amplifier, thereby altering its slew rate. This bit is configured as follows: • • For CR11 = 1, boost mode is on, maximizing the bias current in the output amplifier, and optimizing its slew rate but increasing the power dissipation. For CR11 = 0, boost mode is off (default at power-up), reducing the bias current in the output amplifier and the overall power consumption. CR10: internal/external reference. This bit determines if the DAC uses its internal reference or an externally applied reference. This bit is configured as follows: • • For CR10 = 1, the internal reference is enabled. The reference output depends on data loaded to CR12. For CR10 = 0, the external reference is selected (default at power-up). CR9: channel monitor enable (see Channel Monitor Function). This bit is configured as follows: • • For CR9 = 1, the monitor is enabled which enables the channel monitor function. After a write to the monitor channel in the SFR register, the selected channel output routes to the MON_OUT pin. VOUT39 operates as the MON_OUT pin. For CR9 = 0, the monitor is disabled (default at powerup). When the monitor is disabled, the MON_OUT pin assumes its normal DAC output function. CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0 CR8: thermal monitor function. This function monitors the AD5384 internal die temperature, when enabled. The thermal monitor powers down the output amplifiers when the temperature exceeds 130°C. This function protects the device when power dissipation is exceeded, if a number of output channels are simultaneously short circuited. If the die temperature drops below 130°C, a soft power-up reenables the output amplifiers. This bit is configured as follows: • • For CR8 = 1, the thermal monitor is enabled. For CR8 = 0, the thermal monitor is disabled (default at power-up). CR7: don’t care. CR6 to CR2: toggle function enable. This function toggles the output between two codes loaded to the A and B register for each DAC. Control Register Bit CR6 to Control Register Bit CR2 enable individual groups of eight channels for operation in toggle mode. A Logic 1, written to any bit, enables a group of channels, and a Logic 0 disables a group. LDAC is used to toggle between the two registers. Table 13 shows the decoding for toggle mode operation. For example, CR6 controls group w, which contains Channel 32 to Channel 39, CR6 = 1 enables these channels. CR1 and CR0: don’t care. Table 13. Toggle Function Enable CR Bit CR6 CR5 CR4 CR3 CR2 Group 4 3 2 1 0 Channels 32 to 39 24 to 31 16 to 23 8 to 15 0 to 7 Channel Monitor Function REG1 = REG0 = 0, A5 to A0 = 001010, and DB13 to DB8 = contain data to address the monitored channel. The AD5384 has a channel monitor function that consists of a multiplexer address via the interface, allows any channel output to be routed to the MON_OUT pin for monitoring, using an external ADC. In channel monitor mode, VOUT39 becomes the MON_OUT pin, to which all monitored pins are routed. Enable the channel monitor function in the control register before any channels are routed to the MON_OUT pin. On the AD5384, DB13 to DB8 contain the channel address for the monitored channel. Selecting Channel Address 63 three-states the MON_OUT pin. Rev. C | Page 21 of 33 AD5384 Data Sheet Table 14. Channel Monitor Decoding REG1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 DB12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 DB11 DB10 DB9 DB8 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 Values 0b1000 to 0b1110 are reserved 1 1 1 1 REG1 REG0 A5 A4 A3 A2 A1 A0 0 0 0 0 1 0 1 0 VOUT0 VOUT1 AD5384 CHANNEL MONITOR DECODING VOUT39/MON_OUT CHANNEL ADDRESS DB13–DB8 Figure 25. Channel Monitor Decoding Rev. C | Page 22 of 33 04652-027 VOUT37 VOUT38 DB7 to DB0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X MON_OUT VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 VOUT13 VOUT14 VOUT15 VOUT16 VOUT17 VOUT18 VOUT19 VOUT20 VOUT21 VOUT22 VOUT23 VOUT24 VOUT25 VOUT26 VOUT27 VOUT28 VOUT29 VOUT30 VOUT31 VOUT32 VOUT33 VOUT34 VOUT35 VOUT36 VOUT37 VOUT38 VOUT39 Undefined X Three-state Data Sheet AD5384 HARDWARE FUNCTIONS RESET FUNCTION Bringing the RESET line low resets the contents of the internal registers to their power-on reset state. RESET is a negative edgesensitive input. The default corresponds to m at full scale and to c at zero. The contents of the DAC registers are cleared, setting VOUT0 to VOUT39 to 0 V. The hardware reset activation time takes 270 µs. The falling edge of RESET initiates the reset process; BUSY goes low during this process, returning high when RESET is complete. While BUSY is low, all interfaces are disabled, and all LDAC pulses are ignored. When BUSY returns high, the device resumes normal operation, and the status of the RESET pin is ignored until the next falling edge is detected. Do not bring RESET low when the AD5384 is in power-down mode. ASYNCHRONOUS CLEAR FUNCTION Bringing the CLR line low loads the contents of the DAC registers with the data contained in the user-configurable CLR register, and sets VOUT0 to VOUT39 accordingly. Use this function in system calibration to load zero scale and full scale to all channels. The execution time for CLR is 35 µs. BUSY AND LDAC FUNCTIONS BUSY is a digital CMOS output that indicates the status of the AD5384. The value of x2, the internal data loaded to the DAC data register, is calculated each time the user writes new data to the corresponding x1, c, or m registers. During the calculation of x2, the BUSY output goes low. While BUSY is low, the user can continue writing new data to the x1, m, or c registers, but no DAC output updates can take place. The DAC outputs are updated by bringing the LDAC input low. If LDAC goes low while BUSY is active, the LDAC event is stored, and the DAC outputs update immediately after BUSY goes high. The user can hold the LDAC input permanently low, in which case, the DAC outputs update immediately after BUSY goes high. BUSY also goes low during power-on reset and when a falling edge is detected on the RESET pin. During this time, all interfaces are disabled, and any events on LDAC are ignored. The AD5384 contains an extra feature, whereby a DAC register does not update unless its x2 register has been written to since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers fill with the contents of the x2 registers. However, the AD5384 updates the DAC register only if the x2 data has changed, thereby removing unnecessary digital crosstalk. POWER-ON RESET The AD5384 contains a power-on reset generator and state machine. The power-on reset generator resets all registers to a predefined state and configures the analog outputs as high impedance. The BUSY pin goes low during the power-on reset sequencing, preventing data writes to the device. POWER-DOWN FEATURE The AD5384 contains a global power-down feature that puts all channels into low power mode and reduces the analog power consumption to 2 µA maximum and digital power consumption to 20 µA maximum. In power-down mode, the output amplifier can be configured as a high impedance output, or it can provide a 100 kΩ load to ground. The contents of all internal registers remain in power-down mode. When exiting power-down mode, the settling time of the amplifier elapses before the outputs settle to their correct values. POWER SUPPLY SEQUENCING The power-on reset circuitry requires that the AVDDx is applied before or within 10 ms of DVDDx, which ensures that the registers are correctly loaded with their default values. If it is not possible for AVDDx to be applied within 10 ms of DVDDx, a software or hardware reset is used to load the default register values. Rev. C | Page 23 of 33 AD5384 Data Sheet INTERFACES The 24-bit data-word format for the serial interface is shown in Table 15. The bit descriptions are as follows: The AD5384 contains a serial interface that can be programmed as DSP-, SPI-, MICROWIRE-, or I2C-compatible. Select DSP, SPI, MICROWIRE, or I2C interface mode by using the SPI/I2C pin . To minimize both the power consumption of the device and the on-chip digital noise, the active interface powers up fully only when the device is being written to on the falling edge of SYNC. • • DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL INTERFACE • • The serial interface operates with a minimum of three wires in standalone mode or five wires in daisy-chain mode. Daisychaining allows many devices to be cascaded together to increase system channel count. Tie the SPI/I2C (Ball B8) high to enable the DSP-, SPI-, or MICROWIRE-compatible serial interface. The following are the serial interface control pins: • • • • • When toggle mode is enabled, the A/B bit selects whether the data write is to the A register or B register. When toggle mode is disabled, set A/B to zero to select the A data register. R/W is the read or write control bit. A5 to A0 are used to address the input channels. REG1 and REG0 select the register to which data is written, as shown in Table 7. DB13 to DB0 contain the input data-word. X is a don’t care condition. Standalone Mode Connect the DCEN (daisy-chain enable) pin low to enable standalone mode. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift register. Any further edges on SYNC, except for a falling edge, are ignored until 24 bits are clocked in. Once 24 bits are shifted in, SCLK is ignored. For another serial transfer to take place, reset the counter by the falling edge of SYNC. SYNC/AD0, DIN/SDA, and SCLK/SCL are the standard 3-wire interface pins. DCEN/AD1 selects standalone mode or daisy-chain mode. SDO is the data out pin for daisy-chain mode. Figure 3 and Figure 5 show the timing diagrams for a serial write to the AD5384 in standalone and in daisy-chain modes. Table 15. 40-Channel, DAC Serial Input Register Configuration MSB A/B R/W A5 A4 A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 Rev. C | Page 24 of 33 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 LSB DB0 Data Sheet AD5384 Daisy-Chain Mode Readback Mode For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. This daisy-chain mode is useful in system diagnostics and in reducing the number of serial interface lines. Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, Bits A5 to A0, in association with Bit REG1 and Bit REG0, select the register to be read. The remaining data bits in the write sequence are don’t cares. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. For a read of a single register, use the NOP command to clock out the data from the selected register on SDO. Figure 26 shows the readback sequence. Connect the DCEN (daisy-chain enable) pin high, to enable daisy-chain mode. The first falling edge of SYNC starts the write cycle. The SCLK is applied continuously to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the DIN input on the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24N, where N is the total number of AD5384 devices in the chain. For example, to read back the m register of Channel 0 on the AD5384, the following sequence must be followed. First, write 0x404XXX to the AD5384 input register. This configures the AD5384 for read mode with the m register of Channel 0 selected. Note that Data Bit DB13 to Data Bit DB0 are don’t cares. Follow this with a second write, an NOP condition, 0x000000. During this write, the data from the m register clocks out on the SDO line; data clocked out contains the data from the m register in Bit DB13 to Bit DB0, and the top 10 bits contain the address information as previously written. In readback mode, the SYNC signal frames the data. Data clocks out on the rising edge of SCLK and is valid on the falling edge of the SCLK signal. If the SCLK idles high between the write and read operations of a readback operation, the first bit of data clocks out on the falling edge of SYNC. When the serial transfer to all devices is complete, SYNC goes high, latches the input data in each device in the daisy-chain, and prevents any further data from clocking into the input shift register. If SYNC is taken high before 24 clocks are clocked into the device, it is considered a bad frame, and the data is discarded. The serial clock is either a continuous or a gated clock. A continuous SCLK source is used only if SYNC is held low for the correct number of clock cycles. In gated clock mode, use a burst clock containing the exact number of clock cycles and take SYNC high after the final clock to latch the data. SCLK 24 48 SYNC DB23 DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ DB0 NOP CONDITION DB23 SDO UNDEFINED SELECTED REGISTER DATA CLOCKED OUT Figure 26. Serial Readback Operation Rev. C | Page 25 of 33 DB0 04652-028 DIN AD5384 Data Sheet I2C SERIAL INTERFACE Acknowledge Bit (ACK) The AD5384 features an I2C-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5384 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagrams that incorporate three different modes of operation. The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data-word. ACK is always generated by the receiving device. The AD5384 devices generate an ACK when receiving an address or data by pulling SDA low during the ninth clock period. Monitoring ACK allows detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault occurs. In the event of an unsuccessful data transfer, the bus master reattempts communication. Select I2C mode by configuring the SPI/I2C pin to a Logic 0. The device is connected to this bus as a slave device, and no clock is generated by the AD5384. The AD5384 has a 7-bit slave address, 1010 1 (AD1)(AD0) The 5 MSBs are hard coded, and the two LSBs are determined by the state of the AD1 and AD0 pins. The ability to hardware-configure AD1 and AD0 allows four of these devices to be configured on the bus. Slave Addresses A bus master initiates communication with a slave device by issuing a start condition, followed by the 7-bit slave address. When idle, the AD5384 waits for a start condition followed by its slave address. The LSB of the address word is the read/write (R/W) bit. The AD5384 devices are receive-only devices; when communicating with these, R/W = 0. After receiving the proper address 1010 1(AD1)(AD0), the AD5384 issues an ACK by pulling SDA low for one clock cycle. I2C Data Transfer During each SCL clock cycle, one data bit transfers. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals that configure start and stop conditions. When the I2C bus is not busy, the external pull-up resistors pull both SDA and SCL high. The AD5384 has four different user programmable addresses determined by the AD1 and AD0 bits. Start and Stop Conditions Write Operation A master device initiates communication by issuing a start condition. A start condition is a high to low transition on SDA with SCL high. A stop condition is a low to high transition on SDA while SCL is high. A start condition from the master signals the beginning of a transmission to the AD5384. The stop condition frees the bus. If a repeated start condition (Sr) generates instead of a stop condition, the bus remains active. Data can be written to the AD5384 DACs in three modes: 4-byte mode, 3-byte mode, and 2-byte mode. 4-Byte Mode When writing to the AD5384 DACs, the user must begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte; this addresses the specific channel in the DAC to be addressed and also is acknowledged by the DAC. Two bytes of data are then written to the DAC, as shown in Figure 27. A stop condition follows. This lets the user update a single channel within the AD5384 at any time, and requires four bytes of data to transfer from the master. Repeated Start Conditions A repeated start (Sr) condition can indicate a change of data direction on the bus. Use Sr when the bus master is writing to several I2C devices and wants to maintain control of the bus. SCL SDA 1 0 1 0 1 AD1 START COND BY MASTER AD0 R/W 0 ACK BY AD538x MSB 0 A5 ADDRESS BYTE A4 A3 A2 A1 A0 ACK BY AD538x POINTER BYTE SCL REG1 REG0 MSB LSB MSB LSB ACK BY AD538x ACK BY AD538x MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE Figure 27. 4-Byte, I2C Write Operation Rev. C | Page 26 of 33 STOP COND BY MASTER 04652-029 SDA Data Sheet AD5384 3-Byte Mode This is then followed by the two data bytes, REG1 and REG0, which determine the register to be updated. In 3-byte mode, the user can update more than one channel in a write sequence without having to write the device address byte each time. The device address byte is required only once; subsequent channel updates require the pointer byte and the data bytes. In 3-byte mode, the use must begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte. This addresses the specific channel in the DAC to be addressed and also is acknowledged by the DAC. If a stop condition does not follow the data bytes, another channel can be updated by sending a new pointer byte, followed by the data bytes. This mode requires only three bytes to be sent to update any channel once the device is initially addressed, and it reduces the software overhead in updating the AD5384 channels. A stop condition at any time exits this mode. Figure 28 shows a typical configuration. SCL SDA 0 1 1 1 0 AD1 AD0 START COND BY MASTER R/W 0 ACK BY AD538x MSB 0 A5 A4 A3 A2 A1 A0 ACK BY AD538x POINTER BYTE FOR CHANNEL N ADDRESS BYTE SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY AD538x ACK BY AD538x LEAST SIGNIFICANT DATA BYTE MOST SIGNIFICANT DATA BYTE DATA FOR CHANNEL N SCL SDA 0 0 A5 A4 A3 A2 A1 A0 MSB ACK BY AD538x POINTER BYTE FOR CHANNEL NEXT CHANNEL SCL REG1 REG0 MSB LSB MSB LSB ACK BY AD538x ACK BY AD538x LEAST SIGNIFICANT DATA BYTE MOST SIGNIFICANT DATA BYTE DATA FOR CHANNEL NEXT CHANNEL Figure 28. 3-Byte, I2C Write Operation Rev. C | Page 27 of 33 STOP COND BY MASTER 04652-030 SDA AD5384 Data Sheet bytes for the present address, automatically increments to the next address. 2-Byte Mode Following initialization of 2-byte mode, the user can update channels sequentially. The device address byte is required only once, and the pointer byte is configured for auto-increment or burst mode. The REG0 and REG1 bits in the data byte determine which register updates. In this mode, following initialization, only two data bytes are required to update a channel. The channel address automatically increments from Address 0. This mode allows transmission of data to all channels in one block, and it reduces the software overhead in configuring all channels. A stop condition at any time exits this mode. Toggle mode is not supported in 2-byte mode. Figure 29 shows a typical configuration. The user must begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by a specific pointer byte (0xFF) that initiates the burst mode of operation. The address pointer initializes to Channel 0, and upon receiving the two data SCL SDA 1 0 1 0 1 AD1 START COND BY MASTER AD0 R/W 0 ACK BY AD538x MSB 0 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1 ACK BY AD538x POINTER BYTE ADDRESS BYTE SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY AD538x ACK BY AD538x LEAST SIGNIFICANT DATA BYTE MOST SIGNIFICANT DATA BYTE CHANNEL 0 DATA SCL SDA REG1 REG0 MSB LSB MSB LSB ACK BY CONVERTER ACK BY AD538x LEAST SIGNIFICANT DATA BYTE MOST SIGNIFICANT DATA BYTE CHANNEL 1 DATA SCL REG1 REG0 MSB LSB MSB LSB ACK BY AD538x LEAST SIGNIFICANT DATA BYTE MOST SIGNIFICANT DATA BYTE CHANNEL N DATA FOLLOWED BY STOP Figure 29. 2-Byte, 12C Write Operation Rev. C | Page 28 of 33 ACK BY STOP CONVERTER COND BY MASTER 04652-031 SDA Data Sheet AD5384 APPLICATIONS INFORMATION In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Separate and confine the analog and digital sections to certain areas of the printed circuit board (PCB) of the AD5384. If the AD5384 is in a system where multiple devices require an AGND-to-DGND connection, make the connection at one point only, a star ground point established as near to the device as possible. For supplies with multiple pins (AVDDx, and AVCCx), tie these pins together. Allow ample supply bypassing of 10 µF capacitators in parallel with 0.1 µF capacitors on each supply, located as near the package as possible and ideally right up against the AD5384 device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor has low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies, so that it can handle transient currents due to internal logic switching. In this case, the AVDD is applied first. This voltage does not appear at the AVDD pin of the AD5384 until the DVDD is applied and brings the EN pin high. The result is that the AVDD and DVDD are both applied to the AD5384 at the same time. Table 16. Power Supply Sequencing First Power Supply AVDD = 3 V DVDD = 3 V AVDD = DVDD Second Power Supply DVDD ≥ 3 V AVDD ≥ 3 V DVDD = AVDD DVDD = AVDD AVDD = DVDD AVDD = 5 V DVDD = 5 V DVDD = 3 V AVDD = 3 V The power supply lines of the AD5384 use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals, such as clocks, with digital ground to avoid radiating noise elsewhere on the board, and do not run them near the reference inputs. A ground line routed between the DIN and SCLK lines helps to reduce crosstalk between them (this is not required on a multilayer board because there is a separate ground plane; however, separating the lines helps). It is essential to minimize noise on the VIN and REF_IN lines. Avoid crossover of digital and analog signals. Run the traces on opposite sides of the board at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best; however, it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. Recommended Operation See Figure 30. See Figure 31. See Figure 30; assumes separate analog and digital supplies. See Figure 31; assumes separate analog and digital supplies. See Figure 32. Hardware reset or see Figure 33. DVDD ≥ 3V AVDD = 3V SD103C OR EQUIVALENT DVDD AVDD AD5384 DAC GND SIGNAL GND AGND DGND 04652-130 POWER SUPPLY DECOUPLING Figure 30. AVDD first followed by DVDD AVDD ≥ 3V DVDD = 3V SD103C OR EQUIVALENT DVDD AVDD POWER SUPPLY SEQUENCING AD5384 Rev. C | Page 29 of 33 DAC GND SIGNAL GND AGND DGND 04652-131 For proper operation, DVDD must be applied first and AVDD applied simultaneously or within 10 ms of DVDD. This ensures that the power-on reset circuitry sets the registers to their default values and keeps the analog outputs at 0 V until a valid write operation takes place. When AVDD cannot be applied within 10 ms of DVDD, a hardware reset must be issued. This triggers the power-on reset circuitry and loads the default register values. For cases where the power supply applied first has the same or lower voltage than the second supply, a Schottkey diode can be used to supply power until the second power supply turns on. Table 18 lists power supply sequences and the recommended diode connection. Alternatively, a load switch such as the ADP196 can be used to delay the first power supply until the second power supply turns on. Figure 32 shows a typical configuration using the ADP196. Figure 31. DVDD first followed by AVDD AD5384 Data Sheet ADP196 AVDD VIN1 VOUT1 VIN2 VOUT2 AD5384 AVDD AVCCx EN AGND DIN/SDA SYNC/AD0 SCLK/SCL VOUT0 DVDD AVCCx AD5384 DGND 04652-132 DVDD AGND OUTPUT PORT AD7476 CS VOUT39/MON_OUT VIN SCLK ADP196 VIN1 VIN2 VOUT1 GND AD5384 CONTROLLER AGNDx DVDD VOUT38 VOUT2 DAC_GND SIGNAL_GND 04652-032 DVDD INPUT PORT SDATA Figure 32. AVDD Power Supply Controlled by a Load Switch EN AGND Figure 34. Typical Channel Monitoring Circuit AVDD TOGGLE MODE FUNCTION DGND 04652-133 AVDD AGND Figure 33. DVDD Power Supply Controlled by a Load Switch MONITOR FUNCTION The AD5384 contains a channel monitor function that consists of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring, using an external ADC. In channel monitor mode, VOUT39 becomes the MON_OUT pin, to which all monitored signals are routed. Enable the channel monitor function in the control register before any channels are routed to the MON_OUT pin. Table 14 shows the decoding information required to route any channel to MON_OUT. Selecting Channel Address 63 three-states the MON_OUT pin. Figure 34 shows a typical monitoring circuit implemented using a 12-bit SAR ADC in a 6-lead SOT package. The controller output port selects the channel to monitor, and the input port reads the converted data from the ADC. The toggle mode function allows an output signal to be generated using the LDAC control signal, which switches between two DAC data registers. This function is configured using the SFR control register as follows: A write with REG1 = REG0 = 0 and A5 to A0 = 001100 specifies a control register write. The toggle mode function is enabled in groups of eight channels using Bit CR6 to Bit CR2 in the control register (see Table 12). Figure 35 shows a block diagram of toggle mode implementation. Each of the 40 DAC channels on the AD5384 contains an A and B data register. Note that the B registers load only when toggle mode is enabled. The sequence of events when configuring the AD5384 for toggle mode is 1. 2. 3. 4. Enable toggle mode for the required channels via the control register. Load data to A registers. Load data to B registers. Apply LDAC. DATA REGISTER A DAC REGISTER VOUT DATA REGISTER B LDAC CONTROL INPUT A/B Figure 35. Toggle Mode Function Rev. C | Page 30 of 33 04652-033 INPUT INPUT DATA REGISTER 14-BIT DAC Data Sheet AD5384 The LDAC is used to switch between the A and B registers in determining the analog output. The first LDAC configures the output to reflect the data in the A registers. This mode offers significant advantages if the user wants to generate a square wave at the output of all 40 channels, as can be required to drive a liquid crystal-based variable optical attenuator. In this case, the user writes to the control register, and enables the toggle function by setting CR6 to CR2 = 1, thus enabling the five groups of eight for toggle mode operation. The user must then load data to all 40 A and B registers. Toggling LDAC sets the output values to reflect the data in the A and B registers. The frequency of the LDAC determines the frequency of the square wave output. Enable the thermal monitor via the CR8 bit in the control register. The output amplifiers on the AD5384 automatically power down if the die temperature exceeds approximately 130°C. After a thermal shutdown occurs, reenable the device by executing a soft power-up, if the temperature drops below 130°C, or by turning off the thermal monitor function via the control register. AD5384 IN A MEMS-BASED OPTICAL SWITCH In their feed-forward control paths, MEMS-based optical switches require high resolution DACs that offer high channel density with 14-bit monotonic behavior. The 40-channel, 14-bit AD5384 DAC satisfies these requirements. In the circuit in Figure 32, the 0 V to 5 V outputs of the AD5384 are amplified to achieve an output range of 0 V to 200 V, which is used to control actuators that determine the position of MEMS mirrors in an optical switch. The exact position of each mirror is measured using sensors. The sensor outputs are multiplexed into a high resolution ADC in determining the mirror position. The control loop is closed and driven by an ADSP-21065L, a 32-bit SHARC® DSP with an SPI-compatible SPORT interface. The ADSP-21065L writes data to the DAC, controls the multiplexer, and reads data from the ADC via the serial interface. Toggle mode is disabled via the control register. The first LDAC that follows the disabling of toggle mode, updates the outputs with the data contained in the A registers. THERMAL MONITOR FUNCTION The AD5384 contains a temperature shutdown function to protect the chip if multiple outputs are shorted. The shortcircuit current of each output amplifier is typically 40 mA. Operating the AD5384 at 5 V leads to a power dissipation of 200 mW per shorted amplifier. With five channels shorted, this leads to an extra watt of power dissipation. For the 100-ball CSP_BGA, the θJA is typically 44°C/W. REF_OUT REF_IN - AVDDx OUTPUT RANGE 0V TO 200V VOUT1 14-BIT DAC G = 50 ACTUATORS FOR MEMS MIRROR ARRAY SENSOR AND MULTIPLEXER 14-BIT DAC AD5384 VOUT39 8-CHANNEL ADC (AD7856) OR SINGLE-CHANNEL ADC (AD7671) G = 50 ADSP-21065L Figure 36. MEMS-Based Optical Switch Rev. C | Page 31 of 33 04652-034 5V 0.01µF AD5384 Data Sheet OPTICAL ATTENUATORS The AD5384 controls the optical attenuator for each wavelength, ensuring that the power is equalized in all wavelengths before being multiplexed onto the fiber. Equalizing the power prevents information loss and saturation from occurring at amplification stages further along the fiber. Based on its high channel count, high resolution, monotonic behavior, and high level of integration, the AD5384 is ideally targeted at optical attenuation applications used in dynamic gain equalizers, variable optical attenuators (VOAs), and optical add-drop multiplexers (OADMs). In these applications, each wavelength is individually extracted using an arrayed wave guide; its power is monitored using a photodiode, transimpedance amplifier, and an ADC in a closed-loop control system. ADD PORTS DROP PORTS OPTICAL SWITCH 11 12 DWDM IN PHOTODIODES ATTENUATOR DWDM OUT ATTENUATOR FIBRE AWG AWG FIBRE 1n–1 1n ATTENUATOR ATTENUATOR TIA/LOG AMP (AD8304/AD8305) N:1 MULTIPLEXER CONTROLLER 16-BIT ADC ADG731 (40:1 MUX) AD7671 (0V TO 5V, 1MSPS) Figure 37. OADM Using the AD5384 as Part of an Optical Attenuator Rev. C | Page 32 of 33 04652-035 AD5384, 40-CHANNEL, 14-BIT DAC Data Sheet AD5384 OUTLINE DIMENSIONS A1 BALL CORNER 10.10 10.00 SQ 9.90 A1 BALL CORNER 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M 8.80 BSC SQ 0.80 BSC BOTTOM VIEW TOP VIEW 1.11 1.01 0.91 DETAIL A DETAIL A 0.34 NOM 0.29 MIN SEATING PLANE *0.50 0.45 0.40 BALL DIAMETER COPLANARITY 0.12 11-18-2011-A 1.40 1.35 1.20 *COMPLIANT TO JEDEC STANDARDS MO-275-DDAA-1 WITH THE EXCEPTION TO BALL DIAMETER. Figure 38. 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-100-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5384BBCZ-5 AD5384BBCZ-5REEL7 1 Resolution 14 Bits 14 Bits Temperature Range –40°C to +85°C –40°C to +85°C Output Channels 40 40 Linearity Error (LSB) ±4 ±4 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004-2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04652-0-6/14(C) Rev. C | Page 33 of 33 Package Description 100-Ball CSP_BGA 100-Ball CSP_BGA Package Option BC-100-2 BC-100-2