AD5532-1

a FEATURES High Integration: 32-Channel DAC in 12 12 mm2 LFBGA Adjustable Voltage Output Range Guaranteed Monotonic Readback Capability DSP-/Microcontroller-Compatible Serial Interface Output Impedance 0.5 (AD5532-1, AD5532-2) 500 (AD5532-3) 1 k (AD5532-5) Output Voltage Span 10 V (AD5532-1, AD5532-3, AD5532-5) 20 V (AD5532-2) Infinite Sample-and-Hold Capability to 0.018% Accuracy Temperature Range –40 C to +85 C APPLICATIONS Level Setting Instrumentation Automatic Test Equipment Industrial Control Systems Data Acquisition Low Cost I/O 32-Channel, 14-Bit Voltage-Output DAC AD5532* GENERAL DESCRIPTION The AD5532 is a 32-channel voltage-output 14-bit DAC with an additional infinite sample-and-hold mode. The selected DAC register is written to via the 3-wire serial interface and VOUT for this DAC is then updated to reflect the new contents of the DAC register. DAC selection is accomplished via address bits A0–A4. The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from VSS + 2 V to VDD – 2 V because of the headroom of the output amplifier. The device is operated with AVCC = 5 V ± 5%, DVCC = 2.7 V to 5.25 V, VSS = –4.75 V to –16.5 V and VDD = 8 V to 16.5 V and requires a stable +3 V reference on REF_IN as well as an offset voltage on OFFS_IN. PRODUCT HIGHLIGHTS 1. 32-channel, 14-bit DAC in one package, guaranteed monotonic. 2. The AD5532 is available in a 74-lead LFBGA package with a body size of 12 mm × 12 mm. 3. Droopless/Infinite Sample-and-Hold Mode. FUNCTIONAL BLOCK DIAGRAM DVCC AVCC REF IN REF OUT OFFS IN VDD VSS AD5532 VOUT 0 VIN TRACK / RESET BUSY DAC GND AGND DGND MUX MODE ADC 14-BIT BUS DAC VOUT 31 DAC OFFS OUT DAC SER /PAR INTERFACE CONTROL LOGIC SYNC / CS ADDRESS INPUT REGISTER WR SCLK D IN D OUT A4 –A0 CAL OFFSET SEL *Protected by U.S. Patent No. 5,969,657; other patents pending. R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 (V 8 V t 16.5 V; AV 4.75 V to 5.25 V; DV = 2 AD5532–SPECIFICATIONS Output=Rangeo from V, V+ 2=V–t4.75 V–to2–16.5 outputs=unloaded. All specifications.7TV to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; V oV V. All DD SS CC CC SS DD MIN to TMAX unless otherwise noted.) Parameter1 DAC DC PERFORMANCE Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Gain Full-Scale Error VOLTAGE REFERENCE REF_IN Nominal Input Voltage Input Voltage Range3 Input Current REF_OUT Output Voltage Output Impedance3 Reference Temperature Coefficient 3 ANALOG OUTPUTS (VOUT 0–31) Output Temperature Coefficient 3, 4 DC Output Impedance3 AD5532-1 AD5532-3 AD5532-5 Output Range Resistive Load3, 5 Capacitive Load3, 5 AD5532-1 AD5532-3 AD5532-5 Short-Circuit Current3 DC Power-Supply Rejection Ratio3 DC Crosstalk3 ANALOG OUTPUT (OFFS_OUT) Output Temperature Coefficient 3, 4 DC Output Impedance3 Output Range Output Current Capacitive Load DIGITAL INPUTS3 Input Current Input Low Voltage Input High Voltage Input Hysteresis (SCLK and CS Only) Input Capacitance DIGITAL OUTPUTS (BUSY, DOUT)3 Output Low Voltage, DVCC = 5 V Output High Voltage, DVCC = 5 V Output Low Voltage, DVCC = 3 V Output High Voltage, DVCC = 3 V High Impedance Leakage Current High Impedance Output Capacitance A Version2 AD5532-1/-3/-5 AD5532-2 Only 14 ± 0.39 ±1 90/170/250 3.52 ±2 14 ± 0.39 ±1 180/350/500 7 ±2 Unit Bits % of FSR max LSB max mV min/typ/max typ % of FSR max Conditions/ Comments ± 0.15% typ ± 0.5% typ, Monotonic See Figure 6 3.0 2.85/3.15 1 3 280 60 20 0.5 500 1 VSS + 2/VDD – 2 5 500 15 40 10 –70 –70 250 20 1.3 50 to REF_IN–12 10 100 ± 10 0.8 0.4 2.4 2.0 200 10 0.4 4.0 0.4 2.4 ±1 15 3.0 2.85/3.15 1 3 280 60 20 0.5 V V min/max µA max V typ kΩ typ ppm/°C typ ppm/°C typ Ω typ Ω typ kΩ typ V min/max kΩ min pF max nF max nF max mA typ dB typ dB typ µV max ppm/°C typ kΩ typ mV typ µA max pF max µA max V max V max V min V min mV typ pF max V max V min V max V min µA max pF typ < 1 nA typ VSS + 2 /VDD – 2 5 500 100 µA Output Load 10 –70 –70 250 20 1.3 50 to REF_IN–12 10 100 ± 10 0.8 0.4 2.4 2.0 200 10 0.4 4.0 0.4 2.4 ±1 15 VDD = +15 V ± 5% VSS = –15 V ± 5% Source Current ± 5 µA typ DVCC = 5 V ± DVCC = 3 V ± DVCC = 5 V ± DVCC = 3 V ± 5% 10% 5% 10% Sinking 200 µA Sourcing 200 µA Sinking 200 µA Sourcing 200 µA DOUT Only DOUT Only –2– REV. 0 AD5532 Parameter1 POWER REQUIREMENTS Power-Supply Voltages VDD VSS AVCC DVCC Power-Supply Currents 6 IDD ISS AICC DICC Power Dissipation6 AC CHARACTERISTICS3 Output Voltage Settling Time OFFS_IN Settling Time Digital-to-Analog Glitch Impulse Digital Crosstalk Analog Crosstalk Digital Feedthrough Output Noise Spectral Density @ 1 kHz A Version2 AD5532-1/-3/-5 AD5532-2 Only Unit Conditions/ Comments 8/16.5 –4.75/–16.5 4.75/5.25 2.7/5.25 15 15 33 1.5 280 22 10 1 5 1 0.2 400 8/16.5 –4.75/–16.5 4.75/5.25 2.7/5.25 15 15 33 1.5 280 30 20 1 5 1 0.2 400 5 6 V min/max V min/max V min/max V min/max mA max mA max mA max mA max mW typ µs max µs max nV-s typ nV-s typ nV-s typ nV-s typ nV/(√Hz) typ 10 mA typ. All Channels Full-Scale 10 mA typ. All Channels Full-Scale 26 mA typ 1 mA typ VDD = 10 V, VSS = –5 V 500 pF, 5 kΩ Load Full-Scale Change 500 pF, 5 kΩ Load; 0 V–3 V Step 1 LSB Change Around Major Carry NOTES 1 See Terminology. 2 A Version: Industrial temperature range –40 °C to +85°C; typical at +25°C. 3 Guaranteed by design and characterization, not production tested. 4 AD780 as reference for the AD5532. Ensure that you do not exceed T J (max). See Maximum Ratings. Output unloaded. Specifications subject to change without noti ce. SHA MODE Parameter 1 A Version2 AD5532-1/-3/-5 AD5532-2 Only ± 0.018 ± 50 3.46/3.52/3.6 0 to 3 70 40 1 20 1 3 16 5 ± 0.018 ± 100 6.88/7/7.12 0 to 3 70 40 1 20 1 3 16 5 Unit % max mV max min/typ/max V mV max mV max µA max pF typ µA max µs max µs max nV-s typ Conditions/ Comments ± 0.006% typ after Offset and Gain Adjustment ± 10 mV typ. See Figure 7 See Figure 7 Nominal Input Range 50 mV typ. Referred to VIN. See Figure 7 12 mV typ. Referred to VIN. See Figure 7 100 nA typ. VIN Acquired on 1 Channel ANALOG CHANNEL VIN to VOUT Nonlinearity3 Offset Error Gain ANALOG INPUT (VIN) Input Voltage Range Input Lower Deadband Input Upper Deadband Input Current Input Capacitance4 ANALOG INPUT (OFFS_IN) Input Current AC CHARACTERISTICS Output Settling Time4 Acquisition Time AC Crosstalk4 NOTES 1 See Terminology. 100 nA typ Output Unloaded A version: Industrial temperature range –40 °C to +85°C; typical at +25°C. Input range 100 mV to 2.96 V. 4 Guaranteed by design and characterization, not production tested. 2 3 Specifications subject to change without notice. REV. 0 –3– AD5532 TIMING CHARACTERISTICS PARALLEL INTERFACE Parameter1, 2 t1 t2 t3 t4 t5 t6 Limit at TMIN, TMAX (A Version) 0 0 50 50 20 0 Unit ns min ns min ns min ns min ns min ns min Conditions/Comments CS to WR Setup Time CS to WR Hold Time CS Pulsewidth Low WR Pulsewidth Low A4–A0, CAL, OFFS_SEL to WR Setup Time A4–A0, CAL, OFFS_SEL to WR Hold Time NOTES 1 See Interface Timing Diagram. 2 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. SERIAL INTERFACE Parameter1, 2 fCLKIN t1 t2 t3 t4 t5 t6 t7 t8 4 t9 4 t10 t11 3 Limit at TMIN, TMAX (A Version) 14 28 28 10 50 10 5 5 20 60 400 400 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min ns min Conditions/Comments SCLK Frequency SCLK High Pulsewidth SCLK Low Pulsewidth SYNC Falling Edge to SCLK Falling Edge Setup Time SYNC Low Time DIN Setup Time DIN Hold Time SYNC Falling Edge to SCLK Rising Edge Setup Time SCLK Rising Edge to DOUT Valid SCLK Falling Edge to DOUT High Impedance 10th SCLK Falling Edge to SYNC Falling Edge for Readback 24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write NOTES 1 See Serial Interface Timing Diagrams. 2 Guaranteed by design and characterization, not production tested. 3 In SHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns. 4 These numbers are measured with the load circuit of Figure 2. Specifications subject to change without notice. PARALLEL INTERFACE TIMING DIAGRAMS CS TO OUTPUT PIN 200 A IOL WR 1.6V CL 50pF 200 A IOH A4 – A0, CAL, OFFS SEL Figure 1. Parallel Write (SHA Mode Only) Figure 2. Load Circuit for DOUT Timing Specifications –4– REV. 0 AD5532 SERIAL INTERFACE TIMING DIAGRAMS t1 SCLK 1 t3 2 t2 3 4 5 6 7 8 9 10 SYNC t4 t5 t6 DIN MSB LSB Figure 3. 10-Bit Write (SHA Mode and Both Readback Modes) t1 SCLK 1 t3 2 t2 3 4 5 21 22 23 24 1 SYNC t4 t5 t6 t 11 DIN MSB LSB Figure 4. 24-Bit Write (DAC Mode) t1 SCLK 10 t7 1 2 t2 3 4 5 6 7 8 9 10 11 12 13 14 SYNC t 10 DOUT MSB t4 t8 t9 LSB Figure 5. 14-Bit Read (Both Readback Modes) REV. 0 –5– AD5532 ABSOLUTE MAXIMUM RATINGS 1, 2 (TA = 25°C unless otherwise noted) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V AVCC to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V Digital Outputs to DGND . . . . . . . . . –0.3 V to DVCC + 0.3 V REF_IN to AGND, DAC_ GND . . . . . . . . . . –0.3 V to +7 V VIN to AGND, DAC_GND . . . . . . . . . . . . . . . –0.3 V to +7 V VOUT0–31 to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V VOUT0–31 to VSS . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +24 V OFFS_IN to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V OFFS_OUT to AGND . . . . AGND – 0.3 V to AVCC + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C 74-Lead LFBGA Package, θJA Thermal Impedance . . . 41°C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Model AD5532ABC-1 AD5532ABC-2 AD5532ABC-3 AD5532ABC-5 AD5533ABC-1* EVAL-AD5532EB *Separate Data Sheet. Function 32 DACs, 32-Channel SHA 32 DACs, 32-Channel SHA 32 DACs, 32-Channel SHA 32 DACs, 32-Channel SHA 32-Channel SHA Only Evaluation Board Output Impedance 0.5 Ω typ 0.5 Ω typ 500 Ω typ 1 kΩ typ 0.5 Ω typ Output Voltage Span 10 V 20 V 10 V 10 V 10 V Package Description 74-Lead LFBGA 74-Lead LFBGA 74-Lead LFBGA 74-Lead LFBGA 74-Lead LFBGA Package Option BC-74 BC-74 BC-74 BC-74 BC-74 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5532 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –6– REV. 0 AD5532 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L A B C D E F G H J K L 1 2 3 4 5 6 7 8 9 10 11 74-Lead LFBGA Ball Configuration LFBGA Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C6 Ball Name N/C A4 A2 A0 CS/SYNC DVCC SCLK OFFSET_SEL BUSY TRACK/RESET N/C VO16 N/C A3 A1 WR DGND DIN CAL SER/PAR DOUT REF_IN VO18 DAC_GND1 N/C LFBGA Number C10 C11 D1 D2 D10 D11 E1 E2 E10 E11 F1 F2 F10 F11 G1 G2 G10 G11 H1 H2 H10 H11 J1 J2 J6 Ball Name AVCC1 REF_OUT VO20 DAC_GND2 AVCC2 OFFS_OUT VO26 VO14 AGND1 OFFS_IN VO25 VO21 AGND2 VO6 VO24 VO8 VO5 VO3 VO23 VIN VO4 VO7 VO22 VO19 VSS2 LFBGA Number J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 Ball Name VO9 VO11 VO17 VO15 VO27 VSS3 VSS1 VSS4 VDD2 VO2 VO10 VO13 VO12 N/C VO28 VO29 VO30 VDD3 VDD1 VDD4 VO31 VO0 VO1 N/C REV. 0 –7– AD5532 PIN FUNCTION DESCRIPTION Pin AGND (1–2) AVCC (1–2) VDD (1–4) VSS (1–4) DGND DVCC DAC_GND(1–2) REF_IN REF_OUT VOUT (0–31) VIN A4–A11, A02 CAL1 CS/SYNC WR1 OFFSET_SEL1 SCLK2 DIN2 DOUT SER/PAR1 OFFS_IN OFFS_OUT BUSY TRACK/RESET2 Function Analog GND Pins. Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. VDD Supply Pins. Voltage range from 8 V to 16.5 V. VSS Supply Pins. Voltage range from –4.75 V to –16.5 V. Digital GND Pins. Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. Reference GND Supply for All the DACs. Reference Voltage for Channels 0–31. Reference Output Voltage. Analog Output Voltages from the 32 Channels. Analog Input Voltage. Connect this to AGND if operating in DAC mode only. Parallel Interface: 5-Address Pins for 32 Channels. A4 = MSB of Channel Address. A0 = LSB. Parallel Interface: Control input that allows all 32 channels to acquire VIN simultaneously. This pin is both the active low Chip Select pin for the parallel interface and the Frame Synchronization pin for the serial interface. Parallel Interface: Write pin. Active low. This is used in conjunction with the CS pin to address the device using the parallel interface. Parallel Interface: Offset Select Pin. Active high. This is used to select the offset channel. Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in SHA mode). Data Input for Serial Interface. Data must be valid on the falling edge of SCLK. Output from the DAC Registers for readback. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low, the parallel interface will be used. If it is tied high, the serial interface will be used. Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to this pin if the user wants to drive this pin with the Offset Channel. Offset Output. This is the acquired/programmed offset voltage which can be tied to OFFS_IN to offset the span. This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns high when the acquisition operation is complete. If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the gain/offset stage is switched directly to VIN. The addressed channel begins to acquire VIN on the rising edge of TRACK. See TRACK Input section for further information. This input can also be used as a means of resetting the complete device to its power-on-reset conditions. This is achieved by applying a low-going pulse of between 50 ns and 150 ns to this pin. See section on RESET Function for further details. NOTES 1 Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition. 2 Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition. OUTPUT VOLTAGE FULL-SCALE ERROR RANGE IDEAL GAIN IDEAL TRANSFER FUNCTION OFFSET RANGE 0 DAC CODE REFIN VOUT GAIN ERROR + OFFSET ERROR IDEAL TRANSFER FUNCTION OFFSET ERROR ACTUAL TRANSFER FUNCTION IDEAL GAIN 50mV 16k 0V 70mV 2.96 3V UPPER DEADBAND VIN LOWER DEADBAND Figure 6. DAC Transfer Function (OFFS_IN = 0) Figure 7. SHA Transfer Function –8– REV. 0 AD5532 TERMINOLOGY DAC MODE Integral Nonlinearity (INL) Output Noise Spectral Density This is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed as a percentage of full-scale span. Differential Nonlinearity (DNL) This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per root Hertz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/(√Hz)1/2. Output Temperature Coefficient Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ± 1 LSB maximum ensures monotonicity. Offset This is a measure of the change in analog output with changes in temperature. It is expressed in ppm/°C. DC Power-Supply Rejection Ratio DC Power-Supply Rejection Ratio (PSRR) is a measure of the change in analog output for a change in supply voltage (VDD and VSS). It is expressed in dBs. VDD and VSS are varied ± 5%. DC Crosstalk Offset is a measure of the output with all zeros loaded to the DAC and OFFS_IN = 0. Since the DAC is lifted off the ground by approximately 50 mV, this output will typically be: VOUT = Gain × 50 mV Full-Scale Error This the DC change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of all other DACs. It is expressed in µV. SHA MODE VIN to VOUT Nonlinearity This is a measure of the output error with all 1s loaded to the DAC. It is expressed as a percentage of full-scale range. See Figure 6. It is calculated as: Full-Scale Error = VOUT(Full-Scale) – (Ideal Gain × REFIN) where Ideal Gain = 3.52 for AD5532-1/-3/-5 Ideal Gain = 7 for AD5532-2 Output Settling Time This is a measure of the maximum deviation from a straight line passing through the endpoints of the VIN versus VOUT transfer function. It is expressed as a percentage of the full-scale span. Offset Error This is a measure of the output error when VIN = 70 mV. Ideally, with VIN = 70 mV: VOUT = (Gain × 70) – ((Gain – 1) × VOFFS_IN) mV Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal). It is expressed in mV and can be positive or negative. See Figure 7. Gain Error This is the time taken from when the last data bit is clocked into the DAC until the output has settled to within ± 0.39%. OFFS_IN Settling Time This is the time taken from a 0 V–3 V step change in input voltage on OFFS_IN until the output has settled to within ± 0.39%. Digital-to-Analog Glitch Impulse This is the area of the glitch injected into the analog output when the code in the DAC register changes state. It is specified as the area of the glitch in nV-secs when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). Digital Crosstalk This is a measure of the span error of the analog channel. It is the deviation in slope of the transfer function expressed in mV. See Figure 7. It is calculated as: Gain Error = Actual Full-Scale Output – Ideal Full-Scale Output – Offset Error where Ideal Full-Scale Output = Gain × 2.96 – ((Gain – 1) × VOFFS_IN) AC Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale while a full-scale code change (all 1s to all 0s and vice versa) is being written to another DAC. It is expressed in nV-secs. Analog Crosstalk This is the area of the glitch that occurs on the output of one channel while another channel is acquiring. It is expressed in nV-secs. Output Settling Time This the area of the glitch transferred to the output (VOUT) of one DAC due to a full-scale change in the output (VOUT) of another DAC. The area of the glitch is expressed in nV-secs. Digital Feedthrough This is the time taken from when BUSY goes high to when the output has settled to ± 0.018%. Acquisition Time This is a measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to, i.e., CS/SYNC is high. It is specified in nV-secs and is measured with a worst-case change on the digital input pins, e.g., from all 0s to all 1s and vice versa. This is the time taken for the VIN input to be acquired. It is the length of time that BUSY stays low. REV. 0 –9– AD5532 –Typical Performance Characteristics 1.0 0.8 0.6 DNL ERROR – LSBs VREFIN = 3V VOFFS_IN = 0V TA = 25 C DNL ERROR – LSBs 1.0 0.2 5.325 DAC LOADED TO MIDSCALE VREFIN = 3V VOFFS_IN = 0V 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 2k 4k 6k 8k 10k 12k 14k 16k DAC CODE INL MAX 0.0 INL MIN –0.1 0.0 INL ERROR – % FSR 0.5 DNL MAX 5.315 0.1 VOUT – V 5.305 5.295 –0.5 DNL MIN 5.285 –1.0 –40 –0.2 0 40 TEMPERATURE – C 80 5.275 –40 0 40 TEMPERATURE – C 80 Figure 8. Typical DNL Plot Figure 9. INL Error and DNL Error vs. Temperature Figure 10. VOUT vs. Temperature 3.535 TA = 25 C VREFIN = 3V 10.0 TA = 25 C VREFIN = 3V VOFFS_IN = 0.5V 5.309 5.308 5.307 5.306 5.305 5.304 5.303 TA = 25 C VREFIN = 3V VOFFS_IN = 0V 8.0 3.530 VOUT – V VOUT – V 6.0 VOUT – V 4.0 3.525 2.0 0.0 5.302 3.520 –2.0 5.301 6 4 2 –2 –4 0 SINK/SOURCE CURRENT – mA –6 TIME BASE – 2 s/DIV TIME BASE – 50ns/DIV Figure 11. VOUT Source and Sink Capability Figure 12. Full-Scale Settling Time Figure 13. Major Code Transition Glitch Impulse 0.0024 0.0020 0.0016 0.0012 TA = 25 C VREFIN = 3V VOFFS_IN = 0V 100 90 70k 63791 60k 50k FREQUENCY 5V BUSY VOUT TA = 25 C VREFIN = 3V VIN = 0 1.5V 1V VIN – V 2.96 TA = 25 C VREFIN = 3V VIN = 1.5V VOFFS_IN = 0V VOUT ERROR – V 0.0008 0.0004 0.0000 –0.0004 –0.0008 –0.0012 –0.0016 –0.0020 –0.0024 0.1 40k 30k 20k 10k 10 0% 2s 0 200 5.2670 5.2676 VOUT – V 1545 5.2682 Figure 14. VIN to VOUT Accuracy After Offset and Gain Adjustment (SHA Mode) Figure 15. Acquisition Time and Output Settling Time (SHA Mode) Figure 16. SHA-Mode Repeatability (64K Acquisitions) –10– REV. 0 AD5532 FUNCTIONAL DESCRIPTION Reset Function The AD5532 can be thought of as consisting of 32 DACs and an ADC (for SHA mode) in a single package. In DAC mode a 14-bit digital word is loaded into one of the 32 DAC registers via the serial interface. This is then converted (with gain and offset) into an analog output voltage (VOUT0–VOUT31). To update a DAC’s output voltage the required DAC is addressed via the serial port. When the DAC address and code have been loaded the selected DAC converts the code. On power-on, all the DACs, including the offset channel, are loaded with zeros. The internal DAC outputs are at 50 mV typical (negative full-scale). If the OFFS_IN pin is driven by the on-board offset channel, the outputs VOUT0 to VOUT31 are also at 50 mV on power-on since OFFS_IN = 50 mV, VOUT = (Gain × VDAC) –(Gain –1) × VOFFS_IN = 50 mV. Output Buffer Stage—Gain and Offset The reset function on the AD5532 can be used to reset all nodes on this device to their power-on-reset condition. This is implemented by applying a low-going pulse of between 50 ns and 150 ns to the TRACK/RESET pin on the device. If the applied pulse is less than 50 ns it is assumed to be a glitch and no operation takes place. If the applied pulse is wider than 150 ns this pin adopts its track function on the selected channel, VIN is switched to the output buffer and an acquisition on the channel will not occur until a rising edge of TRACK. SHA Mode The function of the output buffer stage is to translate the 0 V–3 V output of the DAC to a wider range. This is done by gaining up the DAC output by 3.52/7 and offsetting the voltage by the voltage on OFFS_IN pin. AD5532-1/AD5532-3/AD5532-5: In SHA mode the input voltage VIN is sampled and converted into a digital word. The noninverting input to the output buffer (gain and offset stage) is tied to VIN during the acquisition period to avoid spurious outputs while the DAC acquires the correct code. This is completed in 16 µs max. At this time the updated DAC output assumes control of the output voltage. The output voltage of the DAC is connected to the noninverting input of the output buffer. Since the channel output voltage is effectively the output of a DAC there is no droop associated with it. As long as power is maintained to the device the output voltage will remain constant until this channel is addressed again. Analog Input (SHA Mode) VOUT = 3.52 × VDAC – 2.52 × VOFFS_IN AD5532-2: VOUT = 7 × VDAC – 6 × VOFFS_IN VDAC is the output of the DAC. VOFFS_IN is the voltage at the OFFS_IN pin. The following table shows how the output range on VOUT relates to the offset voltage supplied by the user: Table I. Sample Output Voltage Ranges The equivalent analog input circuit is shown in Figure 17. The Capacitor C1 is typically 20 pF and can be attributed to pin capacitance and 32 off-channels. When a channel is selected, an extra 7.5 pF (typ) is switched in. This Capacitor C2 is charged to the previously acquired voltage on that particular channel so it must charge/discharge to the new level. It is essential that the external source can charge/discharge this additional capacitance within 1 µs–2 µs of channel selection so that VIN can be acquired accurately. For this reason a low impedance source is recommended. ADDRESSED CHANNEL VIN C1 20pF C2 7.5pF VOFFS_IN (V) 0.5 1 VDAC (V) 0 to 3 0 to 3 VOUT (AD5532-1/-3/-5) –1.26 to +9.3 –2.52 to +8.04 VOUT (AD5532-2) Headroom Limited –6 to +15 VOUT is limited only by the headroom of the output amplifiers. VOUT must be within maximum ratings. Offset Voltage Channel The offset voltage can be externally supplied by the user at OFFS_IN or it can be supplied by an additional offset voltage channel on the device itself. The offset can be set up in two ways. In SHA mode the required offset voltage is set up on VIN and acquired by the offset channel. In DAC mode the code corresponding to the offset value is loaded directly into the offset DAC. This offset channel’s DAC output is directly connected to OFFS_OUT. By connecting OFFS_OUT to OFFS_IN this offset voltage can be used as the offset voltage for the 32 output amplifiers. It is important to choose the offset so that VOUT is within maximum ratings. Figure 17. Analog Input Circuit Large source impedances will significantly affect the performance of the ADC. This may necessitate the use of an input buffer amplifier. TRACK Function (SHA Mode) Normally in SHA mode of operation, TRACK is held high and the channel begins to acquire when it is addressed. However, if TRACK is low when the channel is addressed, VIN is switched to the output buffer and an acquisition on the channel will not occur until a rising edge of TRACK. At this stage the BUSY pin will go low until the acquisition is complete, at which point the DAC assumes control of the voltage to the output buffer and VIN is free to change again without affecting this output value. REV. 0 –11– AD5532 PIN DRIVER VIN BUSY TRACK OUTPUT STAGE VOUT1 DEVICE UNDER TEST CONTROLLER DAC ACQUISITION CIRCUIT AD5532 THRESHOLD VOLTAGE ONLY ONE CHANNEL SHOWN FOR SIMPLICITY Figure 18. Typical ATE Circuit Using TRACK Input This is useful in an application where the user wants to ramp up VIN until VOUT reaches a particular level (Figure 18). VIN does not need to be acquired continuously while it is ramping up. TRACK can be kept low and only when VOUT has reached its desired voltage is TRACK brought high. At this stage, the acquisition of VIN begins. In the example shown, a desired voltage is required on the output of the pin driver. This voltage is represented by one input to a comparator. The microcontroller/microprocessor ramps up the input voltage on VIN through a DAC. TRACK is kept low while the voltage on VIN ramps up so that VIN is not continually acquired. When the desired voltage is reached on the output of the pin driver, the comparator output switches. The µC/µP then knows what code is required to be input in order to obtain the desired voltage at the DUT. The TRACK input is now brought high and the part begins to acquire VIN. At this stage BUSY goes low until VIN has been acquired. The output buffer is then switched from VIN to the output of the DAC. MODES OF OPERATION DOUT line in a 14-bit serial format. The full acquisition time must elapse before the DAC register data can be clocked out. 4. Readback Mode Again, this is a readback mode but no acquisition is performed. The relevant channel is addressed (10-bit write, MSB first) and on the next falling edge of SYNC, the data in the relevant DAC register is clocked out onto the DOUT line in a 14-bit serial format. The user must allow 400 ns (min) between the last SCLK falling edge in the 10-bit write and the falling edge of SYNC in the 14-bit readback. The serial write and read words can be seen in Figure 19. This feature allows the user to read back the DAC register code of any of the channels. In DAC mode this is useful in verification of write cycles. In SHA mode readback is useful if the system has been calibrated and the user wants to know what code in the DAC corresponds to a desired voltage on VOUT. If the user requires this voltage again, he can input the code directly to the DAC register without going through the acquisition sequence. INTERFACES Serial Interface The AD5532 can be used in four different modes of operation. These modes are set by two mode bits, the first two bits in the serial word. Table II. Modes of Operation The SER/PAR pin is tied high to enable the serial interface and to disable the parallel interface. The serial interface is controlled by four pins as follows: SYNC, DIN, SCLK Mode Bit 1 0 0 1 1 1. DAC Mode Mode Bit 2 0 1 0 1 Operating Mode SHA Mode DAC Mode Acquire and Readback Readback Standard 3-wire interface pins. The SYNC pin is shared with the CS function of the parallel interface. DOUT Data Out pin for reading back the contents of the DAC registers. The data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. Mode Bits In this standard mode a selected DAC register is loaded serially. This requires a 24-bit write (10 bits to address the relevant DAC plus an extra 14 bits of DAC data). MSB is written first. The user must allow 400 ns (min) between successive writes in DAC mode. 2. SHA Mode There are four different modes of operation as described above. Cal Bit In this mode a channel is addressed and that channel acquires the voltage on VIN. This mode requires a 10-bit write (see Figure 21) to address the relevant channel (VOUT0–VOUT31, offset channel or all channels) MSB is written first. 3. Acquire and Readback Mode In DAC mode this is a test bit. When it is high it is used to load all zeros or all ones to the 32 DACs simultaneously. In SHA mode all 32 channels acquire VIN simultaneously when this bit is high. In SHA mode the acquisition time is then 45 µs (typ) and accuracy may be reduced. This bit is set low for normal operation. Offset_Sel Bit If this is set high, the offset channel is selected and Bits A4– A0 are ignored. Test Bit This mode allows the user to acquire VIN and read back the data in a particular DAC register. The relevant channel is addressed (10-bit write, MSB first) and VIN is acquired in 16 µs (max). Following the acquisition, after the next falling edge of SYNC , the data in the relevant DAC register is clocked out onto the This must be set low for correct operation of the part. A4–A0 Used to address any one of the 32 channels (A4 = MSB of address, A0 = LSB). REV. 0 –12– AD5532 MSB 0 MODE BIT 1 0 MODE BIT 2 CAL OFFSET SEL 0 TEST BIT LSB A4 – A0 MODE BITS a. 10-Bit Input Serial Write Word (SHA Mode) MSB 0 1 CAL OFFSET SEL 0 TEST BIT MODE BITS A4 – A0 DB1 3 – DB0 LSB b. 24-Bit Input Serial Write Word (DAC Mode) MSB 1 0 CAL OFFSET SEL 0 TEST BIT MODE BITS 10-BIT SERIAL WORD WRITTEN TO PART 14-BIT DATA READ FROM PART AFTER NEXT FALLING EDGE OF SYNC (DB13 = MSB OF DAC WORD) LSB A4 – A0 MSB DB1 3 – DB0 LSB c. Input Serial Interface (Acquire and Readback Mode) MSB 1 1 CAL OFFSET SEL 0 TEST BIT MODE BITS 10-BIT SERIAL WORD WRITTEN TO PART 14-BIT DATA READ FROM PART AFTER NEXT FALLING EDGE OF SYNC (DB13 = MSB OF DAC WORD) LSB A4 – A0 MSB DB1 3 – DB0 LSB d. Input Serial Interface (Readback Mode) Figure 19. Serial Interface Formats DB13–DB0 These are used to write a 14-bit word into the addressed DAC register. Clearly, this is only valid when in DAC mode. The serial interface is designed to allow easy interfacing to most microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI, SPI, DSP56000, TMS320, and ADSP-21xx, without the need for any glue logic. When interfacing to the 8051, the SCLK must be inverted. The Microprocessor/Microcontroller Interface section explains how to interface to some popular DSPs and microcontrollers. Figures 3, 4, and 5 show the timing diagram for a serial read and write to the AD5532. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers. Any further edges on SYNC are ignored until the correct number of bits are shifted in or out. Once the correct number of bits for the selected mode have been shifted in or out, the SCLK is ignored. In order for another serial transfer to take place the counter must be reset by the falling edge of SYNC. In readback, the first rising SCLK edge after the falling edge of SYNC causes DOUT to leave its high impedance state and data is clocked out onto the DOUT line and also on subsequent SCLK rising edges. The DOUT pin goes back into a high impedance state on the falling edge of the fourteenth SCLK. Data on the DIN line is latched in on the first SCLK falling edge after the REV. 0 falling edge of the SYNC signal and on subsequent SCLK falling edges. During readback DIN is ignored. The serial interface will not shift data in or out until it receives the falling edge of the SYNC signal. Parallel Interface (SHA Mode Only) The SER/PAR bit must be tied low to enable the parallel interface and disable the serial interface. The parallel interface is controlled by 9 pins. CS Active low package select pin. This pin is shared with the SYNC function for the serial interface. WR Active low write pin. The values on the address pins are latched on a rising edge of WR. A4–A0 Five address pins (A4 = MSB of address, A0 = LSB). These are used to address the relevant channel (out of a possible 32). Offset_Sel Offset select pin. This has the same function as the Offset_Sel bit in the serial interface. When it is high, the offset channel is addressed. The address on A4–A0 is ignored in this case. Cal When this pin is high, all 32 channels acquire VIN simultaneously. The acquisition time is then 45 µs (typ) and accuracy may be reduced. –13– AD5532 MICROPROCESSOR INTERFACING AD5532 to ADSP-21xx Interface AD5532* D OUT SYNC SCLK D IN *ADDITIONAL PINS OMITTED FOR CLARITY MISO PC7 SCK MOSI MC68HC11* The ADSP-21xx family of DSPs are easily interfaced to the AD5532 without the need for extra logic. A data transfer is initiated by writing a word to the TX register after the SPORT has been enabled. In a write sequence data is clocked out on each rising edge of the DSP’s serial clock and clocked into the AD5532 on the falling edge of its SCLK. In readback 16 bits of data are clocked out of the AD5532 on each rising edge of SCLK and clocked into the DSP on the rising edge of SCLK. DIN is ignored. The valid 14 bits of data will be centered in the 16-bit RX register when using this configuration. The SPORT control register should be set up as follows: TFSW INVRFS DTYPE ISCLK TFSR IRFS ITFS SLEN SLEN SLEN = RFSW = 1, Alternate Framing = INVTFS = 1, Active Low Frame Signal = 00, Right Justify Data = 1, Internal Serial Clock = RFSR = 1, Frame Every Word = 0, External Framing Signal = 1, Internal Framing Signal = 1001, 10-Bit Data Words (SHA Mode Write) = 0111, 3× 8-Bit Data Words (DAC Mode Write) = 1111, 16-Bit Data Words (Readback Mode) Figure 21. AD5532 to MC68HC11 Interface AD5532 to PIC16C6x/7x The PIC16C6x/7x Synchronous Serial Port (SSP) is configured as an SPI Master with the Clock Polarity bit = 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). See user PIC16/17 Microcontroller User Manual. In this example I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5532. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two or three consecutive read/write operations are needed depending on the mode. Figure 22 shows the connection diagram. AD5532* SCLK D OUT D IN PIC16C6x/7x* SCK/RC3 SDO/RC5 SDI/RC4 RA1 Figure 20 shows the connection diagram. AD5532* D OUT SYNC DR TFS RFS D IN SCLK *ADDITIONAL PINS OMITTED FOR CLARITY DT SCLK ADSP-2101/ ADSP-2103* SYNC *ADDITIONAL PINS OMITTED FOR CLARITY Figure 22. AD5532 to PIC16C6x/7x Interface AD5532 to 8051 Figure 20. AD5532 to ADSP-2101/ADSP-2103 Interface AD5532 to MC68HC11 The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for Master Mode (MSTR = 1), Clock Polarity Bit (CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is configured by writing to the SPI Control Register (SPCR)—see 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5532, the MOSI output drives the serial data line (DIN) of the AD5532 and the MISO input is driven from DOUT. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5532, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to transmit 10-data bits in SHA mode it is important to left-justify the data in the SPDR register. PC7 must be pulled low to start a transfer. It is taken high and pulled low again before any further read/write cycles can take place. A connection diagram is shown in Figure 21. The AD5532 requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode serial data enters and exits through RxD and a shift clock is output on TxD. Figure 23 shows how the 8051 is connected to the AD5532. Because the AD5532 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD5532 requires its data with the MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account. AD5532* SCLK D OUT D IN SYNC *ADDITIONAL PINS OMITTED FOR CLARITY P1.1 TxD RxD 8051* Figure 23. AD5532 to 8051 Interface –14– REV. 0 AD5532 APPLICATION CIRCUITS AD5532 in a Typical ATE System POWER SUPPLY DECOUPLING The AD5532 is ideally suited for use in Automatic Test Equipment. Several DACs are required to control pin drivers, comparators, active loads and signal timing. Traditionally, sample-and-hold devices were used in this application. The AD5532 has several advantages: no refreshing is required, there is no droop, pedestal error is eliminated and there is no need for extra filtering to remove glitches. Overall a higher level of integration is achieved in a smaller area (see Figure 24). PARAMETRIC MEASUREMENT SYSTEM BUS UNIT DAC DAC DAC ACTIVE LOAD STORED DATA AND INHIBIT PATTERN FORMATTER In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5532 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the AD5532 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (VSS, VDD, AVCC) it is recommended to tie those pins together. The AD5532 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. The power supply lines of the AD5532 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). It is essential to minimize noise on VIN and REFIN lines. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a doublesided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. DRIVER DAC DAC PERIOD GENERATION AND DELAY TIMING DUT DAC COMPARE REGISTER DAC COMPARATOR DACs SYSTEM BUS Figure 24. AD5532 in an ATE System Typical Application Circuit (SHA Mode) The AD5532 can be used to set up voltage levels on 32 channels as shown in the circuit below. An AD780 provides the 3 V reference for the AD5532, and for the AD5541 16-bit DAC. A simple 3-wire interface is used to write to the AD5541. The DAC output is buffered by an AD820. It is essential to minimize noise on VIN and REFIN when laying out this circuit. AVCC AVCC DVCC VSS VDD AD5541* AD820 VIN CS DIN SCLK AD5532* REF OFFS_IN OFFS_OUT REFIN VOUT 0–31 AD780* VOUT SCLK DIN *ADDITIONAL PINS OMITTED FOR CLARITY SYNC Figure 25. Typical Application Circuit REV. 0 –15– AD5532 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 74-Lead LFBGA (BC-74) 0.394 (10.00) BSC 11 10 9 8 7 6 5 4 3 2 1 0.472 (12.00) BSC A1 TOP VIEW 0.472 (12.00) BSC 0.039 (1.00) BSC BOTTOM VIEW A B C D E 0.394 F (10.00) G BSC H J K L DETAIL A 0.067 (1.70) MAX 0.010 (0.25) MIN 0.039 (1.00) BSC DETAIL A 0.033 (0.85) MIN 0.024 (0.60) BSC BALL DIAMETER SEATING PLANE CONTROLLING DIMENSIONS ARE IN MILLIMETERS –16– REV. 0 PRINTED IN U.S.A. C3744–2.5–4/00 (rev. 0) 00939