AD5560JBCZ-REEL

Data Sheet AD5560 1.2 A Programmable Device Power Supply with Integrated 16-Bit Level Setting DACs FEATURES ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► GENERAL DESCRIPTION Programmable device power supply (DPS) ► FV, MI, MV, FNMV functions 5 internal current ranges (on-chip RSENSE) ► ±5 µA, ±25 µA, ±250 µA, ±2.5 mA, ±25 mA 2 external high current ranges (external RSENSE) ► EXTFORCE1: ±1.2 A maximum ► EXTFORCE2: ±500 mA maximum Integrated programmable levels ► All 16-bit DACs: force DAC, comparator DACs, clamp DACs, offset DAC, OSD DAC, DGS DAC Programmable Kelvin clamp and alarm Offset and gain correction registers on-chip Ramp mode on force DAC for power supply slewing Programmable slew rate feature, 1 V/μs to 0.3 V/μs DUTGND Kelvin sense and alarm 25 V FV span with asymmetrical operation within −22 V/+25 V On-chip comparators Gangable for higher current Guard amplifier System PMU connections Current clamps Die temperature sensor and shutdown feature On-chip diode thermal array Diagnostic register allows access to internal nodes Open-drain alarm flags (temperature, current clamp, Kelvin alarm) SPI-/MICROWIRE-/DSP-compatible interface 64-lead (10 mm × 10 mm) TQFP with exposed pad (on top) 72-ball (8 mm × 8 mm) flip-chip BGA The AD5560 is a high performance, highly integrated device power supply consisting of programmable force voltages and measure ranges. This part includes the required DAC levels to set the programmable inputs for the drive amplifier, as well as clamping and comparator circuitry. Offset and gain correction is included on-chip for DAC functions. A number of programmable measure current ranges are available: five internal fixed ranges and two external customer-selectable ranges (EXTFORCE1 and EXTFORCE2) that can supply currents up to ±1.2 A and ±500 mA, respectively. The voltage range possible at this high current level is limited by headroom and the maximum power dissipation. Current ranges in excess of ±1.2 A or at high current and high voltage combinations can be achieved by paralleling or ganging multiple DPS devices. Open-drain alarm outputs are provided in the event of overcurrent, overtemperature, or Kelvin alarm on either the SENSE or DUTGND line. The DPS functions are controlled via a simple 3-wire serial interface compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards running at clock speeds of up to 50 MHz. APPLICATIONS ► Automatic test equipment (ATE) ► Device power supply Rev. F DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Data Sheet AD5560 TABLE OF CONTENTS Features................................................................ 1 Applications........................................................... 1 General Description...............................................1 Functional Block Diagram......................................3 Specifications........................................................ 4 Timing Characteristics......................................12 Timing Diagrams.............................................. 13 Absolute Maximum Ratings.................................15 ESD Caution.....................................................15 Pin Configurations and Function Descriptions.....16 Typical Performance Characteristics................... 20 Terminology......................................................... 28 Theory of Operation.............................................29 Force Amplifier................................................. 29 DAC Reference Voltage (VREF)........................ 29 Open-Sense Detect (OSD) Alarm and Clamp..29 Device Under Test Ground (DUTGND)............ 29 GPO................................................................. 29 Comparators.....................................................30 Current Clamps................................................ 30 Short-Circuit Protection.................................... 30 Guard Amplifier................................................ 30 Compensation Capacitors................................ 30 Current Range Selection.................................. 31 High Current Ranges........................................31 Ideal Sequence for Gang Mode....................... 33 Compensation for Gang Mode......................... 33 System Force/Sense Switches.........................34 Die Temperature Sensor and Thermal Shutdown....................................................... 34 Measure Output (MEASOUT).......................... 34 VMID Voltage..................................................... 34 Force Amplifier Stability....................................36 Poles and Zeros in a Typical System............... 37 Minimizing the Number of External Compensation Components...........................37 Extra Poles and Zeros in the AD5560.............. 37 Compensation Strategies................................. 38 Optimizing Performance for a Known Capacitor Using Autocompensation Mode..... 38 Adjusting the Autocompensation Mode............39 Dealing with Parallel Load Capacitors..............39 DAC Levels...................................................... 40 Force and Comparator DACs...........................40 Clamp DACs.....................................................40 OSD DAC......................................................... 40 DUTGND DAC................................................. 40 Offset DAC....................................................... 40 Offset and Gain Registers................................ 41 Reference Selection......................................... 41 Calibration........................................................ 41 Additional Calibration....................................... 42 System Level Calibration..................................42 Choosing AVDD/AVSS Power Supply Rails....... 42 Choosing HCAVSSx and HCAVDDx Supply Rails............................................................... 43 Power Dissipation.............................................43 Package Composition and Maximum Vertical Force................................................. 43 Slew Rate Control............................................ 43 Serial Interface.................................................... 45 SPI Interface.....................................................45 SPI Write Mode................................................ 45 SDO Output......................................................45 RESET Function...............................................45 BUSY Function.................................................45 LOAD Function.................................................45 Register Update Rates..................................... 46 Control Registers.................................................47 DPS and DAC Addressing............................... 47 Readback Mode............................................... 57 DAC Readback.................................................58 Power-On Default.............................................58 Using the HCAVDDx and HCAVSSx Supplies....59 Power Supply Sequencing............................... 59 Required External Components....................... 60 Power Supply Decoupling................................ 61 Applications Information...................................... 63 Thermal Considerations................................... 63 Temperature Contour Map on the Top of the Package......................................................... 64 Outline Dimensions............................................. 65 Ordering Guide.................................................65 Evaluation Boards............................................ 66 REVISION HISTORY 11/2022—Rev. E to Rev. F Changes to RESET Function Section............................................................................................................45 Changes to Table 23...................................................................................................................................... 53 analog.com Rev. F | 2 of 66 Data Sheet AD5560 FUNCTIONAL BLOCK DIAGRAM Figure 1. analog.com Rev. F | 3 of 66 Data Sheet AD5560 SPECIFICATIONS HCAVDDx ≤ (AVSS + 33 V), HCAVDDx ≤ AVDD, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, DVCC = 2.3 V to 5.5 V, VREF = 5 V, gain (m), offset (c), and DAC offset registers are at default values; AGND = DGND = 0 V; TJ = 25°C to 90°C, maximum specifications, unless otherwise noted. FSV is full-scale voltage, FSVR is full-scale voltage range, FSC is full-scale current, FSCR is full-scale current range. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments AVSS + 2.25 AVDD − 2.25 V Allow ±500 mV for external RSENSE voltage drop HCAVSS1x + 1.75 HCAVSS1x − 1.75 V Allow ±500 mV for external RSENSE voltage drop HCAVSS1x + 1.2 5 HCAVDD1x − 1.2 V 5 Allow ±500 mV for external RSENSE voltage drop; reduced headroom/footroom, clamps must be enabled2 AVSS + 2.25 AVDD − 2.25 V Allow ±500 mV for external RSENSE voltage drop HCAVSS2x + 1.75 HCAVDD2x − 1.7 V 5 Allow ±500 mV for external RSENSE voltage drop HCAVSS2x + 1.25 HCAVDD2x − 1.2 V 5 Allow ±500 mV for external RSENSE voltage drop; reduced headroom/footroom, clamps must be enabled2 AVSS + 2.75 AVDD − 2.75 V Internal current ranges, includes ±500 mV for internal RSENSE voltage drop Headroom/Footroom1 −2.75 +2.75 V Internal current ranges to AVDD/AVSS, includes ±500 mV for internal RSENSE voltage drop Headroom/Footroom1 −2.25 +2.25 V External current ranges, EXTFORCE1/ EXTFORCE2 to HCAVDDx and HCAVSSx supplies; includes ±500 mV for external RSENSE voltage drop Force Output Voltage Span −22 +25 V May be a skewed range but within headroom requirements and maximum power dissipation for current range Forced Voltage Linearity Error −2 +2 mV Forced Voltage Offset Error −50 +50 mV Uncalibrated, use c register to calibrate, measured at midscale μV/°C Standard deviation = 23 μV/°C mV Uncalibrated, use m register to calibrate ppm/°C Standard deviation = 3 ppm/°C FORCE VOLTAGE Force Output Voltage1 EXTFORCE1 EXTFORCE2 FORCE Forced Voltage Offset Error Tempco1 Forced Voltage Gain Error 27 −25 Forced Voltage Gain Error Tempco1 +25 4 Short-Circuit Current Limit3 Clamps off EXTFORCE1 −3.5 ±2.7 +3.5 A Positive and negative dc short-circuit current EXTFORCE2 −1.25 ±0.9 +1.25 A Positive and negative dc short-circuit current FORCE −75 ±50 +75 mA ±25 mA range, positive and negative dc short- circuit current −20 ±10 +20 mA All other ranges, positive and negative dc short-circuit current Active CFx Buffer −64 +64 mA DC Load Regulation1 −1 +1 mV EXTFORCE1 range, ±1 A load current change +0.4 −0.4 Load Transient Response1 NSD1 mV EXTFORCE2 range, ±0.5 A load current change 70 mV 1.2 A load step into 100 μF DUT capacitance (10 mΩ ESR), autocompensation mode 140 mV 1.2 A load step into 30 µF DUT capacitance (10 mΩ ESR), autocompensation mode 350 nV/√Hz Measured at 1 kHz, at output of FORCE MEASURE CURRENT RANGES Internal Sense Resistors1 analog.com Sense resistors are trimmed to within 1%, nominal ±500 mV VRSENSE 100 kΩ ±5 µA current range Rev. F | 4 of 66 Data Sheet AD5560 SPECIFICATIONS Table 1. (Continued) Parameter Min Typ Max Unit Test Conditions/Comments 20 kΩ ±25 µA current range 2 kΩ ±250 µA current range 200 Ω ±2.5 mA current range 20 Ω ±25 mA current range Measure Current Ranges Specified current ranges with VREF = 5 V and MI gain = 20, or with VREF = 2.5 V and MI gain = 5 ±5 µA Set using internal sense resistor ±25 µA Set using internal sense resistor ±250 µA Set using internal sense resistor ±2.5 mA Set using internal sense resistor ±25 mA Set using internal sense resistor ±500 mA EXTFORCE2, set by user with external sense resistor, limited by headroom requirements and maximum power dissipation ±1200 mA EXTFORCE1, set by user with external sense resistor, limited by headroom requirements and maximum power dissipation MEASURE CURRENT Differential Input Voltage Range1 −0.64 +0.64 V All offset DAC/supply combinations settings, all gain settings are measure current = (IDUT × RSENSE × MI gain), unless otherwise noted Maximum voltage across RSENSE, MI gain = 20 −0.7 +0.7 V Maximum voltage across RSENSE, MI gain = 10 V Measure current block alone (internal node) % FSC At 0 A, MI gain = 20, MEASOUT gain = 1 ppm of FSC/°C Standard deviation = 13 ppm/°C % FSC At 0 A, MI gain = 10, MEASOUT gain = 1 ppm of FSC/°C Standard deviation = 13 ppm/°C % FSC At 0 A, MI gain = 20, MEASOUT gain = 0.2 ppm of FSC/°C Standard deviation = 13 ppm/°C % FSC At 0 A, MI gain = 10, MEASOUT gain = 0.2 ppm of FSC/°C Standard deviation = 15 ppm/°C % FSC Internal current ranges, all gain settings Output Voltage Span1 Offset Error 25 −1 Offset Error Tempco1 Offset Error −1 −1.5 Offset Error Tempco1 Offset Error +1.5 −1 −1.5 Offset Error Tempco1 Offset Error +1 +1.5 3 −3 Offset Error Tempco1 +3 8 Gain Error −2 Gain Error1 −1 Gain Error Tempco1 +2 +1 20 % FSC External current ranges, excluding RSENSE ppm/°C Standard deviation = 5 ppm/°C MEASOUT Gain = 1 Linearity Error All supply conditions −0.01 +0.01 % FSCR Linearity Error −0.06 +0.06 % FSCR MI gain = 20 Linearity Error −0.05 +0.05 % FSCR MI gain = 10 MEASOUT Gain = 0.2 MI gain = 20 and 10 Nominal supply (±16.5 V, 0x8000 offset DAC) MEASOUT Gain = 0.2 Low supply (−25 V/+8 V, 0xD4EB offset DAC) Linearity Error −0.125 +0.125 % FSCR MI gain = 20 Linearity Error −0.175 +0.175 % FSCR MI gain = 10 Linearity Error −0.0875 +0.0875 % FSCR MI gain = 20 Linearity Error −0.1 +0.1 % FSCR MI gain = 10 −0.005 +0.005 %FSVR/V % of FS change at measure output per volts change in DUT voltage MEASOUT Gain = 0.2 Common-Mode Error analog.com High supply (−5 V/+28 V, 0xD1D offset DAC) Rev. F | 5 of 66 Data Sheet AD5560 SPECIFICATIONS Table 1. (Continued) Parameter Min NSD1 Typ Max Unit Test Conditions/Comments 900 nV/√Hz MI gain = 20, MEASOUT gain = 1, measured at MEASOUT at 1 kHz, inputs grounded 550 nV/√Hz MI gain = 10, MEASOUT gain = 1, measured at MEASOUT at 1 kHz, inputs grounded 170 nV/√Hz MI gain = 20, MEASOUT gain = 0.2, measured at MEASOUT at 1 kHz, inputs grounded 110 nV/√Hz MI gain = 10, MEASOUT gain = 0.2, measured at MEASOUT at 1 kHz, inputs grounded MEASURE VOLTAGE MEASOUT Gain 1 and MEASOUT Gain 0.2 Measure Voltage Range1 AVSS + 2.75 AVDD − 2.75 V Gain Error −0.1 +0.1 % FS Gain Error Tempco1 3 ppm/°C All voltage ranges Standard deviation = 2 ppm/°C MEASOUT Gain = 1 Linearity Error −2 +2 mV Offset Error −12 +12 mV Offset Error Tempco1 2 µV/°C Standard deviation = 12 µV/°C NSD1 100 nV/√Hz At 1 kHz, at MEASOUT, inputs grounded MEASOUT Gain = 0.2 Linearity Error Offset Error −5.5 +5.5 mV Referred to MV input, nominal supply (±16.5 V, 0x8000 offset DAC) −9 +24 mV Referred to MV input, low supply (−25 V/+8 V, 0xD4EB offset DAC) −4 +13 mV Referred to MV input, high supply (−5 V/+28 V, 0xD1D offset DAC) mV Referred to MV output Offset Error Tempco1 −30 10 +20 µV/°C Standard deviation = 12 µV/°C, referred to MV output NSD1 50 nV/√Hz At 1 kHz, at MEASOUT, inputs grounded COMBINED LEAKAGE Leakage Current Includes SYS_SENSE, SYS_FORCE, EXTFORCE1, EXTFORCE2, EXTMEASIH1, EXTMEASIH2, EXTMEASIL, FORCE, and SENSE; measured with PD = 1, SW-INH = 0 (power up and tristate) −37.5 +37.5 nA −30 +30 nA ±0.4 nA/°C Leakage Current Tempco1 ±0.1 TJ = 25°C to 70°C SENSE INPUT Leakage Current −2.5 +2.5 nA Leakage Current Tempco1 ±0.01 nA/°C Pin Capacitance1 10 pF Measured with PD = 1, SW-INH = 0 (power-up and tristate) EXTMEASIH1, EXTMEASIH2, EXTMEASIL Leakage Current −2.5 +2.5 nA Leakage Current Tempco1 ±0.01 nA/°C Pin Capacitance1 5 pF Measured with PD = 1, SW-INH = 0 (power-up and tristate) FORCE OUTPUT, FORCE Maximum Current Drive1 −30 +30 mA Leakage Current −10 +10 nA analog.com Measured with PD = 1, SW-INH = 0 (power-up and tristate) Rev. F | 6 of 66 Data Sheet AD5560 SPECIFICATIONS Table 1. (Continued) Parameter Min Typ Max Unit Leakage Current Tempco1 ±0.03 nA/°C Pin Capacitance1 120 pF Test Conditions/Comments EXTFORCE1 OUTPUTS Maximum Current Drive1 −1200 +1200 mA Set with external sense resistor, limited by headroom and power dissipation Leakage Current −7.5 +7.5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) ±0.06 nA/°C Leakage Current Tempco1 ±0.03 Pin Capacitance1 275 pF EXTFORCE2 OUTPUTS Maximum Current Drive1 −500 Leakage Current −5 Leakage Current Tempco1 ±0.02 Pin Capacitance1 100 +500 mA Set with external sense resistor, limited by headroom and power dissipation +5 nA Measured with PD = 1, SW-INH = 0 (power-up and tristate) ±0.05 nA/°C pF SYS_SENSE Voltage Range AVSS AVDD V Leakage Current −2.5 +2.5 nA ±0.025 nA/°C 280 Ω Leakage Current Tempco1 ±0.005 Path On Resistance Pin Capacitance1 5 SYS_SENSE high-Z, force amplifier inhibited AVDD = 16.5 V, AVSS = −16.5 V pF SYS_FORCE Voltage Range AVSS AVDD V Current Carrying Capability1 −25 +25 mA Leakage Current −2.5 +2.5 nA ±0.025 nA/°C Leakage Current Tempco1 ±0.005 Path On Resistance 35 Pin Capacitance1 5 Ω SYS_FORCE high-Z, force amplifier inhibited AVDD = 16.5 V, AVSS = −16.5 V pF SYS_DUTGND Voltage Range AVSS Path On Resistance 300 AVDD V 400 Ω AVDD = 16.5 V, AVSS = −16.5 V CURRENT CLAMP Clamp Accuracy Programmed clamp value Programmed % of FS clamp value + 10 MI gain = 20, with clamp separation of 2 V, and 1 V separation from AGND/0 A Programmed clamp value Programmed % of FS clamp value + 20 MI gain = 10, with clamp separation of 2 V, and 1 V separation from AGND/0 A VCLL to VCLH1 2 V 10% of FSCR (MI gain = 20), 20% of FSCR (MI gain = 10), restriction to prevent both clamps activating together VCLL to 0 A1 1 V 5% of FSCR (MI gain = 20), 10% of FSCR (MI gain = 10), restriction to avoid impinging on FV before programmed level VCLH to 0 A1 1 V 5% of FSCR (MI gain 20), 10% of FSCR (MI gain = 10), restriction to avoid impinging on FV before programmed level Clamp Activation Response Time1 20 100 μs Measured from BUSY going low to visible clamping Clamp Recovery1 2 5 μs Measured from BUSY going low to visible recovery Alarm Delay1 50 μs Time for CLALM to flag FORCE AMPLIFIER analog.com Rev. F | 7 of 66 Data Sheet AD5560 SPECIFICATIONS Table 1. (Continued) Parameter Slew Rate1 Min Typ Max Unit Test Conditions/Comments 1 V/µs Fastest slew rate, controlled via serial interface 0.312 V/µs Slowest slew rate, controlled via serial interface Maximum Stable Load Capacitance1 160 µF Voltage Overshoot/Undershoot1 5 % SETTLING TIME (FORCE AMPLIFIER) Compensation Register 1 = 0x4880 (229 nF to 380 nF, ESR 74 to 140 mΩ) Of programmed value (≥1 V) To within 10 mV of programmed value FV (1200 mA EXTFORCE1 Range)1 16 25 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load FV (900 mA EXTFORCE1 Range)1 18 30 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load FV (500 mA EXTFORCE2 Range)1 34 53 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load FV (300 mA EXTFORCE2 Range)1 25 50 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load FV (25 mA Range)1, 3 125 180 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load FV (2.5 mA Range)1, 3 300 500 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load FV (250 µA Range)1, 3 300 500 µs 10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load FV (25 µA Range)1, 3 400 600 µs 10 V step, RDUT = 400 kΩ, CDUT = 0.22 µF, full dc load 20 40 µs 1 V step, RDUT = 200 kΩ, CDUT = 0.22 µF, full dc load FV (5 µA Range)1, 3 Compensation Register 1 = 0x8880 (1.7 μF to 2.9 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 16 25 µs 3 V step, CDUT = 2.2 µF, full dc load FV (100 mA EXTFORCE2 Range)1 60 80 µs 8 V step, CDUT = 2.2 µF, full dc load Compensation Register 1 = 0xB880 (7.9 μF to 13 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 FV (100 mA EXTFORCE2 Range)1 55 70 µs 3 V step, CDUT = 10 µF, full dc load 210 260 µs 8 V step, CDUT = 10 µF, full dc load Compensation Register 1 = 0xC880 (13 μF to 22 μF, ESR 74 to 140 mΩ) FV (180 mA EXTFORCE1 Range)1 65 80 µs 3 V step, CDUT = 20 µF, full dc load FV (100 mA EXTFORCE2 Range)1 310 370 µs 8 V step, CDUT = 20 µF, full dc load SETTLING TIME (FV, MEASURE CURRENT) Compensation Register 1 = 0x4880 (229 nF to 380 nF, ESR 74 to 140 mΩ) To within 10 mV of programmed value MI (1200 mA EXTFORCE1 Range)1 30 40 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load MI (900 mA EXTFORCE1 Range)1 32 42 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load MI (500 mA EXTFORCE2 Range)1 69 95 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load MI (300 mA EXTFORCE2 Range)1 70 100 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load MI (25 mA Range)1, 3 650 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load MI (2.5 mA Range)1, 3 6400 MI Buffer Alone1 10 15 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load µs 0.5 V step using MEASOUT high-Z to within 10 mV of final value SETTLING TIME (FV, MEASURE VOLT- Compensation Register 1 = 0x4880 (229 nF to AGE) 380 nF, ESR 74 to 140 mΩ) To within 10 mV of programmed value MV (1200 mA Range)1 16 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load MV (900 mA Range)1 20 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load MV (500 mA Range)1 34 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load MV (300 mA Range)1 25 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load MV (25 mA Range)1, 3 125 180 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load MV (2.5 mA Range)1, 3 300 500 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load analog.com Rev. F | 8 of 66 Data Sheet AD5560 SPECIFICATIONS Table 1. (Continued) Parameter Typ Max Unit Test Conditions/Comments MV (250 µA Range)1, 3 Min 300 500 µs 10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load MV Buffer Alone1 2 5 µs 10 V step using MEASOUT high-Z to within 10 mV of final value SETTLING TIME (FV) SAFE MODE To within 100 mV of programmed value FV (1200 mA EXTFORCE1 Range1 25 µs 3.7 V step, RDUT = 3.1 Ω, CDUT = 0.22 µF, full dc load FV (180 mA EXTFORCE1 Range)1 303 µs 3 V step, RDUT = 16 Ω, CDUT = 0. 22 µF to 20 μF, full dc load FV (100 mA EXTFORCE2 Range)1 660 FV (25 mA Range)1, 3 760 µs 8 V step, RDUT = 33.3 Ω, CDUT = 0. 22 µF to 20 μF, full dc load 1000 µs 20 V step, RDUT = 400 Ω, CDUT = 0.22 µF, full dc load 0.5 % of FV CDUT = 10 μF, changing from higher to adjacent lower ranges (except EXTFORCE1 to EXTFORCE2) mV CDUT = 10 μF, changing from lower (5 µA) to higher range (EXTFORCE1) % of FV CDUT = 100 μF, changing between all ranges SWITCHING TRANSIENTS Range Change Transient1 20 0.5 DAC SPECIFICATIONS Force/Comparator/Offset DACs Resolution 16 Bits Voltage Output Span −22 +25 V VREF = 5 V, minimum and maximum values set by offset DAC Differential Nonlinearity1 −1 +1 LSB Guaranteed monotonic −20 +20 mV Offset DAC Gain Error Clamp DAC CLL < CLH Resolution 16 Bits Voltage Output Span −22 +25 V VREF = 5 V, minimum and maximum values set by offset DAC Differential Nonlinearity1 −1 +1 LSB Guaranteed monotonic OSD DAC Resolution 16 Bits Voltage Output Span 0.62 5 V Differential Nonlinearity1 −2 +2 LSB VREF = 5 V DGS DAC Resolution 16 Bits Voltage Output Span 0 5 V Differential Nonlinearity1 −2 +2 LSB 6 µs VREF = 5 V Comparator DAC Dynamic Output Voltage Settling Time1 3.5 Slew Rate1 1 1 V change to 1 LSB V/µs Digital-to-Analog Glitch Energy1 10 nV-s Glitch Impulse Peak Amplitude1 40 mV REFERENCE INPUT VREF DC Input Impedance 1 VREF Input Current −10 VREF Range1 2 MΩ Typically 100 MΩ +10 µA Per input; typically ±30 nA 5 V COMPARATOR Error analog.com Measured directly at comparator; does not include measure block errors −7 +7 mV Uncalibrated Rev. F | 9 of 66 Data Sheet AD5560 SPECIFICATIONS Table 1. (Continued) Parameter Min Typ Max Unit VOLTAGE COMPARATOR With respect to the measured voltage Propagation Delay1 Error1 Test Conditions/Comments 0.25 −12 µs +12 mV 1 µs +1.5 % Uncalibrated CURRENT COMPARATOR Propagation Delay1 Error1 0.25 −1.5 Of programmed current range, uncalibrated MEASURE OUTPUT, MEASOUT Measure Output Voltage Span1 −12.81 +12.81 V MEASOUT gain = 1, VREF = 5 V, offset DAC = 0x8000 Measure Output Voltage Span1 −6.405 +6.405 V MEASOUT gain = 1, VREF = 2.5 V Measure Output Voltage Span1 0 5.125 V MEASOUT gain = 0.2, VREF = 5 V, offset DAC = 0x8000 Measure Output Voltage Span1 0 2.56 V MEASOUT gain = 0.2, VREF = 2.5 V 115 Ω +100 nA Measure Pin Output Impedance Output Leakage Current −100 Output Capacitance1 Short-Circuit Current1 5 When HW_INH is low pF −10 +10 mA −200 +200 mV 900 mV OPEN-SENSE DETECT/CLAMP/ ALARM Measurement Accuracy Clamp Accuracy 600 Alarm Delay1 50 μs DUTGND Voltage Range1 −1 Pull-Up Current +50 Leakage Current −1 Trip Point Accuracy −30 Alarm Delay1 +1 V +70 μA Pull-up for purpose of detecting open circuit on DUTGND, can be disabled +1 μA When pull-up disabled, DGS DAC = 0x3333 (1 V with VREF = 5 V); if DUTGND voltage is far away from one of comparator thresholds, more leakage may be present +10 mV 50 μs GUARD AMPLIFIER Voltage Range1 AVSS + 2.25 Voltage Span1 AVDD − 2.25 V 25 V Output Offset −10 +10 mV Short-Circuit Current1 −20 +20 mA 100 nF Load Capacitance1 Output Impedance 100 Ω Alarm Delay1 200 μs If it moves 100 mV away from input level % Relative to a temperature change DIE TEMPERATURE SENSOR Accuracy1 −10 Output Voltage at 25°C Output Scale Factor1 Output Voltage Range1 +10 1.54 V 4.7 1 mV/°C 2 V SPI INTERFACE LOGIC Logic Inputs Input High Voltage, VIH analog.com 1.7/2.0 V (2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant input levels Rev. F | 10 of 66 Data Sheet AD5560 SPECIFICATIONS Table 1. (Continued) Parameter Min Typ Input Low Voltage, VIL Input Current, IINH, IINL −1 Input Capacitance, CIN1 Max Unit Test Conditions/Comments 0.7/0.8 V (2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant input levels +1 µA 10 pF CMOS Logic Outputs Output High Voltage, VOH SDO, CPOL, CPOH, GPO, CPO DVCC − 0.4 V Output Low Voltage, VOL 0.4 V IOL = 500 µA +1 μA SDO, CPOL, CPOH, CPO 10 pF SDO, CPOL, CPOH, CPO Output Low Voltage, VOL 0.4 V IOL = 500 µA, CL = 50 pF, RPULLUP = 1 kΩ Output Capacitance1 10 pF Tristate Leakage Current −1 Output Capacitance1 10 10 Open-Drain Logic Outputs BUSY, TMPALM, CLALM, KELALM POWER SUPPLIES HCAVDD1x 4 28 V |HCAVDDx – HCAVSSx| < 33 V, HCAVSSx ≥ AVSS, HCAVDDx ≤ AVDD HCAVSS1x −25 −5 V HCAVDD2x 4 28 V HCAVSS2x −25 −5 V AVDD 8 28 V AVSS −25 −5 V DVCC 2.3 5.5 V 30 mA All ranges mA All ranges AIDD 4 AISS4 −30 |HCAVDDx – HCAVSSx| < 33 V, HCAVSSx ≥ AVSS, HCAVDDx ≤ AVDD |AVDD – AVSS| < 33 V DICC 3 mA AIDD4 27 mA Channel inhibited/tristate, HW_INH or SW-INH low mA Channel inhibited/tristate, HW_INH or SW-INH low AISS4 −27 HCAVDDx and HCAVSSx supply currents shown are excluding load currents; however, for power budget calculations, the supply currents here are consumed by the load HCAIDD1 20 mA When enabled, excluding load conditions HCAIDD1 0.5 mA When disabled HCAISS1 −20 mA When enabled, excluding load condition HCAISS1 −0.5 mA When disabled HCAIDD2 15 mA When enabled, excluding load conditions HCAIDD2 0.25 mA When disabled HCAISS2 −15 mA When enabled, excluding load conditions HCAISS2 −0.25 mA When disabled POWER-DOWN CURRENTS Supply currents on power-up or during a power-down condition HCAIDD HCAISS 250 −250 HCAIDD HCAISS AISS DICC analog.com μA 250 −250 AIDD μA μA μA 5 −5 mA mA 3 mA Rev. F | 11 of 66 Data Sheet AD5560 SPECIFICATIONS Table 1. (Continued) Parameter Min Typ Max Unit EXTFORCE1 10 W EXTFORCE2 5 W 5 % Test Conditions/Comments Maximum Power Dissipation Power-Up Overshoot1 Power Supply Sensitivity1 Of programmed value DC to 1 kHz ΔForced Voltage/ΔAVDD −65 dB −30 dB at 100 kHz ΔForced Voltage/ΔAVSS −65 dB −25 dB at 100 kHz ΔForced Voltage/ΔHCAVDDx −90 dB −60 dB at 100 kHz ΔForced Voltage/ΔHCAVSSx −90 dB −62 dB at 100 kHz ΔMeasured Current/ΔAVDD −50 dB −25 dB at 100 kHz ΔMeasured Current/ΔAVSS −43 dB −20 dB at 100 kHz ΔMeasured Current/ΔHCAVDDx −90 dB −60 dB at 100 kHz ΔMeasured Current/ΔHCAVSSx −90 dB −60 dB at 100 kHz ΔMeasured Voltage/ΔAVDD −65 dB −30 dB at 100 kHz ΔMeasured Voltage/ΔAVSS −65 dB −25 dB at 100 kHz ΔMeasured Voltage/ΔHCAVDDx −90 dB −60 dB at 100 kHz ΔMeasured Voltage/ΔHCAVSSx −90 dB −65 dB at 100 kHz ΔForced Voltage/ΔDVCC −80 dB −46 dB at 100 kHz ΔMeasured Current/ΔDVCC −80 dB −36 dB at 100 kHz ΔMeasured Voltage/ΔDVCC −80 dB −46 dB at 100 kHz 1 Guaranteed by design and characterization, not subject to production test. 2 Programmable clamps must be enabled if taking advantage of reduced headroom/footroom. 3 Clamps disabled. 4 Not including internal pull-up current between AVDD/AVSS and HCAVDDx/HCAVSSx pins. TIMING CHARACTERISTICS HCAVDDx ≤ AVSS + 33 V, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, VREF = 5 V (TJ = 25°C to 90°C, maximum specifications, unless otherwise noted). Table 2. SPI Interface Parameter1, 2, 3 DVCC = 2.3 V to 2.7 V DVCC = 2.7 V to 3.3 V DVCC = 4.5 V to 5.5 V Unit Description tUPDATE 600 600 600 ns max Channel update cycle time t1 25 20 20 ns min SCLK cycle time; 60/40 duty cycle t2 10 8 8 ns min SCLK high time t3 10 8 8 ns min SCLK low time t4 10 10 10 ns min SYNC falling edge to SCLK falling edge setup time t5 15 15 15 ns min Minimum SYNC high time t6 5 5 5 ns min 24th SCLK falling edge to SYNC rising edge t7 5 5 5 ns min Data setup time t8 4.5 4.5 4.5 ns min Data hold time t 94 40 35 30 ns max SYNC rising edge to BUSY falling edge t10 1.5 1.5 1.5 μs max BUSY pulse width low for DAC x1 write 280 280 280 ns max BUSY pulse width low for other register write analog.com Rev. F | 12 of 66 Data Sheet AD5560 SPECIFICATIONS Table 2. SPI Interface (Continued) Parameter1, 2, 3 DVCC = 2.3 V to 2.7 V DVCC = 2.7 V to 3.3 V DVCC = 4.5 V to 5.5 V Unit Description t11 25 20 10 ns min RESET pulse width low t12 400 400 400 µs max RESET time indicated by BUSY low t13 250 250 250 ns min Minimum SYNC high time in readback mode t14 5, 6 t15 45 35 25 ns max SCLK rising edge to SDO valid 30 30 30 ns max SYNC rising edge to SDO high-Z 20 20 20 ns min LOAD pulse width low LOAD TIMING t16 t17 150 150 150 ns min BUSY rising edge to force output response time t18 0 0 0 ns min BUSY rising edge to LOAD falling edge t19 150 150 150 ns min LOAD rising edge to FORCE output response time 150 150 150 ns min LOAD rising edge to current range response 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 4 and Figure 5. 4 This is measured with the load circuit shown in Figure 2. 5 This is measured with the load circuit shown in Figure 3. 6 Longer SCLK cycle time is required for correct operation of readback mode; consult timing diagrams and timing specifications. TIMING DIAGRAMS Figure 2. Load Circuit for Open Drain Figure 3. Load Circuit for CMOS analog.com Rev. F | 13 of 66 Data Sheet AD5560 SPECIFICATIONS Figure 4. SPI Write Timing Figure 5. SPI Read Timing analog.com Rev. F | 14 of 66 Data Sheet AD5560 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating AVDD to AVSS 34 V AVDD to AGND −0.3 V to +34 V AVSS to AGND −34 V to +0.3 V HCAVDDx to HCAVSSx 34 V HCAVDDx to AGND −0.3 V to +34 V HCAVSSx to AGND −34 V to +0.3 V HCAVDDx to AVSS −0.3 V to AVSS + 34 V HCAVDDx to AVDD −0.3 V to AVDD + 0.3 V HCAVSSx to AVSS +0.3 V to AVSS − 0.3 V DVCC to DGND −0.3 V to +7 V AGND to DGND −0.3 V to +0.3 V REFGND to AGND −0.3 V to +0.3 V Digital Inputs to DGND −0.3 V to DVCC + 0.3 V Analog Inputs to AGND AVSS − 0.3 V to AVDD + 0.3 V EXTFORCE1 and EXTFORCE2 to AGND1 AVDD − 28 V Storage Temperature −65°C to +125°C Operating Junction Temperature 25°C to 90°C Reflow Profile J-STD 20 (JEDEC) Junction Temperature 150°C max Power Dissipation 10 W max (EXTFORCE1 stage) 5 W max (EXTFORCE2 stage) ESD 1 HBM 1500 V FICDM 500 V When an EXTFORCE1 or EXTFORCE2 stage is enabled and the supply differential |AVDD − AVSS| > 28 V, take care to ensure that these pins are not directly shorted to AVSS voltage at any time because this can cause damage to the device. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. analog.com Rev. F | 15 of 66 Data Sheet AD5560 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. TQFP_EP Pin Configuration Table 4. TQFP_EP Pin Function Descriptions Pin No. Mnemonic Description 1 CLALM Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. 2 KELALM Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either latched or unlatched. 3 TMPALM Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. 4 CPOH/CPO Comparator High Output (CPOH) or Window Comparator Output (CPO). 5 CPOL Comparator Low Output. 6 BUSY Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels. 7 SDO Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic purposes. 8 DVCC Digital Supply Voltage. 9 DGND Digital Ground Reference Point. 10 SCLK Clock Input, Active Falling Edge. 11 SDI Serial Data Input. 12 SYNC Frame Sync, Active Low. 13 RCLK Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied to this input to drive the ramp circuitry. Tie RCLK low if it is unused. 14 RESET Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value. 15 CLEN/LOAD Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as LOAD input (see the system control register, Address 0x1). 16 HW_INH/LOAD Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system control register, Address 0x1). 17 REFGND Accurate Ground Reference for Applied Voltage Reference. 18 VREF Reference Input for DAC Channels, Input Range 2 V to 5 V. 19, 44 AGND 20, 30, 45 AVSS Analog Ground. Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as measure blocks. 22 MEASOUT Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND. analog.com Rev. F | 16 of 66 Data Sheet AD5560 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 4. TQFP_EP Pin Function Descriptions (Continued) Pin No. Mnemonic Description 23 CC3 Compensation Capacitor Input 3. 24 CC0 Compensation Capacitor Input 0. 25 CC1 Compensation Capacitor Input 1. 26 CC2 Compensation Capacitor Input 2. 27 SLAVE_IN Slave Input When Ganging Multiple DPS Devices. 28 MASTER_OUT Master Output When Ganging Multiple DPS Devices. 29 SYS_SENSE External Sense Signal Output. 31 SYS_FORCE External Force Signal Input. 32 FORCE Output Force Pin for Internal Current Ranges. 34 NC No Connect. 35 CF4 Feedforward Capacitor 4. 36 CF3 Feedforward Capacitor 3. 37 CF2 Feedforward Capacitor 2. 38 CF1 Feedforward Capacitor 1. 39 CF0 Feedforward Capacitor 0. 40 DUTGND Device Under Test Ground. 41 SENSE Input Sense Line. 42 EXTMEASIL Low Side Measure Current Line for External High Current Ranges. 43 GUARD/SYS_DUTGND Guard Amplifier Output Pin or System Device Under Test Ground Pin. See DPS Register 2 in Table 19 for addressing details. 47 EXTMEASIH1 Input High Measure Line for External High Current Range 1. 48 EXTMEASIH2 HCAVDD1A, HCAVDD1B, HCAVDD1C EXTFORCE1A, EXTFORCE1B, EXTFORCE1C HCAVSS1A, HCAVSS1B, HCAVSS1C HCAVSS2A, HCAVSS2B Input High Measure Line for External High Current Range 2. Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA. 54, 60 EXTFORCE2A, EXTFORCE2B HCAVDD2A, HCAVDD2B High Current Positive Analog Supply Voltage, for EXTFORCE2 Range. 64 GPO Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT. 65 EP The exposed pad is internally connected to AVSS. 49, 55, 61 50, 56, 62 51, 57, 63 52, 58 53, 59 analog.com High Current Positive Analog Supply Voltage, for EXTFORCE1 Range. Output Force. This pin is used for high Current Range 1, up to a maximum of ±1.2 A. High Current Negative Analog Supply Voltage, for EXTFORCE1 Range. High Current Negative Analog Supply Voltage, for EXTFORCE2 Range. Rev. F | 17 of 66 Data Sheet AD5560 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 7. Flip-Chip BGA Pin Configuration, Bottom Side (BGA Balls Are Visible) Table 5. Flip-Chip BGA Pin Function Descriptions Pin No. Mnemonic Description A1 GPO Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT. A2, A3 EXTFORCE1C Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A. A4 EXTFORCE2B Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA. A5, A6 EXTFORCE1B Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A. A7 EXTFORCE2A Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA. A8, A9 EXTFORCE1A Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A. B1 CLALM Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. B2, C2 HCAVSS1C High Current Negative Analog Supply Voltage for EXTFORCE1 Range. B3, C3 HCAVDD1C High Current Positive Analog Supply Voltage for EXTFORCE1 Range. B4 HCAVDD2B High Current Positive Analog Supply Voltage for EXTFORCE2 Range. B5, C5 HCAVSS1B High Current Negative Analog Supply Voltage for EXTFORCE1 Range. B6, C6 HCAVDD1B High Current Positive Analog Supply Voltage for EXTFORCE1 Range. B7 HCAVDD2A High Current Positive Analog Supply Voltage for EXTFORCE2 Range. B8, C8 HCAVSS1A High Current Negative Analog Supply Voltage for EXTFORCE1 Range. B9, C9 HCAVDD1A High Current Positive Analog Supply Voltage for EXTFORCE1 Range. C1 KELALM Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either latched or unlatched. C4 HCAVSS2B High Current Negative Analog Supply Voltage for EXTFORCE2 Range. C7 HCAVSS2A High Current Negative Analog Supply Voltage for EXTFORCE2 Range. D1 TMPALM Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched or unlatched. D2 CPOH/CPO Comparator High Output (CPOH) or Window Comparator Output (CPO). analog.com Rev. F | 18 of 66 Data Sheet AD5560 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 5. Flip-Chip BGA Pin Function Descriptions (Continued) Pin No. Mnemonic Description D3 CPOL Comparator Low Output. D7 EXTMEASIH2 Input High Measure Line for External High Current Range 2. D8 EXTMEASIH1 D9, H3, J8 AVDD Input High Measure Line for External High Current Range 1. Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as measure blocks. E1 BUSY Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels. E2 SDO Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic purposes. E3 DVCC Digital Supply Voltage. E7 GUARD/SYS_DUTGND Guard Amplifier Output Pin or System Device Under Test Ground Pin. See DPS Register 2 in Table 19 for addressing details. E8 AGND E9, G4, J4 AVSS Analog Ground. Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as measure blocks. F1 DGND Digital Ground Reference Point. F2 SCLK Clock Input, Active Falling Edge. F3 SDI Serial Data Input. F7 SENSE Input Sense Line. F8 EXTMEASIL Low Side Measure Current Line for External High Current Ranges. F9 DUTGND Device Under Test Ground. G1 SYNC Frame Sync, Active Low. G2 RCLK Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied to this input to drive the ramp circuitry. Tie RCLK low if it is unused. G3 RESET Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value. G5 CC0 Compensation Capacitor Input 0. G6 SYS_SENSE External Sense Signal Output. G7 SYS_FORCE External Force Signal Input. G8 CF2 Feedforward Capacitor 2. G9 CF0 Feedforward Capacitor 0. H1 CLEN/LOAD Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as LOAD input (see the system control register, Address 0x1). H2 VREF Reference Input for DAC Channels, Input Range is 2 V to 5 V. H4 MEASOUT Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND. H5 CC1 Compensation Capacitor Input 1. H6 MASTER_OUT Master Output When Ganging Multiple DPS Devices. H7 SLAVE_IN Slave Input When Ganging Multiple DPS Devices. H8 CF3 Feedforward Capacitor 3. H9 CF1 Feedforward Capacitor 1. J1 HW_INH/LOAD Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system control register, Address 0x1). J2 REFGND Accurate Ground Reference for Applied Voltage Reference. J3 AGND Analog Ground. J5 CC3 Compensation Capacitor Input 3. J6 CC2 Compensation Capacitor Input 2. J7 FORCE Output Force Pin for Internal Current Ranges. J9 CF4 Feedforward Capacitor 4. analog.com Rev. F | 19 of 66 Data Sheet AD5560 TYPICAL PERFORMANCE CHARACTERISTICS Figure 8. Force Voltage Linearity vs. Code, VREF = 5 V, No Load Figure 9. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1, MEASOUT Gain = 0.2, Nominal Supplies) Figure 10. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1, MEASOUT Gain = 0.2, Positive Skew Supply) analog.com Figure 11. Measure Voltage Linearity vs. Code (MEASOUT Gain 1, MEASOUT Gain = 0.2, Negative Skew Supply) Figure 12. Measure Current Linearity vs. Code (MEASOUT Gain = 1, MI Gain = 20), TJ = 25°C Figure 13. Measure Current Linearity vs. Code (MEASOUT Gain = 1, MI Gain = 10) Rev. F | 20 of 66 Data Sheet AD5560 TYPICAL PERFORMANCE CHARACTERISTICS Figure 14. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2, MI Gain = 20) Figure 15. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2, MI Gain = 10) Figure 16. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 1, MI Gain = 20) analog.com Figure 17. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 0.2, MI Gain = 20) Figure 18. Leakage Current vs. Stress Voltage (Force and Combined Leakage) Figure 19. Leakage Current vs. Temperature (Force and Combined Leakage), VSTRESS = 9 V Rev. F | 21 of 66 Data Sheet AD5560 TYPICAL PERFORMANCE CHARACTERISTICS Figure 20. Leakage Current vs. Stress Voltage Figure 23. MI Positive Gain Error vs. Temperature, MI Gain = 20, MEASOUT Gain = 1 Figure 21. Leakage Current vs. Temperature, VSTRESS = 9 V Figure 24. FV Gain Error vs. Temperature Figure 22. MI Offset Error vs. Temperature, MI Gain = 20, MEASOUT Gain = 1 and 0.2 Figure 25. FV Offset Error vs. Temperature analog.com Rev. F | 22 of 66 Data Sheet AD5560 TYPICAL PERFORMANCE CHARACTERISTICS Figure 26. MV Gain Error vs. Temperature, MEASOUT Gain = 1 Figure 29. MV Offset Error vs. Temperature, MEASOUT Gain = 0.2 Figure 27. MV Offset Error vs. Temperature, MEASOUT Gain = 1 Figure 30. Range Change 2.5 mA to 25 mA, Safe Mode, 2.5 mA ILOAD, 10 μF Load Figure 28. MV Gain Error vs. Temperature, MEASOUT Gain = 0.2 Figure 31. Range Change 25 mA to 2.5 mA, Safe Mode, 2.5 mA ILOAD, 10 μF Load analog.com Rev. F | 23 of 66 Data Sheet AD5560 TYPICAL PERFORMANCE CHARACTERISTICS Figure 32. Range Change 25 mA to EXTFORCE2, Safe Mode, 25 mA ILOAD, 10 μF Load Figure 35. Autocompensation Mode 90% to 10% ILOAD Change, EXTFORCE2 Range, 10 µF Load Figure 33. Range Change EXTFORCE2 to 25 mA, Safe Mode, 25 mA ILOAD, 10 µF Load Figure 36. Autocompensation Mode 10% to 90% ILOAD Change, EXTFORCE2 Range, 10 µF Load Figure 34. Kick/Droop Response vs. IRANGE, Compensation, and CLOAD,, 10% to 90% to 10% ILOAD Change Figure 37. Safe Mode 80% to 10%, EXTFORCE2 Range, 10 µF Load analog.com Rev. F | 24 of 66 Data Sheet AD5560 TYPICAL PERFORMANCE CHARACTERISTICS Figure 38. Safe Mode 10% to 90%, EXTFORCE2 Range, 10 µF Load Figure 41. Transient Response FVMI Mode, 25 mA Range, Autocompensation Mode Figure 39. MEASOUT TSENSE Temperature Sensor vs. Temperature (Multiple Devices) Figure 42. Transient Response FVMI Mode, 25mA Range, Safe Mode Figure 40. Transient Response FVMI Mode, ±250 µA Range, Autocompensation Mode Figure 43. Transient Response FVMI Mode, EXTFORCE1 Range, Autocompensation Mode analog.com Rev. F | 25 of 66 Data Sheet AD5560 TYPICAL PERFORMANCE CHARACTERISTICS Figure 44. Transient Response FVMI Mode, EXTFORCE1 Range, Safe Mode Figure 47. NSD vs. Amplifier Stage and Gain Setting at 1 kHz Figure 45. Transient Response FVMI Mode, EXTFORCE2 Range, Autocompensation Mode Figure 48. ACPSRR of AVDD vs. Frequency Figure 46. Transient Response FVMI Mode, EXTFORCE2 Range, Safe Mode analog.com Figure 49. ACPSRR of AVSS vs. Frequency Rev. F | 26 of 66 Data Sheet AD5560 TYPICAL PERFORMANCE CHARACTERISTICS Figure 50. ACPSRR of DVCC vs. Frequency Figure 52. ACPSRR of HCAVSSx vs. Frequency Figure 51. ACPSRR of HCAVDDx vs. Frequency Figure 53. ICLAMP Value vs. RLOAD – Cal at 1Ohm analog.com Rev. F | 27 of 66 Data Sheet AD5560 TERMINOLOGY Offset Error Slew Rate Offset error is a measure of the difference between the actual voltage and the ideal voltage at midscale or at zero current expressed in millivolts (mV) or percentage of full-scale range (%FSR). The slew rate is the rate of change of the output voltage expressed in volts per microsecond (V/μs). Gain Error Differential Nonlinearity DNL Gain error is the difference between full-scale error and zero-scale error. It is expressed in percentage of full-scale range (%FSR). DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonicity. Gain Error = Full-Scale Error − Zero-Scale Error Output Voltage Settling Time where: Full-Scale Error is the difference between the actual voltage and the ideal voltage at full scale. Zero-Scale Error is the difference between the actual voltage and the ideal voltage at zero scale. Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a full-scale input change. Linearity Error Digital-to-Analog Glitch Energy Linearity error, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the full-scale range. It is measured after adjusting for offset error and gain error and is expressed in millivolts (mV). Digital-to-analog glitch energy is the amount of energy that is injected into the analog output at the major code transition. It is specified as the area of the glitch in nanovolts per second (nV-sec). It is measured by toggling the DAC register data between 0x7FFF and 0x8000. Common-Mode (CM) Error CM error is the error at the output of the amplifier due to the common-mode input voltage. It is expressed in percentage of full-scale voltage range per volt (%FSVR/V). AC Power Supply Rejection Ratio (ACPSRR) Clamp limit is a measure of where the clamps begin to function fully and limit the clamped voltage or current. ACPSRR is a measure of the part’s ability to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.2 V p-p. The ratio of the amplitude of the signal on the output to the amplitude of the modulation is the ACPSRR. It is expressed in decibels (dB). Leakage Current VSTRESS Leakage current is the current measured at an output pin when the circuit connected to that pin is in high impedance state. VSTRESS is the stress voltage applied to each pin during leakage testing. Clamp Limit analog.com Rev. F | 28 of 66 Data Sheet AD5560 THEORY OF OPERATION The AD5560 is a single-channel, device power supply for use in semiconductor automatic test equipment. All the DAC levels required to operate the device are available on chip. This device contains programmable modes to force a pin voltage and measure the corresponding current (FVMI) covering a wide current measure range of up to ±1.2 A. A voltage sense amplifier allows measurement of the DUT voltage. Measured current or voltage is available on the MEASOUT pin. FORCE AMPLIFIER The force amplifier is a unity gain amplifier forcing voltage directly to the device under test (DUT). This high bandwidth amplifier allows suppression of load transient induced glitching on the amplifier output. Headroom and footroom requirements for the amplifier are 2.25 V and an additional ±500 mV dropped across the selected sense resistor with full-scale current flowing. The amplifier is designed to drive high currents up to ±1.2 A with the capability of ganging together outputs of multiple AD5560 devices for currents in excess of ±1.2 A. The force amplifier can be compensated to ensure stability when driving DUT capacitances of up to 160 μF. The device is capable of supplying transient currents in excess of ±1.2 A when powering a DUT with a large decoupling capacitor. A clamp enable pin (CLEN) allows disabling of the clamp circuitry to allow the amplifier to quickly charge this large capacitance. An extra control bit (GPO) is available to switch out DUT decoupling when making low current measurements. HW_INH Function A hardware inhibit pin (HW_INH/LOAD) allows disabling of the force amplifier, making the output high impedance. This function is also available through the serial interface (see the SW-INH bit in the DPS Register 1, Address 0x2). This pin can also be configured as a LOAD function to allow multiple devices to be synchronized. Note that either CLEN or HW_INH can be chosen as a LOAD function. DAC REFERENCE VOLTAGE (VREF) One analog reference input, VREF, supplies all DAC levels with the necessary reference voltage to generate the required dc levels. It clamps the sense line to within a programmable threshold level (plus a VBE) of the force line, where the programmable threshold is set by the OSD DAC voltage level. This limits the maximum or minimum voltage that can appear on the FORCE pin; it can be driven no higher than [V(FIN DAC) + threshold + VBE] and no lower than [V(FIN DAC) − threshold − VBE]. ► It triggers an alarm on KELALM if the force line goes more than the threshold voltage away (OSD DAC level) from the sense line. ► It translates the V(force − sense) voltage to a level relative to AGND so that it can be measured through the MEASOUT pin. ► The open-sense detect level is programmable over the range 0.62 V to 5 V (16-bit OSD DAC plus one diode drop). The 5 V OSD DAC can be accessed through the serial interface (see the DAC register addressing portion of Table 24). There is a 10 kΩ resistor that can be connected between the FORCE and SENSE pins by use of SW11. This 10 kΩ resistor is intended to maintain a force/sense connection when a DUT is not in place. It is not intended to be connected when measurements are being made because this defeats the purpose of the OSD circuit in identifying an open circuit between FORCE and SENSE. In addition, the sense path has a 2.5 kΩ resistor in series; there-fore, if the 10 kΩ switch is closed, errors may become apparent when in high current ranges. DEVICE UNDER TEST GROUND (DUTGND) DUTGND is the ground level of the DUT. DUTGND Kelvin Sense KELALM flags when the voltage at the DUTGND pin moves too far away from the AGND line (>1 V default setting of the DGS DAC). This alarm trigger is programmable via the serial interface. The threshold for the alarm function is programmable using the DUTGND SENSE DAC (DGS DAC) (see Table 24). The DUTGND pin has a 50 μA pull-up resistor that allows the alarm function to detect whether DUTGND is open. Setting the disable DUTALM bit high (Register 0x6, Bit 10) disables the 50 μA pull-up resistor and also disables the alarm feature. The alarm feature can also be set to latched or unlatched (Register 0x6, Bit 11). Kelvin Alarm (KELALM) The open-drain active low Kelvin alarm pin flags the user when an open occurs in either the sense or DUTGND line; it can be programmed to be either latched or unlatched (Register 0x6, Bit 13, Bit 11, Bit 7). The delay in the alarm flag is 50 μs. OPEN-SENSE DETECT (OSD) ALARM AND CLAMP GPO The open-sense detect (OSD) circuitry protects the DUT from overvoltage when the force and sense lines of the force amplifier becoming disconnected from each other. The GPO pin can be used as an extra control bit for external switching functions, such as for switching out DUT decoupling when making low current measurements. This block performs three functions related to the force and sense lines. The GPO pin is also internally connected to an array of thermal diodes scattered across the AD5560. The diagnostic register (Address 0x7) details the addressing and location of the diodes. These analog.com Rev. F | 29 of 66 Data Sheet AD5560 THEORY OF OPERATION can be used for diagnostic purposes to determine the thermal gradients across the die and across a board containing many AD5560 devices. When selected, the anode of these diodes is connected to GPO and the cathode to AGND. The AD5560 evaluation board uses the ON Semiconductor® ADT7461 temperature sensor for the purpose of analyzing the temperature at different points across the die. COMPARATORS The DUT measured value is monitored by two comparators (CPOL, CPOH). These comparators give the advantage of speed for go-nogo testing. Table 6. Comparator Output Function Test Condition CPOL CPOH (VDUT or IDUT) > CPH 0 (VDUT or IDUT) < CPH 1 (VDUT or IDUT) > CPL 1 (VDUT or IDUT) < CPL 0 CPH > (VDUT or IDUT) > CPL 1 1 To minimize the number of comparator output lines routed back to the controller, it is possible to change the comparator function to a window comparator that outputs on one single pin, CPO. This pin is shared with CPOH and, when configured through the serial interface, it provides information on whether the measured DUT current or voltage is inside or outside the window set by the CPL and CPH DAC levels (see Table 24). Table 7. Comparator Output Function in CPO Mode Test Condition CPO Output (VDUT or IDUT) > CPL and < CPH 1 (VDUT or IDUT) < CPL or > CPH 0 CURRENT CLAMPS High and low current clamps are included on chip. These protect the DUT in the event of a short circuit. The CLH and CLL levels are set by the 16-bit DAC levels. The clamp works to limit the current supplied by the force amplifier to within the set levels. The clamp circuitry compares the voltage across the sense resistor (multiplied by an in-amp gain of 10 or 20) to compare to the programmed clamp limit and activates the clamp circuit if either the high level or low level is exceeded, thus ensuring that the DUT current can never exceed the programmed clamp limit + 10% of full-scale current. If a clamp level is exceeded, this is flagged via the latched opendrain CLALM pin, and the resulting alarm information can be read back via the SPI interface. The clamp levels should not be set to the same level; instead, they should be set a minimum of 2 V apart (irrespective of the MI gain setting). This equates to 10% of FSCR (MI gain = 20) (20% of FSCR, MI gain of 10) apart. They should also be 1 V away from the 0 A level. analog.com The clamp register limits the CLL clamp to the range 0x0000 to 0x7FFF; any code in excess of this is seen as 0x7FFF. Similarly, the CLH clamp registers are limited to the range 0x8000 to 0xFFFF (see Table 24). Clamp Alarm Function (CLALM) The CLALM open-drain output flags the user when a clamp limit has been hit; it can be programmed to be either latched or unlatched. Clamp Enable Function (CLEN/LOAD) Pin 15 (CLEN) allows the user to disable the clamping function when powering a device with large DUT capacitance, thus allowing increased current drive to the device and, therefore, speeding up the charging time of the load capacitance. CLEN is active high. This pin can also be configured as LOAD to allow multiple devices to be synchronized. Note that either CLEN or HW_INH can be chosen as a LOAD function. SHORT-CIRCUIT PROTECTION The AD5560 force amplifier stage has built-in short-circuit protection per stage as noted in the Specifications section. When the current clamps are disabled, the user must minimize the duration of time that the device is left in a short-circuit condition (for all current ranges). GUARD AMPLIFIER A guard amplifier allows the user to force the shield of the coaxial cable to be driven to the same forced voltage at the DUT, ensuring minimal voltage drops across the cable to minimize errors from cable insulation leakage. The guard amplifier also has an alarm function that flags the open-drain KELALM pin when the guard output is shorted. The delay in the alarm flag is 200 μs. The guard amplifier output (GUARD/SYS_DUTGND, Pin 43) can also be configured to function as a SYS_DUTGND pin; to do this, the guard amplifier must be tristated via software (see DPS Register 2, Table 19). COMPENSATION CAPACITORS The force amplifier is capable of driving DUT capacitances up to 160 μF. Four external compensation capacitor (CCx) inputs are provided to ensure stability into the maximum load capacitance while ensuring that settling time is optimized. In addition, five CFx capacitor inputs are provided to switch across the sense resistors to further optimize stability and settling time perform-ance. The AD5560 has three compensation modes: safe mode, autocompensation mode, and manual compensation mode, all of which are described in more detail in the Force Amplifier Stability section. Rev. F | 30 of 66 Data Sheet AD5560 THEORY OF OPERATION The range of suggested compensation capacitors allows optimum performance for any capacitive load from 0 pF to 160 μF using one of the modes previously listed. Although there are four compensation input pins and five feed-forward capacitor inputs pins, all capacitor inputs may be used only if the user intends to drive large variations of DUT load capacitances. If the DUT load capacitance is known and does not change for all combinations of voltage ranges and test conditions, then it is possible only one set of CCx and CFx capacitors may be required. Table 8. Suggested Compensation Capacitor Selection Capacitor Value CC0 100 pF CC1 100 pF CC2 330 pF CC3 3.3 nF CF0 4.7 nF CF1 22 nF CF2 100 nF CF3 470 nF CF4 2.2 μF The voltage range for the CCx and CFx pins is the same as the voltage range expected on FORCE; therefore, choice of capacitors should take this into account. CFx capacitors can have 10% tolerance; this extra variation directly affects settling times, especially when measuring current in the low current ranges. Selection of CCx should be at ≤5% tolerance. CURRENT RANGE SELECTION Integrated thin film resistors minimize external components and allow easy selection of current ranges from ±5 µA to ±25 mA. Using external current sense resistors, two higher current ranges are possible: EXTFORCE1 can drive currents up to ±1.2 A, while EXTFORCE2 is designed to drive currents up to ±500 mA. The analog.com voltage drop across the selected sense resistor is ±500 mV when full-scale current is flowing through it. The measure current amplifier has two gain settings, 10 and 20. The two gain settings allow users to achieve the quoted/ specified current ranges with large or small voltage swings. The gain of 20 setting is intended for use with a 5 V reference, and the gain of 10 setting is for use with a 2.5 V reference. Both combinations ensure the specified current ranges. Other VREF/gain setting combinations should only be used to achieve smaller current ranges. Attempting to achieve greater current ranges than the specified ranges is outside the intended operation of the AD5560. The maximum guaranteed voltage across RSENSE is ±0.64 V (gain of 20) or ±0.7 V (gain of 10). HIGH CURRENT RANGES For currents in excess of 1200 mA, a gang mode is available whereby multiple devices are ganged together to achieve higher currents. In gang mode, the loop is controlled by the master AD5560. This loop drives a maximum capacitance of 160 µF for this mode. There are two methods of ganging channels together; these are described in the Master and Slaves in Force Voltage (FV) Mode section and the Master in FV Mode, Slaves in Force Current (FI) Mode section. Master and Slaves in Force Voltage (FV) Mode All devices are placed in force voltage (FV) mode. One device acts as the master device and the other devices act as slaves. By connecting in this manner, any device can be configured as the master. Here, the MASTER_OUT pin of the master device is connected to the output of the force amplifier, and it feeds the inputs of each slave force amplifier (via the SLAVE_IN pin ). All devices are connected externally to the DUT. For current to be shared equally, there must be good matching between each of the paths to the DUT. Settings for DPS Register 2 are master = 0x0000, slave = 0x0400. Clamps should be disabled in the slave devices. Rev. F | 31 of 66 Data Sheet AD5560 THEORY OF OPERATION Figure 54. Simplified Block Diagram of High Current Ganging Mode Master in FV Mode, Slaves in Force Current (FI) Mode The master device is placed into FV mode, and all slave devices into force current (FI) mode. The measured current of the master device (MASTER_OUT) is applied to the input of all slave devices analog.com (SLAVE_IN), and the slaves act as followers. All channels work to share the current equally among all devices in the gang. Because the slaves force current, matching the DUT paths is not so critical. Settings for DPS Register 2 are master = 0x0200, slave = 0x0600. Clamps should be disabled in the slave devices. Rev. F | 32 of 66 Data Sheet AD5560 THEORY OF OPERATION Figure 55. Simplified Block Diagram of Gang Mode, Using an FV/FI Combination The EXTFORCE1, EXTFORCE2, or ±25 mA ranges can be used for the gang mode. Therefore, it is possible to gang devices to get a high voltage/high current combination, or a low voltage/high current combination. For example, ganging five 25 V/25 mA devices using the 25 mA range achieves a 25 V/625 mA range, whereas five 15 V/200 mA devices using the EXTFORCE2 path can achieve a 15 V/1 A range. Similarly, ganging four 3.5 V/1.2 A devices using the EXTFORCE1 path results in a 3.5 V/4.8 A DPS. IDEAL SEQUENCE FOR GANG MODE Use the following steps to bring devices into and out of gang mode: 1. Choose the master device and force 0 V output, corresponding to zero current. 2. Select slave DPS 1 and place it in slave mode (keep slaves in high-Z mode via SW-INH or HW_INH until ready to gang). 3. Select to gang in either current or voltage mode. 4. Repeat Step 2 and Step 3 one at a time through the chain of slaves. 5. Load the required voltage to the master device. The other devices copy either voltage or current as programmed. analog.com To remove devices from the gang, the master device should be programmed to force 0 V out again. The procedure for removing devices should be the reverse of Step 1 through Step 5. 1. Note that this may not always be possible in practice; therefore, it is also possible to gang and ungang while driving a load. Just ensure that the slave devices are in high-Z mode while configuring them into the required range and gang setting. Gang mode extends only to the ±25 mA range and the two high current ranges, EXTFORCE1 and EXTFORCE2. Therefore, where an accurate measurement is required at a low current, the user should remove slaves from the gang to move to the appropriate lower current range to make the measurement. Similarly, slaves can be brought back into the gang if needed. COMPENSATION FOR GANG MODE When ganging, the slave devices should be set to the fastest response. When slaves are in FI mode, the AD5560 force amplifier overrides other compensation settings to enforce CFx = 0, RZ = 0, and gmx ≤ 1. This is done internally to the force amplifier; therefore, readback does not show that the signals inside the force amplifier actually change. Rev. F | 33 of 66 Data Sheet AD5560 THEORY OF OPERATION SYSTEM FORCE/SENSE SWITCHES System force/sense switches allow easy connection of a central or system parametric measurement unit (PMU) for calibration or additional measurement purposes. The system device under test ground (SYS_DUTGND) switch is shared with the GUARD/SYS_DUTGND pin (Pin 43). See the DPS Register 2 in Table 19 for addressing details. DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN There are three types of temperature sensors in the AD5560. ► The first is a temperature sensor available on the MEASOUT pin and expressed in voltage terms. Nominally at 25°C, this sensor reads 1.54 V. It has a temperature coefficient of 4.7 mV/°C. This sensor is active during power-down mode. Die Temp = (VMEASOUT(TSENSE) − 1.54)/0.0047 + 25°C Based on typical temperature sensor output voltage at 25°C and output scaling factor. ► The second type of temperature sensor is related to the thermal shutdown feature in the device. Here, there are sensors located in the middle of the enabled power stage, which are used to trip the thermal shutdown. The thermal shutdown feature senses only the power stages, and the power stage that it senses is determined by the active stage. If ranges of fUG, the load pole is above the bandwidth of the AD5560. Ignore it with RZ[2:0] = 0, RP[2:0] = 0. This ends the algorithm 12. If RC < (R0/25), then the ESR is negligible. Attempt to cancel the load pole with RZ zero. Choose an ideal zero frequency of 2 × FP for some safety margin and then choose the RZ[2:0] value that gives the closest frequency on a logarithmic scale. This ends the algorithm. 13. Otherwise, this is a troublesome window in which a load pole and a load zero cannot be ignored. Use the following steps: ► To cancel the load pole at FP, choose an ideal zero frequency of 6 × FP (this is more conservative than the 2 × FP suggested earlier, but there is more that can go wrong with miscalculation). Then choose the RZ[2:0] value that gives the closest zero to this ideal frequency of 6 × FP on a logarithmic scale. ► To cancel the ESR zero at FZ, choose an ideal pole frequency of 2 × FZ. ► Then choose the RP[2:0] value that gives the closest pole to this ideal frequency of 2 × FZ on a logarithmic scale. This ends the algorithm. ADJUSTING THE AUTOCOMPENSATION MODE The autocompensation algorithm assumes that there is 1 Ω of resistance (RC) from the AD5560 to the DUT. If a particular application has resistance that differs greatly from this, then it is likely that the autocompensation algorithm is nonoptimal. If using the autocompensation algorithm as a starting point, consider that overstating the CR capacitance and understating the ESR RC is likely to give a faster response but could cause oscillations. Understating CR and overstating RC is more likely to slow things down and reduce phase margin but not create an oscillator. RFM = RF/(1 + [2 × (CFx/2.2 μF)]) It is often advisable to err on the side of simplicity. Rather than insert a pole and zero at similar frequencies, it may be better to add none at all. Set RP[2:0] = RZ[2:0] = 0 to push them beyond the AD5560 bandwidth. That is, RFM is up to 3× smaller than RF, when the selected CFx capacitor is large compared to 2.2 μF. DEALING WITH PARALLEL LOAD CAPACITORS Then calculate R0 = RC + (RS ||RFM) where RC takes its value from the assumptions in Step 2. 7. If RC > (R0/5), then the ESR is large enough to make the DUT look resistive. Choose RZ[2:0] = 0, RP[2:0] = 0. This ends the algorithm analog.com In the event that the load capacitance consists of two parallel capacitors with different ESRs, it is highly likely that the overall complex impedance at the unity gain bandwidth is dominated by the larger capacitor and its ESR. Assuming that the smaller capacitor does not exist normally is a safer simplifying assumption. A more complex alternative is to calculate the overall impedance at the expected unity gain bandwidth and use this to calculate Rev. F | 39 of 66 Data Sheet AD5560 THEORY OF OPERATION an equivalent series CR and RC that have the same complex impedance at that particular frequency. where: RSENSE is the sense resistor. MI_AMP_GAIN is the gain of the MI amp (either 10 or 20). DAC LEVELS This device contains all the dedicated DAC levels necessary for operation: a 16-bit DAC for the force amplifier, two 16-bit DACs for the clamp high and low levels, two 16-bit DACs for the comparator high and low levels, a 16-bit DAC to set a programmable open sense voltage, and a 16-bit offset DAC to bias or offset a number of DACs on chip (FORCE, CLL, CLH, CPL, CPH). FORCE AND COMPARATOR DACS The architecture of the main force amplifier DAC consists of a 16-bit R-2R DAC, whereas the comparator DACs are resistor-string DACs followed by an output buffer amplifier. This resistor-string architecture guarantees DAC monotonicity. The 16-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. The comparator DAC is similarly arranged. The force and comparator DACs have a 25.62 V span, including overrange to enable offset and gain errors to be calibrated out. The transfer function for these 16-bit DACs is CODE −5.125 × V VOUT = 5.125 × VREF × DAC 16 REF × 2 OFFSET_DAC_CODE + DUTGND 216 (1) The architecture of the clamp DAC consists of a 16-bit resistorstring DAC followed by an output buffer amplifier. This resistorstring architecture guarantees DAC monotonicity. The 16-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. The transfer function for these 16-bit DACs is (2) The transfer function for the clamp current value is analog.com DAC CODE 216 (4) The offset DAC does not affect the OSD DAC output range. DUTGND DAC Similarly, the DUTGND DAC (DGS) is a 16-bit DAC and uses a resistor string DAC to guarantee monotonicity. The 16-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. This function is used to program the voltage difference needed between the DUTGND and AGND lines before the alarm circuit flags an error. The DUTGND DAC has a range of 0 V to 5 V. The transfer function for this 16-bit DAC is shown in Equation 1. In addition to the offset and gain trim, there is also a 16-bit offset DAC that offsets the output of each DAC on chip. There-fore, depending on headroom available, the input to the force amplifier can be arranged either symmetrically or asymmetrically about DUTGND but always within a voltage span of 25 V. Some extra gain is included to allow for system error correction using the m (gain) and c (offset) registers. The usable voltage range is −22 V to +25 V. Full scale loaded to the offset DAC does not give a useful output voltage range because the output amplifiers are limited by available footroom. Table 15 shows the effect of the offset DAC on other DACs in the device (clamp, comparator, and force DACs). The clamp DACs have a 25.62 V span, including overrange, to enable offset and gain errors to be calibrated out. − 32768 5.125 × VREF× DAC CODE 16 2 ICLL, ICLH= RSENSE×MI_AMP_GAIN VOUT = VREF × OFFSET DAC CLAMP DACS OFFSET_DAC_CODE +DUTGND 216 The OSD DAC is a 16-bit DAC function, again a resistor string DAC guaranteeing monotonicity. The 16-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. The OSD function is used to program the voltage difference needed between the force and sense lines before the alarm circuit flags an error. The OSD DAC has a range of 0.62 V to 5 V. The transfer function is as follows: The offset DAC does not affect the OSD DAC output range. where DAC CODE is X2 (see the Offset and Gain Registers section). CODE −5.125 × V VCLH,  VCLL = 5.125 × VREF× DAC 16 REF× 2 OSD DAC (3) Table 15. Offset DAC Relationship with Other DACs, VREF = 5 V Offset DAC Code DAC Code1 DAC Output Voltage Range 0 0 0.00 0 32,768 12.81 0 65,535 25.62 … … … 32,768 0 −12.81 Rev. F | 40 of 66 Data Sheet AD5560 THEORY OF OPERATION Offset DAC Code DAC Code1 DAC Output Voltage Range x1 registers and their associated offset and gain registers are 16 bit. 32,768 32,768 0.00 REFERENCE SELECTION 32,768 65,535 12.81 … … … 57,344 0 −22.42 57,344 32,768 −9.61 57,344 65,535 3.20 … … … 65,355 … Footroom limitations Table 15. Offset DAC Relationship with Other DACs, VREF = 5 V (Continued) The voltage applied to the VREF pin determines the output voltage range and span applied to the force amplifier, clamp, and comparator inputs and the current ranges. OFFSET AND GAIN REGISTERS This device can be used with a reference input ranging from 2 V to 5 V. However, for most applications, a reference input of 5 V is able to meet all voltage range requirements. The DAC amplifier gain is 5.125, which gives a DAC output span of 25.625 V. The DACs have gain and offset registers that can be used to calibrate out system errors. In addition, the gain register can be used to reduce the DAC output range to the desired force voltage range. Each DAC level contains independent offset and gain control registers that allow the user to digitally trim offset and gain. These registers give the user the ability to calibrate out errors in the complete signal chain (including the DAC) using the internal m and c registers, which hold the correction factors. Using a 5 V reference and setting the m (gain) register to one-fourth scale or 0x4000 gives an output voltage span of 6.25 V. Because the force DAC has 18 bits of resolution even with only one-fourth of the output voltage span, it is still possible to achieve 16-bit resolution in this 6.25 V range. The digital input transfer function for the DACs can be represented as The measure current amplifier has two gain settings, 10 and 20. The two gain settings allow users to achieve the quoted/speci-fied current ranges with large or small voltage swings. The 20 gain setting is intended for use with a 5 V reference, and the 10 gain setting is for use with a 2.5 V reference. Both combinations ensure the specified current ranges. Other VREF/gain setting combinations should be used only to achieve smaller current ranges. See Table 27 for suggested references for use with the AD5560. 1 DAC code shown for 16-bit force DAC. x2 = [x1 × (m + 1)/2n] + (c – 2n – 1) where: x2 is the data-word loaded to the resistor string DAC. x1 is the 16-bit data-word written to the DAC input register. m is the code in the gain register (default code = 216 – 1). n is the DAC resolution (n = 16). c is the code in the offset register (default code = 215). Offset and Gain Registers for the Force Amplifier DAC The force amplifier input (FIN) DAC level contains independent offset and gain control registers that allow the user to digitally trim offset and gain. There is one set of registers for the force voltage range: x1, m, and c. Offset and Gain Registers for the Comparator DACs The comparator DAC levels contain independent offset and gain control registers that allow the user to digitally trim offset and gain. There are seven sets of registers consisting of a combination of x1, m, and c, one set each for the five internal force current ranges and one set each for the two external high current ranges. Offset and Gain Registers for the Clamp DACs The clamp DAC levels contain independent offset and gain control registers that allow the user to digitally trim offset and gain. One set of registers covers the VSENSE range, the five internal force current ranges, and the two external high current ranges. Both clamp DAC analog.com CALIBRATION Calibration involves determining the gain and offset of each channel in each mode and overwriting the default values in the m and c registers of the individual DACs. Reducing Zero-Scale Error Zero-scale error can be reduced as follows: 1. Set the output to the lowest possible value. 2. Measure the actual output voltage and compare it to the required value. This is the zero-scale error. 3. Calculate the number of LSBs equivalent to the zero-scale error, and add or subtract this number to the default value of the c register. Reducing Gain Error Gain error can be reduced as follows: 1. Measure the zero-scale error. 2. Set the output to the highest possible value. 3. Measure the actual output voltage and compare it to the required value. This is the gain error. Rev. F | 41 of 66 Data Sheet AD5560 THEORY OF OPERATION 4. Calculate the number of LSBs equivalent to the gain error and subtract this number from the default value of the m register. Note that only positive gain error can be reduced. f. Load these values to the appropriate FIN DAC m and FIN DAC c registers (Register 0x9 and Register 0xA). 2. Calibrate the measure voltage (two-point calibration). Calibration Example a. Connect SYS_FORCE to FORCE (via SW8) and SYS_SENSE to SENSE (via SW9), and close the internal force/sense switch (via SW11). b. Force the voltage on FORCE via SYS_FORCE and measure the voltage at MEASOUT. The difference is the error between the actual forced voltage and the voltage at MEASOUT. 3. Calibrate the measure current (two-point calibration). Nominal offset coefficient = 32,768 (0x8000) Nominal gain coefficient = 65,535 (0xFFFF) For example, the gain error = 0.5%, and the offset error = 100 mV. Gain error (0.5%) calibration is as follows: 65,535 × 0.995 = 65,207 Therefore, load Code 1111 1110 1011 0111 (0xFEB7) to the m register. Offset error (100 mV) calibration is as follows: LSB size = 10.25/65,535 = 156 µV Offset coefficient for 100 mV offset = 100/0.156 = 641 LSBs Therefore, load Code 0111 1101 0111 1111 (0x7D7F) to the c register. ADDITIONAL CALIBRATION The techniques described in the Calibration section are usually sufficient to reduce the zero-scale and gain errors. However, there are limitations whereby the errors may not be sufficiently reduced. For example, the offset (c) register can only be used to reduce the offset caused by negative zero-scale error. A positive offset cannot be reduced. Likewise, if the maximum voltage is below the ideal value, that is, a negative gain error, the gain (m) register cannot be used to increase the gain to compensate for the error. These limitations can be overcome by increasing the reference value. a. In FV mode, write zero scale to the FIN DAC registers (Register 0x8 to Register 0xA). b. Disconnect the FORCE pin and the SENSE pin. Connect SYS_FORCE to FORCE (via SW8) and SYS_SENSE to SENSE (via SW9). c. Connect the SYS_FORCE pin to an external ammeter and its other terminal to the SYS_SENSE pin. d. Connect the SYS_SENSE pin to a precision resistor (RDUT), where RDUT = RSENSE × 20 of the current range, and connect its other terminal to ground (see Figure 58). e. Measure the error between the ammeter reading and the MEASOUT reading by forcing ±10 V to the FIN DAC registers (Register 0x8 to Register 0xA). f. Repeat Step 3a through Step3e across all current ranges. 4. Similarly, calibrate the comparator and clamp DACs, and load the appropriate gain and offset registers. Calibrating these DACs requires some successive approximation to determine where the comparator trips or the clamps engage. SYSTEM LEVEL CALIBRATION There are many ways to calibrate the device on power-on. Following is an example of how to calibrate the FIN DAC registers (Register 0x8 to Register 0xA) of the device without a DUT or DUT board connected. The calibration procedure for the force and measure circuitry is as follows: 1. Calibrate the force voltage (two-point calibration). a. Write zero scale to the FIN DAC registers (Register 0x8 to Register 0xA). b. Connect SYS_FORCE to FORCE (via SW8) and SYS_SENSE to SENSE (via SW9), and close the internal force/sense switch (SW11). c. Using the system PMU, measure the error between the voltage at FORCE/SENSE and the desired value. d. Similarly, load full scale to the FIN DAC registers (Register 0x8 to Register 0xA) and measure the error between the voltage at FORCE/SENSE and the desired value. e. Calculate the m and c values. analog.com Figure 58. Measure Current Calibration CHOOSING AVDD/AVSS POWER SUPPLY RAILS As noted in the Specifications section, the minimum supply variation across the part is |AVDD − AVSS| ≥ 16 V and ≤ 33 V, AVDD ≥ 8 V, and AVSS ≤ −5 V. For the AD5560 circuits to operate correctly, the supply rails must take into account not only the force voltage range but also the internal DAC minimum voltage level, as well as headroom/footroom. Rev. F | 42 of 66 Data Sheet AD5560 THEORY OF OPERATION The DAC amplifier gains VREF by 5.125, and the offset DAC centers that range about some chosen point. Because the DAC minimum voltage (VMIN) is used in other parts of the circuit (MEASOUT gain of 0.2), it is important that AVSS be chosen based on the following: AVSS ≤ −5.125 × (VREF × (OFFSET_DAC_CODE/216)) − AVSS_Headroom − VDUTGND − (RCABLE × ILOAD) where: AVSS_Headroom is the 2.75 V headroom (includes the RSENSE voltage drop). VDUTGND is the voltage range anticipated at DUTGND. RCABLE is the cable/path resistance. ILOAD is the maximum load current. When choosing AVDD, remember to take into account the specified current ranges. The measure current block has either a gain of 20 or 10 and must have sufficient headroom/ footroom to operate correctly. As the nominal, VRSENSE is ±0.5 V for the full-scale specified current flowing for all ranges. If this is gained by 20, the measure current amplifier output (internal node) voltage range is ±10 V with full-scale current and the default offset DAC setting. The measure current block needs ±2.25 V footroom/headroom for correct operation in addition to the ±0.5 V VRSENSE. For simplicity, when VREF = 5 V, minimum |AVDD − AVSS| = 31.125 V (VREF × 5.125 + headroom + footroom); otherwise, there can be unanticipated effects resulting from headroom/ footroom issues. This does not take into account cable loss or DUTGND contributions. Similarly, when VREF = 2.5 V, minimum |AVDD − AVSS| = 18.3 V and, when VREF = 2 V, minimum |AVDD − AVSS| = 16 V. The AD5560 is designed to settle fast into large capacitive loads; therefore, when slewing, the device draws 2× to 3× the current range from the AVDD/AVSS supplies. When supply rails are chosen, they should be capable of supplying each DPS channel with sufficient current to slew. CHOOSING HCAVSSX AND HCAVDDX SUPPLY RAILS All output stages of the AD5560 are symmetrical; they can source and sink the rated current. Supply design/bypassing should account for this. POWER DISSIPATION The maximum power dissipation allowed in the EXTFORCE1 stage is 10 W, whereas in the EXTFORCE2 stage, it is 5 W. Take care to ensure that the device is adequately cooled to remove the heat. The quiescent current is ~0.8 W with an internal current range enabled and ~1 W with external current ranges, EXTFORCE1 or EXTFORCE2, enabled. This device is specified for performance up to 90°C junction temperature (TJ). PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE The exposed pad and leads of the TQFP package have a 100% tin finish. The exposed paddle is connected internally to AVSS. The simulated maximum allowable force for a single lead is 0.18 lbs; total allowable force for the package is 11.5 lbs. The quoted maximum force may cause permanent lead bending. Other package failure (die, mold, board) may occur first at lower forces. SLEW RATE CONTROL There are two methods of achieving different slew rates using the AD5560. One method is using the programmable slew rate feature that gives eight programmable rates. The second method is using the ramp feature and an external clock. Programmable Slew Rate Eight programmable modes of slew rates are available to choose from through the serial interface, enabling the user to choose different rates to power up the DUT. The different slew rates are achieved by variation in the internal compensation of the force DAC output amplifier. The slew rates available are 1.000 V/µs, 0.875 V/µs, 0.750 V/µs, 0.625 V/µs, 0.5 V/µs, 0.4375 V/µs, 0.35V µs, and 0.313 V/µs. Ramp Function Selection of HCAVSSx and HCAVDDx supplies is determined by the EXTFORCE1 and EXTFORCE2 output ranges. The supply rails chosen must take into account headroom and footroom, DUTGND voltage range, cable loss, supply tolerance, and VRSENSE. If diodes are used in series with the HCAVSSx and HCAVDDx supplies pins (shown in Figure 60), the diode voltage drop should also be factored into the supply rail calculation. Included in the AD5560 is a ramp function that enables the user to apply a rising or falling voltage ramp to the DUT. The user supplies a clock, RCLK, to control the timing. The AD5560 is designed to settle fast into large capacitive loads in high current ranges; therefore, when slewing, the device draws 2× to 3× the current range from the HCAVSSx and HCAVDDx supplies. When choosing supply rails, ensure that they are capable of supplying each DPS channel with sufficient current to slew. The contents of the FIN DAC x1 register are the ramp start value. The user must load the end code register and the step size register. The sign is now generated from the difference between the FIN DAC x1 register and the end code; then the step size value is added to or subtracted from FIN DAC x1, calibrated and stored. The user must supply a clock to the RCLK pin to load the new code analog.com This function is controlled via the serial interface and requires programming of a number of registers to determine the end value, the ramp size, and the clock divider register to determine the update rate. Rev. F | 43 of 66 Data Sheet AD5560 THEORY OF OPERATION to the DAC. The output settles in 1.2 µs for a step of 10 mV with CDUT in the lowest range of