Quad, 12-Bit, Parallel Input,
Unipolar/Bipolar, Voltage Output DAC
AD5725
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVSS
AVDD
VREFP
VL
12
A0
A1
R/W
CS
I/O
REGISTER
AND
CONTROL
LOGIC
12
DB0
TO
DB11
AD5725
INPUT
REG A
DAC 12
REG A
DAC A
VOUTA
INPUT
REG B
DAC 12
REG B
DAC B
VOUTB
INPUT
REG C
DAC 12
REG C
DAC C
VOUTC
INPUT
REG D
DAC 12
REG D
DAC D
VOUTD
APPLICATIONS
DGND
Industrial automation
Closed-loop servo control, process control
Automotive test and measurement
Programmable logic controllers
CLR
LDAC
VREFN
06442-001
+5 V to ±15 V operation
Unipolar or bipolar operation
±0.5 LSB max INL error, ±1 LSB max DNL error
Settling time: 10 µs max (10 V step)
Double-buffered inputs
Simultaneous updating via LDAC
Asynchronous CLR to zero/mid scale
Readback
Operating temperature range: −40°C to +85°C
iCMOS® process technology
Figure 1.
GENERAL DESCRIPTION
The AD5725 is a quad, 12-bit, parallel input, voltage output
digital-to-analog converter that offers guaranteed monotonicity,
integral nonlinearity (INL) of ±0.5 LSB maximum and 10 µs
maximum settling time.
Output voltage swing is set by two reference inputs, VREFP and
VREFN. By setting the VREFN input to 0 V and the VREFP to a
positive voltage, the DAC provides a unipolar positive output
range. A similar configuration with VREFP at 0 V and VREFN at a
negative voltage provides a unipolar negative output range.
Bipolar outputs are configured by connecting both VREFP and
VREFN to nonzero voltages. This method of setting output voltage
ranges has advantages over the bipolar offsetting methods
because it is not dependent on internal and external resistors
with different temperature coefficients.
Digital controls allow the user to load or read back data from
any DAC, load any DAC, and transfer data to all DACs at
one time.
The AD5725 is available in a 28-lead SSOP package. It can be
operated from a wide variety of supply and reference voltages,
with supplies ranging from single +5 V to ±15 V, and references
from +2.5 V to ±10 V. Power dissipation is less than 270 mW
with ±15 V supplies and only 40 mW with a +5 V supply.
Operation is specified over the temperature range of −40°C
to +85°C.
iCMOS® Process Technology
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, and increased ac and dc performance.
Rev. C
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Technical Support
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AD5725
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 15
Applications ....................................................................................... 1
DAC Architecture....................................................................... 15
Functional Block Diagram .............................................................. 1
Output Amplifiers ...................................................................... 15
General Description ......................................................................... 1
Reference Inputs ......................................................................... 15
Revision History ............................................................................... 2
Parallel Interface ......................................................................... 15
Specifications..................................................................................... 3
Data Coding ................................................................................ 15
AC Performance Characteristics ................................................ 5
CLR............................................................................................... 15
Timing Characteristics ............................................................... 6
Power Supplies ............................................................................ 17
Absolute Maximum Ratings ............................................................ 8
Reference Configuration ........................................................... 17
ESD Caution .................................................................................. 8
Single +5 V Supply Operation .................................................. 18
Pin Configuration and Function Descriptions ............................. 9
Outline Dimensions ....................................................................... 19
Typical Performance Characteristics ........................................... 10
Ordering Guide .......................................................................... 19
,
Terminology .................................................................................... 14
REVISION HISTORY
8/13—Rev. B to Rev. C
Change Junction Temperature from 105°C to 150°C; Changed
Power Dissipation Package Condition from Derate 10 mW/°C
Above 70°C to Derate 10 mW/°C Above 60°C; Table 5 .............. 8
4/13—Rev. A to Rev. B
Changes to VREFN Input Current Parameter, Table 1 .................... 3
Changes to Figure 27 and Figure 28............................................. 17
Changes to Figure 29 and Figure 30............................................. 18
12/08—Rev. 0 to Rev. A
Changes to Figure 26 ...................................................................... 13
7/07—Revision 0: Initial Version
Power Dissipation Package (Derate 10 mW/°C Above 60°C)
Rev. C | Page 2 of 20
Data Sheet
AD5725
SPECIFICATIONS
AVDD = +15 V, AVSS = −15 V, DGND = 0 V; VREFP = +10 V; VREFN = −10 V, VL = 5 V. All specifications TMIN to TMAX, unless otherwise noted. 1
Table 1.
Parameter
ACCURACY
Resolution
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
Zero-Scale TC 2
Full-Scale Error
Full-Scale TC2
REFERENCE INPUT
VREFP
Reference Input Range 3
Input Current
VREFN
Reference Input Range3
Input Current2
Large Signal Bandwidth2
OUTPUT CHARACTERISTICS2
Output Current
DIGITAL INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current2
Input Capacitance2
DIGITAL OUTPUTS (SDO)
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLY CHARACTERISTICS
Power Supply Sensitivity2
AIDD
AISS
Power Dissipation
1
2
3
Value
Unit
12
±0.5
±1
±1
±2
±15
±2
±20
Bits
LSB max
LSB max
LSB max
LSB max
ppm FSR/°C typ
LSB max
ppm FSR/°C typ
B grade
A grade
Guaranteed monotonic
RL = 2 kΩ
RL = 2 kΩ
RL = 2 kΩ
RL = 2 kΩ
VREFN + 2.5
AVDD − 2.5
±2.75
V min
V max
mA max
Typically 1.5 mA
−10
VREFP − 2.5
0
−2.75
160
V min
V max
mA max
mA min
kHz typ
±5
mA max
2.4
0.8
1
8
V min
V max
µA max
pF typ
4
0.4
V min
V max
IOH = 0.4 mA
IOL = −1.6 mA
30
3
2.5
270
ppm FSR/V max
mA/channel max
mA/channel max
mW max
14.25 V ≤ AVDD ≤ 15.75 V
Outputs unloaded, VREFP = 2.5 V, typically 2.125 mA
Outputs unloaded, typically 1.625 mA
All supplies can be varied ±5%, and operation is guaranteed. Device is tested with nominal supplies.
Guaranteed by design and characterization, not production tested.
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
Rev. C | Page 3 of 20
Test Conditions/Comments
Outputs unloaded
Typically −2 mA
−3 dB, VREFP = 0 V to 10 V p-p
RL = 2 kΩ, CL = 100 pF
VL = 2.7 V to 5.5 V, JEDEC compliant
TA = 25°C
TA = 25°C
AD5725
Data Sheet
AVDD = +5 V, AVSS = −5 V/0 V, DGND = 0 V; VREFP = +2.5 V; VREFN = −2.5 V/0 V, VL = 5 V. All specifications TMIN to TMAX, unless
otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
Zero-Scale TC 2
Full-Scale Error
Full-Scale TC2
REFERENCE INPUT
VREFP
Reference Input Range 3
Input Current2
VREFN
Reference Input Range3
Large Signal Bandwidth2
OUTPUT CHARACTERISTICS2
Output Current
DIGITAL INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current2
Input Capacitance2
DIGITAL OUTPUTS (SDO)
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLY CHARACTERISTICS
Power Supply Sensitivity2
AIDD
AISS
Power Dissipation
Value
Unit
Test Conditions/Comments
Outputs unloaded
12
±0.5
±1
±1
±2
±1
±5
±10
100
±5
±10
100
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
ppm FSR/°C typ
LSB max
LSB max
ppm FSR/°C typ
VREFN + 2.5
AVDD − 2.5
±0.5
V min
V max
mA max
−2.5
0
VREFP − 2.5
450
V min
V min
V max
kHz typ
AVSS = −5 V
AVSS = 0 V
±1.25
mA max
2.4
0.8
1
8
V min
V max
µA max
pF typ
RL = 2 kΩ, CL = 100 pF
VL = 2.7 V to 5.5 V, JEDEC compliant
TA = 25°C
TA = 25°C
4
0.4
V min
V max
IOH = 0.4 mA
IOL = −1.6 mA
100
2
1.5
70
40
ppm FSR/V typ
mA/channel max
mA/channel max
mW max
mW max
Outputs unloaded.
Outputs unloaded, AVSS = −5 V
AVSS = −5 V
AVSS = 0 V
B grade
A grade
B grade, AVSS = 0 V 1
A grade, AVSS = 0 V1
Guaranteed monotonic
AVSS = −5 V
AVSS = 0 V
AVSS = −5 V
AVSS = 0 V
Code 0x0000
−3 dB, VREFP = 0 V to 2.5 V p-p
For single supply operation only (VREFN = 0 V, AVSS = 0 V): Due to internal offset errors, INL and DNL are measured beginning at code 0x005.
Guaranteed by design and characterization, not production tested.
3
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
1
2
Rev. C | Page 4 of 20
Data Sheet
AD5725
AC PERFORMANCE CHARACTERISTICS 1
AVDD = +15 V/+5 V, AVSS = −15 V/−5 V/0 V, DGND = 0 V; VREFP = +10 V/+2.5 V; VREFN = −10 V/−2.5 V/0 V, VL = 5 V. All specifications
TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
Slew Rate
Analog Crosstalk
Digital Feedthrough
1
A Grade
B Grade
Unit
Test Conditions/Comments
10
7
2.2
72
5
10
7
2.2
72
5
µs typ
µs typ
V/µs typ
dB typ
nV-s typ
To 0.01%, 10 V step, RL = 1 kΩ
To 0.01%, 2.5 V step, RL = 1 kΩ
10% to 90%
Guaranteed by design and characterization, not production tested.
Rev. C | Page 5 of 20
AD5725
Data Sheet
TIMING CHARACTERISTICS 1, 2
AVDD = +5 V/+15 V, AVSS = −5 V/0 V/−15 V, DGND = 0 V; VREFP = +2.5 V/+10 V; VREFN = −2.5 V/0 V/−10 V, VL = 5 V. All specifications
TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
tWCS
tWS
tWH
tAS
tAH
tLS
tLH
tWDS
tWDH
tLDW
tRESET
tRCS
tRDH
tRDS
tDZ
tCSD
1
2
Limit at TMIN, TMAX
10
0
0
0
0
5
5
5
0
10
10
30
0
0
15
35
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
Description
Chip Select Write Pulse Width
Write Setup, tWCS = 10 ns
Write Hold, tWCS = 10 ns
Address Setup
Address Hold
Load Setup
Load Hold
Write Data Setup, tWCS = 10 ns
Write Data Hold, tWCS = 10 ns
Load Data Pulse Width
Reset Pulse Width
Chip Select Read Pulse Width
Read Data Hold, tRCS = 30 ns
Read Data Setup, tRCS = 30 ns
Data to High-Z, CL = 10 pF
Chip Select to Data, CL = 100 pF
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
Guaranteed by design and characterization, not production tested.
Rev. C | Page 6 of 20
Data Sheet
AD5725
Timing Diagrams
10ns
CS
tRCS
tRDS
tRDH
R/W
R/W
tAS
tAH
ADDRESS
A0/A1
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
tLH
tLS
tDZ
DATA VALID
HIGH-Z
tCSD
06442-002
HIGH-Z
LDAC
tWDS
DATA IN
DATA1
VALID
tWDH
DATA2
VALID
DATA3
VALID
DATA4
VALID
06442-004
tAS
DATA
OUT
tWH
tWS
CS
Figure 4. Single Buffer Mode Timing
Figure 2. Data Read Timing
10ns
tWCS
CS
CS
tWH
tWS
tWH
tWS
R/W
R/W
tAH
tAS
tAS
A0/A1
ADDRESS
tLH
tLS
ADDRESS
ONE
ADDRESS
TWO
ADDRESS
THREE
ADDRESS
FOUR
tLS
tLDW
LDAC
tLH
tWDH
DATA IN
tRESET
DATA1
VALID
DATA2
VALID
DATA3
VALID
DATA4
VALID
06442-003
DATA IN
RESET
tLDW
tWDS
Figure 5. Double Buffer Mode Timing
Figure 3. Data Write Timing
Rev. C | Page 7 of 20
tWDH
06442-005
LDAC
tWDS
AD5725
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 5.
Parameter
AVSS to DGND
AVDD to DGND
AVSS to AVDD
VL to DGND
Current into Any Pin
Digital Pin Voltage to DGND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
28-Lead SSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Power Dissipation Package
(Derate 10 mW/°C Above 60°C)
Reflow Soldering
Time at Peak Temperature
Lead Temperature (Soldering, 60 sec)
Rating
+0.3 V to −16.5 V
−0.3 V to +16.5 V
+0.3 V to −33 V
−0.3 V to +7 V
±15 mA
−0.3 V to +7 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
100°C/W
39°C/W
900 mW
10 sec to 40 sec
300°C
Rev. C | Page 8 of 20
Data Sheet
AD5725
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VREFP 1
28 VREFN
VOUTB 2
27 VOUTC
VOUTA 3
26 VOUTD
AVSS 4
25 AVDD
DGND 5
CLR 6
LDAC 7
DB0 (LSB) 8
DB1 9
24 VL
AD5725
23 CS
TOP VIEW
(Not to Scale)
22 A0
21 A1
20 R/W
19 DB11 (MSB)
DB3 11
18 DB10
DB4 12
17 DB9
DB5 13
16 DB8
DB6 14
15 DB7
06442-006
DB2 10
Figure 6. Pin Configuration Diagram
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
VREFP
2
3
4
5
6
VOUTB
VOUTA
AVSS
DGND
CLR
7
8
9
10
11
12
13
14
15
16
17
18
19
20
LDAC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
R/W
21
22
23
24
25
26
27
28
A1
A0
CS
VL
AVDD
VOUTD
VOUTC
VREFN
Description
Positive DAC Reference Input. The voltage applied to this pin defines the full-scale output voltage.
Allowable range is AVDD − 2.5 V to VREFN + 2.5 V.
Buffered Analog Output Voltage of DAC B.
Buffered Analog Output Voltage of DAC A.
Negative Analog Supply Pin. Voltage ranges from 0 V to −15 V.
Digital Ground Pin.
Active Low Input. Sets input registers and DAC registers to zero scale (0x000) for the AD5725-1 or midscale
(0x800) for the AD5725.
Active Low Load DAC Input.
Data Bit 0 (LSB).
Data Bit 1.
Data Bit 2.
Data Bit 3.
Data Bit 4.
Data Bit 5.
Data Bit 6.
Data Bit 7.
Data Bit 8.
Data Bit 9.
Data Bit 10.
Data Bit 11 (MSB).
Read/Write Pin. Active low to write data to DAC; Active high to read back previous data at data bit pins with
VL connected to +5 V.
Address Bit 1.
Address Bit 0.
Active Low Chip Select Pin.
Voltage Supply for Readback Function. Can be left open circuit if not used.
Positive Analog Supply Pin. Voltage ranges from +5 V to +15 V.
Buffered Analog Output Voltage of DAC D.
Buffered Analog Output Voltage of DAC C.
Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale output voltage.
Allowable range is AVSS to VREFP − 2.5 V.
Rev. C | Page 9 of 20
AD5725
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.5
AVDD = +15V
AVSS = –15V
VREFN = –10V
TA = 25°C
0.8
0.3
MAX INL ERROR (LSB)
0.4
0.2
0
–0.2
–0.4
AVDD = 5V
AVSS = 0V
VREFN = 0V
TA = 25°C
0.2
0.1
0
–0.1
–0.2
–0.6
7
8
9
10
12
11
VREFP (V)
–0.4
1.0
1.2
1.8
2.0
2.4
2.2
2.6
2.8
3.0
80
80
Figure 10. INL vs. VREFP (VSUPPLY = +5 V)
0.05
0
–0.1
FULL-SCALE ERROR (LSB)
0
–0.05
–0.10
–0.15
AVDD = 5V
AVSS = 0V
VREFN = 0V
TA = 25°C
–0.20
–0.25
1.0
1.2
1.4
AVDD = +15V
AVSS = –15V
VREFP = +10V
VREFN = –10V
2kΩ LOAD
–0.2
DAC D
–0.3
–0.4
–0.5
DAC C
DAC B
–0.6
DAC A
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
VREFP (V)
–0.7
–40
06442-018
MAX DNL ERROR (LSB)
1.6
VREFP (V)
Figure 7. DNL vs. VREFP (VSUPPLY = ±15 V)
–20
0
20
40
60
TEMPERATURE (°C)
Figure 8. DNL vs. VREFP (VSUPPLY = +5 V)
Figure 11. Full-Scale Error vs. Temperature
1.0
0.3
AVDD = +15V
AVSS = –15V
VREFN = –10V
TA = 25°C
0.8
0.2
ZERO-SCALE ERROR (LSB)
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
AVDD = +15V
AVSS = –15V
VREFP = +10V
VREFN = –10V
2kΩ LOAD
0.1
0
DAC A
–0.1
DAC D
DAC C
–0.2
DAC B
–0.8
–1.0
6
7
8
9
10
VREFP (V)
11
12
06442-019
MAX INL ERROR (LSB)
1.4
06442-020
6
06442-017
–1.0
06442-023
–0.3
–0.8
06442-024
MAX DNL ERROR (LSB)
0.6
0.4
Figure 9. INL vs. VREFP (VSUPPLY = ±15 V)
–0.3
–40
–20
0
20
40
60
TEMPERATURE (°C)
Figure 12. Zero-Scale Error vs. Temperature
Rev. C | Page 10 of 20
Data Sheet
AD5725
0.3
0.4
0.3
DAC A
DAC B
DAC C
DAC D
INL ERROR (LSB)
0.1
0
–0.1
AVDD = +15V
AVSS = –15V
VREFP = +10V
VREFN = –10V
1500
2500
2000
3500
3000
4000
DAC (Code)
–0.4
0
500
0.20
0.2
0.15
DAC A
DAC B
DAC C
DAC D
DNL ERROR (LSB)
INL ERROR (LSB)
–0.1
–0.2
3500
4000
+85°C
+25°C
–40°C
0.05
0
–0.05
AVDD = +15V
AVSS = –15V
VREFP = +10V
VREFN = –10V
–0.15
1500
2000
2500
3000
3500
4000
DAC (Code)
–0.20
06442-026
–0.4
1000
3000
–0.10
AVDD = 5V
AVSS = 0V
VREFP = 2.5V
VREFN = 0V
TA = 25°C
500
2500
0.10
0
0
2000
Figure 16. INL vs. DAC Code
0.3
–0.3
1500
DAC (Code)
Figure 13. Channel-to-Channel Matching (VSUPPLY = ±15 V)
0.1
1000
06442-028
1000
–0.1
0
500
1000
1500
2000
2500
3000
3500
4000
DAC (Code)
Figure 14. Channel-to-Channel Matching (VSUPPLY = +5 V)
06442-042
500
0
–0.3
–0.3
0
0.1
–0.2
AVDD = +15V
AVSS = –15V
VREFP = +10V
VREFN = –10V
TA = 25°C
–0.2
+85°C
+25°C
–40°C
0.2
06442-025
INL ERROR (LSB)
0.2
Figure 17. DNL vs. DAC Code
16
1.7995
14
1.5995
AVDD = +15V
AVSS = –15V
VREFP = +10V
VREFN = –10V
TA = 25°C
1.3995
12
1.1995
IVREFP (mA)
8
6
0.9995
0.7995
0.5995
0.3995
0.1995
–0.0005
3
5
VREFP (V)
7
9
11
13
0
500
1000
1500
2000
2500
3000
DAC (Code)
Figure 18. IVREFP vs. DAC Code
Figure 15. IDD vs. VREFP
Rev. C | Page 11 of 20
3500
4000
06442-029
4 AVDD = +15V
AVSS = –15V
VREFN = –10V
2
DIGITAL INPUTS HIGH
TA = 25°C
0
–7
–5
–3
–1
1
06442-027
IDD (mA)
10
AD5725
Data Sheet
12
AVDD = +15V
AVSS = –15V
VREFP = +10V
VREFN = –10V
TA = 25°C
0.9
0.8
NOISE DENSITY (mV)
FULL-SCALE VOLTAGE (V)
10
1.0
AVDD = +15V
AVSS = –15V
VREFP = +10V
VREFN = –10V
TA = 25°C
8
6
4
0.7
0.6
0.5
0.4
0.3
0.2
0.1
2
1
100
10
LOAD RESISTANCE (kΩ)
06442-035
0.1
–0.1
1
10
100
1k
100k
10k
NOISE FREQUENCY (Hz)
Figure 19. Output Voltage Swing vs. Resistive Load
06442-044
0
0
0.01
Figure 22. Output Noise Spectral Density vs. Frequency
2
20
0
15
–2
AVDD = +15V
AVSS = –15V
VREFP = +10V
VREFN = –10V
TA = 25°C
DATA = 0x000
10
–4
IOUT (µA)
GAIN (dB)
5
–6
–8
0
–5
–10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–20
–15
–10
5
10
15
10
Figure 23. IOUT vs. VOUT (VSUPPLY = ±15 V)
8
25
AVDD = 15V
AVSS = 0V
VREFP = 10V
VREFN = 0V
TA = 25°C
DATA = 0x800
IDD
6
20
AVDD = +15V
AVSS = –15V
15
IOUT (µA)
2
0
10
5
–2
0
–4
ISS
–5
–6
–8
–35
–15
5
25
45
65
TEMPERATURE (°C)
85
06442-045
POWER SUPPLY CURRENT (mA)
0
VOUT (V)
Figure 20. Small Signal Response
4
–5
06442-040
–16
10
–15
06442-041
–14
–10
06442-036
–12
AVDD = +15V
AVSS = –15V
VREFP = 0V ± 100mV
VREFN = –10V
DATA BITS = +5V
TA = 25°C
Figure 21. Power Supply Current vs. Temperature
–10
0
1
2
3
4
5
6
7
8
VOUT (V)
Figure 24. IOUT vs. VOUT (VSUPPLY = +15 V)
Rev. C | Page 12 of 20
9
Data Sheet
AD5725
1.0
VREFP = +10V
VREFN = –10V
TA = 25°C
BW = 100kHz
0x800 → 0x7FF (±15V SUPPLY)
0x7FF → 0x800 (±15V SUPPLY)
0x800 → 0x7FF (±5V SUPPLY)
0x7FF → 0x800 (±5V SUPPLY)
0.8
GLITCH AMPLITUDE (V)
AVDD = +15V
AVSS = –15V
1
0.6
0.4
0.2
0
M 2s
A CH1
0V
–0.4
0
100
200
300
400
500
600
700
TIME (ns)
Figure 26. Output Glitch
Figure 25. Broadband Noise
Rev. C | Page 13 of 20
800
900
1000
06442-043
CH1 50µV
06442-046
–0.2
AD5725
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 16.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 17.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5725 is
monotonic over its full operating temperature range.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally, the output should be
VREFP − 1 LSB. Full-scale error is expressed in LSBs. A plot of
full-scale error vs. temperature can be seen in Figure 11.
Full-Scale Error TC
Full-scale error TC is a measure of the change in full-scale error
with a change in temperature. Full-scale error TC is expressed
in ppm FSR/°C.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when
0x0000 (straight binary coding) is loaded to the DAC register.
Ideally, the output voltage should be VREFN. A plot of zero-scale
error vs. temperature can be seen in Figure 12.
Zero-Scale Error TC
Zero-scale error TC is a measure of the change in zero-scale
error with a change in temperature. Zero-scale error TC is
expressed in ppm FSR/°C.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
change.
Slew Rate
The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltageoutput DAC is usually limited by the slew rate of the amplifier
used at its output. Slew rate is measured from 10% to 90% of the
output signal and is given in V/µs.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
It is specified in nV-sec and measured with a full-scale code
change on the data bus.
Power Supply Sensitivity
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage.
Analog Crosstalk
Analog crosstalk is the dc change in the output level of one
DAC in response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC while
monitoring another DAC. It is expressed in dB.
Rev. C | Page 14 of 20
Data Sheet
AD5725
THEORY OF OPERATION
The AD5725 is a quad voltage output, 12-bit parallel input DAC
featuring a 12-bit data bus with readback capability. The AD5725
operates from single or dual supplies ranging from +5 V up to
±15 V. The output voltage range is set by the reference voltages
applied at the VREFP and VREFN pins.
DAC ARCHITECTURE
Each of the four DACs is a voltage switched, high impedance
(50 kΩ), R-2R ladder configuration. Each 2R resistor is driven
by a pair of switches that connect the resistor to either VREFH
or VREFL.
OUTPUT AMPLIFIERS
The output amplifiers are capable of generating both unipolar
and bipolar output voltages. They are capable of driving a load
of 2 kΩ in parallel with 500 pF to DGND. The source and sink
capabilities of the output amplifiers can be seen in Figure 23
and Figure 24. The slew rate is 2.2 V/µs with a full-scale settling
time of 10 µs. The amplifiers are short-circuit protected.
Careful attention to grounding is important for accurate
operation of the AD5725. With four outputs and two references
there is potential for ground loops. Since the AD5725 has no
analog ground, the ground must be specified with respect to the
reference.
REFERENCE INPUTS
All four DACs share common positive reference (VREFP) and
negative reference (VREFN) inputs. The voltages applied to these
reference inputs set the output high and low voltage limits on all
four of the DACs. Each reference input has voltage restrictions
with respect to the other reference and to the power supplies.
VREFN can be any voltage between AVSS and VREFP − 2.5 V and
VREFP can be any value between AVDD – 2.5 V and
VREFN + 2.5 V. Note that because of these restrictions, the
AD5725 references cannot be inverted (VREFN cannot be
greater than VREFP).
It is important to note that the AD5725 VREFP input both sinks
and sources current. Also, the input current of both VREFP and
VREFN are code dependent. Many references have limited current
sinking capability and must be buffered with an amplifier to
drive VREFP. The VREFN reference input has no such special
requirements.
PARALLEL INTERFACE
See Table 7 for the digital control logic truth table. The parallel
interface consists of a 12-bit bidirectional data bus, two register
select inputs, A0 and A1, a R/W input, a chip select (CS), and a
load DAC (LDAC) input. Control of the DACs and bus
direction is determined by these inputs as shown in Table 7.
Digital data bits are labeled with the MSB defined as Data Bit 11
and the LSB as Data Bit 0. All digital pins are TTL/CMOS
compatible.
The register select inputs A0 and A1 select individual DAC
Register A (Binary Code 00) through Register D (Binary Code 11).
Decoding of the registers is enabled by the CS input. When CS
is high, no decoding takes place, and neither the writing nor the
reading of the input registers is enabled. The loading of the
second bank of registers is controlled by the asynchronous
LDAC input. By taking LDAC low while CS is high, all output
registers can be updated simultaneously. Note that the tLDW
required pulse width for updating all DACs is a minimum of
10 ns. The R/W input, when enabled by CS, controls the writing
to and reading from the input register.
DATA CODING
The AD5725 uses binary coding. The output voltage can be
calculated as follows:
VOUT = VREFN +
(VREFP
− VREFN ) × D
4096
where D is the digital code in decimal.
CLR
The CLR function can be used either at power-up or at any time
during the DACs operation. The CLR function is independent
of CS. This pin is active low and sets the DAC registers to either
midscale code (0x800) for the AD5725 or zero code (0x000) for
the AD5725-1. The CLR to midscale code is most useful when
the DAC is configured for bipolar references and an output of
0 V is desired.
It is recommended that the reference inputs be bypassed with
0.2 µF capacitors when operating with ±10 V references. This
limits the reference bandwidth.
Rev. C | Page 15 of 20
AD5725
Data Sheet
Table 7. AD5725 Logic Truth Table
A1
A0
R/W
CS
CLR
LDAC
INPUT REG
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
X
X
X
X
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
X
X
X
X
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
X
X
X
X
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
High
X
High
High
High
High
High
High
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
High
High
High
High
High
High
High
High
Low
High
X
X
Write
Write
Transparent
Write
Write
Transparent
Write
Write
Transparent
Write
Write
Transparent
Write
Hold
Write Input
Write
Hold
Write Input
Write
Hold
Write Input
Write
Hold
Write Input
Read
Hold
Read Input
Read
Hold
Read Input
Read
Hold
Read Input
Read
Hold
Read Input
Hold
Update all DAC registers
Hold
Hold
Hold
All Registers set to mid/zero scale
All Registers latched to mid/zero scale
Rev. C | Page 16 of 20
DAC REG
MODE
DAC
A
B
C
D
A
B
C
D
A
B
C
D
All
All
All
All
Data Sheet
AD5725
POWER SUPPLIES
Power supplies required are AVSS, AVDD, and VL. The AVSS
supply can be set between −15 V and 0 V. AVDD is the positive
supply; its operating range is between +5 V and +15 V.
VL is the digital output supply voltage for the readback function.
It is normally connected to +5 V. This pin is a logic reference
input only. It does not supply current to the device. If the readback
function is not used, VL can be left open-circuit. While VL does
not supply current to the AD5725, it does supply current to the
digital outputs when the readback function is used.
REFERENCE CONFIGURATION
Output voltage ranges can be configured as either unipolar or
bipolar, and within these choices, a wide variety of options
exists. The unipolar configuration can be either a positive or a
negative voltage output, and the bipolar configuration can be
either symmetrical or nonsymmetrical.
+15V
+15V
+
0.1µF
INPUT
VREFP
OP1177
OUTPUT
0.2µF
ADR01
TRIM
AVDD
10kΩ
Unipolar positive full-scale operation can usually be set with a
reference with the correct output voltage. This is preferable to
using a reference and dividing down to the required value. For a
10 V full-scale output, the circuit can be configured as shown in
Figure 29. In this configuration, the full-scale value is set first by
adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V.
VREFN
AVSS
+10V OPERATION
06442-007
0.1µF
10µF
The 0.2 µF bypass capacitors shown at the reference inputs in
Figure 28 should be used whenever ±10 V references are used.
Applications with single references or references to ±5 V may
not require the 0.2 µF bypassing. The 6.2 Ω resistor in series
with the output of the reference amplifier is to keep the amplifier
from oscillating with the capacitive load. We have found that
this is large enough to stabilize this circuit. Larger resistor
values are acceptable, provided that the drop across the resistor
does not exceed a VBE. Assuming a minimum VBE of 0.6 V and a
maximum current of 2.75 mA, the resistor should be under
200 Ω for the loading of a single AD5725.
Using two separate references is not recommended. Having two
references can cause different drifts with time and temperature,
whereas with a single reference, most drifts will track.
10µF
AD5725
–15V
Figure 28 (Symmetrical Bipolar Operation) shows the AD5725
configured for ±10 V operation. See the AD688 data sheet for a
full explanation of reference operation. Adjustments may not be
required for many applications since the AD688 is a very high
accuracy reference. However, if additional adjustments are
required, adjust the AD5725 full scale first. Begin by loading the
digital full-scale code (0xFFF). Then, adjust the gain adjust
potentiometer to attain a DAC output voltage of 9.9976 V.
Then, adjust the balance adjust to set the mid-scale output
voltage to 0.000 V.
Figure 27. Unipolar +10 V Operation
+15V
39kΩ
+15V
6
4
0.1µF
3
1
12
AVDD
10µF
VREFP
0.2µF
AD688 FOR ±10V
AD588 FOR ±5V
5
AD5725
14
GAIN
100kΩ
15
6.2Ω
VREFN
0.2µF
8
13
AVSS
7
0.1µF
1µF
–15V
±5 OR ±10V OPERATION
10µF
06442-008
BALANCE
100kΩ
6.2Ω
Figure 28. Symmetrical Bipolar Operation
Rev. C | Page 17 of 20
AD5725
Data Sheet
Figure 29 shows the AD5725 configured for −10 V to 0 V
operation. An ADR01 and OP1177 are configured to produce a
−10 V output, which is connected directly to VREFP for the
reference voltage.
+15V
U1
+15V
10µF
VOUT
ADR01
AVDD
VREFP
TEMP
TRIM
GND
AD5725
For operation with a +5 V supply, the reference voltage should
be set between +1.0 V and +2.5 V for optimum linearity. Figure 30
shows an ADR03 used to supply a +2.5 V reference voltage. The
headroom of the reference and DAC are both sufficient to support
a +5 V supply with ±5 V tolerance. AVDD and VL should be
connected to the same supply. Separate bypassing to each pin
should be used.
+5V
+15V
U2
10µF
V+
VREFN
AVSS
0.2µF
V–
INPUT
0.1µF
VREFP
OUTPUT
0V TO –10V OPERATION
–15V
06442-009
–15V
+15V
OP1177
0.1µF
10µF
0.01µF
ADR03
AVDD
10µF
0.2µF
TRIM
AD5725
10kΩ
GND
Figure 29. Unipolar −10 V Operation
VREFN
AVSS
0V TO 2.5V OPERATION
SINGLE 5V SUPPLY
0.1µF
–15V
Figure 30. +5 V Single-Supply Operation
Rev. C | Page 18 of 20
10µF
06442-010
0.1µF
VIN
SINGLE +5 V SUPPLY OPERATION
Data Sheet
AD5725
OUTLINE DIMENSIONS
10.50
10.20
9.90
15
28
5.60
5.30
5.00
1
8.20
7.80
7.40
14
0.65 BSC
SEATING
PLANE
8°
4°
0°
COMPLIANT TO JEDEC STANDARDS MO-150-AH
0.95
0.75
0.55
060106-A
0.38
0.22
0.05 MIN
COPLANARITY
0.10
0.25
0.09
1.85
1.75
1.65
2.00 MAX
Figure 31. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5725ARSZ-1500RL7
AD5725ARSZ-1REEL
AD5725ARSZ-500RL7
AD5725ARSZ-REEL
AD5725BRSZ-1500RL7
AD5725BRSZ-1REEL
AD5725BRSZ-500RL7
AD5725BRSZ-REEL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
INL
(LSB)
1
1
1
1
0.5
0.5
0.5
0.5
Clear Action
Clear to zero scale
Clear to zero scale
Clear to midscale
Clear to midscale
Clear to zero scale
Clear to zero scale
Clear to midscale
Clear to midscale
Z = RoHS Compliant Part.
Rev. C | Page 19 of 20
Package Description
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP]
Package
Option
RS-28
RS-28
RS-28
RS-28
RS-28
RS-28
RS-28
RS-28
AD5725
Data Sheet
NOTES
©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06442-0-8/13(C)
Rev. C | Page 20 of 20
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