Single-Channel, 16-Bit Current and Voltage DAC with
Dynamic Power Control and HART Connectivity
Data Sheet
AD5753
FEATURES
GENERAL DESCRIPTION
16-bit resolution and monotonicity
Positive and negative DPC for thermal management
Current or voltage output available on a single terminal
Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA,
0 mA to 24 mA, ±20 mA, ±24 mA, and −1 mA to +22 mA
Voltage output ranges (with 20% overrange): 0 V to 5 V,
0 V to 10 V, ±5 V, and ±10 V
User programmable offset and gain
Advanced on-chip diagnostics, including a 12-bit ADC
2 external ADC input pins
On-chip reference
Robust architecture, including output fault protection
−40°C to +115°C temperature range
40-lead, 6 mm × 6 mm LFCSP package
The AD5753 is a single-channel, voltage and current output
digital-to-analog converter (DAC) that operates with a power
supply range from a minimum of −33 V on AVSS to a maximum of
+33 V on AVDD1 with a maximum operating voltage of 60 V
between the two rails. On-chip dynamic power control (DPC)
minimizes package power dissipation. This minimization is
achieved by using buck dc-to-dc converters optimized for
minimum on-chip power dissipation to regulate the voltage
(VDPC+ and VDPC−) that is sent to the VIOUT output driver circuitry
from the ±5 V to ±27 V supply voltage. The CHART pin enables a
Highway Addressable Remote Transducer® (HART) signal to be
coupled on the current output.
APPLICATIONS
Process control
Actuator control
Channel isolated analog outputs
Programmable logic controller (PLC) and distributed control
systems (DCS) applications
HART network connectivity
The AD5753 uses a versatile, 4-wire, serial peripheral interface
(SPI) that operates at clock rates of up to 50 MHz and is
compatible with standard SPI, QSPI™, MICROWIRE™, digital
signal processor (DSP), and microcontroller interface standards.
The interface features an optional SPI cyclic redundancy check
(CRC) and a watchdog timer (WDT). The AD5753 offers
improved diagnostic features from earlier versions of similar
DACs, such as output current monitoring and an integrated, 12-bit
diagnostic analog-to-digital converter (ADC). The inclusion of
a line protector on the VIOUT, +VSENSE, and −VSENSE pins provides
additional robustness.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Range of advanced diagnostic features, including
integrated ADC with two external input pins.
DPC, using integrated buck dc-to-dc converters for
thermal management, which enables higher channel count
in small size module housing.
Programmable power control (PPC) mode to enable faster
than DPC settling time (15 μs typical).
Highly robust with output protection from miswire events
(±38 V).
HART compliant.
COMPANION PRODUCTS
Product Family: AD5758, AD5755-1, AD5422
HART Modems: AD5700, AD5700-1
External References: ADR431, ADR3425, ADR4525
Digital Isolators: ADuM142D, ADuM141D
Power: LT8300, ADP2360, ADM6339, ADP1031
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5753
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage Output ............................................................................ 37
Applications ....................................................................................... 1
Fault Protection .......................................................................... 37
General Description ......................................................................... 1
Current Output ........................................................................... 38
Product Highlights ........................................................................... 1
HART Connectivity ................................................................... 38
Companion Products ....................................................................... 1
Digital Slew Rate Control .......................................................... 38
Revision History ............................................................................... 2
Address Pins ................................................................................ 39
Functional Block Diagram .............................................................. 3
WDT ............................................................................................ 40
Specifications..................................................................................... 4
User Digital Offset and Gain Control...................................... 40
AC Performance Characteristics .............................................. 10
DAC Output Update and Data Integrity Diagnostics ........... 41
Timing Characteristics .............................................................. 11
GPIO Pins .................................................................................... 42
Absolute Maximum Ratings.......................................................... 15
Use of Key Codes ........................................................................ 42
Thermal Resistance .................................................................... 15
Software Reset ............................................................................. 42
ESD Caution ................................................................................ 15
Calibration Memory CRC ......................................................... 42
Pin Configuration and Function Descriptions ........................... 16
Internal Oscillator Diagnostics ................................................. 43
Typical Performance Characteristics ........................................... 18
Sticky Diagnostic Results Bits ................................................... 43
Voltage Output ............................................................................ 18
Background Supply and Temperature Monitoring ................ 43
Current Outputs ......................................................................... 22
Output Fault ................................................................................ 43
DC-to-DC Block......................................................................... 27
ADC Monitoring ........................................................................ 44
Reference ..................................................................................... 28
Register Map ................................................................................... 49
General ......................................................................................... 29
Writing to Registers ................................................................... 49
Terminology .................................................................................... 30
Reading from Registers ............................................................. 50
Theory of Operation ...................................................................... 32
Programming Sequence to Enable the Output ...................... 53
DAC Architecture ....................................................................... 32
Register Details ........................................................................... 55
Serial Interface ............................................................................ 32
Applications Information .............................................................. 71
Power-On State of the AD5753 ................................................ 33
Example Module Power Calculation ....................................... 71
Power Supply Considerations ................................................... 33
Outline Dimensions ....................................................................... 73
Device Features and Diagnostics .................................................. 35
Ordering Guide .......................................................................... 73
Power Dissipation Control ........................................................ 35
Interdie 3-Wire Interface ........................................................... 36
REVISION HISTORY
5/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 73
Data Sheet
AD5753
FUNCTIONAL BLOCK DIAGRAM
AVDD2
VLDO
VLOGIC
DGND
CLKOUT
AD0
AD1
RESET
LDAC
SCLK
SDI
SYNC
SDO
AGND
NIC
MCLK
10MHz
POWER
MANAGEMENT
BLOCK
POWER-ON
RESET
AVDD1
VDPC+
CALIBRATION
MEMORY
PGND1
DC-TO-DC
CONVERTER
DIGITAL
BLOCK
3-WIRE INTERFACE
DATA AND
CONTROL
REGISTERS
WATCHDOG
TIMER
16
DAC
REG
VDPC+
16
16-BIT
DAC
-
IOUT
RANGE
SCALING
USER GAIN
USER OFFSET
STATUS
REGISTER
IOUT
RSET
RB
RA
VX
VDPC–
CHART
HART_EN
VDPC+
FAULT
REFIN
SW+
AD5753
+VSENSE
VOUT
RANGE
SCALING
REFERENCE
BUFFERS
VOUT
VIOUT
–VSENSE
REFOUT
VREF
VDPC–
REFGND
GPIO_0
GPIO_1
CCOMP
TEMPERATURE
SENSOR
12-BIT
ADC
ANALOG
DIAGNOSTICS
GPIO_2
DC-TO-DC
CONVERTER
ADC2
AVSS
SW–
VDPC–
PGND2
17285-002
ADC1
Figure 1.
Rev. 0 | Page 3 of 72
AD5753
Data Sheet
SPECIFICATIONS
AVDD1 = VDPC+ = 15 V, dc-to-dc converter disabled, AVDD2 = 5 V, AVSS = VDPC− = −15 V, VLOGIC = 1.71 V to 5.5 V, AGND = DGND =
REFGND = PGND1 = 0 V, REFIN = 2.5 V external, voltage output: load resistance (RLOAD) = 1 kΩ, load capacitor (CLOAD) = 220 pF,
current output: RLOAD = 300 Ω. All specifications at TA = −40°C to +115°C, TJ (junction temperature) < 125°C, unless otherwise noted.
Table 1.
Parameter
OUTPUT VOLTAGE (VOUT)
Output Voltage Overranges
Output Voltage Offset Ranges
Resolution
VOLTAGE OUTPUT ACCURACY
Total Unadjusted Error (TUE)
TUE Long-Term Stability 1
Output Drift
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
Zero-Scale Error Temperature
Coefficient (TC) 2
Bipolar Zero Error
Bipolar Zero Error TC2
Offset Error
Offset Error TC2
Gain Error
Gain Error TC2
Full-Scale Error
Full-Scale Error TC2
VOLTAGE OUTPUT
CHARACTERISTICS
Headroom
Min
0
0
−5
−10
0
0
−6
−12
−0.3
−0.4
16
Typ
Max
5
10
+5
+10
6
12
+6
+12
+5.7
+11.6
Unit
V
V
V
V
V
V
V
V
V
V
Bits
Test Conditions/Comments
Trimmed VOUT ranges
Untrimmed overranges
Untrimmed negatively offset ranges
Loaded and unloaded, accuracy specifications
refer to trimmed VOUT ranges only, unless
otherwise noted
−0.05
−0.01
+0.05
+0.01
15
0.35
−0.006
−1
−0.02
±5 V, ±10 V
±5 V, ±10 V
2
V
Footroom
2
V
Minimum voltage required between VIOUT and
VDPC+ supply
Minimum voltage required between VIOUT and
VDPC− supply
Short-Circuit Current
Load2
Capacitive Load Stability2
1
−0.022
−0.022
−0.022
+0.001
±0.4
±0.002
±0.3
±0.001
±0.6
±0.001
±0.5
+0.017
TA = 25°C
Drift after 1000 hours, TJ = 150°C
Output drift
All ranges
Guaranteed monotonic, all ranges
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
DC Output Impedance
DC Power Supply Rejection
Ratio (PSRR)
VOUT and −VSENSE CommonMode Rejection Ratio
(CMRR)
−0.017
±0.002
±0.3
1.5
+0.006
+1
+0.02
% FSR
% FSR
ppm FSR
ppm FSR/°C
% FSR
LSB
% FSR
ppm FSR/°C
+0.022
+0.022
+0.022
16
10
2
mA
kΩ
nF
µF
7
10
mΩ
µV/V
10
µV/V
Rev. 0 | Page 4 of 72
For specified performance
External compensation capacitor of 220 pF
connected
Error in VOUT voltage due to changes in −VSENSE
voltage
Data Sheet
Parameter
OUTPUT CURRENT (IOUT)
Resolution
CURRENT OUTPUT ACCURACY
(EXTERNAL RSET) 3
Unipolar Ranges
TUE
TUE Long-Term Stability
Output Drift
INL
DNL
Zero-Scale Error
Zero-Scale TC2
Offset Error
Offset Error TC2
Gain Error
Gain Error TC2
Full-Scale Error
Full-Scale Error TC2
Bipolar Ranges
TUE
TUE Long-Term Stability1
Output Drift
INL
DNL
Zero-Scale Error
Zero-Scale TC2
Bipolar Zero Error
Bipolar Zero Error TC2
Offset Error
Offset Error TC2
Gain Error
Gain Error TC2
Full-Scale Error
Full-Scale Error TC2
CURRENT OUTPUT ACCURACY
(INTERNAL RSET)
Unipolar Ranges
TUE
TUE Long-Term Stability1
Output Drift
INL
DNL
Zero-Scale Error
Zero-Scale TC2
Offset Error
AD5753
Min
0
0
4
−20
−24
−1
16
Typ
Max
24
20
20
+20
+24
+22
Unit
mA
mA
mA
mA
mA
mA
Bits
Test Conditions/Comments
Assumes ideal 13.7 kΩ resistor
4 mA to 20 mA, 0 mA to 20 mA, and 0 mA to
24 mA ranges
−0.05
−0.01
+0.05
+0.01
125
2
−0.007
−1
−0.03
−0.03
−0.05
−0.05
±0.002
±0.5
±0.001
±0.7
±0.002
±3
±0.002
±3
5
+0.007
+1
+0.03
+0.03
+0.05
+0.05
% FSR
% FSR
ppm FSR
ppm FSR/°C
% FSR
LSB
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
TA = 25°C
Drift after 1000 hours, TJ = 150°C
Guaranteed monotonic
±20 mA, ±24 mA, and −1 mA to +22 mA ranges
−0.06
−0.012
+0.06
+0.012
125
12
−0.013
−1
−0.04
−0.02
−0.04
−0.06
−0.06
±0.003
±0.5
±0.003
±0.4
±0.002
±0.6
±0.002
±3
±0.003
±3
15.5
+0.013
+1
+0.04
+0.02
+0.04
+0.06
+0.06
% FSR
% FSR
ppm FSR
ppm FSR/°C
% FSR
LSB
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
TA = 25°C
Drift after 1000 hours, TJ = 150°C
Guaranteed monotonic
4 mA to 20 mA, 0 mA to 20 mA, and 0 mA to
24 mA ranges
−0.12
+0.12
380
3
−0.01
−1
−0.04
−0.04
±0.001
±0.5
±0.001
6
+0.01
+1
+0.04
+0.04
% FSR
ppm FSR
ppm FSR/°C
% FSR
LSB
% FSR
ppm FSR/°C
% FSR
Rev. 0 | Page 5 of 72
Drift after 1000 hours, TJ = 150°C
Output drift
Guaranteed monotonic
AD5753
Parameter
Offset Error TC2
Gain Error
Gain Error TC2
Full-Scale Error
Full-Scale Error TC2
Bipolar Ranges
TUE
TUE Long-Term Stability1
Output Drift
INL
DNL
Zero-Scale Error
Zero-Scale TC2
Bipolar Zero Error
Bipolar Zero Error TC2
Offset Error
Offset Error TC2
Gain Error
Gain Error TC2
Full-Scale Error
Full-Scale Error TC2
CURRENT OUTPUT
CHARACTERISTICS
Headroom
Footroom
Data Sheet
Min
−0.1
−0.12
Typ
±1
±0.003
±3
±0.003
±3
Reference TC2
Output Noise (0.1 Hz to
10 Hz)2
Noise Spectral Density2
Capacitive Load2
Load Current
Short-Circuit Current
Line Regulation
Load Regulation
Thermal Hysteresis2
+0.1
+0.12
Unit
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
Test Conditions/Comments
±20 mA, ±24 mA, and −1 mA to +22 mA ranges
−0.12
+0.12
380
3
−0.02
−1
−0.06
−0.02
−0.06
−0.12
−0.12
±0.001
±2
±0.002
±0.3
±0.001
±1
±0.003
±3
±0.003
±3
6
+0.02
+1
+0.06
+0.02
+0.06
+0.12
+0.12
% FSR
ppm FSR
ppm FSR/°C
% FSR
LSB
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
% FSR
ppm FSR/°C
2.3
V
2.3 or 0
V
Resistive Load2
Output Impedance
DC PSRR
REFERENCE INPUT/OUTPUT
Reference Input
Reference Input Voltage 4
DC Input Impedance
Reference Output
Output Voltage
Max
1000
Ω
Drift after 1000 hours, TJ = 150°C
Output drift
Guaranteed monotonic
Minimum voltage required between VIOUT and
VDPC+ supply
Minimum voltage required between VIOUT and
VDPC− supply; unipolar ranges do not require any
footroom and takes on the 0 value
The dc-to-dc converter is characterized with
a maximum load of 1 kΩ, chosen such that
headroom and footroom compliance is not
exceeded
Midscale output
100
0.1
MΩ
µA/V
2.5
120
V
MΩ
For specified performance
55
2.495
2.5
2.505
V
TA = 25°C (including drift after 1000 hours at TJ =
150°C)
+10
ppm/°C
µV p-p
−10
7
80
1000
3
5
1
140
150
nV/√Hz
nF
mA
mA
ppm/V
ppm/mA
ppm
Rev. 0 | Page 6 of 72
At 10 kHz
Data Sheet
Parameter
VLDO OUTPUT
Output Voltage
Output Voltage TC2
Output Voltage Accuracy
Externally Available Current
Short-Circuit Current
Load Regulation
Capacitive Load
DC-TO-DC
Start-Up Time
Switch
Peak Current Limit2
Oscillator
Oscillator Frequency (fSW)
Minimum Duty Cycle
Current Output DPC Mode
VDPC+ and VDPC− Voltage
Range
AD5753
Min
VDPC+ and VDPC− Voltage
Accuracy
Voltage Output DPC Mode
VDPC+ and VDPC− Voltage
Range
VDPC+ and VDPC− Voltage
Accuracy
VIOUT LINE PROTECTOR
On Resistance, RON
Overvoltage Response Time,
tRESPONSE
Overvoltage Leakage Current
Max
Unit
Test Conditions/Comments
55
0.8
0.1
V
ppm/°C
%
mA
mA
mV/mA
µF
Recommended operation
1.25
ms
3.3
30
−2
+2
30
150
400
500
5
±4.95
mA
V
2.5
V
±5
±25.677
V
−500
+500
mV
±25
V
+250
mV
2.3
±5
±15
−250
User programmable in 50 mA steps via the
DCDC_CONFIG2 register
kHz
%
±27
VDPC+ and VDPC− Headroom
Current Output PPC Mode
VDPC+ and VDPC− Voltage
Range
Typ
Current output dynamic power control mode
Assuming sufficient supply margin between
AVDD1 and VDPC+, and AVSS and VDPC−; see the
Power Dissipation Control section for further
details; maximum operating range of
|VDPC+ to VDPC−| = 50 V
Typical voltage headroom between VIOUT and
VDPC+ or VDPC−; only applicable when dc-to-dc
converter is in regulation, that is, when the load
is sufficiently high
Programmable power control mode
Assuming sufficient supply margin between
(AVDD1 and VDPC+) and (AVSS and VDPC−); see the
Power Dissipation Control section for further
details; maximum operating range of |VDPC+ to
VDPC−| = 50 V
Only applicable when dc-to-dc is operating in
regulation, that is, when the load is sufficiently
high
Voltage output dynamic power control mode
5 V = −VSENSE (MIN) + 15 V; 25 V = −VSENSE (MAX) + 15 V;
where VSENSE (MIN) = −10 V and VSENSE (MAX) = +10 V;
assuming sufficient supply margin between AVDD1
and VDPC+, and AVSS and VDPC−; see the Power
Dissipation Control section for further details;
maximum operating range of |VDPC+ to VDPC−| = 50 V
Only applicable when dc-to-dc is operating in
regulation, that is, when the is load sufficiently
high
12
250
Ω
ns
TA = 25°C
±100
µA
Line protector fault detect block sinks current
for a positive fault and sources current for a
negative fault
Rev. 0 | Page 7 of 72
AD5753
Parameter
ADC
Resolution
Input Voltage Range
ADC1 Pin
ADC2 Pin
Total Error
ADC1 Pin
ADC2 Pin
All other ADC Inputs
Conversion Time2
GENERAL-PURPOSE
INPUT/OUTPUT OUTPUT
ISOURCE or ISINK5
Output Voltage
Low, VOL
High, VOH
GPIO INPUT
Input Voltage
High, VIH
Low, VIL
Input Current
Input Capacitance
DIGITAL OUTPUTS
SDO
Output Voltage
Low, VOL
High, VOH
High Impedance Leakage
Current
High Impedance Output
Capacitance2
FAULT
Output Voltage
Low, VOL
Data Sheet
Min
Typ
Max
12
DIGITAL INPUTS
Input Voltage
3 V ≤ VLOGIC ≤ 5.5 V
High, VIH
Low, VIL
1.71 V ≤ VLOGIC < 3 V
High, VIH
Low, VIL
Input Current
Pin Capacitance2
Test Conditions/Comments
Bits
0
−0.5
0
0
−15
0.5
+0.5
1.25
2.5
+15
V
V
V
V
V
ADC_IP_SELECT = 10000
ADC_IP_SELECT = 10010, AVSS must be ≤ −1 V
ADC_IP_SELECT = 01111
ADC_IP_SELECT = 10001
−0.25
−0.3
−0.5
−0.5
+0.25
+0.3
+0.5
+0.5
2.5 V input range
1.25 V input range
0 V to 0.5 V and ±0.5 V input ranges
±0.3
100
% FSR
% FSR
% FSR
% FSR
% FSR
μs
VLOGIC/1 kΩ
mA
Assume 1 kΩ is connected to the GPIO pin
V
V
ISOURCE = 2 mA
ISOURCE = 2 mA
0.4
VLOGIC − 0.2
0.7 × VLOGIC
0.3 × VLOGIC
1.35
2.6
0.4
VLOGIC − 0.2
−1
+1
2.2
0.4
VLOGIC −
0.05
0.7 × VLOGIC
2.4
V
V
μA
pF
V
V
μA
V
V
V
0.3 × VLOGIC
V
V
0.2 × VLOGIC
+1.5
V
V
μA
0.8 × VLOGIC
−1.5
Table 18 lists all ADC input nodes
Sinking = 200 μA
Sourcing = 200 μA
pF
0.6
High, VOH
Unit
pF
Rev. 0 | Page 8 of 72
10 kΩ pull-up resistor to VLOGIC
At 2.5 mA
10 kΩ pull-up resistor to VLOGIC
Per pin, internal pull-down on SCLK, SDI, RESET,
and LDAC; internal pull-up on SYNC
Per pin
Data Sheet
Parameter
POWER REQUIREMENTS
Supply Voltages
AVDD1 6
AVDD2
AVSS6
VLOGIC
Supply Quiescent Currents6
AIDD1 7
AD5753
Min
Max
Unit
Test Conditions/Comments
7
5
−33
33
33
0
V
V
V
Maximum operating range of |AVDD1 to AVSS| = 60 V
Maximum operating range of |AVDD2 to AVSS| = 50 V
Maximum operating range of |AVDD1 to AVSS| = 60 V;
for bipolar output ranges, VOUT or IOUT headroom
must be obeyed when calculating AVSS
maximum; for unipolar current output ranges,
AVSS maximum = 0 V; for unipolar voltage output
ranges, AVSS maximum = −2.5 V
1.71
5.5
V
0.05
0.11
mA
0.05
0.11
mA
3.3
3.6
mA
2.9
3.1
mA
AIDD27
AISS7
−0.11
−0.11
−0.05
0.05
−1.3
−0.2
−3.1
1.0
0.8
2.3
−1.0
−0.15
−2.3
ILOGIC7
IDPC+7
IDPC−7
Typ
0.01
1.3
1
3.1
mA
mA
mA
mA
mA
mA
mA
mA
mA
Power Dissipation
120
mW
145
mW
180
mW
200
mW
105
Quiescent current, assuming no load current
Voltage output mode, dc-to-dc converter
enabled but not active
Current output mode, dc-to-dc converter
enabled but not active
Voltage output mode, dc-to-dc converter
enabled but not active
Current output mode, dc-to-dc converter
enabled but not active
Voltage output mode
Current output mode
VIH = VLOGIC, VIL = DGND
Voltage output mode
Unipolar current output mode
Bipolar current output mode
Voltage output mode
Unipolar current output mode
Bipolar current output mode
Power dissipation assuming an ideal power
supply and excluding external load power
dissipation, current output DPC mode, negative
rail DPC disabled, 0 mA to 20 mA range; see the
Example Module Power Calculation section for
calculation methodology
AVDD1 = 24 V, AVDD2 = 5 V, AVSS = −15 V, RLOAD = 1 kΩ,
IOUT = 20 mA
AVDD1 = 24 V, AVDD2 = 5 V, AVSS = −15 V, RLOAD = 0 Ω,
IOUT = 20 mA
AVDD1 = AVDD2 = 24 V, AVSS = −15 V, RLOAD = 1 kΩ,
IOUT = 20 mA
AVDD1 = AVDD2 = 24 V, AVSS = −15 V, RLOAD = 0 Ω,
IOUT = 20 mA
AVDD1 = 24 V, AVDD2 = 5 V, AVSS = −24 V, RLOAD = 1 kΩ,
IOUT = −20 mA, negative rail DPC enabled
The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
Guaranteed by design and characterization; not production tested.
3
See the Current Output section for more information about the internal and external RSET resistors.
4
The AD5753 is factory calibrated with an external 2.5 V reference connected to REFIN.
5
Where ISOURCE is the current source and ISINK is the current sink.
6
Production tested to AVDD1 maximum = 30 V and AVSS minimum = −30 V.
7
Where AIDD1 is the current on the AVDD1 supply, AIDD2 is the current on the AVDD2 supply, AISS is the current on the AVSS supply, ILOGIC is the current on the VLOGIC supply,
IDPC+ and IDPC− are the currents on the VDPC+ and VDPC− supplies, respectively.
1
2
Rev. 0 | Page 9 of 72
AD5753
Data Sheet
AC PERFORMANCE CHARACTERISTICS
AVDD1 = VDPC+ = 15 V, dc-to-dc converter disabled, AVDD2 = 5 V, AVSS = VDPC− = −15 V, VLOGIC = 1.71 V to 5.5 V, AGND = DGND =
REFGND = PGND1 = 0 V, REFIN = 2.5 V external, voltage output: RLOAD = 1 kΩ, CLOAD = 220 pF, current output: RLOAD = 300 Ω. All
specifications at TA = −40°C to +115°C, TJ < 125°C, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE 1
Voltage Output
Output Voltage Settling Time
Min
Typ
6
12
Slew Rate
Power-On Glitch Energy
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Feedthrough
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
Output Noise Spectral Density
AC PSRR
Max
20
20
15
Unit
Test Conditions/Comments
Output voltage settling time specifications also apply to the
enabled dc-to-dc converter
5 V step to ±0.03% FSR, 0 V to 5 V range
10 V step to ±0.03% FSR, 0 V to 10 V range
100 mV step to 1 LSB (16-bit LSB), 0 V to 10 V range
0 V to 10 V range, digital slew rate control disabled
3
25
5
25
2
0.2
µs
µs
µs
V/µs
nV-sec
nV-sec
mV
nV-sec
LSB p-p
185
70
nV/√Hz
dB
Measured at 10 kHz, midscale output, 0 V to 10 V range
200 mV, 50 Hz and 60 Hz sine wave superimposed on power
supply voltage
15
15
µs
µs
200
µs
0.2
LSB p-p
To 0.1% FSR (0 mA to 24 mA), dc-to-dc converter disabled
PPC mode, dc-to-dc converter enabled, dc-to-dc current limit =
150 mA
DPC mode, dc-to-dc converter enabled; external inductor and
capacitor components as described in Table 10, dc-to-dc current
limit = 150 mA
16-bit LSB, 0 mA to 24 mA range
0.8
80
nA/√Hz
dB
16-bit LSB, 0 V to 10 V range
Current Output
Output Current Settling Time
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
Output Noise Spectral Density
AC PSRR
1
Measured at 10 kHz, midscale output, 0 mA to 24 mA range
200 mV, 50 Hz and 60 Hz sine wave superimposed on power
supply voltage
Guaranteed by design and characterization; not production tested.
Rev. 0 | Page 10 of 72
Data Sheet
AD5753
TIMING CHARACTERISTICS
AVDD1 = VDPC+ = 15 V, dc-to-dc converter disabled, AVDD2 = 5 V, AVSS = VDPC− = −15 V, VLOGIC = 1.71 V to 5.5 V, AGND = DGND =
REFGND = PGND1 = 0 V, REFIN = 2.5 V external, voltage output: RLOAD = 1 kΩ, CLOAD = 220 pF, current output: RLOAD = 300 Ω. All
specifications at TA = −40°C to +115°C, TJ < 125°C, unless otherwise noted. The units indicate the minimum or maximum time the
action takes to complete.
Table 3.
Parameter 1, 2, 3
t1
1.71 V ≤ VLOGIC < 3 V
33
120
16
60
16
60
10
3 V ≤ VLOGIC ≤ 5.5 V
20
66
10
33
10
33
10
Unit
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
33
33
ns minimum
10
500
10
500
ns minimum
ns minimum
1.5
500
1.5
500
µs minimum
µs minimum
5
6
750
1.5
250
600
5
6
750
1.5
250
600
ns minimum
ns minimum
ns minimum
µs minimum
ns minimum
ns maximum
2
2
µs maximum
See the AC Performance
Characteristics section
1.5
µs maximum
t14
See the AC Performance
Characteristics section
1.5
µs maximum
t15
t16
t17
5
40
100
5
28
100
µs minimum
ns maximum
µs minimum
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
1
2
3
Description
Serial clock input (SCLK) cycle time, write operation
SCLK cycle time, read operation
SCLK high time, write operation
SCLK high time, read operation
SCLK low time, write operation
SCLK low time, read operation
SYNC falling edge to SCLK falling edge setup time,
write operation
SYNC falling edge to SCLK falling edge setup time,
read operation
24th or 32nd SCLK falling edge to SYNC rising edge
SYNC high time (applies to all register writes outside
of those listed in this table)
SYNC high time (DAC_INPUT register write)
SYNC high time (DAC_CONFIG register write, where
the Range[3:0] bits change; see the Calibration
Memory CRC section for more timing information
Data setup time
Data hold time
LDAC falling edge to SYNC rising edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
LDAC falling edge to DAC output response time,
digital slew rate control disabled.
LDAC falling edge to DAC output response time,
digital slew rate control enabled.
DAC output settling time
SYNC rising edge to DAC output response time
(LDAC = 0)
RESET pulse width
SCLK rising edge to SDO valid
RESET rising edge to first SCLK falling edge after
SYNC falling edge (t17 does not appear in the timing
diagrams)
Guaranteed by design and characterization; not production tested.
All input signals are specified with tR = tF = 5 ns (10% to 90% of VLOGIC) and timed from a voltage level of 1.2 V. tR is rise time. tF is fall time.
See Figure 2, Figure 3, Figure 4, and Figure 5.
Rev. 0 | Page 11 of 72
AD5753
Data Sheet
Timing Diagrams
t1
SCLK
1
2
24
t3
t6
t2
t4
t5
SYNC
t8
t7
SDI
MSB
LSB
t11
t11
t10
LDAC
t9
t13
t12
VIOUT
LDAC = 0
t13
t14
VIOUT
17285-003
t15
RESET
Figure 2. Serial Interface Timing Diagram
SCLK
1
24
1
24
t6
SYNC
MSB
LSB
MSB
LSB
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
MSB
SDO
LSB
UNDEFINED
t16
Figure 3. Readback Timing Diagram
Rev. 0 | Page 12 of 72
SELECTED REGISTER DATA
CLOCKED OUT
17285-004
SDI
Data Sheet
AD5753
1
24 1
2
SCLK
SYNC
t8
t7
SDI
SDO
DISABLED
SDO
D23
D22
1
0
D21
D20
D19
D18
D17
FAULT
PIN
DIG
DIAG
ANA
DIAG
WDT
ADC
BUSY
STATUS
D16
ADC
CHN[4]
D11
D1
D0
ADC
ADC
ADC
ADC
CHN[0]
DATA[11]
DATA[1]
DATA[0]
SDO
DISABLED
EXTRA SCLK FALLING EDGES ARE RECEIVED AFTER THE 24TH (OR 32ND, IF CRC IS ENABLED) SCLK, BEFORE SYNC RETURNS HIGH, SDO CLOCKS OUT 0.
Figure 4. Autostatus Readback Timing Diagram
200µA
TO OUTPUT
PIN
IOL
VOH (MIN) OR
VOL (MAX)
CL
30pF
200µA
IOH
Figure 5. Load Circuit for the SDO Timing Diagram
Rev. 0 | Page 13 of 72
17285-006
1IF ANY
17285-005
t16
AD5753
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
±200 mA do not cause silicon controlled rectifier (SCR) latch-up.
Table 4.
Parameter
AVDD1 to AGND, DGND
AVSS to AGND, DGND
AVDD1 to AVSS
AVDD2, VDPC+ to AGND, DGND
AVDD2, VDPC+ to VDPC−
VDPC− to AGND, DGND
Rating
−0.3 V to +44 V
+0.3 V to −35 V
−0.3 V to +66 V
−0.3 V to +35 V
−0.3 V to +55 V
VLOGIC to DGND
Digital Inputs to DGND (SCLK,
SDI, SYNC, AD0, AD1, RESET,
LDAC)
Digital Outputs to DGND (FAULT,
SDO, CLKOUT)
GPIO_0, GPIO_1, and GPIO_2 to
AGND
REFIN, REFOUT, VLDO, CHART to
AGND
RA to AGND
RB to AGND
VIOUT to AGND
+VSENSE to AGND
−VSENSE to AGND
CCOMP to AGND
SW+ to AGND
−0.3 V to +6 V
−0.3 V to VLOGIC + 0.3 V or +6 V
(whichever voltage is less)
THERMAL RESISTANCE
+0.3 V to AVSS −0.3 V or −35 V
(whichever voltage is less)
−0.3 V to VLOGIC + 0.3 V or +6 V
(whichever voltage is less)
−0.3 V to VLOGIC + 0.3 V or +6 V
(whichever voltage is less)
−0.3 V to AVDD2 + 0.3 V or +6 V
(whichever voltage is less)
−0.3 V to +4.5 V
−0.3 V to +4.5 V
±38 V
±38 V
±38 V
AVSS − 0.3 V to VDPC+ + 0.3 V
−0.3 V to AVDD1 + 0.3 V or +33 V
(whichever voltage is less)
SW− to AGND
+0.3 V to AVSS − 0.3 V or −33 V
(whichever voltage is less)
AGND, DGND to REFGND
AGND, DGND to PGND1, PGND2
Industrial Operating
Temperature Range (TA)1
Storage Temperature Range
Junction Temperature
(TJ Maximum)
Power Dissipation
Lead Temperature
Soldering
Electrostatic Discharge (ESD)
Human Body Model2
Field Induced Charged
Device Model3
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−40°C to +115°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
θJA is the junction to ambient thermal resistance and ΨJT is the
junction to top of package thermal resistance.
Table 5. Thermal Resistance
Package Type
CP-40-151
1
θJA
38
ΨJT
0.5
Unit
°C/W
Test Condition 1: Thermal impedance simulated values are based on a
JEDEC 2S2P thermal test board with thermal vias. See JEDEC and JESD51.
ESD CAUTION
−65°C to +150°C
125°C
(TJ maximum − TA)/θJA
JEDEC industry standard
J-STD-020
±4 kV
±750 V
Power dissipated on the chip must be derated to keep the junction
temperature below 125°C.
2
As per ANSI/ESDA/JEDEC JS-001, all pins.
3
As per ANSI/ESDA/JEDEC JS-002, all pins.
1
Rev. 0 | Page 14 of 72
Data Sheet
AD5753
40
39
38
37
36
35
34
33
32
31
PGND1
VDPC+
ADC2
VIOUT
+VSENSE
CCOMP
–VSENSE
NIC
VDPC–
PGND2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
AD5753
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
SW–
AVSS
NIC
FAULT
AD0
AD1
SYNC
SDI
SCLK
CLKOUT
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. CONNECT THE EXPOSED PAD TO THE POTENTIAL
OF THE VDPC– PIN, OR, ALTERNATIVELY, THE
EXPOSED PAD CAN BE LEFT ELECTRICALLY
UNCONNECTED. IT IS RECOMMENDED THAT THE
PAD BE THERMALLY CONNECTED TO A COPPER
PLANE FOR ENHANCED THERMAL PERFORMANCE.
17285-007
REFOUT
VLDO
VLOGIC
SDO
DGND
RESET
GPIO_0
GPIO_1
GPIO_2
LDAC
11
12
13
14
15
16
17
18
19
20
SW+
AVDD1
AVDD2
ADC1
AGND
REFGND
RA
RB
CHART
REFIN
Figure 6. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
SW+
2
3
4
5
6
7
AVDD1
AVDD2
ADC1
AGND
REFGND
RA
8
RB
9
CHART
10
11
REFIN
REFOUT
12
13
VLDO
VLOGIC
14
SDO
15
16
DGND
RESET
17
18
19
20
GPIO_0
GPIO_1
GPIO_2
LDAC
Description
Switching Output for the Positive DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect the
external inductor as shown in Figure 77.
Positive Analog Supply. The voltage range on this pin is from 7 V to 33 V.
Positive Low Voltage Analog Supply. The voltage range on this pin is from 5 V to 33 V.
Multiplexed ADC External Input 1.
Ground Reference Point for the Analog Circuitry. This pin must be connected to 0 V.
Ground Reference Point for Internal Reference. This pin must be connected to 0 V.
External Current Setting Resistor. An external precision, low drift, 13.7 kΩ current setting resistor can be connected
between RA and RB to improve the current output temperature drift performance. It is recommended to place the
external resistor as close as possible to the AD5753.
External Current Setting Resistor. An external precision, low drift, 13.7 kΩ current setting resistor can be connected
between RA and RB to improve the current output temperature drift performance. It is recommended to place the
external resistor as close as possible to the AD5753.
HART Input Connection. The HART signal must be ac-coupled to this pin. If the HART signal is not being used, leave
this pin unconnected. This pin is disconnected from the HART summing node by default and is connected via the
HART_EN bit in the GP_CONFIG1 register.
External 2.5 V Reference Voltage Input.
Internal 2.5 V Reference Voltage Output. REFOUT must be connected to REFIN to use the internal reference. A
capacitor between REFOUT and REFGND is not recommended.
3.3 V Low Dropout (LDO) Output Voltage. VLDO must be decoupled to the AGND with a 0.1 µF capacitor.
Digital Supply. The voltage range on this pin is from 1.71 V to 5.5 V. VLOGIC must be decoupled to DGND with a 0.1 µF
capacitor.
Serial Data Output. This pin clocks data from the serial register in readback mode. The maximum SCLK speed for
readback mode is 15 MHz and this speed is dependent on the VLOGIC voltage. See Table 3 for the timing specifications.
Digital Ground.
Hardware Reset. Active low input. Do not write an SPI command within 100 μs of issuing a reset either by using the
hardware RESET pin or via software.
General-Purpose Input/Output 0.
General-Purpose Input/Output 1.
General-Purpose Input/Output 2.
Load DAC. Active low input. This pin updates the DAC_OUTPUT register and, consequently, the DAC output. Do
not assert LDAC within the 500 ns window before the rising edge of SYNC or 1.5 µs after the rising edge of SYNC
(see Table 3 for the timing specifications).
Rev. 0 | Page 15 of 72
AD5753
Pin No.
21
Mnemonic
CLKOUT
22
SCLK
23
24
SDI
SYNC
25
26
27
AD1
AD0
FAULT
28
29
NIC
AVSS
30
SW−
31
32
PGND2
VDPC−
33
34
NIC
−VSENSE
35
CCOMP
36
+VSENSE
37
38
39
VIOUT
ADC2
VDPC+
40
PGND1
EPAD
Data Sheet
Description
Optional Clock Output Signal (Disabled by Default). This pin is a divided down version of the internal 10 MHz
internal oscillator, which generates the master clock (MCLK), and is configured in the GP_CONFIG1 register.
Serial Clock Input. Data is clocked to the input shift register on the falling edge of the SCLK. In write mode, this pin
operates at clock speeds of up to 50 MHz and this speed is dependent on the VLOGIC voltage. In read mode, the maximum
SCLK speed is 15 MHz and this speed is dependent on the VLOGIC voltage. See Table 3 for the timing specifications.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Frame Synchronization Signal for the Serial Interface. Active low input. While SYNC is low, data is transferred in on
the falling edge of SCLK.
Address Decode 1 for the AD5753 Device.
Address Decode 0 for the AD5753 Device.
Fault Pin. Active low, open-drain output. This pin is high impedance when no faults are detected and is asserted
low when certain faults are detected. Some of these faults include an open circuit in current mode, a short circuit
in voltage mode, a CRC error, or an overtemperature error (see the Output Fault section). This pin must be connected to
VLOGIC with a 10 kΩ pull-up resistor.
Not Internally Connected.
Negative Analog Supply. The voltage range on this pin is 0 V to −33 V. If using the device solely for unipolar current
output purposes, the AVSS can be set to 0 V. For a unipolar voltage output, AVSS (maximum) is −2 V. When using
bipolar output ranges, the VOUT or IOUT headroom must be obeyed when calculating the AVSS maximum. For
example, for a ±10 V output, the AVSS maximum is −12.5 V. See the AVSS Considerations section for an important
note on power supply sequencing.
Switching Output for the Negative DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect the pin
and external inductor as shown in Figure 78.
Power to Ground.
Negative Supply for Current and Voltage Output Stage. To use the dc-to-dc feature of the device, connect the
external capacitor as shown in Figure 78.
Not Internally Connected.
Sense Connection for Negative Voltage Output Load Connection for VOUT Mode. This pin must stay within ±10 V of
AGND for specified operation. For specified operation, VDPC− tracks −VSENSE with respect to AGND. It is
recommended to connect a series 1 kΩ resistor to this pin.
Optional Compensation Capacitor Connection for the Voltage Output Buffer. Connecting a 220 pF capacitor
between this pin and the VIOUT pin allows the voltage output to drive up to 2 µF. The addition of this capacitor
reduces the bandwidth of the output amplifier, increasing the settling time.
Sense Connection for Positive Voltage Output Load Connection for Voltage Output Mode. It is recommended to
connect a series 1 kΩ resistor to this pin.
Voltage or Current Output Pin. VIOUT is a shared pin that provides either a buffered output voltage or current.
Multiplexed ADC External Input 2.
Positive Supply for Current and Voltage Output Stage. To use the dc-to-dc feature of the device, connect the
external capacitor as shown in Figure 77.
Power to Ground.
Exposed Pad. Connect the exposed pad to the potential of the VDPC− pin, or, alternatively, the exposed pad can be left
electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced
thermal performance.
Rev. 0 | Page 16 of 72
Data Sheet
AD5753
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE OUTPUT
0.0020
+5V RANGE
+10V RANGE
±5V RANGE
±10V RANGE
+10V RANGE WITH DC-TO-DC ENABLED
0.0015
0.0015
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
1kΩ LOAD
TA = 25°C
0.0010
INL ERROR (%FSR)
0.0010
INL ERROR (%FSR)
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
1kΩ LOAD
0.0005
0
0.0005
+5V RANGE, INL MIN
+10V RANGE, INL MIN
±5V RANGE, INL MIN
±10V RANGE, INL MIN
0
+5V RANGE, INL MAX
+10V RANGE, INL MAX
±5V RANGE, INL MAX
±10V RANGE, INL MAX
–0.0005
–0.0005
8192
16384
24576
32768
40960
49152
57344
65536
DAC CODE
–0.0015
25
0.8
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
1kΩ LOAD
TA = 25°C
0.8
DNL ERROR (LSB)
0.4
0.2
0
–0.2
0.4
0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
0
8192
16384
24576
32768
40960
49152
57344
65536
DAC CODE
–1.0
–40
Figure 11. DNL Error vs Temperature
0.008
AVDD1 = VDPC+ = 15V
AVSS = VDPC– = –15V
1kΩ LOAD
TA = 25°C
0.004
0.006
+5V RANGE, TUE MIN
+10V RANGE, TUE MIN
±5V RANGE, TUE MIN
±10V RANGE, TUE MIN
+5V RANGE, TUE MAX
+10V RANGE, TUE MAX
±5V RANGE, TUE MAX
±10V RANGE, TUE MAX
0.004
TUE (%FSR)
0
–0.002
–0.004
0.002
0
–0.002
–0.006
+5V RANGE
+10V RANGE
±5V RANGE
±10V RANGE
+10V RANGE WITH DC-TO-DC ENABLED
–0.008
0
8192
16384
24576
32768
40960
49152
DAC CODE
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
1kΩ LOAD
–0.004
57344
65536
17285-209
TUE (%FSR)
0.002
–0.010
125
115
TEMPERATURE (ºC)
Figure 8. DNL Error vs. DAC Code
0.006
25
–0.006
–40
25
70
105
TEMPERATURE (°C)
Figure 12. TUE vs. Temperature
Figure 9. TUE vs. DAC Code
Rev. 0 | Page 17 of 72
125
17285-212
–1.0
DNL ERROR MAX
DNL ERROR MIN
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
ALL RANGES
0.6
17285-208
DNL ERROR (LSB)
0.6
125
Figure 10. INL Error vs. Temperature
1.0
+5V RANGE
+10V RANGE
±5V RANGE
±10V RANGE
+10V RANGE WITH DC-TO-DC ENABLED
105
TEMPERATURE (°C)
Figure 7. INL Error vs. DAC Code
1.0
70
17285-211
0
17285-207
–0.0015
17285-210
–0.0010
–0.0010
AD5753
Data Sheet
0.008
0.002
0
–0.002
–0.004
–0.006
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
1kΩ LOAD
25
0.005
0
–0.005
–0.010
–0.015
70
105
125
TEMPERATURE (°C)
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
1kΩ LOAD
–0.020
–40
17285-214
–0.010
–40
0.010
125
Figure 16. Bipolar Zero Error vs. Temperature
0.002
0.008
5V RANGE
10V RANGE
5V RANGE
10V RANGE
±5V RANGE
±10V RANGE
0.006
0
–0.001
–0.002
–0.003
–0.004
–0.005
0.004
0.002
0
–0.002
–0.004
–0.006
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
1kΩ LOAD
–0.008
25
70
105
125
TEMPERATURE (°C)
–0.010
–40
17285-215
–0.006
–40
105
125
Figure 17. Zero-Scale Error vs. Temperature
0.005
5V RANGE
10V RANGE
±5V RANGE
±10V RANGE
0.008
70
TEMPERATURE (°C)
Figure 14. Offset Error vs. Temperature
0.010
25
17285-218
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
1kΩ LOAD
ZERO-SCALE ERROR (%FSR)
OFFSET ERROR (%FSR)
105
70
TEMPERATURE (°C)
Figure 13. Full-Scale Error vs. Temperature
0.001
25
17285-217
0.004
–0.008
±5V RANGE
±10V RANGE
0.015
BIPOLAR ZERO ERROR (%FSR)
0.006
FULL-SCALE ERROR (%FSR)
0.020
5V RANGE
10V RANGE
±5V RANGE
±10V RANGE
0.004
0V TO 10V RANGE, MAX INL
0V TO 10V RANGE, MIN INL
1kΩ LOAD
TA = 25°C
0.003
INL ERROR (%FSR)
0.004
0.002
0
0.002
0.001
0
–0.001
–0.002
–0.002
–0.003
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
1kΩ LOAD
–0.006
–40
25
–0.004
70
105
TEMPERATURE (°C)
125
–0.005
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AVDD1 /|AVSS| SUPPLY (V)
Figure 18. INL Error vs. AVDD1/|AVSS| Supply
Figure 15. Gain Error vs. Temperature
Rev. 0 | Page 18 of 72
17285-219
–0.004
17285-216
GAIN ERROR (%FSR)
0.006
Data Sheet
AD5753
1.0
15
0.8
10
OUTPUT VOLTAGE (V)
0.4
0.2
0
–0.2
–0.4
–0.6
5
0
–5
–10
AVDD1 /|AVSS| SUPPLY (V)
–15
17285-220
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Figure 22. Full-Scale Positive Step
15
0.05
AVDD1 = VDPC+ = +15V
AVSS = VDPC = –15V
±10V RANGE
OUTPUT UNLOADED
TA = 25°C
0V TO 10V RANGE, MAX TUE
0V TO 10V RANGE, MIN TUE
0.04
10
OUTPUT VOLTAGE (V)
0.03
0.01
0
–0.01
–0.02
–0.03
5
0
–5
–10
1kΩ LOAD
TA = 25°C
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AVDD1 /|AVSS| SUPPLY (V)
–15
17285-221
–0.04
0
–5
Figure 20. TUE vs. AVDD1/|AVSS| Supply
0.0006
15
Figure 23. Full-Scale Negative Step
0.0010
0.0008
10
5
TIME (μs)
17285-224
TUE (%FSR)
0.02
0.10
AVDD1 = VDPC+ = +15V
AVSS = VDPC = –15V
±10V RANGE
TA = 25°C
HIGH TO LOW
LOW TO HIGH
0.05
0
0.0004
VOUT (V)
0.0002
0
–0.0002
–0.0004
–0.05
–0.010
–0.015
AVDD1 = VDPC+ = +15V
AVSS = VDPC = –15V
0 TO 10V RANGE
1kΩ LOAD
TA = 25°C
–0.0006
–0.020
–0.0008
–0.0010
–20
–16
–12
–8
–4
0
4
8
12
16
OUTPUT CURRENT (mA)
20
17285-222
OUTPUT VOLTAGE DELTA (V)
15
TIME (μs)
Figure 19. DNL Error vs. AVDD1/|AVSS| Supply
–0.05
10
5
0
–5
17285-223
1kΩ LOAD
TA = 25°C
–0.8
Figure 21. Sink and Source Capability of the Output Amplifier
–0.025
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
Figure 24. Digital-to-Analog Glitch Major Code Transition
Rev. 0 | Page 19 of 72
4.0
17285-226
DNL ERROR (%FSR)
0.6
–1.0
AVDD1 = VDPC+ = +15V
AVSS = VDPC = –15V
±10V RANGE
OUTPUT UNLOADED
TA = 25°C
0V TO 10V RANGE, MAX DNL
0V TO 10V RANGE, MIN DNL
AD5753
20
AVDD1 = VDPC+ = +15V
AVSS = VDPC = –15V
0V TO 10V RANGE
OUTPUT UNLOADED
15
4.925
TA = 25°C
4.920
10
4.915
5
VOUT (V)
0
4.910
4.905
–5
4.900
–10
0
1
2
3
4
5
6
7
8
9
10
TIME (Seconds)
4.895
17285-228
–15
0
0.5
0
2.5
3.0
3.5
4.0
AVDD2 = 15V
VDPC+ = 15V
VDPC– = –15V
1kΩ LOAD
CLOAD = 220pF
–10
–20
200
VIOUT PSRR (dB)
–30
100
0
–100
–40
–50
–60
–70
–200
–80
–300
0
1
2
3
4
5
6
7
8
9
10
TIME (ms)
–100
10
1k
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 29. VOUT PSRR vs. Frequency
Figure 26. Peak-to-Peak Noise (100 kHz Bandwidth)
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
±10V RANGE MIDSCALE CODE
TA = 25°C
10kΩ LOAD
CLOAD = 220pF
VDPC+
2
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
±10V RANGE MIDSCALE CODE
TA = 25°C
10kΩ LOAD
CLOAD = 220pF
SYNC
VOUT
VOUT
4
4
CH3 2.00V
CH4 50.0mV
1.00µs
CH2 10.0mV
CH4 10.0mV
2.00µs
Figure 30. Voltage Output Ripple
Figure 27. VOUT vs. Time on Output Enable
Rev. 0 | Page 20 of 72
17285-233
3
100
17285-232
–90
17285-229
–400
17285-234
OUTPUT VOLTAGE (μV)
300
2.0
Figure 28. VOUT vs. Time on Power-Up
0V TO 10V RANGE – MIDSCALE CODE
OUTPUT UNLOADED
AVDD1 = VDPC+ = +15V
AVSS = VDPC = –15V
TA = 25°C
1.5
TIME (µs)
Figure 25. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
400
1.0
17285-230
OUTPUT VOLTAGE (μV)
Data Sheet
Data Sheet
AD5753
CURRENT OUTPUTS
4mA TO
4mA TO
4mA TO
4mA TO
0.002
EXTERNAL RSET
INTERNAL RSET
EXTERNAL RSET, WITH DC-TO-DC CONVERTER
INTERNAL RSET, WITH DC-TO-DC CONVERTER
0.002
0.001
0
AVDD = +15V
AVSS = –15V
TA =25°C
300Ω LOAD
0
8192
0mA TO 20mA RANGE, MAX INL
0mA TO 24mA RANGE, MAX INL
4mA TO 20mA RANGE, MAX INL
±24mA RANGE, MAX INL
–0.001
–0.002
–0.003
0mA TO 20mA RANGE, MIN INL
0mA TO 24mA RANGE, MIN INL
4mA TO 20mA RANGE, MIN INL
±24mA RANGE, MIN INL
16384
24576
32768
40960
49152
57344
65536
DAC CODE
–0.005
–40
4mA TO
4mA TO
4mA TO
4mA TO
0.8
0.003
EXTERNAL RSET
INTERNAL RSET
EXTERNAL RSET, WITH DC-TO-DC CONVERTER
INTERNAL RSET, WITH DC-TO-DC CONVERTER
125
AVDD1 = +15V
AVSS = –15V
0.002
0.001
0.4
0.2
0
–0.2
–0.4
0
–0.001
0mA TO 20mA RANGE, INL MAX
0mA TO 24mA RANGE, INL MAX
4mA TO 20mA RANGE, INL MAX
±24mA RANGE, INL MAX
0mA TO 20mA RANGE, INL MIN
0mA TO 24mA RANGE, INL MIN
4mA TO 20mA RANGE, INL MIN
±24mA RANGE, INL MIN
–0.002
–0.003
–0.004
–0.6
–0.005
–0.8
0
8192
16384
24576
32768
40960
49152
57344
65536
DAC CODE
–0.006
–40
17285-237
–1.0
105
Figure 34. INL Error vs. Temperature, Internal RSET
INL ERROR (%FSR)
DNL ERROR (LSB)
0.6
20mA,
20mA,
20mA,
20mA,
70
TEMPERATURE (°C)
Figure 31. INL Error vs. DAC Code
1.0
25
70
105
125
TEMPERATURE (ºC)
Figure 32. DNL Error vs. DAC Code
0.015
25
17285-242
–0.002
0
–0.004
17285-236
–0.001
AVDD1 = +15V
AVSS = –15V
0.001
INL ERROR (%FSR)
DNL ERROR (%FSR)
0.003
20mA,
20mA,
20mA,
20mA,
17285-240
0.004
Figure 35. INL Error vs. Temperature, External RSET
1.0
4mA TO 20mA, EXTERNAL RSET
4mA TO 20mA, INTERNAL RSET
0.8
0.010
DNL ERROR MAX
DNL ERROR MIN
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
ALL RANGES
0.6
DNL ERROR (LSB)
0
–0.005
–0.010
0.4
0.2
0
–0.2
–0.4
–0.6
–0.015
0
8192
16384
24576
32768
40960
49152
DAC CODE
57344
65536
Figure 33. TUE vs. DAC Code
–1.0
–40
25
115
TEMPERATURE (ºC)
Figure 36. DNL Error vs. Temperature
Rev. 0 | Page 21 of 72
125
17285-536
–0.020
–0.8
4mA TO 20mA, EXTERNAL RSET, WITH DC-TO-DC CONVERTER
4mA TO 20mA, INTERNAL RSET, WITH DC-TO-DC CONVERTER
17285-238
TUE (%FSR)
0.005
AD5753
Data Sheet
0.15
0.15
0mA TO 20mA, INTERNAL RSET
0mA TO 24mA, INTERNAL RSET
4mA TO 20mA, INTERNAL RSET
p/m 24mA, INTERNAL RSET
0mA TO 20mA, EXTERNAL RSET
0mA TO 24mA, EXTERNAL RSET
4mA TO 20mA, EXTERNAL RSET
p/m 24mA, EXTERNAL RSET
AVDD1 = +15V
AVSS = –15V
0.10
FULL-SCALE ERROR (%FSR)
0.05
0
–0.15
–40
25
0
–0.05
–0.10
115
125
TEMPERATURE (°C)
AVDD1 = +15V
AVSS = –15V
–0.15
–40
0.04
AVDD1 = +15V
AVSS = –15V
ZERO-SCALE ERROR (%FSR)
0
–0.01
0mA TO 20mA MIN TUE
0mA TO 24mA MIN TUE
4mA TO 20mA MIN TUE
p/m 24mA, MIN TUE
0mA TO 20mA MAX TUE
0mA TO 24mA MAX TUE
4mA TO 20mA MAX TUE
p/m 20mA, MAX TUE
0.02
0.01
0
–0.01
125
115
TEMPERATURE (°C)
–0.04
–40
0.04
125
0.10
0mA TO 20mA, INTERNAL RSET
0mA TO 24mA, INTERNAL RSET
4mA TO 20mA, INTERNAL RSET
p/m 24mA, INTERNAL RSET
0.05
GAIN ERROR (%FSR)
0.02
0.01
0
–0.01
0
–0.05
–0.02
25
115
TEMPERATURE (°C)
125
Figure 39. Offset Error vs. Temperature
–0.15
–40
0mA TO 20mA, EXTERNAL RSET
0mA TO 24mA, EXTERNAL RSET
4mA TO 20mA, EXTERNAL RSET
p/m 24mA, EXTERNAL RSET
25
115
TEMPERATURE (°C)
Figure 42. Gain Error vs. Temperature
Rev. 0 | Page 22 of 72
125
17285-442
–0.04
–40
–0.10
0mA TO 20mA, EXTERNAL RSET
0mA TO 24mA, EXTERNAL RSET
4mA TO 20mA, EXTERNAL RSET
p/m 24mA, EXTERNAL RSET
–0.03
17285-439
OFFSET ERROR (%FSR)
115
Figure 41. Zero-Scale Error vs. Temperature
AVDD1 = +15V
AVSS = –15V
0mA TO 20mA, INTERNAL RSET
0mA TO 24mA, INTERNAL RSET
4mA TO 20mA, INTERNAL RSET
p/m 24mA, INTERNAL RSET
25
TEMPERATURE (°C)
Figure 38. TUE Error vs. Temperature, External RSET
0.03
0mA TO 20mA, INTERNAL RSET
0mA TO 24mA, INTERNAL RSET
4mA TO 20mA, INTERNAL RSET
p/m 24mA, INTERNAL RSET
0mA TO 20mA, EXTERNAL RSET
0mA TO 24mA, EXTERNAL RSET
4mA TO 20mA, EXTERNAL RSET
p/m 24mA, EXTERNAL RSET
–0.02
–0.03
17285-438
TUE ERROR (%FSR)
0.01
25
AVDD1 = +15V
AVSS = –15V
0.03
0.02
–0.04
–40
125
Figure 40. Full-Scale Error vs. Temperature
0.03
–0.03
115
TEMPERATURE (°C)
Figure 37. TUE Error vs. Temperature, Internal RSET
–0.02
25
17285-440
–0.10
0mA TO 20mA TUE MIN
0mA TO 24mA TUE MIN
4mA TO 20mA TUE MIN
p/m 24mA TUE MIN
0mA TO 20mA TUE MAX
0mA TO 24mA TUE MAX
4mA TO 20mA TUE MAX
p/m 24mA TUE MAX
0.05
17285-441
–0.05
17285-437
TUE ERROR (%FSR)
0.10
Data Sheet
0.03
0.6
0.02
0.4
0.01
0
–0.01
–0.02
0
–0.2
–0.4
–0.8
–0.05
–1.0
8
10
12
14
16
20
18
22
24
28
26
30
17285-266
–0.6
–0.04
AVDD1 /|AVSS| SUPPLY (V)
0.05
0.04
12
14
16
18
20
22
24
26
28
30
0.005
4mA TO 20mA RANGE MAX INL
4mA TO 20mA RANGE MIN INL
0.003
INL ERROR (%FSR)
0.02
0.01
0
–0.01
–0.02
–0.03
0.001
0
–0.001
–0.003
6
8
10
12
14
16
18
20
22
24
26
28
30
AVDD1 /|AVSS| SUPPLY (V)
–0.005
17285-269
–0.05
6
8
10
12
14
16
Figure 44. TUE vs. AVDD1/|AVSS| Supply, External RSET
20
22
24
26
28
30
Figure 47. INL Error vs. AVDD1/|AVSS| Supply, Internal RSET
1.0
0.005
4mA TO 20mA RANGE MAX INL
4mA TO 20mA RANGE MIN INL
4mA TO 20mA RANGE MAX DNL
4mA TO 20mA RANGE MIN DNL
0.8
18
AVDD1 /|AVSS| SUPPLY (V)
17285-265
RLOAD = 300Ω
TA = 25°C
–0.04
0.6
0.003
INL ERROR (%FSR)
0.4
0.2
0
–0.2
–0.4
–0.6
0.001
–0.001
–0.003
RLOAD = 300Ω
TA = 25°C
6
8
10
12
14
16
18
20
22
24
26
28
AVDD1 /|AVSS| SUPPLY (V)
30
Figure 45. DNL Error vs. AVDD1/|AVSS| Supply, Internal RSET
–0.005
RLOAD = 300Ω
TA = 25°C
6
8
10
12
14
16
18
20
22
24
26
28
AVDD1 /|AVSS| SUPPLY (V)
Figure 48. INL Error vs. AVDD1/|AVSS| Supply, External RSET
Rev. 0 | Page 23 of 72
30
17285-268
–0.8
17285-264
DNL ERROR (LSB)
10
Figure 46. DNL Error vs. AVDD1/|AVSS| Supply, External RSET
0.03
–1.0
8
AVDD1 /|AVSS| SUPPLY (V)
RLOAD = 300Ω
TA = 25°C
4mA TO 20mA RANGE MAX TUE
4mA TO 20mA RANGE MIN TUE
RLOAD = 300Ω
TA = 25°C
6
Figure 43. TUE vs. AVDD1/|AVSS| Supply, Internal RSET
TUE (%FSR)
0.2
–0.03
6
4mA TO 20mA RANGE MAX DNL
4mA TO 20mA RANGE MIN DNL
0.8
DNL ERROR (LSB)
TUE (%FSR)
0.04
1.0
RLOAD = 300Ω
TA = 25°C
4mA TO 20mA RANGE MAX TUE
4mA TO 20mA RANGE MIN TUE
17285-267
0.05
AD5753
AD5753
Data Sheet
AVDD1 = 24V
AVSS = –24V
4mA TO 20mA RANGE
FULL-SCALE STEP
1kΩ LOAD
TA = 25ºC
AVDD1
3
IOUT
CH4 10.0mV
4.00ms
CH1 5.00V
CH4 5.00V
CH4
12
TA = 25°C
AVDD1 = +15V
AVSS = –15V
4mA TO 20mA RANGE
10 FULL-SCALE STEP
300Ω LOAD
TA = 25°C
IOUT AND V DPC+ VOLTAGE (V)
3
IOUT
8
6
4
IOUT WITH 150mA IDCDCLIMIT (V)
VDPC+ WITH 150mA IDCDCLIMIT (V)
IOUT WITH 400mA IDCDCLIMIT (V)
VDPC+ WITH 400mA IDCDCLIMIT (V)
CH4 20.0mV
17285-260
2
400ns
0
–100 –50
0
50
100 150 200 250 300 350 400 450 500
SETTLING TIME (µs)
Figure 53. IOUT and VDPC+ Voltage vs. Settling Time where IDCDCLIMIT is the
DC-to-DC Converter Current Limit
Figure 50. Output Current vs. Time on Output Enable
10
AVDD1 = +30V
AVSS = –15V
0mA TO 24mA RANGE
1kΩ LOAD
TA = 25°C
12
9
IOUT AND V DPC+ VOLTAGE (V)
14
10
8
6
4
2
0
8
IOUT AT
IOUT AT
IOUT AT
IOUT AT
7
–40°C
+25°C
+85°C
+125°C
0
5
10
15
20
25
30
OUTPUT CURRENT (mA)
Figure 51. DC-to-DC Converter Headroom vs. Output Current
VDPC+
VDPC+
VDPC+
VDPC+
AT
AT
AT
AT
–40°C
+25°C
+85°C
+125°C
6
5
4
3
AVDD1 = +15V
AVSS = –15V
4mA TO 20mA RANGE
FULL-SCALE STEP
300Ω LOAD
IDCDCLIMIT = 150mA
2
1
0
–100 –50
17285-257
DC-TO-DC CONVERTER HEADROOM (V)
16
17285-231
SYNC
CH3 2.00V
80.0µs
Figure 52. Output Current and VDPC+ Settling Time
Figure 49. Output Current vs. Time on Power-Up
4
VDPC+ WITH 400mA LIMIT (V)
IOUT WITH 400mA LIMIT (V)
VDPC+ WITH 150mA LIMIT (V)
IOUT WITH 150mA LIMIT(V)
0
50 100 150 200 250 300 350 400 450 500 550
SETTLING TIME (µs)
17285-453
CH3 5.00V
17285-261
CH1
CH4
17285-452
4
Figure 54. IOUT and VDPC+ Voltage vs. Settling Time Including Temperature
Rev. 0 | Page 24 of 72
Data Sheet
AD5753
20
VDPC+
0
TA = 25°C
AVDD2
VDPC+
VDPC–
2
IOUT PSRR (dB)
–20
3
IOUT
–40
–60
–80
4
B
B
W
W
2.00µs
–120
10
17285-355
CH3 2.00V BW CH2 10.0mV
CH4 10.0mV
100
1k
10k
100k
FREQUENCY (Hz)
Figure 56. IOUT PSRR vs. Frequency
Figure 55. Output Current Ripple vs. Time with DC-to-DC Converter
Rev. 0 | Page 25 of 72
1M
10M
17285-256
–100
AD5753
Data Sheet
90
90
80
80
70
OUTPUT EFFICIENCY (%)
100
70
60
50
40
30
–8
–4
30
20
1kΩ LOAD
300Ω LOAD
0Ω LOAD
300Ω LOAD
0Ω LOAD
0
–24 –20 –16 –12
40
AVDD1 = 28V, 1kΩ, LOAD
AVDD1 = 28V, 300Ω, LOAD
AVDD1 = 15V, 300Ω, LOAD
10
0
4
8
12
16
20
24
OUTPUT CURRENT (mA)
0
–40
0.18
80
0.16
POWER DISSIPATION (W)
90
70
60
50
40
30
10
0
–40
1kΩ LOAD
300Ω LOAD
0Ω LOAD
300Ω LOAD
0Ω LOAD
25
0.12
0.10
0.08
0.06
0.02
125
105
85
TEMPERATURE (°C)
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
1kΩ LOAD
300Ω LOAD
0Ω LOAD
300Ω LOAD
0Ω LOAD
= 28V,
= 28V,
= 28V,
= 15V,
= 15V,
0
–24 –20 –16 –12
–8
–4
0
4
8
12
16
20
24
OUTPUT CURRENT (mA)
Figure 58. DC-to-DC Efficiency vs. Temperature
Figure 61. Power Dissipation vs. Output Current
0.16
90
AVDD1 = 28V, 1kΩ LOAD
AVDD1 = 28V, 300Ω LOAD
AVDD1 = 15V, 300Ω LOAD
80
0.14
POWER DISSIPATION (W)
70
60
50
40
30
0.12
0.10
0.08
0.06
0.04
20
0.02
10
0
–24 –20 –16 –12
–8
–4
0
4
8
12
16
OUTPUT CURRENT (mA)
20
24
17285-459
OUTPUT EFFICIENCY (%)
125
0.14
0.04
17285-284
DC-TO-DC EFFICIENCY (%)
0.20
= 28V,
= 28V,
= 28V,
= 15V,
= 15V,
105
Figure 60. Output Efficiency vs. Temperature
100
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
85
TEMPERATURE (°C)
Figure 57. DC-to-DC Efficiency vs. Output Current
20
25
17285-288
= 28V,
= 28V,
= 28V,
= 15V,
= 15V,
50
17285-461
10
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
60
0
–40
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
= 28V,
= 28V,
= 28V,
= 15V,
= 15V,
25
1kΩ
300Ω
0Ω
300Ω
0Ω
85
105
TEMPERATURE (°C)
Figure 62. Power Dissipation vs. Temperature
Figure 59. Output Efficiency vs. Output Current
Rev. 0 | Page 26 of 72
125
17285-285
20
17285-457
DC-TO-DC EFFICIENCY (%)
DC-TO-DC BLOCK
Data Sheet
AD5753
REFERENCE
2.5005
TA = 25°C
AVDD2 = 5V
TA = 25°C
AVDD2
REFOUT (V)
2.5000
3
2.4995
REFOUT
4
CH4 1.00 V
10.0µs
2.4985
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
LOAD CURRENT (mA)
Figure 63. REFOUT Turn On Transient
5
Figure 66. REFOUT vs. Load Current
2.50044
AVDD1 = VDPC+ = +15V
AVSS = VDPC– = –15V
TA = 25°C
2
1
0
–1
–2
–3
2.50042
2.50041
2.50040
2.50039
2.50038
2.50037
1
2
3
4
5
6
7
8
9
10
TIME (µs)
2.50035
17285-271
0
2.5030
2.5025
10
12
14
16
18
20
22
24
26
28
30
30 DEVICES SHOWN
AVDD2 = 15V
2.5020
2.5015
REFOUT (V)
0.5
0
2.5010
2.5005
2.5000
2.4995
–0.5
2.4990
2.4985
–1.0
2.4980
–1.5
0
2
4
6
8
10
12
14
16
18
TIME (ms)
20
17285-272
OUTPUT VOLTAGE (μV)
8
Figure 67. Reference Output Voltage vs. AVDD2 Supply
AVDD1 = VDPC+ = 15V
AVSS = VDPC– = –15V
TA = 25°C
1.0
6
AVDD2 SUPPLY (V)
Figure 64. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
1.5
4
17285-274
2.50036
–4
Figure 65. Peak-to-Peak Noise (100 kHz Bandwidth)
2.4975
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 68. REFOUT vs. Temperature
Rev. 0 | Page 27 of 72
100
120
17285-367
OUTPUT VOLTAGE (μV)
3
–5
TA = 25°C
2.50043
REFERENCE OUTPUT VOLTAGE (V)
4
17285-273
CH3 2.00V
17285-270
2.4990
AD5753
Data Sheet
GENERAL
80
10.15
VLOGIC = 3.3V
TA = 25°C
70
AVDD2 = 5.5V
TA = 25°C
10.10
MCLK FREQUENCY (MHz)
VLOGIC CURRENT (µA)
60
50
40
30
20
10.05
10.00
9.95
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
LOGIC INPUT VOLTAGE (V)
9.90
–40
25
3.31
VOUT = 0V
TA = 25°C
1.5
3.29
1.0
3.28
0.5
VLDO (V)
0
3.27
3.26
3.25
–0.5
3.24
–1.0
AISS
3.23
–1.5
0
5
10
15
20
30
25
35
AVDD1 /|AVSS| VOLTAGE SUPPLY (V)
17285-278
–2.0
3.22
1.0
AIDD1
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
IOUT = 0mA
TA = 25°C
0
5
10
15
20
25
30
AVDD1 VOLTAGE SUPPLY (V)
35
17285-279
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
LOAD CURRENT (mA)
Figure 73. VLDO vs. Load Current
Figure 70. AIDD1/AISS Current vs. AVDD1/|AVSS| Voltage Supply
0.9
3.21
Figure 71. AIDD1 Current vs. AVDD1 Voltage Supply
Rev. 0 | Page 28 of 72
17285-276
AIDD1 /AISS CURRENT (mA)
125
AVDD2 = 15V
TA = 25°C
3.30
AIDD1
AIDD1 CURRENT (mA)
105
Figure 72. MCLK Frequency vs. Temperature
Figure 69. VLOGIC Current vs. Logic Input Voltage
2.0
70
TEMPERATURE (°C)
17285-282
0
17285-281
10
Data Sheet
AD5753
TERMINOLOGY
Total Unadjusted Error (TUE)
TUE is a measure of the output error that takes into account
various errors, such as INL error, offset error, gain error, and
output drift over supplies, temperature, and time. TUE is
expressed in % FSR.
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy, also known as INL, is a measure
of the maximum deviation, either in LSBs or % FSR, from the
best fit line passing through the DAC transfer function.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures monotonicity.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5753 is
monotonic over the full operating temperature range.
Zero-Scale or Negative Full-Scale Error
Zero-scale or negative full-scale error is the error in the DAC
output voltage when 0x0000 (straight binary coding) is loaded
to the DAC output register.
Zero-Scale Temperature Coefficient (TC)
Zero-scale TC is a measure of the change in zero-scale error
with a change in temperature. Zero-scale error TC is expressed
in ppm FSR/°C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC output register. Ideally, the output is
full-scale − 1 LSB. Full-scale error is expressed in % FSR.
Headroom
Headroom is the difference between the voltage required at the
output, which is the programmed voltage in voltage output
mode and the programmed current × RLOAD in current output
mode, and the voltage supplied by the positive supply rail, VDPC+.
Headroom is relevant when the output is positive with respect
to ground.
Footroom
Footroom is the difference between the voltage required at the
output, which is the programmed voltage in voltage output
mode and the programmed current × RLOAD in current output
mode, and the voltage supplied by the negative supply rail, AVSS.
Footroom is relevant when the output is negative with respect
to ground.
VOUT or −VSENSE Common-Mode Rejection Ratio (CMRR)
VOUT or −VSENSE CMRR is the error in the VOUT voltage that
occurs due to changes in the –VSENSE voltage.
Current Loop Compliance Voltage
Current loop compliance voltage is the maximum voltage at the
VIOUT pin for which the output current is equal to the
programmed value.
Voltage Reference Thermal Hysteresis
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC output register is
loaded with 0x8000 (straight binary coding).
Voltage reference thermal hysteresis is the difference in output
voltage measured at +25°C compared to the output voltage
measured at +25°C after cycling the temperature from +25°C to
−40°C to +115°C and then back to +25°C.
Bipolar Zero Temperature Coefficient (TC)
Bipolar zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in ppm FSR/°C.
Voltage Reference TC
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated by using the box method. This method defines the
TC as the maximum change in the reference output over a given
temperature range expressed in ppm/°C and is as follows:
Offset Error
Offset error is the deviation of the analog output from the ideal and
is measured using ¼ scale and ¾ scale digital code measurements.
It is expressed in % FSR.
VREF _ MAX − VREF _ MIN
6
=
TC
×10
V
REF
_
NOM
×
Temp
Range
Offset Error (TC)
Offset error TC is a measure of the change in the offset error
with a change in temperature. It is expressed in ppm FSR/°C.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
DAC transfer characteristic slope deviation from the ideal value
expressed in % FSR.
Gain Error Temperature Coefficient (TC)
Gain error TC is a measure of the change in gain error with
changes in temperature. Gain error TC is expressed in
ppm FSR/°C.
where:
VREF_MAX is the maximum reference output measured over the
total temperature range.
VREF_MIN is the minimum reference output measured over the
total temperature range.
VREF_NOM is the nominal reference output voltage, 2.5 V.
Temp Range is the specified temperature range, −40°C to
+115°C.
Rev. 0 | Page 29 of 72
AD5753
Data Sheet
Line Regulation
Line regulation is the change in reference output voltage due to
a specified change in power supply voltage. It is expressed in
ppm/V.
Power-On Glitch Energy
Power-on glitch energy is the impulse injected into the analog
output when the AD5753 is powered on. It is specified as the
area of the glitch in nV-sec.
Load Regulation
Load regulation is the change in reference output voltage due to
a specified change in reference load current. It is expressed in
ppm/mA.
Digital-to-Analog Glitch Energy
Digital-to-analog glitch energy is the energy of the impulse injected
into the analog output when the input code in the DAC output
register changes state. It is normally specified as the area of the
glitch in nV-sec. The worst case usually occurs when the digital
input code is changed by 1 LSB at the major carry transition
(0x7FFF to 0x8000).
Dynamic Power Control (DPC)
In DPC mode, the AD5753 circuitry senses the output voltage
and dynamically regulates the supply voltage, VDPC+, to meet
compliance requirements plus an optimized headroom voltage
for the output buffer.
Programmable Power Control (PPC)
In PPC mode, the VDPC+ voltage is user programmable to a fixed
level that must accommodate the required maximum output load.
Output Voltage Settling Time
Output voltage settling time is the amount of time the output takes
to settle to a specified level for a full-scale input change. This
specification depends on the manner in which the DPC feature
is configured, such as enabled, disabled, or PPC mode enabled,
and on the characteristics of the external dc-to-dc inductor and
capacitor components used.
Slew Rate
The device slew rate is a limitation in the rate of change of the
output voltage. The output slewing speed of a voltage output
DAC is usually limited by the slew rate of the amplifier used at
the output. Slew rate is measured from 10% to 90% of the
output signal and is expressed in V/µs.
Glitch Impulse Peak Amplitude
Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in the
DAC output register changes state. It is specified as the amplitude
of the glitch in millivolts and the worst case usually occurs when
the digital input code is changed by 1 LSB at the major carry
transition (0x7FFF to 0x8000).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the DAC analog output from the DAC digital inputs. However,
the digital feedthrough is measured when the DAC output is
not updated, which occurs when the LDAC pin is held high. The
digital feedthrough is specified in nV-sec and measured with a
full-scale code change on the data bus.
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the power supply voltage.
Rev. 0 | Page 30 of 72
Data Sheet
AD5753
The AD5753 is a single-channel, precision voltage and current
output DAC designed to meet the requirements of industrial
factory automation and process control applications. The device
provides a high precision, fully integrated, single-chip solution for
generating a unipolar, bipolar current, or voltage output. Package
power dissipation is minimized by incorporating on-chip DPC and
then regulating the supply voltage, VDPC+ and VDPC−, to the VIOUT
output driver from ±4.95 V to ±27 V by using complementary
buck dc-to-dc converters optimized for minimum on-chip power
dissipation. The AD5753 consists of a two die solution with the
dc-to-dc converter circuitry and the VIOUT line protector located on
the dc-to-dc die. The remaining circuitry is on the main die.
Interdie communication is performed over an internal 3-wire
interface.
Voltage Output Mode
If voltage output mode is enabled, the voltage output from the
DAC is buffered and scaled to output a software selectable
unipolar or bipolar voltage range (see Figure 75).
The available voltage ranges are 0 V to 5 V, ±5 V, 0 V to 10 V,
and ±10 V. A 20% overrange feature is also available via the DAC_
CONFIG register, as well as the function to negatively offset the
unipolar voltage ranges via the GP_CONFIG1 register (see the
General-Purpose Configuration 1 Register section).
+VSENSE
DAC
RANGE
SCALING
VOUT SHORT FAULT
DAC ARCHITECTURE
The DAC core architecture of the AD5753 consists of a voltage
mode R-2R DAC ladder network. The voltage output of the
DAC core is converted to either a current or voltage output at the
VIOUT pin. Only one mode can be enabled at any one time. Both
the voltage and current output stages are supplied by the VDPC+
power rail, which is internally generated from AVDD1, and the
VDPC− power rail, which is internally generated from AVSS.
Current Output Mode
If current output mode is enabled, the voltage output from the
DAC is converted to a current (see Figure 74), which is then
mirrored to the supply rail so that the application only sees a
current source output.
The available current ranges are 0 mA to 20 mA, 0 mA to 24 mA,
4 mA to 20 mA, ±20 mA, ±24 mA, and −1 mA to +22 mA. An
internal or external 13.7 kΩ RSET resistor can be used for the
voltage to current conversion.
VDPC+
R2
R3
16-BIT
DAC
Vx
R1
R4
Figure 74. Voltage to Current Conversion Circuitry
17285-023
VDPC–
IOUT
OPEN FAULT
–VSENSE
Figure 75. Voltage Output
Reference
The AD5753 can operate either with an external or internal
reference. The reference input requires a 2.5 V reference for
specified performance. This input voltage is then internally
buffered before being applied to the DAC.
The AD5753 contains an integrated buffered 2.5 V voltage
reference that is externally available for use elsewhere within the
system. The internal reference drives the integrated 12-bit ADC.
REFOUT must be connected to REFIN to use the internal
reference to drive the DAC.
SERIAL INTERFACE
The AD5753 is controlled over a versatile 4-wire serial interface
that operates at clock rates of up to 50 MHz and is compatible
with SPI, QSPI, MICROWIRE, and DSP standards. Data coding
is always straight binary.
Input Shift Register
RA
RB
VIOUT
RSET
VIOUT
17285-024
THEORY OF OPERATION
With the SPI CRC enabled (default state), the input shift register is
32 bits wide. Data is loaded to the device MSB first as a 32-bit word
under the control of a serial clock input, SCLK. Data is clocked in
on the falling edge of SCLK. If the CRC is disabled, the serial
interface is reduced to 24 bits. A 32-bit frame is still accepted but
the last 8 bits are ignored. See the Register Map section for full
details on the registers that can be addressed via the SPI
interface.
Table 7. Writing to a Register (CRC Enabled)
MSB
D31
Slip Bit
Rev. 0 | Page 31 of 72
[D30:D29]
AD5753
address
[D28:D24]
Register
address
[D23:D8]
Data
LSB
[D7:D0]
CRC
AD5753
Data Sheet
Transfer Function
Table 8 shows the input code to ideal output voltage relationship for
the AD5753 for straight binary data coding of the ±5 V output
range.
Table 8. Ideal Output Voltage to Input Code Relationship
Digital Input, Straight Binary
Data Coding
MSB
LSB
1111 1111
1111
1111
1111 1111
1111
1110
1000 0000
0000
0000
0000 0000
0000
0001
0000 0000
0000
0000
Analog Output
VOUT
2 × VREF × (32,767/32,768)
2 × VREF × (32,766/32,768)
0V
−2 × VREF × (32,767/32,768)
−2 × VREF
POWER-ON STATE OF THE AD5753
On initial power-on or a device reset, the voltage and current
output channel is disabled. The switch connecting the VIOUT via a
30 kΩ pull-down resistor to AGND is open. This switch can be
configured in the DCDC_CONFIG2 register. VDPC+ and VDPC−
are internally driven to ±4.8 V upon power-on, until the dc-todc converters are enabled.
After device power-on or a device reset, a calibration memory
refresh command is required (see the Programming Sequence
to Enable the Output section). It is recommended to wait 500 μs
at minimum after writing this command before writing further
instructions to the device to allow time for internal calibrations
to take place.
AVDD2
SYNC
SCLK
SDI
SOFTWARE
RESET
RESET
HARDWARE
RESET
The AD5753 has the following four supply rails: AVDD1, AVDD2,
AVSS, and VLOGIC. See Table 1 for the voltage range of the four
supply rails and the associated conditions.
AVDD1 Considerations
AVDD1 is the supply rail for the positive dc-to-dc converter and can
range from 7 V to 33 V. Although the maximum value of AVDD1 is
33 V and the minimum value of AVSS is −33 V, the maximum
operating range of |AVDD1 to AVSS| is 60 V. VDPC+ is derived from
AVDD1 and the value depends on the dc-to-dc converter mode of
operation
The dc-to-dc converter requires a sufficient level of margin to be
maintained between AVDD1 and VDPC+ to ensure the dc-to-dc
circuitry operates correctly. This margin is 5% of the maximum
VDPC+ voltage for a given mode of operation.
Table 9. AVDD1 to VDPC+ Margin
Mode of Operation
DPC Voltage Mode
DPC Current Mode
PPC Current Mode
VDPC+ Maximum
15 V
(IOUT maximum × RLOAD) + IOUT headroom
DCDC_CONFIG1[4:0] programmed value
See the Power Dissipation Control section for further details on
the dc-to-dc converter modes of operation.
Calculating Supply Voltage
where:
IOUT maximum = 20 mA; RLOAD = 1 kΩ
IOUT maximum voltage = IOUT maximum × RLOAD = 20 V
IOUT headroom = 2.5 V
INT_AVCC
POWER-ON
RESET
17285-125
3.3V
VLDO
POWER SUPPLY CONSIDERATIONS
Assuming DPC current mode, use the following equation to
calculate the supply voltage:
VDPC+ maximum = IOUT maximum voltage + IOUT headroom
= 22.5 V
Power-On Reset
VLDO
not write SPI commands to the device within 100 μs of a reset
event.
Figure 76. Power-On Reset Block Diagram
The AD5753 incorporates a power-on reset circuit that ensures the
AD5753 is held in reset if the power supplies are insufficient
enough to allow reliable operation. The power-on reset circuit
(see Figure 76) monitors the AVDD2 generated VLDO, the INT_
AVCC voltages, the RESET pin, and the SPI reset signal. The
power-on reset circuit keeps the AD5753 in reset until the voltages
on the VLDO and an internal AVCC voltage node (INT_AVCC) are
sufficient for reliable operation. The AD5753 is reset if the
power-on circuit receives a signal from the RESET pin or if a
software reset is written to the AD5753 via the SPI interface. Do
|VDPC+ to AVDD1| headroom is calculated as 5% of 22.5 V =
1.125 V. Therefore, AVDD1 (minimum) = 22.5 V + 1.125 V =
23.625 V. Assuming a worst case AVDD1 supply rail tolerance of
±10%, this example requires an AVDD1 supply rail of
approximately 26 V.
AVSS Considerations
AVSS is the negative supply rail and has a range of −33 V to 0 V. As
in the case of AVDD1, AVSS must obey the 60 V maximum operating
range of |AVDD1 to AVSS|. VDPC− is derived from AVSS and the value
depends on the dc-to-dc converter mode of operation. The dcto-dc converter requires a sufficient level of margin between
AVSS and VDPC− to ensure the dc-to-dc circuitry operates
correctly. This margin is 5% of the maximum |VDPC−| voltage for
a given mode of operation.
Rev. 0 | Page 32 of 72
Data Sheet
AD5753
Calculating Supply Voltage
Assuming DPC current mode, use the following equation to
calculate the supply voltage:
VDPC− minimum = IOUT minimum voltage + IOUT headroom =
−22.5 V
where:
IOUT minimum = −20 mA; RLOAD = −20 V
IOUT minimum voltage = IOUT minimum × RLOAD = −20 V
IOUT headroom = −2.5 V
VDPC− to AVSS. For unipolar voltage output ranges, the maximum
AVSS is −2 V to enable sufficient footroom for the internal voltage
output circuitry. If negative rail DPC is disabled, connect VDPC−
to AVSS. To avoid power supply sequencing issues, a Schottky diode
must be placed between VDPC− and ground and the ground supply
must always be available.
AVDD2 Considerations
The |VDPC− to AVSS| headroom is calculated as 5% of −22.5 V =
−1.125 V. Therefore, AVSS (minimum) = −22.5 V − 1.125 V =
−23.625 V. Assuming a worst case AVSS supply rail tolerance of
±10%, this example requires an AVSS supply rail of
approximately −26 V.
AVDD2 is the positive low voltage supply rail and has a range of 5 V
to 33 V. If only one positive power rail is available, AVDD2 can be
tied to AVDD1. However, to optimize for reduced power dissipation,
supply AVDD2 with a separate lower voltage supply.
VLOGIC Considerations
VLOGIC is the digital supply for the device and ranges from 1.71 V to
5.5 V. The 3.3 V VLDO output voltage can be used to drive VLOGIC.
For unipolar current output ranges, with negative rail DPC
disabled, AVSS can be tied to AGND (0 V) and can be connected
Rev. 0 | Page 33 of 72
AD5753
Data Sheet
DEVICE FEATURES AND DIAGNOSTICS
POWER DISSIPATION CONTROL
DC-to-DC Converter Operation
The AD5753 contains integrated buck dc-to-dc converter
circuitry that controls the positive and negative (VDPC+ and
VDPC−) power supply to the output buffers. The converter reduces
power consumption from standard designs when using the
device in both current and voltage output modes. AVDD1 is the
supply rail for the dc-to-dc converter and ranges from 7 V to
33 V. VDPC+ is also derived from this supply rail. AVSS is the
supply rail for the negative rail dc-to-dc converter and ranges
from −33 V to 0 V. VDPC− is also derived from this supply rail.
The value of both the VDPC+ and VDPC− rails depends on the dcto-dc converter mode of operation as well as the output load, DPC
voltage mode, DPC current mode, and PPC current mode.
The dc-to-dc converter uses a fixed, 500 kHz frequency, peak
current mode control scheme to step down the AVDD1 and AVSS
inputs to produce VDPC+ and VDPC− to supply the driver circuitry of
the voltage or current output channel. The dc-to-dc converters
incorporate a low-side synchronous switch and, therefore, do
not require an external Schottky diode. The dc-to-dc converters
operate predominantly in discontinuous conduction mode
(DCM), where the inductor current goes to zero for an appreciable
percentage of the switching cycle. To avoid generating lower
frequency harmonics on the VDPC+ and VDPC− regulated output
voltage rails, the dc-to-dc converters do not skip any cycles. The
dc-to-dc converters must therefore transfer a minimum amount
of energy to the load, that is, the current or voltage output stage
and the respective load, to operate at a fixed frequency. Thus,
for light loads, such as a low RLOAD or low IOUT, the VDPC+ and VDPC−
voltage can rise beyond the target value and stop regulating.
This voltage rise is not a fault condition and does not represent
the worst case power dissipation condition in an application.
Figure 77 shows the discrete components needed for the positive
dc-to-dc circuitry and Figure 78 shows the components needed
for the negative dc-to-dc circuitry. The following sections
describe how to select components and circuitry operation. Use
the same circuitry on the negative AVSS rail if the negative DPC
mode is in use, such as if DCDC_CONFIG2 Bit 1 = 1. If the
negative DPC is not in use, tie VDPC− to AVSS.
CIN
4.7µF
0.1µF
LDCDC
47µH
CDCDC
2.2µF
PGND1
The dc-to-dc converter requires a sufficient level of margin
between AVDD1 and VDPC+, and between AVSS and VDPC− to
ensure that the dc-to-dc circuitry operates correctly. This
margin value is 5% of the VDPC+/|VDPC−| maximum.
DPC Voltage Mode
SW+
AVDD1
VDPC+
PGND1
In DPC voltage mode, with the voltage output enabled or disabled,
the converter regulates the VDPC+ supply to 15 V above the
−VSENSE voltage and regulates the VDPC− supply to 15 V below the
−VSENSE voltage. This mode allows the full output voltage range to
be efficiently applied across remote loads, with corresponding
remote grounds at up to ±10 V potential relative to the local
ground supply (AGND) for the AD5753.
17285-021
POSITIVE
DC-TO-DC
CONVERTER
CIRCUITRY
VDPC+
Figure 77. Positive DC-to-DC Circuit
DPC Current Mode
VDPC–
In standard current input module designs, the combined line
and load resistance values typically range from 50 Ω to 750 Ω.
Output module systems must provide enough voltage to meet
the compliance voltage requirement across the full range of load
resistor values. For example, in a 4 mA to 20 mA loop, when
driving 20 mA to a 750 Ω load, a compliance voltage of >15 V is
required. When driving 20 mA into a 50 Ω load, the required
compliance is reduced to >1 V.
NEGATIVE
DC-TO-DC
CONVERTER
CIRCUITRY
AVSS
CIN
4.7µF
PGND2
VDPC–
LDCDC
47µH
CDCDC
2.2µF
PGND2
17285-578
0.1µF
SW–
Figure 78. Negative DC-to-DC Circuit
Table 10. Recommended DC-to-DC Components
Symbol
LDCDC
CDCDC
CIN
Component
PA6594-AE
GCM31CR71H225KA55L
GRM31CR71H475KA12L
Value
47 μH
2.2 μF
4.7 μF
Manufacturer
Coilcraft
Murata
Murata
In DPC current mode, the AD5753 dc-to-dc circuitry senses the
output voltage and regulates the VDPC+ and VDPC− supply voltage to
meet compliance requirements as well as an optimized headroom
voltage for the output buffer. VDPC+ is dynamically regulated to
4.95 V or IOUT × RLOAD + headroom, or whichever voltage is
greater, which excludes the light load condition whereby the
VDPC+ voltage can rise beyond the target value. This same
analysis applies to VDPC−, except with the opposite polarity. As
previously noted, the exclusion of the light load does not represent
the worst case power dissipation condition in an application. The
Rev. 0 | Page 34 of 72
Data Sheet
AD5753
AD5753 is capable of driving up to 24 mA through a 1 kΩ load
for a given input supply (24 V + headroom).
At low output power levels, the regulated headroom increases
above 2.3 V due to the fact that the dc-to-dc circuitry uses a
minimum on time duty cycle. This behavior is expected and
does not impact any worse case power dissipation.
PPC Current Mode
The dc-to-dc converter can also operate in programmable power
control mode, where the VDPC+ and VDPC− voltages are user
programmable to a given level to accommodate the required
maximum output load. This mode represents a trade-off between
the optimized power efficiency of the DPC current mode and the
system settling time with a fixed supply and dc-to-dc disabled. In
PPC current mode, VDPC+ and VDPC− are regulated to a user
programmable level between +5 V and +25.677 V (VDPC+) and
−5 V and −25.677 V (VDPC−), with respect to −VSENSE in steps of
0.667 V. This mode is useful if settling time is an important
requirement of the design. See the DC-to-DC Converter Settling
Time section for information on settling time. If the load is
nonlinear in nature, take care in selecting the programmed level
of VDPC+ and VDPC−. VDPC+ and VDPC− must be set high enough to
obey the output compliance voltage specification. If the load is
unknown, use the external +VSENSE input to the ADC to monitor
the VIOUT pin in current mode to determine the user
programmable value at which to set VDPC+.
DC-to-DC Converter Settling Time
When in DPC current mode, the settling time is dominated by the
dc-to-dc converter settling time and is typically 200 μs without
the digital slew rate control feature enabled. To reduce initial
VIOUT waveform overshoot without adding a capacitor on VIOUT
and thereby affecting HART operation, enable the digital slew
rate control feature by using the DAC_CONFIG register (see
Table 33 for bit descriptions).
Table 11 shows the typical settling time for each dc-to-dc
converter mode. All values shown assume the component uses
recommended by Analog Devices, Inc. (see in Table 10). The
achievable settling time in any given application is dependent on
the choice of external inductor and capacitor components, as
well as the dc-to-dc converter current-limit setting.
Table 11. Settling Time vs. DC-to-DC Converter Mode
DC-to-DC Converter Mode
DPC Current Mode
PPC Current Mode
DPC Voltage Mode
Settling Time (μs)
200
15
15
DC-to-DC Converter Inductor Selection
For typical 4 mA to 20 mA applications, a 47 μH inductor
(shown in Table 10), combined with the 500 kHz switching
frequency, drives up to 24 mA into a load resistance of up to 1 kΩ
with a greater than 24 V + headroom AVDD1 supply. It is
important to ensure that the peak current does not cause the
inductor to saturate, especially at the maximum ambient
temperature. If the inductor enters saturation mode, a decrease
in efficiency results. Larger size inductors translate to lower core
losses. The slew rate control feature of the AD5753 can limit
peak currents during slewing. Program an appropriate current
limit via the DCDC_CONFIG2 register to shut off the internal
switch if the inductor current reaches that limit.
DC-to-DC Converter Input and Output Capacitor Selection
The output capacitor, CDCDC, affects the ripple voltage of the
dc-to-dc converter and limits the maximum slew rate at which
the output current can rise. The ripple voltage is directly related
to the output capacitance. The CDCDC capacitor recommended by
Analog Devices (see Table 10), combined with the recommended
47 μH inductor, results in a 500 kHz ripple with an amplitude
less than 50 mV and a guaranteed stability and operation with
HART capability across all operating modes.
For high voltage capacitors, the capacitor size is often an
indication of the charge storage ability. It is important to
characterize the dc bias voltage vs. the capacitance curve for this
capacitor. Any specified capacitance values reference a dc bias
corresponding to the maximum VDPC+ and VDPC− voltage in the
application. The capacitor temperature range, as well as the
voltage rating, must be considered for a given application. These
considerations are key when selecting the components
described in Table 10.
The input capacitor, CIN, provides much of the dynamic current
required for the dc-to-dc converter (see Table 10 for details),
and a low effective series resistance (ESR) component is
recommended as the input capacitor. For the AD5753, it is
recommended to use a low ESR tantalum or ceramic capacitor of
4.7 μF (1206 size) in parallel with a 0.1 μF (0402 size) capacitor.
Ceramic capacitors must be chosen carefully because they can
exhibit an increased sensitivity to dc bias voltages and temperature.
X5R or X7R dielectrics are preferred because these capacitors
remain stable over wider operating voltage and temperature
ranges. Take care if selecting a tantalum capacitor to ensure a low
ESR value.
CLKOUT
The AD5753 provides a CLKOUT signal to the system for
synchronization purposes. This signal is programmable to eight
frequency options between 416 kHz and 588 kHz with the default
option being 500 kHz, the same switching frequency of the dcto-dc converter. This feature is configured in the GP_CONFIG1
register and is disabled by default
INTERDIE 3-WIRE INTERFACE
A 3-wire interface facilitates communication between the two
die in the AD5753. The 3-wire interface master is located on the
main die and the 3-wire interface slave is on the dc-to-dc die.
The three interface signals are data, DCLK (running at
MCLK/8), and interrupt.
The main purpose of the 3-wire interface is to read from or write
to the DCDC_CONFIG1 and DCDC_CONFIG2 registers.
Addressing these registers via the SPI interface initiates an internal
3-wire interface transfer from the main die to the dc-to-dc die. The
Rev. 0 | Page 35 of 72
AD5753
Data Sheet
For every 3-wire interface write, an automatic read and compare
process can be enabled (default case) to ensure that the contents of
the copy of the main die DCDC_CONFIGx registers match the
contents of the registers on the dc-to-dc die. This comparison is
performed to ensure the integrity of the digital circuitry on the
dc-to-dc die. With this feature enabled, a 3-wire interface (3WI)
transfer takes approximately 300 μs. When disabled, this
transfer time reduces to 30 μs.
The BUSY_3WI flag in the DCDC_CONFIG2 register is asserted
during the 3-wire interface transaction. The BUSY_3WI flag is also
set when the user updates the DAC range via the range bits
(Bits[3:0]) in the DAC_CONFIG register due to the internal
calibration memory refresh caused by this action, which requires a
3-wire interface transfer between the two die. A write to either
of the DCDC_CONFIGx registers must not be initiated while
BUSY_3WI is asserted. If a write occurs while BUSY_3WI is
asserted, the new write is delayed until the current 3-wire
interface transfer completes.
VOLTAGE OUTPUT
Voltage Output Amplifier and ±VSENSE Functionality
The voltage output amplifier is capable of generating both unipolar
and bipolar output voltages. The amplifier is also capable of driving
a 1 kΩ load in parallel with 2 μF with an external compensation
capacitor to AGND. Figure 79 shows the voltage output driving
a load, RLOAD, on top of a common-mode voltage (VCM) of ±10 V.
An integrated 2 MΩ resistor ensures that the amplifier loop is
kept closed and prevents potentially large and destructive
voltages on the VIOUT due to the broken amplifier loop in
applications where a cable may become disconnected from
+VSENSE. If remote sensing of the load is not required, connect
+VSENSE directly to VIOUT and connect −VSENSE directly to AGND via
1 kΩ series resistors.
+VSENSE
AD5753
16-BIT
DAC
VOUT
RANGE
SCALING
2MΩ
VIOUT
–VSENSE
2MΩ
RLOAD
±10V VCM
Figure 79. Voltage Output
3-Wire Interface Diagnostics
Driving Large Capacitive Loads
Any faults on the dc-to-dc die trigger an interrupt to the main
die and an automatic status read of the dc-to-dc die is performed.
After the read transaction, the main die retains a copy of the dc-todc die status bits (VIOUT_OV_ERR, DCDC_P_SC_ERR, and
DCDC_P_PWR_ERR). These values are available in both the
ANALOG_DIAG_RESULTS register, and via the OR’ed analog
diagnostic results bits in the status register. These bits also
trigger the FAULT pin.
The voltage output amplifier is capable of driving capacitive
loads of up to 2 μF with the addition of a 220 pF nonpolarized
compensation capacitor. This capacitor, though allowing the
AD5753 to drive higher capacitive loads and reduce overshoot,
increases the device settling time and, therefore, negatively
affects the bandwidth of the system. Without the compensation
capacitor, capacitive loads of up to 10 nF can be driven.
In response to the interrupt request, the main die (master)
performs a 3-wire interface read operation to read the dc-to-dc
die status. The interrupt is only asserted again by a subsequent dcto-dc die fault flag, upon which the 3-wire interface initiates
another status read transaction. If an interrupt signal is detected
six times in a row, the interrupt detection mechanism is disabled
until a 3-wire interface write transaction completes. This disabling
prevents the 3-wire interface from being blocked because of the
constant dc-to-dc die status reads when the interrupt is toggling.
The INTR_SAT_3WI flag in the DCDC_CONFIG2 register
indicates when this event occurs, and a write to either DCDC_
CONFIGx register resets this bit to 0.
During a 3-wire read or write operation, the address and data bits
in the transaction produce parity bits. These parity bits are checked
on the receive side and if the bits do not match on both die, the
ERR_3WI bit in the DIGITAL_DIAG_RESULTS register is set.
If the read and compare process is enabled and a parity error
occurs, the 3WI_RC_ERR bit in the DIGITAL_DIAG_ RESULTS
register is also set.
Voltage Output Short-Circuit Protection
Under normal operation, the voltage output sinks and sources
up to 12 mA and maintains specified operation. The shortcircuit current is typically 16 mA. If a short circuit is detected,
the FAULT pin goes low and the VOUT_SC_ERR bit in the
ANALOG_DIAG_RESULTS register is set.
FAULT PROTECTION
The AD5753 incorporates a line protector on the VIOUT pin, the
+VSENSE and −VSENSE pins. The line protector operates by clamping
the voltage internal to the line protector to the VDPC+ and VDPC−
rails, thus protecting the internal circuitry from external voltage
faults. If a voltage outside of these limits is detected on the
VIOUT pin, an error flag (VIOUT_OV_ERR) located in the
ANALOG_DIAG_RESULTS register is set.
Rev. 0 | Page 36 of 72
17285-121
3-wire interface master on the main die initiates writes and
reads to and from the registers on the dc-to-dc die using DCLK
as the serial clock. The slave uses an interrupt signal to the dcto-dc die to indicate that a read of the dc-to-dc die internal
status register is required.
Data Sheet
AD5753
CURRENT OUTPUT
IOUT
RANGE
SCALING
16-BIT
DAC
As shown in Figure 74, RSET is an internal sense resistor that forms
part of the voltage to current conversion circuitry. The stability
of the output current value over temperature is dependent on
the stability of the RSET value. To improve the output current
over temperature stability, connect an external 13.7 kΩ, low
drift resistor, instead of the internal resistor, between the RA and
RB pins of the AD5753.
Table 1 shows the AD5753 performance specifications with both
the internal RSET resistor and an external 13.7 kΩ RSET resistor. The
external RSET resistor specification assumes an ideal resistor. The
actual performance depends on the absolute value and
temperature coefficient of the resistor used. Therefore, the
resistor specifications directly affect the gain error of the output
and the TUE.
To arrive at the absolute worst case overall TUE of the output
with a particular external RSET resistor, add the percentage of the
RSET resistor absolute error (the absolute value of the error) to
the TUE of the AD5753 that is using the external RSET resistor
shown in Table 1 (expressed in % FSR). Consider the temperature
coefficient as well as the specifications of the external reference,
if this is the option being used in the system.
The magnitude of the error, derived from summing the absolute
error and TC error of the external RSET resistor and external
reference with the AD5753 TUE specification, is unlikely to
occur because the TC values of the individual components are
unlikely to exhibit the same drift polarity and, therefore, an
element of cancelation occurs. For this reason, add the TC
values with a root of squares method. A further improvement of
the TUE specification is gained by performing a two point
calibration at zero scale and full scale, thus reducing the absolute
errors of the voltage reference and the RSET resistor.
Current Output Open-Circuit Detection
When in current output mode, if the available headroom falls
below the compliance range due to an open-loop circuit or an
insufficient power supply voltage, the IOUT_OC_ERR flag in
the ANALOG_DIAG_RESULTS register is asserted and the
FAULT pin goes low.
CHART
HART_EN
Figure 80 shows the recommended circuit for attenuating and
coupling the HART signal into the AD5753. To achieve 1 mA p-p
at the VIOUT pin, a signal of approximately 125 mV p-p is required
at the CHART pin. The HART signal on the VIOUT pin is inverted
relative to the signal input at the CHART pin.
C1
C2
HART MODEM
OUTPUT
Figure 80. Coupling the HART Signal
As well as their use in attenuating the incoming HART modem
signal, a minimum capacitance of the C1 and C2 capacitors is
required to ensure the bandwidth presented to the modem
output signal allows the 1.2 kHz and 2.2 kHz frequencies through
the capacitor. Assuming a HART signal of 500 mV p-p, the
recommended values are C1 = 47 nF and C2 = 150 nF. Digitally
controlling the output slew rate is necessary to meet the analog
rate of change requirements for HART.
If the HART feature is not required, disable the HART_EN bit
and leave the CHART pin open circuit. However, if the DAC
output signal must be slowed with a capacitor, the HART_EN bit
must be enabled and the required CSLEW capacitor must be
connected to the CHART pin.
DIGITAL SLEW RATE CONTROL
The AD5753 slew rate control feature allows the user to control the
rate at which the output value changes. This feature is available in
both current and voltage mode. Disabling the slew rate control
feature changes the output value at a rate limited by the output
drive circuitry and the attached load. To reduce the slew rate,
enable the slew rate control feature. Enabling this feature causes
the output to digitally step from one output code to the next at a
rate defined by two parameters accessible via the DAC_CONFIG
register. These two parameters are SR_CLOCK and SR_STEP.
SR_CLOCK and SR_STEP define the rate at which the digital
slew is updated. For example, if the selected update rate is 8 kHz,
the output updates every 125 µs. In conjunction with SR_CLOCK,
SR_STEP defines by how much the output value changes at each
update. Together, both parameters define the rate of change of the
output value.
The following equation describes the slew rate as a function of
the step size, the slew rate frequency, and the LSB size:
Slew Time =
HART CONNECTIVITY
The AD5753 has a CHART pin onto which a HART signal can be
coupled. The HART signal appears on the current output if the
HART_EN bit in the GP_CONFIG1 register as well as the VIOUT
output is enabled.
IOUT
17285-027
External Current Setting Resistor
Output Change
Step Size × Slew Rate Frequency × LSB Size
where:
Slew Time is expressed in seconds.
Step Size is the change in output.
Output Change is expressed in amps for current output mode or
volts for voltage output mode.
Slew Rate Frequency is SR_CLOCK.
LSB Size is SR_STEP.
When the slew rate control feature is enabled, all output changes
occur at the programmed slew rate. For example, if the WDT times
out and an automatic clear occurs, the output slews to the clear
value at the programmed slew rate. However, setting the
Rev. 0 | Page 37 of 72
AD5753
Data Sheet
CLEAR_NOW_EN bit in the GP_CONFIG1 register overrides
this default behavior and causes the output to immediately update
to the clear code, rather than at the programmed slew rate.
The slew rate frequency for any given value is the same for all
output ranges. The step size, however, varies across output
ranges for a given value of step size because the LSB size is
different for each output range.
clears the SPI_CRC_ERR bit and causes the FAULT pin to return
high, assuming that there are no other active faults. When
configuring the FAULT_PIN_CONFIG register, the user decides
whether the SPI CRC error affects the FAULT pin. See the
FAULT Pin Configuration Register section for further details.
The SPI CRC feature is used for both transmitting and receiving
data packets.
ADDRESS PINS
UPDATE ON SYNC HIGH
SYNC
SCLK
MSB
D23
SDI
SPI Interface and Diagnostics
The AD5753 is controlled over a 4-wire serial interface with an
8-bit cyclic redundancy check (CRC-8) that is enabled by
default. The input shift register is 32 bits wide and data is
loaded into the device MSB first under the control of a serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
If CRC is disabled, the serial interface is reduced to 24 bits. A
32-bit frame is still accepted but the last 8 bits are ignored.
[D30:D29]
AD5753
address
[D28:D24]
Register address
[D23:D8]
Data
24-BIT DATA
24-BIT DATA TRANSFER—NO CRC ERROR CHECKING
UPDATE ON SYNC HIGH
ONLY IF CRC CHECK PASSED
SYNC
SCLK
MSB
D31
Table 12. Writing to a Register (CRC Enabled)
MSB
D31
Slip Bit
LSB
D0
LSB
D8
SDI
LSB
[D7:D0]
CRC
D7
24-BIT DATA
D0
8-BIT CRC
FAULT PIN GOES LOW
IF CRC CHECK FAILS
FAULT
32-BIT DATA TRANSFER WITH CRC ERROR CHECKING
As shown in Table 12, every SPI frame contains two address
bits. These bits must match the AD0 and AD1 pins for a particular
device to accept the SPI frame on the bus.
SPI Cyclic Redundancy Check
To verify that data is correctly received in noisy environments,
the AD5753 offers a CRC based on a CRC-8. The device, either a
micro or a field-programmable gate array (FPGA), controlling the
AD5753 generates an 8-bit frame check sequence by using the
following polynomial:
C(x) = x8 + x2 + x1 + 1
This 8-bit frame check sequence is added to the end of the dataword and 32 bits are sent to the AD5753 before taking SYNC high.
If the SPI_CRC_EN bit is set high (default state), the user must
supply a frame that is exactly 32 bits wide that contains the 24 data
bits and the 8-bit CRC. If the CRC check is valid, the data is written
to the selected register. If the CRC check fails, the data is ignored,
the FAULT pin goes low, and the FAULT pin status bit and digital
diagnostic status bit (DIG_DIAG_STATUS) in the status register
are asserted. A subsequent readback of the DIGITAL_DIAG_
RESULTS register shows that the SPI_CRC_ERR bit is also set.
This register is per individual bits, a write one per bit clears the
register (see the Sticky Diagnostic Results Bits section for more
details). Therefore, the SPI_CRC_ERR bit is cleared by writing a 1
to Bit D0 of the DIGITAL_DIAG_RESULTS register. Writing a 1
Figure 81. CRC Timing (Assume LDAC = 0)
SPI Interface Slip Bit
Adding the slip bit enhances the interface robustness. The MSB
of the SPI frame must equal the inverse of MSB − 1 for the frame to
be considered valid. If an incorrect slip bit is detected, the data
is ignored and the SLIPBIT_ERROR bit in the DIGITAL_
DIAG_RESULTS register is asserted.
SPI Interface SCLK Count Feature
An SCLK count feature is also built into the SPI diagnostics,
meaning that only SPI frames with exactly 32 SCLK falling
edges (24 if SPI CRC is disabled) are accepted by the interface
as a valid write. SPI frames lengths other than 32 are ignored
and the SCLK_COUNT_ERR flag asserts in the DIGITAL_
DIAG_RESULTS register.
Readback Modes
The AD5753 offers the following four readback modes:
Rev. 0 | Page 38 of 72
Two-stage readback mode
Autostatus readback mode
Shared SYNC autostatus readback mode
Echo mode
17285-025
The AD5753 address pins (AD0 and AD1) are used in conjunction
with the address bits within the SPI frame (see Table 12) to
determine which AD5753 device is being addressed by the system
controller. With the two address pins, up to four devices can be
independently addressed on one board.
Data Sheet
AD5753
The two-stage readback consists of a write to a dedicated
register, TWO_STAGE_READBACK_SELECT, to select the
register location to be read back. This write is followed by a no
operation (NOP) command during which the contents of the
selected register are available on the SDO pin.
Table 13. SDO Contents for Read Operation
MSB
[D31:D30] D29
[D28:24]
0b10
FAULT pin status Register address
LSB
[D23:D8] [D7:D0]
Data
CRC
Bits[D31:D30] = 0b10 are used for synchronization purposes
during readback.
If autostatus readback mode is selected, the contents of the status
register are available on the SDO line during every SPI transaction.
This feature allows the user to continuously monitor the status
register and to act quickly if a fault occurs. The AD5753 powers up
with this feature disabled. When this feature is enabled, the
normal two-stage readback feature is not available. Only the
status register is available on SDO. To read back other registers,
first disable the automatic readback feature before following the
two-stage readback sequence. The automatic status readback
can be reenabled after the register is read back.
The shared AD5753 SYNC autostatus readback is a special
version of the autostatus readback mode used to avoid SDO bus
contention when multiple devices share the same SYNC line.
Echo mode behaves similarly to autostatus readback mode,
except that every second readback consists of an echo (a
repetition) of the previous command written to the AD5753
(see Figure 82). See the Reading from Registers section for
further details on the readback modes.
STATUS
REGISTER
CONTENTS
PREVIOUS
COMMAND
Figure 82. SDO Contents, Echo Mode
WDT
The WDT feature ensures that communication is not lost between
the system controller and the AD5753, and that the SPI
datapath lines function as expected.
When enabled, the WDT alerts the system if the AD5753 has not
received a specific SPI frame in the user programmable timeout
period. When the specific SPI frame is received, the watchdog
resets the timer controlling the timeout alert. The SPI frame
used to reset the WDT is configurable as one of the two
following choices:
After the active WDT fault flag clears, the WDT restarts by
performing a subsequent WDT reset command.
On power-up, the WDT is disabled by default. The default
timeout setting is 1 sec. The default method to reset the WDT is
to write one specific key. On timeout, the default action is to set
the relevant WDT_ERR flag bits and the FAULT pin. See Table 42
for the specific register bit details to support the configurability of
the WDT operation.
USER DIGITAL OFFSET AND GAIN CONTROL
The AD5753 has a USER_GAIN register and a USER_OFFSET
register that trim the gain and offset errors from the entire signal
chain. The 16-bit USER_GAIN register allows the user to adjust the
gain of the DAC channel in steps of 1 LSB. The USER_GAIN
register coding is straight binary, as shown in Table 14. The default
code in the USER_GAIN register is 0xFFFF, which results in a no
gain factor applied to the programmed output. In theory, the gain
can be tuned across the full range of the output. In practice, the
maximum recommended gain trim is approximately 50% of the
programmed range to maintain accuracy.
Table 14. Gain Register Adjustment
17285-019
PREVIOUS
COMMAND
timeout event, regardless if Bit 10 or Bit 9 is enabled, a dedicated
WDT_STATUS bit in the status register, as well as a WDT_ERR bit
in the DIGITAL_DIAG_RESULTS register, alerts the user that the
WDT is timed out. After a WDT timeout occurs, all writes to the
DAC_INPUT register, as well as the hardware or software LDAC
events, are ignored until the active WDT fault flag within the
DIGITAL_DIAG_RESULTS register clears.
A specific key code write to the key register (default).
A valid SPI write to any register.
When a watchdog timeout event occurs, there are two user
configurable actions the AD5753 takes. The first is to load the
DAC output with a user defined clear code stored in the
CLEAR_CODE register. The second is to perform a software
reset. These two actions can be enabled via Bit 10 and Bit 9,
respectively, in the WDT_CONFIG register. On a watchdog
Gain Adjustment Factor
1
65,535/65,536
…
2/65,536
1/65,536
D15
1
1
…
0
0
[D14:D1]
1
1
…
0
0
D0
1
0
…
1
0
The 16-bit USER_OFFSET register allows the user to adjust the
offset of the DAC channel from −32,768 LSBs to +32,768 LSBs
in steps of 1 LSB. The USER_OFFSET register coding is straight
binary, as shown in Table 15. The default code in the USER_
OFFSET register is 0x8000, which results in zero offset
programmed to the output.
Table 15. Offset Register Adjustment
Gain Adjustment
+32,768 LSBs
+32,767 LSBs
…
No Adjustment (Default)
…
−32,767 LSBs
−32,768 LSBs
Rev. 0 | Page 39 of 72
D15
1
1
…
1
…
0
0
[D13:D2]
1
1
…
0
…
0
0
D0
1
0
…
0
…
1
0
AD5753
Data Sheet
The decimal value that is written to the internal DAC register
(DAC code) is calculated with the following equation:
( M + 1)
+ C − 215
216
where:
D is the code loaded to the DAC_INPUT register.
M is the code in the USER_GAIN register (default code = 216 − 1).
C is the code in the USER_OFFSET register (default code = 215).
Data from the DAC_INPUT register is processed by a digital
multiplier and adder and both are controlled by the contents of
the user gain and user offset registers, respectively. The calibrated
DAC data is then loaded to the DAC. The loading of the DAC data
is dependent on the state of the LDAC pin.
Each time data is written to the USER_GAIN or USER_
OFFSET register, the DAC output is not automatically updated.
Instead, the next write to the DAC_INPUT register uses these
user gain and user offset values to perform a new calibration
Both the USER_GAIN register and the USER_OFFSET register
have 16 bits of resolution. The correct method to calibrate the
gain and offset is to first calibrate the gain and then calibrate the
offset.
DAC OUTPUT UPDATE AND DATA INTEGRITY
DIAGNOSTICS
Figure 83 shows a simplified version of the DAC input loading
circuitry. If used, the USER_GAIN and USER_OFFSET registers
must be updated before writing to the DAC_INPUT register.
REFIN
OUTPUT
AMPLIFIER
DAC OUTPUT
REGISTER
(READ ONLY)
16-BIT
DAC
VIOUT
LDAC
(HARDWARE OR SOFTWARE)
CLEAR EVENT
(WDT TIMEOUT)
USER
GAIN AND OFFSET
CALIBRATION
CLEAR CODE
REGISTER
SCLK
SYNC
SDI
DAC INPUT
REGISTER
INTERFACE LOGIC
Figure 83. Simplified Serial Interface of Input Loading Circuitry
Rev. 0 | Page 40 of 72
SDO
17285-026
DAC code = D ×
and to automatically update the output channel. The read only
DAC_OUTPUT register represents the value currently available at
the DAC output, except in the case of user gain and user offset
calibration. In this case, the DAC_OUTPUT register contains
the DAC data input by the user, on which the calibration is
performed and not the result of the calibration.
Data Sheet
AD5753
•
•
•
•
If a write is performed to the DAC_INPUT register with
the hardware LDAC pin tied low, the DAC_OUTPUT
register is updated on the rising edge of SYNC and is
subject to the timing specifications shown in Table 2.
If the hardware LDAC pin is tied high and the DAC_INPUT
register is written to, the DAC_OUTPUT register does not
update until a software LDAC instruction is issued or the
hardware LDAC pin is pulsed low.
If a WDT timeout occurs with the CLEAR_ON_WDT_
FAIL bit set, the CLEAR_CODE register contents are
loaded into the DAC_OUTPUT register.
If the slew rate control feature is enabled, the DAC_
OUTPUT register contains the dynamic value of the DAC
as the register slews between values.
While a WDT fault is active, all writes to the DAC_
INPUT register, as well as hardware or software LDAC events,
are ignored. If the CLEAR_ON_WDT_FAIL bit is set such that
the output is set to the clear code, after the WDT fault flag clears,
the DAC_INPUT register must be written to before the DAC_
OUTPUT register updates. The DAC_INPUT register must be
written to because performing a software or hardware LDAC
only reloads the DAC with the clear code. As described in this
section, after configuring the DAC range via the DAC_CONFIG
register, the DAC_INPUT register must be written to, even if the
contents of the DAC_INPUT register are not changing from the
current value.
The GP_CONFIG2 register contains a bit to enable a global
software LDAC mode, which ignores the device under test
(DUT) address bits of the SW_LDAC command, thus enabling
multiple AD5753 devices to be simultaneously updated by using
a single SW_LDAC command. This feature is useful if the
hardware LDAC pin is not being used in a system containing
multiple AD5753 devices.
DAC Data Integrity Diagnostics
To protect against transient changes to the internal digital
circuitry, the digital block stores both the digital DAC value and
an inverted copy of the digital DAC value. A check is completed
to ensure that the two values correspond to each other before the
DAC is strobed to update to the DAC code. This matching feature
is enabled by default via the INVERSE_DAC_
CHECK_EN bit in the DIGITAL_DIAG_CONFIG register.
Outside of the digital block, the DAC code is stored in latches,
as shown in Figure 84. These latches are potentially vulnerable
to the same transient events that affect the digital block. To
protect the DAC latches against such transients, enable the DAC
latch monitor feature via the DAC_LATCH_MON_EN bit
within the DIGITAL_DIAG_CONFIG register. This latch monitor
feature monitors the actual digital code driving the DAC and
compares the code with the digital code generated within the
digital block. Any difference between the two codes sets the
DAC_LATCH_MON_ERR flag in the DIGITAL_
DIAG_RESULTS register.
DAC LATCHES
DIGITAL
BLOCK
D
Q
D
Q
16-BIT
DAC
Q
Q
17285-028
The DAC_OUTPUT register, and ultimately the DAC output,
updates in any of the following cases:
Figure 84. DAC Data Integrity
GPIO PINS
The AD5753 provides the following three GPIO pins: GPIO_0,
GPIO_1, and GPIO_2. Using the GP_CONFIG register, each of
these pins can be configured as a digital output, a digital input,
or as a 100 kΩ to DGND (default). When configured as a digital
input or output, the GPIO_DATA register is used to read or
write from or to the relevant pins.
USE OF KEY CODES
Key codes are used via the key register for the following
functions (see the Key Register section for full details):
•
•
•
•
Initiating calibration memory refresh.
Initiating a software reset.
Initiating a single ADC conversion.
WDT reset key.
Using specific keys to initiate actions such as a calibration
memory refresh or a device reset provides extra system
robustness because the keys reduce the probability of either task
being initiated in error.
SOFTWARE RESET
A software reset requires two consecutive writes of 0x15FA and
0xAF51 respectively to the key register. A device reset can be
initiated via the hardware RESET pin, the software reset keys, or
automatically after a WDT timeout (if configured to do so). The
RESET_OCCURRED bit in the DIGITAL_DIAG_RESULTS
register is set when the device is reset. This RESET_OCCURRED
bit defaults to 1 on power-up. Both of the diagnostic results
registers implement a write 1 to clear the function that is, a 1
must be written to this bit to clear it (see the Sticky Diagnostic
Results Bits section).
CALIBRATION MEMORY CRC
For every calibration memory refresh cycle, which is either
initiated via a key code write to the key register or automatically
initiated when the Range[3:0] bits of the DAC_CONFIG register, is
changed, an automatic CRC is calculated on the contents of the
calibration memory shadow registers. The result of this CRC is
compared with the factory stored reference CRC value. If the
CRC values match, the read of the entire calibration memory is
considered valid. If the values do not match, the CAL_MEM_
CRC_ERR bit in the DIGITAL_DIAG_RESULTS register is set
to 1. This calibration memory CRC feature is enabled by default
and can be disabled via the CAL_MEM_CRC_EN bit in the
DIGITAL_DIAG_CONFIG register.
Rev. 0 | Page 41 of 72
AD5753
Data Sheet
Two-stage readback commands are permitted while this
calibration memory refresh cycle is active. However, a write to any
register other than the TWO_STAGE_READBACK_SELECT
register or the NOP register sets the INVALID_SPI_ACCESS_
ERR bit in the DIGITAL_DIAG_RESULTS register. As described
in the Programming Sequence to Enable the Output section, a
wait period of 500 µs is recommended after a calibration
memory refresh cycle is initiated.
INTERNAL OSCILLATOR DIAGNOSTICS
An internal frequency monitor uses the internal MCLK to
increment a 16-bit counter at a rate of 1 kHz (MCLK/10,000).
The counter value can be read in the FREQ_MONITOR register.
The user can poll this register periodically and use it as a diagnostic
tool for the internal oscillator (to monitor that the oscillator is
running), and to measure the oscillator frequency. This counter
feature is enabled by default via the FREQ_MON_EN bit in the
DIGITAL_DIAG_CONFIG register.
If the MCLK stops, the AD5753 sends a specific code of
0x07DEAD to the SDO line for every SPI frame. This oscillator
dead code feature is enabled by default and is disabled by clearing
the OSC_STOP_DETECT_EN bit in the GP_CONFIG1 register.
This feature is limited to the maximum readback timing
specifications described in Table 3.
STICKY DIAGNOSTIC RESULTS BITS
The AD5753 contains the following two diagnostic results
registers: digital and analog (see Table 47 and Table 48, respectively
for the diagnostic error bits). The diagnostic result bits contained
within these registers are sticky (R/W-1-C), that is, each bit needs
a 1 to be written to it to clear the error bit. However, if the fault
is still present, even after writing a 1 to the bit in question, the error
bit does not clear to 0. Upon writing Logic 1 to the bit, it updates to
the latest value, which is Logic 1 if the fault is still present and
Logic 0 if the fault is no longer present.
These are the two following exceptions to this R/W-1-C access
within the DIGITAL_DIAG_RESULTS register: CAL_MEM_
UNREFRESHED and SLEW_BUSY. These flags automatically
clear when the calibration memory refreshes or the output slew
is complete.
The status register contains a DIG_DIAG_STATUS and
ANA_DIAG_STATUS bit and both bits are the result of a
logical OR of the diagnostic results bits contained in each
diagnostic results registers. All analog diagnostic flag bits are
included in the logical OR of the ANA_DIAG_STATUS bit and
all digital diagnostic flag bits, with the exception of the SLEW_
BUSY bit, are included in the logical OR of the DIG_DIAG_
STATUS bit. The OR’ed bits within the status register are read
only and not sticky (R/W-1-C).
BACKGROUND SUPPLY AND TEMPERATURE
MONITORING
Excessive die temperature and overvoltage are known to be related
to common cause failures. These conditions can be monitored
in a continuous fashion by using comparators, which eliminates the
requirement to poll the ADC.
Both die have a built-in temperature sensor with a ±5oC accuracy.
The die temperature is monitored by a comparator and the
background temperature comparators are permanently enabled.
Programmable trip points corresponding to 142°C, 127°C,
112°C, and 97°C can be configured in the GP_CONFIG1 register.
If the temperature of either die exceeds the programmed limit, the
relevant status bit in the ANALOG_DIAG_RESULTS register is set
and the FAULT pin is asserted low.
The low voltage supplies on the AD5753 are monitored via low
power static comparators. This monitoring function is disabled
by default and is enabled via the COMPARATOR_CONFIG bits
in the GP_CONFIG2 register. The INT_EN bit in the
DAC_CONFIG register must be set for the REFIN buffer to be
powered up and for this node to be available to the REFIN
comparator. The monitored nodes are REFIN, REFOUT, VLDO,
and INT_AVCC. There is a status bit in the ANALOG_DIAG_
RESULTS register that corresponds to each monitored node. If
any of the monitored node supplies exceed the upper or lower
threshold values (see Table 16 for the threshold values), the
corresponding status bit is set. Note that if a REFOUT fault
occurs, the REFOUT_ERR status bit is set. The INT_AVCC,
VLDO, and temperature comparator status bits can then also be set
because REFOUT is used as the comparison voltage for these
nodes. Like all the other status bits in the ANALOG_DIAG_
RESULTS register, these bits are sticky and need a 1 to be written to
them to clear them, assuming that the error condition is
subsided. If the error condition is still present, the flag remains high
even after a 1 is written to clear it.
Table 16. Comparator Supply Activation Thresholds
Supply
INT_AVCC
VLDO
REFIN
REFOUT
Lower
Threshold (V)
3.8
2.8
2.24
2.24
Nominal
Value/Range (V)
4 to 5
3 to 3.6
2.5
2.5
Upper
Threshold (V)
5.2
3.8
2.83
2.83
OUTPUT FAULT
The AD5753 is equipped with a FAULT pin. This pin is an active
low, open-drain output that connects several AD5753 devices
together to one pull-up resistor for global fault detection. This pin
is high impedance when no faults are detected and is asserted
low when certain faults, such as an open circuit in current
mode, a short circuit in voltage mode, a CRC error, or an
overtemperature error, are detected. Table 17 shows the fault
conditions that automatically force the FAULT pin active and
highlights the user maskable fault bits available via the FAULT_
PIN_CONFIG register (see Table 45). All registers contain a
Rev. 0 | Page 42 of 72
Data Sheet
AD5753
corresponding FAULT pin status bit, FAULT_PIN_STATUS, that
mirrors the inverted current state of the FAULT pin. For example, if
the FAULT pin is active, the FAULT_PIN_STATUS bit is 1.
Table 17. FAULT Pin Trigger Sources1
Fault Type
Digital Diagnostic Faults
Oscillator Stop Detect
Calibration Memory Not Refreshed
Reset Detected
3-Wire Interface Error
WDT Error
3-Wire Read and Compare Parity Error
DAC Latch Monitor Error
Inverse DAC Check Error
Calibration Memory CRC Error
Invalid SPI Access
SCLK Count Error
Slip Bit Error
SPI CRC Error
Analog Diagnostic Faults
VIOUT Overvoltage Error
DC-to-DC Short-Circuit Error
DC-to-DC Power Error
Current Output Open Circuit Error
Voltage Output Short-Circuit Error
DC-to-DC Die Temperature Error
Main Die Temperature Error
REFFOUT Comparator Error
REFIN Comparator Error
INT_AVCC Comparator Error
VLDO Comparator Error
1
2
Mapped to
FAULT Pin
Mask
Ability
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
N/A
N/A
No
Yes
No
Yes
Yes
No
Yes
No2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
No
No
The DIG_DIAG_STATUS, ANA_DIAG_STATUS, and WDT_
STATUS bits of the status register are used in conjunction with
the FAULT pin and the FAULT_PIN_STATUS bit to inform the
user which fault condition is causing the FAULT pin or which
FAULT_PIN_STATUS bit to activate.
ADC MONITORING
The AD5753 incorporates a 12-bit ADC to provide diagnostic
information on user selectable inputs such as supplies, grounds,
internal die temperatures, references, and external signals. See
Table 18 for a full list of these selectable inputs. The ADC reference
is derived from REFOUT and provides independence from the
DAC reference (REFIN) if necessary. The ADC_CONFIG
register configures the ADC mode of operation, either user
initiated individual conversions or sequence mode, and selects
the multiplexed ADC input channel via the ADC_IP_SELECT
bits (see Table 44).
ADC Transfer Function Equations
The ADC has an input range of 0 V to 2.5 V and can be used to
digitize a variety of different nodes. The set of inputs to the ADC
encompasses both unipolar and bipolar ranges, varying from
high to low voltage values. Therefore, to be able to digitize the
voltage values, the voltage ranges outside of the 0 V to 2.5 V
ADC input range must be divided down.
The ADC transfer function equation is dependent on the
selected ADC input node. See Table 18 for a summary of all
transfer function equations).
N/A means not applicable.
Although the SCLK count error cannot be masked in the FAULT_PIN_CONFIG
register, it can be excluded from the FAULT pin by enabling the SPI_DIAG_
QUIET_EN bit (Bit D3 in the GP_CONFIG1 register).
Table 18. ADC Input Node Summary
ADC_IP_SELECT
00000
VIN Node Description
Main die temperature
00001
00010
00011
00100
00101
00110
01100
01101
01110
01111
10000
10001
10010
DC-to-dc die temperature
Reserved
REFIN
Internal 1.23 V reference voltage (REF2)
Reserved
Reserved
ADC2 pin input (±15 V input range)
Voltage on the +VSENSE buffer output
Voltage on the −VSENSE buffer output
ADC1 pin input (0 – 1.25 V input range)
ADC1 pin input (0 – 0.5 V input range)
ADC1 pin input (0 – 2.5 V input range)
ADC1 pin input (± 0.5 V input range)
ADC Transfer Function
T (°C) = (−0.09369 × D) + 307 where D = ADC_CODE (the
ADC result)
T (°C) = (−0.11944 × D) + 436
Reserved
REFIN (V) = (D/212) × 2.75
REF2 (V) = (D/212) × 2.5
Reserved
Reserved
ADC2 (V) = (30 × D)/212 − 15
+VSENSE (V) = ((50 × D)/212) − 25
−VSENSE (V) = ((50 × D)/212) − 25
ADC1 (V) = D/212 × 1.25
ADC1 (V) = D/212 × 2.5 × 1/5 = D/212 × 0.5
ADC1 (V) = D/212 × 2.5
ADC1 (V) = D/212 - 0.5
Rev. 0 | Page 43 of 72
AD5753
ADC_IP_SELECT
10011
10100
10101
10110
11000
11001
11010
11011
11100
11101
11110
11111
Data Sheet
VIN Node Description
Reserved
INT_AVCC
VLDO
VLOGIC
REFGND
AGND
DGND
VDPC+
AVDD2
VDPC−
DC-to-dc die node; configured in the DCDC_CONFIG2 register
00: AGND on dc-to-dc die
01: Internal 2.5 V supply on dc-to-dc die
10: AVDD1
11: AVSS
REFOUT
AVDD2
AGND (dc-to-dc) (V) = (D/212) × 2.5
Internal 2.5 V (dc-to-dc) (V) = (D/212) × 5
AVDD1 (V) = D/212 × 37.5
AVSS (V) = (15 × D/212 − 14) × 2.5
REFOUT (V) = (D/212) × 2.5
AVDD1
AGND
POWER MANAGEMENT
BLOCK
VLDO
ADC Transfer Function
Reserved
INT_AVCC (V) = D/212 × 10
VLDO (V) = D/212 × 10
VLOGIC (V) = D/212 × 10
REFGND (V) = D/212 × 2.5
AGND (V) = D/212 × 2.5
DGND (V) = D/212 × 2.5
VDPC+ (V) = D/212 × 37.5
AVDD2 (V) = D/212 × 37.5
VDPC− (V) = (15 × D/212 − 14) × 2.5
MCLK
10MHz
POWER-ON
RESET
CALIBRATION
MEMORY
TEMPERATURE,
INTERNAL 2.5V SUPPLY,
DC-TO-DC DIE TO AGND
INT_AVCC, REF2
VLOGIC
DGND
CLKOUT
AD0
AD1
RESET
LDAC
SCLK
SDI
SYNC
SDO
FAULT
DIGITAL
BLOCK
DC-TO-DC DIE
3-WIRE INTERFACE
DATA AND
CONTROL
REGISTERS
WATCHDOG
TIMER
16
16
DAC
REG
VDPC+
16-BIT
DAC
REFOUT
RB
IOUT
RANGE
SCALING
–
USER GAIN
USER OFFSET
IOUT
RSET
VX
CHART
HART_EN
REFERENCE
BUFFERS
RA
VDPC–
STATUS
REGISTER
REFIN
PGND1
VDPC+
SW+
VDPC+
+VSENSE
REFIN
+VSENSE
VOUT
RANGE
SCALING
VIOUT
VOUT
–VSENSE
–VSENSE
VREF
CCOMP
VDPCTEMPERATURE
SENSOR
DC-TO-DC DIE
REFGND
GPIO_0
GPIO_1
GPIO_2
AD5753
12-BIT
ADC
ANALOG
DIAGNOSTICS
ADC2
AVSS
SW+
VDPC-
PGND2
17285-041
ADC1
NOTES
1. GRAY ITEMS REPRESENT DIAGNOSTIC ADC INPUT NODES.
Figure 85. Diagnostic ADC Input Nodes
Rev. 0 | Page 44 of 72
Data Sheet
AD5753
ADC Configuration
The ADC is configured using the ADC_CONFIG register via the
SEQUENCE_COMMAND bits (Bits[10:8]), the SEQUENCE_
DATA bits (Bits[7:5]), and the ADC_IP_SELECT bits (Bits[4:0]).
Table 19 shows the contents of the ADC_CONFIG register.
Table 19. ADC Configuration Register
[D10:D8]
Command
[D7:D5]
Data
it starts again with Channel 0 until disabled. Before Command
0b010 is issued, Command 000 and Command 001 must be used
to configure all the required channels to enable key sequencing
mode (see Figure 86). If the sequencing is disabled and later
reenabled, the sequencer is reset to recommence converting on
the first channel in the sequence.
Automatic Sequencing (Command 011)
[D4:D0]
ADC input select
The ADC can be set up to either monitor a single node of interest
or configured to sequence through up to eight nodes of interest.
The sequential conversions can be initiated automatically after
every valid SPI frame is received by the device (automatic sequence
mode), or in a more controlled manner via a specific key code
written to the key register (key sequence mode). When a
conversion is complete, the ADC result is available in the status
register and, if in sequence mode, the sequencer address is
advanced. If autostatus readback mode is used in conjunction with
either sequence mode, the last completed ADC conversion data is
available on the SDO during every SPI frame written to the device.
The sequencer command has a maximum channel depth of
eight channels. Each channel in the sequencer must be configured
with the required ADC input for that sequencer channel via the
ADC_IP_SELECT bits. The number of configured channels must
equal the channel depth. If the active sequencer channel location is
not configured correctly, the sequencer stores the previously
loaded channel value and defaults all other enabled sequencer
channels 0b00000 for all sequencer channels. To avoid any 3-wire
interface related delays between ADC conversions if a dc-to-dc die
node is required to be part of the ADC sequencer, perform this
configuration using the DCDC_ADC_CONTROL_DIAG bits in
the DCDC_CONFIG2 register before configuring the ADC
sequencer. If multiple nodes from the dc-to-dc die are required
within the sequence, key sequencing mode must be used rather
than automatic sequencing mode because the DCDC_ADC_
CONTROL_DIAG bits must be updated between ADC
conversions to configure the next dc-to-dc die node required by the
sequence.
The four ADC modes of operation are key sequencing,
automatic sequencing, single immediate conversion, and single
key conversion. The sequencing modes are mutually exclusive so if
the key sequencing mode is enabled, it disables the automatic
sequencing mode and vice versa.
Key Sequencing (Command 010)
Writing Command 010 to the command bits in the ADC_
CONFIG register enables key sequencing mode. Key sequencing
starts with a write to the key register with Key Code 0x1 ADC and
starts on Channel 0, continuing to Channel N – 1, where N is
the channel depth with every 0x1ADC command. This mode
enables users to control channel switching during sequencing
because the switch only occurs every specific key code command,
rather than for every valid SPI frame, which occurs in
automatic sequencing mode. When the sequence is completed,
Sequencing starts on the next valid SPI frame and starts with
Channel 0, continuing to Channel N − 1 where N is the channel
depth on every valid SPI frame. When the sequence is complete, it
starts again with Channel 0 until disabled. As with the key
sequencing mode, before Command 011 is issued, Command 000
and Command 001 must be used to configure all the required
channels to enable automatic sequencing mode (see Figure 86). If
the sequencing is disabled and later reenabled, the sequencer is
reset to recommence converting on the first channel in the
sequence. When reenabled, the channels do not need to be
reconfigured unless the desired list of nodes changes. Use
automatic sequencing in conjunction with the autostatus
readback mode to ensure that the latest ADC result is available.
Single Immediate Conversion (Command 100)
Single immediate conversion mode initiates a single conversion
on the node currently selected in the ADC_IP_SELECT bits of the
ADC_CONFIG register. Selecting this command stops any active
automatic sequence, which means the sequencer must be reenabled
if required. The sequencer does not need to be reconfigured
because the configuration of the sequencer depth and channels
is stored.
Single Key Conversion (Command 101)
Single key conversion mode sets up an individual ADC input
node to be converted when the user initiates the mode by
writing the 0x1ADC key code to the key register.
Sequencing Mode Setup
A list of the relevant ADC sequencer commands are shown in
Table 20. These commands are available in the ADC_CONFIG
register; see Table 44 for the ADC_CONFIG register bits. The
default depth (000) is equivalent to one diagnostic channel up to a
binary depth value of 111, which is equivalent to eight channels.
Table 20. Command Bits
Value
000
001
010
011
100
101
Rev. 0 | Page 45 of 72
Description
Set the sequencer depth (0 to 7)
Load the sequencer Channel N with the selected ADC
input
Enable or disable key sequencer
Enable or disable automatic sequencer
Perform a single conversion on the currently selected
ADC input
Set up single key conversion, that is, select the ADC mux
input to be used when the 0x1ADC key is written with a
write to the key register (this conversion is outside of the
key sequencing mode)
AD5753
Data Sheet
Use the following procedure to set up the sequencer:
1.
2.
3.
Select the depth.
Load the channels to the sequencer N times for N channels.
Enable the sequencer. Enabling the sequencer also starts
the first conversion.
An example of configuring the sequencer to monitor three
ADC nodes is shown in Figure 86.
SELECT A DEPTH OF 3 CHANNELS
COMMAND[D10:D8] DATA[D7:D5]
SELECT DEPTH
(NUMBER OF CHANNELS)
000
010
DIAGNOSTIC SELECT[D4:D0]
DON’T CARE
SELECT CHANNEL 0 WITH AVDD2 PIN
LOAD DESIRED CHANNEL
N INTO THE SEQUENCER
NO = 0
COMMAND[D10:D8] DATA[D7:D5]
001
000
DIAGNOSTIC SELECT[D4:D0]
AVDD2 MUX
INPUT ADDRESS
SELECT CHANNEL 1 WITH MAIN DIE TEMPERATURE
NO = 1
COMMAND[D10:D8] DATA[D7:D5]
001
001
DIAGNOSTIC SELECT[D4:D0]
MAIN DIE TEMP MUX
INPUT ADDRESS
SELECT CHANNEL 2 WITH VLDO
NO = 2
COMMAND[D10:D8] DATA[D7:D5]
001
DIAGNOSTIC SELECT[D4:D0]
VLDO MUX
INPUT ADDRESS
IS N = DEPTH – 1?
YES
ENABLE AUTOMATIC SEQUENCING
ENABLE FOR AUTO/
KEY SEQUENCING
COMMAND[D10:D8] DATA[D7:D5]
011
001
DIAGNOSTIC SELECT[D4:D0]
DON’T CARE
Figure 86. Example Automatic Sequence Mode Setup for Three ADC Input Nodes
Rev. 0 | Page 46 of 72
17285-031
NO
010
Data Sheet
AD5753
ADC Conversion Timing
Figure 87 shows an example where autostatus readback mode is
enabled. The status register always contains the last completed
ADC conversion result together with the associated mux
address, ADC_IP_SELECT.
This example is applicable irrespective of the ADC conversion
mode in use (key sequencing, automatic sequencing, single
immediate conversion, or single key conversion). During the
first ADC conversion command shown, the contents of the
status register are available on the SDO line. The ADC portion
of this data contains the conversion result of the previously
converted ADC node (ADC Conversion Result 0), as well as the
associated channel address. If another SPI frame is not received
while the ADC is busy converting due to Command 1, the next
data to appear on the SDO line contains the associated conversion
result, ADC Conversion Result 1. However, if an SPI frame is
received while the ADC is busy, the status register contents
available on SDO still contain the previous conversion result
and indicates that the ADC_BUSY flag is high. Any new ADC
conversion instructions received while the ADC_BUSY bit is
active are ignored. If using a sequencer mode, the sequencer
address is updated after the conversion completes.
ADC CONVERSION TIME
SCLK
1
1
24
OR
32
24
OR
32
SYNC
INITIATE
CONVERSION 1
ADC CONVERSION
COMMAND NUMBER 2
ADC CONVERSION
COMMAND NUMBER 1
SDI
ASSUME AUTOSTATUS
READBACK IS ALREADY
ENABLED
ADC CONVERSION
RESULT NUMBER 1
ADC CONVERSION
RESULT NUMBER 0
CONTENTS OF STATUS
REGISTER CLOCKED OUT
1
0
FAULT
PIN
DIG
DIAG
ANA
DIAG
CONTENTS OF STATUS
REGISTER CLOCKED OUT
WDT
STATUS
ADC
BUSY
ADC
ADC
ADC
ADC
ADC
CHN[4]
CHN[0]
DATA[11]
DATA[1]
DATA[0]
NOTES
1. STATUS REGISTER CONTENTS CONTAINING ADC CONVERSION RESULT, CORRESPONDING
ADDRESS, AND ADC BUSY INDICATOR.
2. GRAY ITEMS HIGHLIGHT THE ADC BITS OF THE DATA FRAME SHOWN.
Figure 87. ADC Conversion Timing Example
Rev. 0 | Page 47 of 72
17285-034
SDO
AD5753
Data Sheet
REGISTER MAP
WRITING TO REGISTERS
The AD5753 is controlled and configured via 29 on-chip
registers described in the Register Details section. The four
possible access permissions are as follows:
•
•
•
•
•
R/W: read or write
R: read only
R/W-1-C: read or write 1 to clear
R0: read zero
R0/W: read zero or write
Reading from and writing to reserved registers is flagged as an
invalid SPI access. When accessing registers with reserved bit
fields, the default value of those bit fields must be written. These
values are listed in the Reset column of Table 27 to Table 52.
Use the format data frame in Table 21 when writing to any
register. By default, the SPI CRC is enabled, and the input
register is 32 bits wide with the last eight bits corresponding to
the CRC code. Only frames of exactly 32 bits wide are accepted
as valid. If the CRC is disabled, the input register is 24 bits wide,
and 32-bit frames are also accepted, with the final 8 bits ignored.
Table 22 describes the bit names and functions of Bit D23 to
Bit D16. Bit D15 to Bit D0 depend on the register that is being
addressed.
Table 21. Writing to a Register
MSB
D23
AD1
LSB
D22
AD1
D21
AD0
D20
REG_ADR4
D19
REG_ADR3
D18
REG_ADR2
D17
REG_ADR1
D16
REG_ADR0
[D15:D0]
Data
Table 22. Input Register Decode
Bit
AD1
AD1, AD0
REG_ADR4, REG_ADR3, REG_ADR2,
REG_ADR1, REG_ADR0
Description
Slip bit. This bit must equal the inverse of Bit D22, that is, AD1.
Used in association with the external pins, AD1 and AD0, to determine which AD5753 device is being
addressed by the system controller. Up to four unique devices can be addressed, corresponding to
the AD1 and AD0 addresses of 0b00, 0b01, 0b10, and 0b11.
Selects which register is written to. See Table 26 for a summary of the available registers.
Rev. 0 | Page 48 of 72
Data Sheet
AD5753
Two-Stage Readback Mode
READING FROM REGISTERS
Two-stage readback mode consists of a write to the TWO_
STAGE_READBACK_SELECT register to select the register
location to be read back, followed by a NOP command. To
perform a NOP command, write all zeros to Bits[D15:D0] of
the NOP register (see Table 27). During the NOP command, the
contents of the selected register are available on the SDO pin in
the data frame format shown in Table 23. It is also possible to write
a new two-stage readback command during the second frame, such
that the corresponding new data is available on the SDO pin in the
subsequent frame (see Figure 88). Bits[D31:D30] (or
Bits[D23:D22], if SPI CRC is not enabled) = 0b10 are used as part
of the synchronization during readback. The contents of the first
write instruction to the TWO_STAGE_READBACK_
SELECT register is shown in Table 24.
The AD5753 has four options for readback mode that can be
configured in the TWO_STAGE_READBACK_SELECT register
(see Table 46). These options are as follows:
•
•
•
•
Two-stage readback
Autostatus readback
Shared SYNC autostatus readback
Echo mode
Table 23. SDO Contents for Read Operation
MSB
[D23:D22]
0b10
LSB
D21
FAULT pin status
[D20:16]
Register address
[D15:D0]
Data
Table 24. Reading from a Register Using Two-Stage Readback Mode
D22
AD1
SCLK
D21
AD0
D20
D19
24
OR
32
1
D18
0x13
D17
D16
24
OR
32
1
LSB
D4 D3 D2 D1 D0
READBACK_SELECT[4:0]
[D15:D5]
Reserved
24
OR
32
1
SYNC
SDI
TWO-STAGE
READBACK
*NOP
INPUT WORD SPECIFIES
REGISTER TO BE READ
*ALTERNATIVELY,
WRITE ANOTHER
TWO-STAGE READBACK
NOP
SDO
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 88. Two-Stage Readback Example
Rev. 0 | Page 49 of 72
SELECTED REGISTER DATA
CLOCKED OUT
17285-037
MSB
D23
AD1
AD5753
Data Sheet
Autostatus Readback Mode
The autostatus readback mode can be used in conjunction with
the ADC sequencer to consecutively monitor up to eight different
ADC inputs. See the ADC Monitoring section for further details
on the ADC sequencer. The autostatus readback mode can be
configured via the READBACK_MODE bits in the TWO_
STAGE_READBACK_SELECT register (see the Two-Stage
Readback Select Register section). Figure 89 shows an example
of the data frames for an autostatus readback.
If autostatus readback mode is selected, the contents of the
status register are available on the SDO line during every SPI
transaction. When reading back the status register, the SDO
contents differ from the data frame format shown in Table 23.
The contents of the status register are shown in Table 25.
Table 25. SDO Contents for a Read Operation on the Status Register
MSB
D23 D22 D21
1
0
FAULT_PIN_STATUS
SCLK
1
D20
DIG_DIAG_STATUS
24
OR
32
D19
ANA_DIAG_STATUS
1
D18
WDT_STATUS
24
OR
32
D17
ADC_BUSY
1
LSB
[D16:D12]
[D11:D0]
ADC_CH[4:0] ADC_DATA[11:0]
24
OR
32
SYNC
SDI
ANY WRITE COMMAND
ANY WRITE COMMAND
ANY WRITE COMMAND
CONTENTS OF STATUS
REGISTER CLOCKED OUT
CONTENTS OF STATUS
REGISTER CLOCKED OUT
ASSUME AUTOSTATUS
READBACK IS ALREADY
ENABLED
CONTENTS OF STATUS
REGISTER CLOCKED OUT
Figure 89. Autostatus Readback Example
Rev. 0 | Page 50 of 72
17285-038
SDO
Data Sheet
AD5753
Shared SYNC Autostatus Readback Mode
SPI write is valid. Refer to the example shown in Figure 90.
Configure the shared SYNC autostatus readback mode via the
READBACK_MODE bits in the two-stage readback select register
(see the Two-Stage Readback Select Register section).
The shared SYNC autostatus readback is a special version of the
autostatus readback mode that is used to avoid SDO bus contention when multiple AD5753 devices are sharing the same SYNC
line. If this scenario occurs, the AD5753 devices are distinguished
from each other using the hardware address pins. An internal
flag is set after each valid write to a device and the flag is cleared
on the subsequent falling edge of SYNC. The shared SYNC
autostatus readback mode behaves in a similar manner to the
normal autostatus readback mode, except the device does not
output the status register contents on SDO when SYNC goes
low, unless the internal flag is set, which occurs when the previous
SCLK
1
24
OR
32
1
24
OR
32
Echo Mode
Echo mode behaves in a similar manner to the autostatus
readback mode, except that every second readback consists of
an echo of the previous command written to the AD5753. Echo
mode is useful for checking which SPI instruction is received in
the previous SPI frame. Echo mode can be configured via the
READBACK_MODE bits in the two-stage readback select register
(see the Two-Stage Readback Select Register section).
1
24
OR
32
1
24
OR
32
1
SYNC
DEVICE 0
FLAG SET
SDI
VALID
WRITE TO DEVICE 0
DEVICE 1
FLAG SET
NO FLAG SET
VALID
WRITE TO DEVICE 1
INVALID
WRITE TO DEVICE 0
DEVICE 0 STATUS REG
DEVICE 1 STATUS REG
DEVICE 0
FLAG SET
VALID
WRITE TO DEVICE 0
DEVICE 1
FLAG SET
VALID
WRITE TO DEVICE 1
DEVICE 0 STATUS REG
Figure 90. Shared SYNC Autostatus Readback Example
PREVIOUS COMMAND
STATUS REGISTER CONTENTS
Figure 91. SDO Contents—Echo Mode
Rev. 0 | Page 51 of 72
PREVIOUS COMMAND
17285-040
SDO
17285-039
ASSUME SHARED SYNC
AUTOSTATUS READBACK
IS ALREAD Y ENABLED
FOR BOTH DUTS
AD5753
Data Sheet
8.
PROGRAMMING SEQUENCE TO ENABLE THE
OUTPUT
To write to and set up the AD5753 from a power-on or reset
condition, take the following steps:
1.
2.
3.
4.
5.
6.
7.
Perform a hardware or software reset and wait 100 μs.
Perform a calibration memory refresh by writing 0xFCBA to
the key register. Wait a minimum of 500 μs before proceeding
to Step 3 to allow time for the internal calibrations to
complete. As an alternative to waiting 500 μs for the refresh
cycle to complete, poll the CAL_MEM_UNREFRESHED bit
in the DIGITAL_DIAG_RESULTS register until it is 0.
Write 1 to Bit D13 in the DIGITAL_DIAG_RESULTS register
to clear the RESET_OCCURRED flag.
If the CLKOUT signal is required, configure and enable
CLKOUT via the GP_CONFIG1 register. It is important to
configure this feature before enabling the dc-to-dc converter.
Write to the DCDC_CONFIG2 register to set the dc-to-dc
current limit and enable the negative dc-to-dc converter (if
using negative DPC). Wait 300 μs to allow the 3-wire interface
communication to complete. As an alternative to waiting
300 μs for the 3-wire interface communication to complete,
poll the BUSY_3WI bit in the DCDC_CONFIG2 register
until it is 0.
Write to the DCDC_CONFIG1 register to set up the dc-to-dc
converter mode, which enables the dc-to-dc converter. Wait
300 μs to allow the 3-wire interface communication to
complete. As an alternative to waiting 300 μs for the 3-wire
interface communication to complete, poll the BUSY_3WI bit
in the DCDC_CONFIG2 register until it is 0.
Write to the DAC_CONFIG register to set the INT_EN bit,
which powers up the DAC and internal amplifiers without
enabling the channel output, and configure the output range,
internal or external RSET, and slew rate. Keep the OUT_EN
bit disabled at this point. Wait for a minimum of 500 μs
before proceeding to Step 8 to allow the internal
calibrations to complete. As an alternative to waiting 500 μs
for the internal calibrations to complete, poll the CAL_
MEM_UNREFRESHED bit in the DIGITAL_DIAG_
RESULTS register until it reads 0.
Write a zero-scale DAC code to the DAC_INPUT register.
If a bipolar range is selected in Step 7, then a DAC code
that represents a 0 mA/0 V output must be written to the
DAC_INPUT register. It is important that this step be
completed even if the contents of the DAC_INPUT register
are not changing.
9. If the LDAC functionality is being used, perform either a
software or hardware LDAC command.
10. Rewrite the same word, used in Step 7, to the DAC_CONFIG
register with the OUT_EN bit enabled. Allow a minimum
of 1.25 ms to pass between Step 6 and Step 9, which is the
time from when the dc-to-dc is enabled to when the VIOUT
output is enabled.
11. Write the required DAC code to the DAC_INPUT register.
Figure 92 shows an example of a change to the programming
sequence.
Changing and Reprogramming the Range
After the output is enabled, take the following steps to change
the output range:
1.
2.
3.
4.
5.
Rev. 0 | Page 52 of 72
Write to the DAC_INPUT register. Set the output to 0 mA
or 0 V.
Write to the DAC_CONFIG register. Disable the output
(OUT_EN = 0) and set the new output range. Keep the
INT_EN bit set. Wait 500 μs minimum before proceeding
to Step 3 to allow time for internal calibrations to complete.
Write Code 0x0000 or the case of bipolar ranges, write
Code 0x8000 to the DAC_INPUT register. It is important
that this step be completed even if the contents of the DAC_
INPUT register do not change.
Reload the DAC_CONFIG register word from Step 2 and set
the OUT_EN bit to 1 to enable the output.
Write the required DAC code to the DAC_INPUT register.
Data Sheet
AD5753
EXAMPLE CONFIGURATION TO ENABLE THE OUTPUT CORRECTLY
1. PERFORM HARDWARE OR
SOFTWARE RESET
WRITE
2. PERFORM CALIBRATION
MEMORY REFRESH
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x08
0xFCBA
WAIT = 0
IS CAL_MEM_
UNREFRESHED
= 0?
N
IS WAIT
= 500µs?
N
WAIT = WAIT + 1
3. CLEAR RESET_
OCCURRED BIT
WRITE
4. CONFIGURE CLKOUT
IF REQUIRED
WRITE
5. SET UP THE
DC‐TO‐DC CONVERTER
SETTINGS AND ENABLE
NEGATIVE DC-TO-DC
WRITE
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x14
D13 = 1
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x09
GP CONFIG1 SETTINGS
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x0C
DC-TO-DC SETTINGS
WAIT = 0
IS BUSY_3WI
= 0?
N
IS WAIT
= 300µs?
N
6. SET UP THE
DC-TO-DC CONVERTER MODE
WAIT = WAIT + 1
WRITE
ADDRESS[D23:D20]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x0B
DC-TO-DC MODE
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x06
D6 = 0
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x01
DAC CODE
ADDRESS[D23:D21]
REGISTER ADDRESS[D19:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x07
0x1DAC
ADDRESS[D23:D21]
REGISTER ADDRESS[D19:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x06
D6 = 1
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x01
DAC CODE
WAIT = 0
IS BUSY_3WI
= 0?
N
IS WAIT
= 300µs?
N
WAIT = WAIT + 1
WRITE
7. CONFIGURE THE DAC
(OUTPUT DISABLED)
WAIT = 0
N
IS WAIT
= 500µs?
N
8. WRITE 0mV/0mA DAC
CODE
9. PERFORM AN LDAC COMMAND
WAIT = WAIT + 1
WRITE
WRITE
10. CONFIGURE THE DAC
(OUTPUT ENABLED)
WRITE
11. WRITE THE REQUIRED DAC
CODE
WRITE
17285-118
IS CAL_MEM_
UNREFRESHED
= 0?
NOTES
1. AD[1:0] ARE THE ADDRESS BITS AD1 AND AD0.
Figure 92. Example Configuration to Enable the Output Correctly (CRC Disabled for Simplicity)
Rev. 0 | Page 53 of 72
AD5753
Data Sheet
REGISTER DETAILS
Table 26. Register Summary
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
Name
NOP
DAC_INPUT
DAC_OUTPUT
CLEAR_CODE
USER_GAIN
USER_OFFSET
DAC_CONFIG
SW_LDAC
Key
GP_CONFIG1
GP_CONFIG2
DCDC_CONFIG1
DCDC_CONFIG2
GPIO_CONFIG
GPIO_DATA
WDT_CONFIG
DIGITAL_DIAG_CONFIG
ADC_CONFIG
FAULT_PIN_CONFIG
TWO_STAGE_READBACK_SELECT
DIGITAL_DIAG_RESULTS
ANALOG_DIAG_RESULTS
Status
CHIP_ID
FREQ_MONITOR
Reserved
Reserved
Reserved
DEVICE_ID_3
Description
NOP register.
DAC input register.
DAC output register.
Clear code register.
User gain register.
User offset register.
DAC configuration register.
Software LDAC register.
Key register.
General-Purpose Configuration 1 register.
General-Purpose Configuration 2 register.
DC-to-DC Configuration 1 register.
DC-to-DC Configuration 2 register.
GPIO configuration register.
GPIO data register.
WDT configuration register.
Digital diagnostic configuration register.
ADC configuration register.
FAULT pin configuration register.
Two stage readback select register.
Digital diagnostic results register.
Analog diagnostic results register.
Status register.
Chip ID register.
Frequency monitor register.
Reserved.
Reserved.
Reserved.
Generic ID register.
Reset
0x000000
0x010000
0x020000
0x030000
0x04FFFF
0x058000
0x060C00
0x070000
0x080000
0x090204
0x0A0200
0x0B0000
0x0C0100
0x0D0000
0x0E0000
0x0F0009
0x10005D
0x110000
0x120000
0x130000
0x14A000
0x150000
0x100000
0x170101
0x180000
0x190000
0x1A0000
0x1B0000
0x1C0000
Access
R0/W
R/W
R
R/W
R/W
R/W
R/W
R0/W
R0/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W-1-C
R/W-1-C
R
R
R
R
R
R
R
NOP Register
Address: 0x00, Reset: 0x000000, Name: NOP
Write 0x0000 to Bits[D15:D0] at this address to perform a no operation (NOP) command. Bits[D15:D0] (see Table 21) of this register always
read back as 0x0000.
Table 27. Bit Descriptions for NOP
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
NOP command
Register address.
Write 0x0000 to perform a NOP command.
0x0
0x0
R
R0/W
Rev. 0 | Page 54 of 72
Data Sheet
AD5753
DAC Input Register
Address: 0x01, Reset: 0x010000, Name: DAC_INPUT
Bits[D15:D0] consists of the 16-bit data to be written to the DAC. If the LDAC pin is tied low (active), the DAC_INPUT register contents
are written directly to the DAC_OUTPUT register without any LDAC functionality dependence. If the LDAC pin is tied high, the
contents of the DAC_INPUT register are written to the DAC_OUTPUT register when the LDAC pin is brought low or when the software
LDAC command is written.
Table 28. Bit Descriptions for DAC_INPUT
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
DAC_INPUT_DATA
Register address.
DAC input data.
0x0
0x0
R
R/W
DAC Output Register
Address: 0x02, Reset: 0x020000, Name: DAC_OUTPUT
DAC_OUTPUT is a read only register and contains the latest calibrated 16-bit DAC output value. If a clear event occurs due to a WDT
fault, this register contains the clear code until the DAC is updated to another code.
Table 29. Bit Descriptions for DAC_OUTPUT
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
DAC_OUTPUT_DATA
Register address.
DAC output data. For example, the last calibrated 16-bit DAC output value.
0x0
0x0
R
R
Clear Code Register
Address: 0x03, Reset: 0x030000, Name: CLEAR_CODE
When writing to the CLEAR_CODE register, Bits[D15:D0] consist of the clear code that clears the DAC when a clear event occurs (for
example, a WDT fault). After a clear event, the DAC_INPUT register must be rewritten to with the 16-bit data to be written to the DAC,
even if it is the same data as previously written before the clear event. Performing an LDAC write to the hardware or software does not
update the DAC_OUTPUT register to a new code until the DAC_INPUT register is first written to.
Table 30. Bit Descriptions for CLEAR_CODE
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
CLEAR_CODE
Register address.
Clear code. The DAC clears to this code upon a clear event, for example, a WDT fault.
0x0
0x0
R
R/W
User Gain Register
Address: 0x04, Reset: 0x04FFFF, Name: USER_GAIN
The 16-bit USER_GAIN register allows the user to adjust the gain of the DAC channel in steps of 1 LSB. The USER_GAIN register coding
is straight binary. The default code is 0xFFFF. Theoretically, the gain can be tuned across the full range of the output. However, the
maximum recommended gain trim is approximately 50% of the programmed range to maintain accuracy.
Table 31. Bit Descriptions for USER_GAIN
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
USER_GAIN
Register address.
User gain correction code.
0x0
0xFFFF
R
R/W
Rev. 0 | Page 55 of 72
AD5753
Data Sheet
User Offset Register
Address: 0x05, Reset: 0x058000, Name: USER_OFFSET
The 16-bit USER_OFFSET register allows the user to adjust the offset of the DAC channel by −32,768 LSBs to +32,768 LSBs in steps of 1 LSB.
The USER_OFFSET register coding is straight binary. The default code is 0x8000, which results in zero offset programmed to the output.
Table 32. Bit Descriptions for USER_OFFSET
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
USER_OFFSET
Register address.
User offset correction code.
0x0
0x8000
R
R/W
DAC Configuration Register
Address: 0x06, Reset: 0x060C00, Name: DAC_CONFIG
The DAC_CONFIG register configures the DAC (range, internal or external RSET, and output enable), enables the output stage circuitry,
and configures the slew rate control function.
Table 33. Bit Descriptions for DAC_CONFIG
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:13]
REGISTER_ADDRESS
SR_STEP
0x0
0x0
R
R/W
[12:9]
SR_CLOCK
0x6
R/W
8
SR_EN
0x0
R/W
7
RSET_EXT_EN
Register address.
Slew rate step. In conjunction with the slew rate clock, the slew rate step defines how
much the output value changes at each update. Together, both parameters define the
rate of change of the output value.
000: 4 LSB (default).
001: 12 LSB.
010: 64 LSB.
011: 120 LSB.
100: 256 LSB.
101: 500 LSB.
110: 1820 LSB.
111: 2048 LSB.
Slew rate clock. Slew rate clock defines the rate at which the digital slew is updated.
0000: 240 kHz.
0001: 200 kHz.
0010: 150 kHz.
0011: 128 kHz.
0100: 64 kHz.
0101: 32 kHz.
0110: 16 kHz (default).
0111: 8 kHz.
1000: 4 kHz.
1001: 2 kHz.
1010: 1 kHz.
1011: 512 Hz.
1100: 256 Hz.
1101: 128Hz.
1110: 64 Hz.
1111: 16 Hz.
Enables slew rate control.
0: disable (default).
1: enable.
Enables external current setting resistor.
0: select internal RSET resistor (default).
1: select external RSET resistor.
0x0
R/W
Rev. 0 | Page 56 of 72
Data Sheet
AD5753
Bits
Bit Name
Description
Reset
Access
6
OUT_EN
0x0
R/W
5
INT_EN
0x0
R/W
4
OVRNG_EN
0x0
R/W
[3:0]
Range
Enables VIOUT.
0: disable VIOUT output (default).
1: enable VIOUT output.
Enables internal buffers.
0: disable (default).
1: enable. Setting this bit powers up the DAC and internal amplifiers but does not enable
the output. It is recommended to set this bit and allow a >200 μs delay before enabling the
output. This delay results in a reduced output enable glitch.
Enables 20% voltage overrange.
0: disable (default).
1: enable.
Selects output range. Note that changing the contents of the range bits initiates an internal
calibration memory refresh and. Consequently, a subsequent SPI write must not be performed
until the CAL_MEM_UNREFRESHED bit in the DIGITAL_DIAG_RESULTS register returns to 0.
Writes to invalid range codes are ignored.
0000: 0 V to 5 V voltage range (default).
0001: 0 V to 10 V voltage range.
0010: ±5 V voltage range.
0011: ±10 V voltage range.
1000: 0 mA to 20 mA current range.
1001: 0 mA to 24 mA current range.
1010: 4 mA to 20 mA current range.
1011: ±20 mA current range.
1100: ±24 mA current range.
1101: −1 mA to +22 mA current range.
0x0
R/W
Software LDAC Register
Address: 0x07, Reset: 0x070000, Name: SW_LDAC
Writing 0x1DAC to the SW_LDAC register performs a software LDAC update on the device matching the DUT_ADDRESS, the device
address bits AD1 and AD0, bits within the SPI frame. If the GLOBAL_SW_LDAC bit in the GP_CONFIG2 register is set, the
DUT_ADDRESS bits are ignored and all devices sharing the same SPI bus are updated via the SW_LDAC command. Bits[15:0] of this
register always read back as 0x0000.
Table 34. Bit Descriptions for SW_LDAC
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
LDAC_COMMAND
Register address.
Software LDAC. Write 0x1DAC to this register to perform a software LDAC instruction.
0x0
0x0
R
R0/W
Key Register
Address: 0x08, Reset: 0x080000, Name: Key
The key register accepts specific key codes to perform tasks such as calibration memory refresh and software reset. Bits[15:0] of this
register always read back as 0x0000. All unlisted key codes are reserved.
Table 35. Bit Descriptions for Key
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
KEY_CODE
Register address.
Key code.
0x15FA: first of two keys to initiate a software reset.
0xAF51: second of two keys to initiate a software reset.
0x1ADC: key to initiate a single ADC conversion on the selected ADC channel.
0x0D06: key to reset the WDT.
0xFCBA: key to initiate a calibration memory refresh to the shadow registers. This key
is only valid the first time it is run and has no effect if subsequent writes occur within a
given system reset cycle.
0x0
0x0
R
R0/W
Rev. 0 | Page 57 of 72
AD5753
Data Sheet
General-Purpose Configuration 1 Register
Address: 0x09, Reset: 0x090204, Name: GP_CONFIG1
The GP_CONFIG register configures functions such as the temperature comparator threshold and CLKOUT, as well as enabling other
miscellaneous features.
Table 36. Bit Descriptions for GP_CONFIG1
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:14]
[13:12]
REGISTER_ADDRESS
RESERVED
SET_TEMP_THRESHOLD
0x0
0x0
0x0
R
R
R/W
[11:10]
CLKOUT_CONFIG
0x0
R/W
[9:7]
CLKOUT_FREQ
0x4
R/W
6
HART_EN
0x0
R/W
5
NEG_OFFSET_EN
0x0
R/W
4
CLEAR_NOW_EN
0x0
R/W
3
SPI_DIAG_QUIET_EN
0x0
R/W
2
OSC_STOP_DETECT_EN
0x1
R/W
1
0
Reserved
Reserved
Register address.
Reserved. (Do not alter the default value of this bit)
Sets the temperature comparator threshold value.
00: 142°C (default).
01: 127°C.
10: 112°C.
11: 97°C.
Configures the CLKOUT pin.
00: disable. No clock is output on the CLKOUT pin (default).
01: enable. Clock is output on the CLKOUT pin according to the CLKOUT_FREQ bits
(Bits[9:7]).
10: reserved. Do not select this option.
11: reserved. Do not select this option.
Configure the frequency of CLKOUT.
000: 416 kHz.
001: 435 kHz.
010: 454 kHz.
011: 476 kHz.
100: 500 kHz (default).
101: 526 kHz.
110: 555 kHz.
111: 588 kHz.
Enables the path to the CHART pin.
0: output of the DAC drives the output stage directly (default).
1: CHART path is coupled to the DAC output to allow a HART modem connection or
connection of a slew capacitor.
Enables negative offset in unipolar VOUT mode. When set, this bit offsets the
currently enabled unipolar output range. This bit is only applicable to the 0 V to 6 V
range and the 0 V to 12 V range. The 0 V to 6 V range becomes −300 mV to +5.7 V.
The 0 V to 12 V range becomes −400 mV to +11.6 V.
0: disable (default).
1: enable.
Enables clear to occur immediately, even if the output slew feature is currently enabled.
0: disable (default).
1: enable.
Enables SPI diagnostic quiet mode. When this bit is enabled, SPI_CRC_ERR,
SLIPBIT_ERR, and SCLK_COUNT_ERR are not included in the logical OR calculation,
which creates the DIG_DIAG_STATUS bit in the status register. They are also masked
from affecting the FAULT pin if this bit is set.
0: disable (default).
1: enable.
Enables automatic 0x07DEAD code on SDO if the MCLK stops.
0: disable.
1: enable (default).
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
0x0
0x0
R/W
R/W
Rev. 0 | Page 58 of 72
Data Sheet
AD5753
General-Purpose Configuration 2 Register
Address: 0x0A, Reset: 0x0A0200, Name: GP_CONFIG2
The GP_CONFIG2 register configures and enables functions such as the voltage comparators and the global software LDAC.
Table 37. Bit Descriptions for GP_CONFIG2
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the
FAULT pin.
Reset
0x0
Access
R
[20:16]
15
[14:13]
REGISTER_ADDRESS
Reserved
COMPARATOR_CONFIG
0x0
0x0
0x0
R
R0
R/W
12
11
10
Reserved
Reserved
GLOBAL_SW_LDAC
0x0
0x0
0x0
R/W
R/W
R/W
9
FAULT_TIMEOUT
0x1
R/W
[8:5]
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register address.
Reserved. Do not alter the default value of this bit.
Enables or disables the voltage comparator inputs for test purposes. The
temperature comparator is permanently enabled. See the Background
Supply and Temperature Monitoring section.
00: disable voltage comparators (default).
01: reserved.
10: reserved.
11: enable voltage comparators. The INT_EN bit in the DAC_CONFIG register
must be set to power-up the REFIN buffer and make the REFIN buffer
available to the REFIN comparator.
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
When enabled, the DUT address bits are ignored when performing a
software LDAC command, enabling multiple devices to be simultaneously
updated using one SW_LDAC command.
0: disable (default).
1: enable.
Enables reduced fault detect timeout. This bit configures the delay from
when the analog block indicates a VIOUT fault has been detected to the
associated change of the relevant bit in the ANALOG_DIAG_RESULTS
register. This feature provides flexibility to accommodate a variety of output
load values.
0: fault detect timeout = 25 ms.
1: fault detect timeout = 6.5 ms (default).
Reserved. Do not alter the default value of these bits.
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 0 | Page 59 of 72
AD5753
Data Sheet
DC-to-DC Configuration 1 Register
Address: 0x0B, Reset: 0x0B0000, Name: DCDC_CONFIG1
The DCDC_CONFIG1 register configures the dc-to-dc controller mode.
Table 38. Bit Descriptions for DCDC_CONFIG1
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:8]
7
[6:5]
REGISTER_ADDRESS
Reserved
Reserved
DCDC_MODE
0x0
0x0
0x0
0x0
R
R0
R/W
R/W
[4:0]
DCDC_VPROG
Register address.
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
These two bits configure the dc-to-dc converters.
00: dc-to-dc converter powered off (default).
01: DPC current mode. The positive and negative DPC rails tracks the headroom and
footroom of the current output buffer.
10: DPC voltage mode. The positive DPC rail is regulated to 15 V with respect to
−VSENSE. If enabled, the negative DPC rail is also regulated to −15 V with respect to
−VSENSE.
11: PPC current mode. VDPC+ and VDPC− (if enabled) is regulated to a user programmable
level between ±5 V and ±25.677 V (depending on the DCDC_VPROG bits, Bits[4:0]) with
respect to −VSENSE. If the VDPC− is disabled, the ENABLE_PPC_BUFFERS bit (Bit 11 in the
ADC_CONFIG register) must be set prior to enabling PPC current mode.
DC-to-dc programmed voltage in PPC mode. VDPC+ and VDPC− is regulated to a user
programmable level between ±5 V (0b00000) and ±25.677 V (0b11111), in steps of
0.667 V with respect to −VSENSE.
0x0
R/W
DC-to-DC Configuration 2 Register
Address: 0x0C, Reset: 0x0C0100, Name: DCDC_CONFIG2
The DCDC_CONFIG2 register configures various dc-to-dc die features, such as the dc-to-dc converter current limit and the dc-to-dc die
node, to be multiplexed to the ADC.
Table 39. Bit Descriptions for DCDC_CONFIG2
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the
FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:13]
12
REGISTER_ADDRESS
Reserved
BUSY_3WI
0x0
0x0
0x0
R
R0
R
11
INTR_SAT_3WI
0x0
R
10
DCDC_READ_COMP_DIS
0x0
R/W
[9:8]
7
Reserved
VIOUT_OV_ERR_DEGLITCH
0x1
0x0
R/W
R/W
6
VIOUT_PULLDOWN_EN
Register address.
Reserved. Do not alter the default value of these bits.
Three-wire interface busy indicator.
0: 3-wire interface not currently active.
1: 3-wire interface busy.
Three-wire interface saturation flag. This flag is set to 1 when the
interrupt detection circuitry is automatically disabled due to six
consecutive interrupt signals. A write to either of the dc-to-dc
configuration registers clears this bit to 0.
Disables 3-wire interface read and compare cycle. This read and compare
cycle ensures that copied contents of the dc-to-dc configuration
registers on the main die match the dc-to-dc die contents on the.
0: enable automatic read and compare cycle (default).
1: when set, this bit disables the automatic read and compare cycle
after each 3-wire interface write.
Reserved. Do not alter the default value of these bits.
Adjusts the deglitch time on VIOUT overvoltage error flag.
0: deglitch time set to 1.02 ms (default).
1: deglitch time set to 128 μs.
Enables the 30 kΩ resistor to ground on VIOUT.
0: disable (default).
1: enable.
0x0
R/W
Rev. 0 | Page 60 of 72
Data Sheet
AD5753
Bits
[5:4]
Bit Name
DCDC_ADC_CONTROL_DIAG
[3:1]
DCDC_ILIMIT
Description
Selects which dc-to-dc die node is multiplexed to the ADC on the
main die.
00: AGND on dc-to-dc die.
01: internal 2.5 V supply on dc-to-dc die.
10: AVDD1.
11: reserved. Do not select this option.
These three bits set the dc-to-dc converter current limit.
000: 150 mA (default).
001: 200 mA.
010: 250 mA.
011: 300 mA.
100: 350 mA.
101: 400 mA.
Reset
0x0
Access
R/W
0x0
R/W
0x0
R/W
110: 400 mA.
111: 400 mA.
0
DCDC_NEG_EN
Enables negative dc-to-dc.
0: disable (default).
1: enable.
GPIO Configuration Register
Address: 0x0D, Reset: 0x0D0000, Name: GPIO_CONFIG
The GPIO_CONFIG register configures the GPIO pins as either inputs, outputs or 100 kΩ to DGND.
Table 40. Bit Descriptions for GPIO_CONFIG
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:6]
[5:4]
REGISTER_ADDRESS
Reserved
GPIO_2_CFG
0x0
0x0
0x0
R
R0
R/W
[3:2]
GPIO_1_CFG
0x0
R/W
[1:0]
GPIO_0_CFG
Register address.
Reserved.
Configuration bits for GPIO_2.
00: 100 kΩ to DGND (default).
01: GPO mode. GPIO_2 pin goes to the value of the GPO_2_WRITE bit.
10: GPI mode. GPO_2_READ is the value of the GPIO_2 pin.
11: reserved.
Configuration bits for GPIO_1.
00: 100 kΩ to DGND (default).
01: GPO mode. GPIO_1 pin goes to value in GPO_1_WRITE bit.
10: GPI mode. GPO_1_READ is the value of the GPI_1 pin.
11: reserved.
Configuration bits for GPIO_0.
00: 100 kΩ to DGND (default).
01: GPO mode. GPIO_0 pin goes to value in GPO_0_WRITE bit.
10: GPI mode. GPO_0_WRITE is the value of the GPIO_0 pin.
11: reserved.
0x0
R/W
Rev. 0 | Page 61 of 72
AD5753
Data Sheet
GPIO Data Register
Address: 0x0E, Reset: 0x0E0000, Name: GPIO_DATA
The GPIO_DATA register is used to read and write from and to the GPIO_0, GPIO_1, and GPIO_2 pins.
Table 41. Bit Descriptions for GPIO_DATA
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:6]
5
REGISTER_ADDRESS
Reserved
GPI_2_READ
0x0
0x0
0x0
R
R0
R
4
3
GPO_2_WRITE
GPI_1_READ
0x0
0x0
R/W
R
2
1
GPO_1_WRITE
GPI_0_READ
0x0
0x0
R/W
R
0
GPO_0_WRITE
Register address.
Reserved.
User readable bit. This bit reflects the logic value on the GPIO_2 pin in GPO and GPI
mode.
User writable bit. This bit reflects the GPIO_2 pin logic value in GPO mode.
User readable bit. This bit reflects the logic value on the GPIO_1 pin in GPO and GPI
mode.
User writable bit. This bit reflects the GPIO_1 pin logic value in GPO mode.
User readable bit. This bit reflects the logic value on the GPIO_0 pin in GPO and GPI
mode.
User writable bit. This bit reflects the GPIO_0 pin logic value in GPO mode.
0x0
R/W
WDT Configuration Register
Address: 0x0F, Reset: 0x0F0009, Name: WDT_CONFIG
The WDT_CONFIG register configures the WDT timeout values. This register also configures the acceptable resets for WDT setup and
configures the resulting response to a WDT fault, for example, clears the output or resets the device.
Table 42. Bit Descriptions for WDT_CONFIG
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:11]
10
REGISTER_ADDRESS
Reserved
CLEAR_ON_WDT_FAIL
0x0
0x0
0x0
R
R
R/W
9
RESET_ON_WDT_FAIL
0x0
R/W
8
KICK_ON_VALID_WRITE
0x0
R/W
7
6
Reserved
WDT_EN
0x0
0x0
R/W
R/W
[5:4]
[3:0]
Reserved
WDT_TIMEOUT
Register address.
Reserved. Do not alter the default value of these bits.
Enable clear on WDT fault. If the WDT times out, a clear event occurs, whereby the
output is loaded with the clear code stored in the CLEAR_CODE register.
0: disable (default).
1: enable.
Enables a software reset to automatically occur if the WDT times out.
0: disable (default).
1: enable.
Enables any valid SPI command to reset the WDT. Any active WDT error flags must
be cleared before the WDT can be restarted.
0: disable (default).
1: enable.
Reserved. Do not alter the default value of this bit.
Enables the WDT, then starts the WDT, assuming there are no active WDT fault flags.
0: disable (default).
1: enable.
Reserved. Do not alter the default value of these bits.
Sets the WDT timeout value. Setting WDT_TIMEOUT to a binary value beyond
0b1010 results in the default setting of 1 sec.
0000: 1 ms.
0001: 5 ms.
0010: 10 ms.
0011: 25 ms.
0100: 50 ms.
0101: 100 ms.
0110: 250 ms.
0x0
0x9
R/W
R/W
Rev. 0 | Page 62 of 72
Data Sheet
Bits
Bit Name
AD5753
Description
0111: 500 ms.
1000: 750 ms.
Reset
Access
1001: 1 sec (default).
1010: 2 sec.
Digital Diagnostic Configuration Register
Address: 0x10, Reset: 0x10005D, Name: DIGITAL_DIAG_CONFIG
The DIGITAL_DIAG_CONFIG register configures various digital diagnostic features of interest.
Table 43. Bit Descriptions for DIGITAL_DIAG_CONFIG
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:9]
[8:7]
6
REGISTER_ADDRESS
Reserved
Reserved
DAC_LATCH_MON_EN
0x0
0x0
0x0
0x1
R
R0
R/W
R/W
5
4
Reserved
INVERSE_DAC_CHECK_EN
0x0
0x1
R/W
R/W
3
CAL_MEM_CRC_EN
0x1
R/W
2
FREQ_MON_EN
0x1
R/W
1
0
Reserved
SPI_CRC_EN
Register address.
Reserved. Do not alter the default value of these bits.
Reserved. Do not alter the default value of these bits.
Enables a diagnostic monitor on the DAC latches. This feature monitors the actual
digital code driving the DAC and compares the code with the digital code generated
within the digital block. Any difference between the two codes causes the DAC_
LATCH_MON_ERR flag to be set in the DIGITAL_DIAG_RESULTS register.
0: disable.
1: enable (default).
Reserved. Do not alter the default value of this bit.
Enables check for DAC code vs. inverse DAC code error.
0: disable.
1: enable (default).
Enables the CRC of calibration memory on a calibration memory refresh.
0: disable.
1: enable (default).
Enables the internal frequency monitor on the MCLK.
0: disable.
1: enable (default).
Reserved. Do not alter the default value of this bit.
Enables the SPI CRC function.
0: disable.
1: enable (default).
0x0
0x1
R/W
R/W
ADC Configuration Register
Address: 0x11, Reset: 0x110000, Name: ADC_CONFIG
The ADC_CONFIG register configures the ADC to one of the following four modes of operation: key sequencing, automatic sequencing,
single immediate conversion of the currently selected ADC_IP_SELECT node, and single-key conversion.
Table 44. Bit Descriptions for ADC_CONFIG
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:12]
11
[10:8]
REGISTER_ADDRESS
Reserved
ENABLE_PPC_BUFFERS
SEQUENCE_COMMAND
Register address. Do not alter the default value.
Reserved. Do not alter the default value of these bits.
Enable the sense buffers for PPC mode.
ADC sequence command bits.
000: set the depth of the sequencer. The contents of the SEQUENCE_DATA bits
correspond to the depth of the sequencer (000 = 1 channel, 001 = 2 channels,…,
111 = 8 channels).
001: set the SEQUENCE_DATA[7:5] bits with the channel number for the selected
ADC input, ADC_IP_SELECT[4:0].
0x0
0x0
0x0
0x0
R
R/W
R/W
R/W
Rev. 0 | Page 63 of 72
AD5753
Bits
Bit Name
[7:5]
SEQUENCE_DATA
[4:0]
ADC_IP_SELECT
Data Sheet
Description
010: Enable or disable key sequencer mode, depending on the contents of the
SEQUENCE_DATA[7:5] bits. SEQUENCE_DATA[7:5] = 001 enables the key sequencer.
SEQUENCE_DATA[2:0] ≠ 001 disables the key sequencer.
011: enable/disable automatic sequencer mode, depending on the contents of the
SEQUENCE_DATA[2:0] bits. SEQUENCE_DATA[2:0] = 001: enables the automatic
sequencer. SEQUENCE_DATA[2:0] ≠ 001: disables the automatic sequencer.
100: initiate a single conversion on the ADC_IP_SELECT (Bits[4:0]) input. This disables
autosequencing. The SEQUENCE_DATA bits, Bits[7:5], are not applicable for this
command.
101: set up the ADC for future individual ADC conversions (if not using the key
sequencer) using the 0x1ADC key code. The SEQUENCE_DATA bits, Bits[7:5], are not
applicable for this command.
110: reserved. Do not select this option.
111: reserved. Do not select this option.
The function of the contents of this field is dependent on the command being
issued by the SEQUENCE_COMMAND bits.
Selects which node to multiplex to the ADC. All unlisted 5-bit codes are reserved
and return an ADC result of zero.
00000: main die temperature.
00001: dc-to-dc die temperature.
00010: reserved. Do not select this option.
00011: REFIN. The INT_EN bit in the DAC_CONFIG register must be set for the REFIN
buffer to be powered up and this node to be available to the ADC.
00100: REF2; internal 1.23 V reference voltage.
00101: reserved. Do not select this option.
00110: reserved. Do not select this option.
01100: ADC2 pin input (±15 V input range).
01101: voltage on the +VSENSE buffer output.
01110: voltage on the −VSENSE buffer output
01111: ADC1 pin input (0 V to 1.25 V input range).
10000: ADC1 pin input (0 V to 0.5 V input range).
10001: ADC1 pin input (0 V to 2.5 V input range).
10010: ADC1 pin input (±0.5 V input range).
10011: reserved. Do not select this option.
10100: INT_AVCC.
10101: VLDO.
10110: VLOGIC.
11000: REFGND.
11001: AGND.
11010: DGND.
11011: VDPC+.
11100: AVDD2.
11101: VDPC−.
11110: dc-to-dc die node. Configured in the DCDC_CONFIG2 register.
11111: REFOUT.
Rev. 0 | Page 64 of 72
Reset
Access
0x0
R/W
0x0
R/W
Data Sheet
AD5753
FAULT Pin Configuration Register
Address: 0x12, Reset: 0x120000, Name: FAULT_PIN_CONFIG
The FAULT register masks particular fault bits from the FAULT pin, if so desired.
Table 45. Bit Descriptions for FAULT_PIN_CONFIG
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
15
REGISTER_ADDRESS
INVALID_SPI_ACCESS_ERR
Register address.
If this bit is set, do not map the INVALID_SPI_ACCESS_ERR fault flag to the FAULT pin.
0x0
0x0
R
R/W
14
VIOUT_OV_ERR
If this bit is set, do not map the VIOUT_OV_ERR fault flag to the FAULT pin.
0x0
R/W
13
12
Reserved
INVERSE_DAC_CHECK_ERR
Reserved. Do not alter the default value of this bit.
If this bit is set, do not map the INVERSE_DAC_CHECK_ERR flag to the FAULT pin.
0x0
0x0
R/W
R/W
11
10
Reserved
OSCILLATOR_STOP_DETECT
Reserved. Do not alter the default value of this bit.
If this bit is set, do not map the clock stop error to the FAULT pin.
0x0
0x0
R/W
R/W
9
DAC_LATCH_MON_ERR
If this bit is set, do not map the DAC_LATCH_MON_ERR fault flag to the FAULT pin.
0x0
R/W
8
WDT_ERR
If this bit is set, do not map the WDT_ERR flag to the FAULT pin.
0x0
R/W
7
SLIPBIT_ERR
R/W
SPI_CRC_ERR
Reserved
DCDC_P_SC_ERR
If this bit is set, do not map the SLIPBIT_ERR error flag to the FAULT pin.
If this bit is set, do not map the SPI_CRC_ERR error flag to the pin.
Reserved. Do not alter the default value of this bit.
If this bit is set, do not map the positive rail dc-to-dc short circuit error flag to the
FAULT pin.
0x0
6
5
4
0x0
0x0
0x0
R/W
R/W
R/W
3
IOUT_OC_ERR
If this bit is set, do not map the current output open-circuit error flag to the FAULT pin.
0x0
R/W
2
VOUT_SC_ERR
If this bit is set, do not map the voltage output short-circuit error flag to the FAULT pin.
0x0
R/W
1
DCDC-DIE_TEMP_ERR
If this bit is set, do not map the dc-to-dc die temperature error flag to the FAULT pin.
0x0
R/W
0
MAIN_DIE_TEMP_ERR
If this bit is set, do not map the main die temperature error flag to the FAULT pin.
0x0
R/W
Two-Stage Readback Select Register
Address: 0x13, Reset: 0x130000, Name: TWO_STAGE_READBACK_SELECT
The TWO_STAGE_READBACK_SELECT register selects the address of the register required for a two-stage readback operation. The
address of the register selected for readback is stored in Bits[D4:D0].
Table 46. Bit Descriptions for TWO_STAGE_READBACK_SELECT
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:7]
[6:5]
REGISTER_ADDRESS
Reserved
READBACK_MODE
0x0
0x0
0x0
R
R
R/W
[4:0]
READBACK_SELECT
Register address.
Reserved.
These bits control the SPI readback mode.
0: two-stage SPI readback mode (default).
01: autostatus readback mode. The status register contents are shifted out on SDO for
every SPI frame.
10: shared SYNC autostatus readback mode. This mode allows the use of a shared SYNC
line on multiple devices (distinguished using the hardware address pins). After each valid
write to a device, a flag is set. This mode behaves similar to the normal autostatus readback
mode, except that the device does not output the status register contents on SDO as
SYNC goes low, unless the internal flag is set (previous SPI write is valid).
11: the status register contents and the previous SPI frame instruction are alternately
available on SDO.
Selects readback address for a two-stage readback.
0x00: NOP register (default).
0x01: DAC_INPUT register.
0x02: DAC_OUTPUT register.
0x03: CLEAR_CODE register.
0x04: USER_GAIN register.
0x0
R/W
Rev. 0 | Page 65 of 72
AD5753
Bits
Bit Name
Data Sheet
Description
0x05: USER_OFFSET register.
0x06: DAC_CONFIG register.
0x07: SW_LDAC register.
0x08: key register.
0x09: GP_CONFIG1 register.
0x0A: GP_CONFIG2 register.
0x0B: DCDC_CONFIG1 register.
0x0C: DCDC_CONFIG2 register.
0x0D: GPIO_CONFIG register.
0x0E: GPIO_DATA register.
0x0F: WDT_CONFIG register.
0x10: DIGITAL_DIAG_CONFIG register.
0x11: ADC_CONFIG register.
0x12: FAULT_PIN_CONFIG register.
0x13: TWO_STAGE_READBACK_SELECT register.
0x14: DIGITAL_DIAG_RESULTS register.
0x15: ANALOG_DIAG_RESULTS register.
0x16: Status register.
0x17: CHIP_ID register.
0x18: FREQ_MONITOR register.
0x19: reserved. Do not select this option.
0x1A: reserved. Do not select this option.
0x1B: reserved .Do not select this option.
0x1C: DEVICE_ID_3 register.
Reset
Access
Digital Diagnostic Results Register
Address: 0x14, Reset: 0x14A000, Name: DIGITAL_DIAG_RESULTS
The DIGITAL_DIAG_RESULTS register contains an error flag for the on-chip digital diagnostic features, most of which are configurable using
the digital diagnostic configuration register. This register also contains a flag to indicate that a reset occurred, as well as a flag to indicate
that the calibration memory has not refreshed or an invalid SPI access attempted. With the exception of the CAL_MEM_UNREFRESHED and
SLEW_BUSY flags, all of these flags require a 1 to be written to them to update them to their current value. The CAL_MEM_UNREFRESHED
and SLEW_BUSY flags automatically clear when the calibration memory refresh or output slew, respectively, is complete. When the
corresponding enable bits in the DIGITAL_DIAG_CONFIG register are not enabled, the respective flag bits read as zero.
Table 47. Bit Descriptions for DIGITAL_DIAG_RESULTS
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
15
REGISTER_ADDRESS
CAL_MEM_UNREFRESHED
0x0
0x1
R
R
14
SLEW_BUSY
0x0
R
13
12
11
10
9
RESET_OCCURRED
ERR_3WI
WDT_ERR
Reserved
3WI_RC_ERR
0x1
0x0
0x0
0x0
0x0
R/W-1-C
R/W-1-C
R/W-1-C
R/W-1-C
R/W-1-C
8
DAC_LATCH_MON_ERR
Register address.
Calibration memory unrefreshed flag. Modifying the range bits in the
DAC_CONFIG register also initiates a calibration memory refresh, which
asserts this bit. Unlike the R/W-1-C bits in this register, this bit is automatically
cleared after the calibration memory refresh completes.
0: calibration memory is refreshed.
1: calibration memory is unrefreshed (default on power-up). This bit asserts if
the range bits are modified in the DAC_CONFIG register.
This flag is set to 1 when the DAC is actively slewing. Unlike the R/W-1-C bits
in this register, this bit is automatically cleared when slewing is complete.
This bit flags that a reset occurred (default on power-up is therefore Logic 1).
This bit flags an error in the interdie 3-wire interface communications.
This bit flags a WDT fault.
Reserved.
This bit flags an error if the 3-wire read and compare process is enabled and
a parity error occurs.
This bit flags if the output of the DAC latches does not match the input.
0x0
R/W-1-C
Rev. 0 | Page 66 of 72
Data Sheet
AD5753
Bits
7
6
Bit Name
Reserved
INVERSE_DAC_CHECK_ERR
5
CAL_MEM_CRC_ERR
4
INVALID_SPI_ACCESS_ERR
3
2
Reserved
SCLK_COUNT_ERR
1
SLIPBIT_ERR
0
SPI_CRC_ERR
Description
Reserved.
This bit flags if a fault it detected between the DAC code driven by the digital
core and an inverted copy.
This bit flags a CRC error for the CRC calculation of the calibration memory
upon refresh.
This bit flags if an invalid SPI access is attempted, such as writing to or reading
from an invalid or reserved address. This bit also flags if an SPI write is attempted
directly after powering up but before a calibration memory refresh is performed
or if an SPI write is attempted while a calibration memory refresh is in progress.
Performing a two stage readback is permitted during a calibration memory
refresh and does not cause this flag to set. Attempting to write to a read only
register also causes this bit to assert.
Reserved.
This bit flags an SCLK falling edge count error. 32 clocks are required if SPI
CRC is enabled and 24 clocks or 32 clocks are required if SPI CRC is not enabled.
This bit flags an SPI frame slip bit error, that is, the MSB of the SPI word is not
equal to the inverse of MSB − 1.
This bit flags an SPI CRC error.
Reset
0x0
0x0
Access
R/W-1-C
R/W-1-C
0x0
R/W-1-C
0x0
R/W-1-C
0x0
0x0
R/W-1-C
R/W-1-C
0x0
R/W-1-C
0x0
R/W-1-C
Analog Diagnostic Results Register
Address: 0x15, Reset: 0x150000, Name: ANALOG_DIAG_RESULTS
The ANALOG_DIAG_RESULTS register contains an error flag corresponding to the four voltage nodes (VLDO, INT_AVCC, REFIN, and
REFOUT) monitored in the background by comparators, as well as a flag for the main die temperature, which is also monitored by a
comparator. Voltage output short circuit, current output open circuit, and dc-to-dc error flags are also contained in this register. Like the
DIGITAL_DIAG_RESULTS register, all of the flags contained in this register require a 1 to be written to them to update or clear them.
When the corresponding diagnostic features are not enabled, the respective error flags are read as zero.
Table 48. Bit Descriptions for ANALOG_DIAG_RESULTS
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:14]
13
12
11
10
9
REGISTER_ADDRESS
Reserved
VIOUT_OV_ERR
Reserved
DCDC_P_SC_ERR
Reserved
DCDC_P_PWR_ERR
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R
R0
R/W-1-C
R/W-1-C
R/W-1-C
R/W-1-C
R/W-1-C
8
7
Reserved
IOUT_OC_ERR
0x0
0x0
R/W-1-C
R/W-1-C
6
5
4
3
VOUT_SC_ERR
DCDC_DIE_TEMP_ERR
MAIN_DIE_TEMP_ERR
REFOUT_ERR
0x0
0x0
0x0
0x0
R/W-1-C
R/W-1-C
R/W-1-C
R/W-1-C
2
1
0
REFIN_ERR
INT_AVCC_ERR
VLDO_ERR
Register address.
Reserved.
This bit flags if the voltage at the VIOUT pin goes outside of the VDPC+ rail or AVSS rail.
Reserved.
This bit flags a dc-to-dc short-circuit error for the positive rail dc-to-dc circuit.
Reserved.
This bit flags a dc-to-dc regulation fault, that is, the dc-to-dc circuitry cannot reach
the target VDPC+ voltage due to an insufficient AVDD1 voltage.
Reserved.
This bit flags a current output open circuit error. This error bit is set in the case of a
current output open circuit and in the case where there is insufficient headroom
available to the internal current output driver circuitry to provide the programmed
output current.
This bit flags a voltage output short-circuit error.
This bit flags an overtemperature error for the dc-to-dc die.
This bit flags an overtemperature error for the main die.
This bit flags that the REFOUT node is outside of the comparator threshold levels
or if the short-circuit current limit occurs.
This bit flags that the REFIN node is outside of the comparator threshold levels.
This bit flags that the INT_AVCC node is outside of the comparator threshold levels.
This bit flags that the VLDO node is outside of the comparator threshold levels or if
the short-circuit current limit occurs.
0x0
0x0
0x0
R/W-1-C
R/W-1-C
R/W-1-C
Rev. 0 | Page 67 of 72
AD5753
Data Sheet
Status Register
Address: 0x16, Reset: 0x100000, Name: Status
The Status register contains ADC data and status bits, as well as the WDT, OR'ed analog and digital diagnostics, and the FAULT pin status
bits.
Table 49. Bit Descriptions for Status
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
20
DIG_DIAG_STATUS
0x1
R
19
ANA_DIAG_STATUS
0x0
R
18
17
[16:12]
[11:0]
WDT_STATUS
ADC_BUSY
ADC_CH
ADC_DATA
This bit represents the result of a logical OR of the contents of Bits[15:0] in the DIGITAL_
DIAG_RESULTS register, with the exception of the SLEW_BUSY bit. Therefore, if any of these
bits are high, the DIG_DIAG_STATUS bit is high. Note that this bit is high on power-up due to
the active RESET_OCCURRED flag. A quiet mode is also available (SPI_DIAG_QUIET_EN in
the GP_CONFIG1 register), such that the logical OR function only incorporates Bits[D15:D3]
of the DIGITAL_DIAG_RESULTS register (with the exception of the SLEW_BUSY bit). If an SPI
CRC, SPI slip bit, or SCLK count error occurs, the DIG_DIAG_STATUS bit is not set high.
This bit represents the result of a logical OR of the contents of Bits[13:0] in the
ANALOG_DIAG_RESULTS register. Therefore, if any bit in this register is high, the
ANA_DIAG_STATUS bit is high.
WDT status bit.
ADC busy status bit.
Address of the ADC channel represented by the ADC_DATA bits in the status register.
12 bits of ADC data representing the converted signal addressed by the ADC_CH bits,
Bits[16:12].
0x0
0x0
0x0
0x0
R
R
R
R
Chip ID Register
Address: 0x17, Reset: 0x170101, Name: CHIP_ID
The CHIP_ID register contains the silicon revision ID of both the main die and the dc-to-dc die.
Table 50. Bit Descriptions for CHIP_ID
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:11]
[10:8]
[7:0]
REGISTER_ADDRESS
Reserved
DCDC_DIE_CHIP_ID
MAIN_DIE_CHIP_ID
Register address.
Reserved.
These bits reflect the silicon revision number of the dc-to-dc die.
These bits reflect the silicon revision number of the main die.
0x0
0x0
0x2
0x2
R
R0
R
R
Frequency Monitor Register
Address: 0x18, Reset: 0x180000, Name: FREQ_MONITOR
An internal frequency monitor uses the MCLK to create a pulse at a frequency of 1 kHz (MCLK/10,000). This pulse is used to increment
a 16-bit counter. The value of the counter is available to read in the FREQ_MONITOR register. The user can poll this register periodically
and use it both as a diagnostic tool for the internal oscillator (to monitor that the oscillator is running) and to measure the frequency. This
feature is enabled by default via the FREQ_MON_EN bit in the DIGITAL_DIAG_CONFIG register.
Table 51. Bit Descriptions for FREQ_MONITOR
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
FREQ_MONITOR
Register address.
Internal clock counter value.
0x0
0x0
R
R
Rev. 0 | Page 68 of 72
Data Sheet
AD5753
Generic ID Register
Address: 0x1C, Reset: 0x1C0000, Name: DEVICE_ID_3
Table 52. Bit Descriptions for DEVICE_ID_3
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:8]
[7:3]
[2:0]
REGISTER_ADDRESS
Reserved
Reserved
Generic ID
Register address.
Reserved.
Reserved.
Generic ID.
000: reserved.
001: reserved.
010: AD5753.
011: reserved.
100: reserved.
101: reserved.
110: reserved.
111: reserved.
0x0
0x0
0x0
0x0
R
R
R
R
Rev. 0 | Page 69 of 72
AD5753
Data Sheet
APPLICATIONS INFORMATION
EXAMPLE MODULE POWER CALCULATION
Using the example module shown in Figure 93, the power
dissipation (excluding the power dissipated in the load) of the
module can be calculated using the methodology shown in the
Power Calculation Methodology (RLOAD = 1 kΩ) section.
Assuming a maximum IOUT value of 20 mA and RLOAD value of
1 kΩ, the total module power is calculated as approximately
226 mW. The power associated with the external digital isolation is
not included in the calculations because this power is dependent
on the choice of component used.
Assume the dc-to-dc converter is at 90% efficiency. Therefore,
VDPC+ power = 512.5 mW. The total input power at the AD5753
side of the isolated dc-to-dc power module is therefore 512.5 mW +
19.18 mW = 531.68 mW. Subtracting the 400 mW load power
from this value gives the power associated only with the
AD5753, which is 131.68 mW.
Assuming an 85% efficiency isolated, dc-to-dc power module,
the total input power becomes 625.5 mW (see Figure 93).
Total Module Power = Input Power − Load Power
Therefore, the equation is as follows:
Replacing the 1 kΩ load with a short circuit, the power dissipation
calculation is shown in the Power Calculation Methodology
(RLOAD = 0 Ω) section, which shows that the total module power
becomes approximately 206 mW in a short-circuit load
condition.
Using the voltage and current values in Table 53, the total
quiescent current power is 19.18 mW.
Power Calculation Methodology (RLOAD = 1 kΩ)
Next, use the following equation:
625.5 mW − 400 mW = 225.5 mW
Power Calculation Methodology (RLOAD = 0 Ω)
(VDPC+) × (20 mA + IDPC+) = 4.95 V × 20.5 mA = 101.5 mW
Table 53. Quiescent Current Power Calculation
Voltage (V)
AVDD1 = 24
AVDD2 = 5
AVSS = −15
VLOGIC = 3.3
Current (mA)
AIDD1 = 0.05
AIDD2 = 2.9
AISS = 0.23
ILOGIC = 0.01
Assume dc-to-dc converter at 65% efficiency. Therefore, VDPC+
power = 156.2 mW. The total input power at the AD5753 side of
the isolated dc-to-dc power module is therefore 156.2 mW +
19.18 mW = 175.38 mW. Subtracting the 0 mW load power
from this value gives the power associated only with the
AD5753, which is 175.38 mW.
Power (mW)
1.2
14.5
3.45
0.033
Using the voltage and current values in Table 53, the total
quiescent current power is 19.18 mW.
Assuming an 85% efficiency isolated, dc-to-dc power module,
the total input power becomes 206.33 mW (see Figure 93).
Next, perform the following calculation:
(VDPC+) × (20 mA + IDPC+) = 22.5 V × 20.5 mA = 461.25 mW
Total Module Power = Input Power − Load Power
Therefore, the equation is as follows:
206.33 mW − 0 mW = 206.33 mW
Rev. 0 | Page 70 of 72
Data Sheet
AD5753
(3) TOTAL MODULE POWER
(1) TOTAL INPUT POWER
+24V
+24V RAIL
–15V
ISOLATED
DC-TO-DC
POWER
MODULE
(85% EFFICIENCY)
+5V
AVDD2
+5V
ADuM412D
+3.3V
LDO
AVDD1
+24V
DC-TO-DC
CIRCUITRY
VDPC+
AD5753
OUTPUT
CIRCUITRY
VI OUT
(2) LOAD POWER
R LOAD
VDPC–
DC-TO-DC
CIRCUITRY
NOTES
1. GRAY ITEMS HIGHLIGHT THE THREE DIFFERENT AREAS USED IN CALCULATIONS.
Figure 93. Example Module Containing the AD5753
Preliminary Techni cal Data
Rev. 0 | Page 71 of 72
17285-020
AVSS
–15V
AD5753
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
40
31
30
1
0.50
BSC
TOP VIEW
1.00
0.95
0.85
0.45
0.40
0.35
*4.70
4.60 SQ
4.50
EXPOSED
PAD
21
11
20
PIN 1
INDICATOR
10
BOTTOM VIEW
0.25 MIN
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5
WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.
11-22-2013-B
PIN 1
INDICATOR
6.10
6.00 SQ
5.90
Figure 94. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.95 mm Package Height
(CP-40-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5753BCPZ-REEL
AD5753BCPZ-RL7
EVAL-AD5753SDZ
1
Temperature Range
−40°C to +115°C
−40°C to +115°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17285-0-5/19(0)
Rev. 0 | Page 72 of 72
Package Option
CP-40-15
CP-40-15
工商网监
湘ICP备2023018690号
