AD5757

Quad Channel, 16-Bit, Serial Input, 4 mA to 20 mA Output DAC, Dynamic Power Control, HART Connectivity AD5757 FEATURES 16-bit resolution and monotonicity Dynamic power control for thermal management or external PMOS mode Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, or 0 mA to 24 mA ±0.05% total unadjusted error (TUE) maximum User programmable offset and gain On-chip diagnostics On-chip reference (±10 ppm/°C maximum) −40°C to +105°C temperature range a dc-to-dc boost converter optimized for minimum on-chip power dissipation. Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5757. The part uses a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, DSP, and microcontroller interface standards. The interface also features optional CRC-8 packet error checking, as well as a watchdog timer that monitors activity on the interface. APPLICATIONS Process control Actuator control PLCs HART network connectivity PRODUCT HIGHLIGHTS 1. 2. 3. 4. Dynamic power control for thermal management. 16-bit performance. Multichannel. HART compliant. GENERAL DESCRIPTION The AD5757 is a quad, current output DAC that operates with a power supply range from 10.8 V to 33 V. On-chip dynamic power control minimizes package power dissipation by regulating the voltage on the output driver from 7.4 V to 29.5 V using COMPANION PRODUCTS Product Family: AD5755-1, AD5755 External References: ADR445, ADR02 Digital Isolators: ADuM1410, ADuM1411 Power: ADP2302, ADP2303 Additional companion products on the AD5757 product page FUNCTIONAL BLOCK DIAGRAM AVCC 5.0V AGND AVDD +15V SWx VBOOST_x 7.4V TO 29.5V DC-TO-DC CONVERTER DVDD DGND LDAC SCLK SDIN SYNC SDO CLEAR FAULT ALERT AD1 AD0 REFOUT REFIN REFERENCE DAC CHANNEL B DAC CHANNEL C GAIN REG A OFFSET REG A DAC CHANNEL A DIGITAL INTERFACE + DAC A IOUT_x CURRENT AND VOLTAGE OUTPUT RANGE SCALING RSET_x CHARTx AD5757 NOTES 1. x = A, B, C, AND D. DAC CHANNEL D 09225-101 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD5757 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Companion Products ....................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Detailed Functional Block Diagram .............................................. 3 Specifications..................................................................................... 4 AC Performance Characteristics ................................................ 6 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 13 Current Outputs ......................................................................... 13 DC-to-DC Block......................................................................... 18 Reference ..................................................................................... 19 General......................................................................................... 20 Terminology .................................................................................... 21 Theory of Operation ...................................................................... 22 DAC Architecture....................................................................... 22 Power-On State of the AD5757 ................................................ 22 Serial Interface ............................................................................ 22 Transfer Function ....................................................................... 23 Registers ........................................................................................... 24 Programming Sequence to Write/Enable the Output Correctly ...................................................................................... 25 Changing and Reprogramming the Range ............................. 25 Data Registers ............................................................................. 26 Control Registers........................................................................ 28 Readback Operation .................................................................. 31 Device Features............................................................................... 33 Output Fault................................................................................ 33 Digital Offset and Gain Control............................................... 33 Status Readback During a Write .............................................. 33 Asynchronous Clear................................................................... 33 Packet Error Checking............................................................... 33 Watchdog Timer......................................................................... 34 Output Alert................................................................................ 34 Internal Reference ...................................................................... 34 External Current Setting Resistor ............................................ 34 HART ........................................................................................... 34 Digital Slew Rate Control.......................................................... 35 Power Dissipation Control........................................................ 35 DC-to-DC Converters............................................................... 35 AICC Supply Requirements—Static .......................................... 37 AICC Supply Requirements—Slewing ...................................... 37 External PMOS Mode................................................................ 38 Applications Information .............................................................. 39 Current Output Mode with Internal RSET ................................ 39 Precision Voltage Reference Selection..................................... 39 Driving Inductive Loads............................................................ 39 Transient Voltage Protection .................................................... 40 Microprocessor Interfacing....................................................... 40 Layout Guidelines....................................................................... 40 Galvanically Isolated Interface ................................................. 41 Outline Dimensions ....................................................................... 42 Ordering Guide .......................................................................... 42 REVISION HISTORY 5/11—Rev. 0 to Rev. A Changes Features Section ................................................................ 1 Changes to Figure 2.......................................................................... 3 Changed AVDD Min Parameter from 10.8 V to 9 V ..................... 5 Changes to Pin 22, Pin31, Pin 49 Descriptions .......................... 11 Changes to Pin 58 Descriptions.................................................... 12 Changes to Figure 8, Figure 9, and Figure 10 ............................. 13 Added Figure 23, Renumbered Sequentially .............................. 15 Added Figure 29.............................................................................. 16 Added External PMOS Mode Section and Figure 62 ................ 38 Rev. A | Page 2 of 44 4/11—Revision 0: Initial Version AD5757 DETAILED FUNCTIONAL BLOCK DIAGRAM AVCC 5.0V AGND AVDD +15V SWA VBOOST_A DVDD DGND LDAC CLEAR SCLK SDIN SYNC SDO FAULT POWER-ON RESET DC-TO-DC CONVERTER POWER CONTROL 16 16 7.4V TO 29.5V VSEN1 REG R2 VSEN2 INPUT SHIFT REGISTER AND CONTROL INPUT REG A GAIN REG A OFFSET REG A + DAC REG A DAC A R3 IOUT_A STATUS REGISTER ALERT WATCHDOG TIMER (SPI ACTIVITY) VREF R1 RSET_A CHARTA REFOUT REFIN AD1 AD0 DAC CHANNEL A REFERENCE BUFFERS DAC CHANNEL B DAC CHANNEL C DAC CHANNEL D SWB, SWC, SWD VBOOST_B, VBOOST_C, VBOOST_D 09225-001 IOUT_B, IOUT_C, IOUT_D RSET_B, RSET_C, RSET_D CHARTB, CHARTC, CHARTD AD5757 Figure 2. Rev. A | Page 3 of 44 AD5757 SPECIFICATIONS AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 CURRENT OUTPUT Output Current Ranges Min 0 0 4 16 Typ Max 24 20 20 Unit mA mA mA Bits Assumes ideal resistor −0.05 TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift 2 Gain Error Gain TC2 Full-Scale Error Full-Scale TC2 DC Crosstalk ACCURACY (INTERNAL RSET) Total Unadjusted Error (TUE) 3 , 4 TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error3, 4 Offset Error Drift2 Gain Error Gain TC2 Full-Scale Error3, 4 Full-Scale TC2 DC Crosstalk4 OUTPUT CHARACTERISTICS2 Current Loop Compliance Voltage Output Current Drift vs. Time 90 140 Resistive Load 1000 ppm FSR ppm FSR Ω −0.006 −1 −0.05 −0.05 −0.05 ±0.009 100 +0.05 +0.006 +1 +0.05 +0.05 +0.05 % FSR ppm FSR % FSR LSB % FSR ppm FSR/°C % FSR ppm FSR/°C % FSR ppm FSR/°C % FSR % FSR % FSR ppm FSR % FSR % FSR LSB % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR V Drift after 1000 hours, ¾ scale output, TJ = 150°C External RSET Internal RSET The dc-to-dc converter has been characterized with a maximum load of 1 kΩ, chosen such that compliance is not exceeded; see Figure 31 and DC-DC MaxV bits in Table 24 Test Conditions/Comments Resolution ACCURACY (EXTERNAL RSET) Total Unadjusted Error (TUE) Drift after 1000 hours, TJ = 150°C Guaranteed monotonic ±0.005 ±4 ±0.004 ±3 ±0.008 ±5 0.0005 External RSET −0.14 −0.11 −0.006 −0.004 −1 −0.05 −0.04 −0.12 −0.06 −0.14 −0.1 ±0.009 180 +0.14 +0.11 +0.006 +0.004 +1 +0.05 +0.04 +0.12 +0.06 +0.14 +0.1 TA = 25°C Drift after 1000 hours, TJ = 150°C TA = 25°C Guaranteed monotonic TA = 25°C ±0.007 ±6 ±0.002 ±9 ±0.007 ±14 −0.011 VBOOST_x − 2.4 TA = 25°C TA = 25°C Internal RSET VBOOST_x − 2.7 Output Impedance DC PSRR REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance 100 0.02 1 MΩ μA/V 4.95 45 5 150 5.05 V MΩ For specified performance Rev. A | Page 4 of 44 AD5757 Parameter 1 Reference Output Output Voltage Reference TC2 Output Noise (0.1 Hz to 10 Hz)2 Noise Spectral Density2 Output Voltage Drift vs. Time2 Capacitive Load2 Load Current Short-Circuit Current Line Regulation2 Load Regulation2 Thermal Hysteresis2 DC-TO-DC Switch Switch On Resistance Switch Leakage Current Peak Current Limit Oscillator Oscillator Frequency Maximum Duty Cycle DIGITAL INPUTS2 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance DIGITAL OUTPUTS2 SDO, ALERT VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance FAULT VOL, Output Low Voltage VOL, Output Low Voltage VOH, Output High Voltage POWER REQUIREMENTS AVDD DVDD AVCC AIDD DICC AICC IBOOST 5 Power Dissipation Min 4.995 −10 Typ 5 ±5 7 100 180 1000 9 10 3 95 160 5 Max 5.005 +10 Unit V ppm/°C μV p-p nV/√Hz ppm nF mA mA ppm/V ppm/mA ppm ppm Test Conditions/Comments TA = 25°C At 10 kHz Drift after 1000 hours, TJ = 150°C See Figure 42 See Figure 43 See Figure 42 First temperature cycle Second temperature cycle 0.425 10 0.8 11.5 13 89.6 2 −1 2.6 0.8 +1 14.5 Ω nA A MHz % V V μA pF This oscillator is divided down to give the dc-to-dc converter switching frequency At 410 kHz dc-to-dc switching frequency JEDEC compliant Per pin Per pin 0.4 DVDD − 0.5 −1 2.5 +1 V V μA pF Sinking 200 μA Sourcing 200 μA 0.4 0.6 3.6 9 2.7 4.5 7 9.2 33 5.5 5.5 7.5 11 1 1 155 V V V V V V mA mA mA mA mW 10 kΩ pull-up resistor to DVDD At 2.5 mA 10 kΩ pull-up resistor to DVDD VIH = DVDD, VIL = DGND, internal oscillator running, over supplies Over supplies Per channel, current output mode, 0 mA output AVDD = 15 V, DVCC = 5 V, dc-to-dc converter enable, current output mode, outputs disabled 1 2 Temperature range: −40°C to +105°C; typical at +25°C. Guaranteed by design and characterization; not production tested. 3 For current outputs with internal RSET, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled loaded with the same code. 4 See the Current Output Mode with Internal RSET section for more explanation of the dc crosstalk. 5 Efficiency plots in Figure 33, Figure 34, Figure 35, and Figure 36 include the IBOOST quiescent current. Rev. A | Page 5 of 44 AD5757 AC PERFORMANCE CHARACTERISTICS AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 DYNAMIC PERFORMANCE Current Output Output Current Settling Time Min Typ Max Unit Test Conditions/Comments Output Noise (0.1 Hz to 10 Hz Bandwidth) Output Noise Spectral Density 1 15 See test conditions/ comments 0.15 0.5 μs ms LSB p-p nA/√Hz To 0.1% FSR (0 mA to 24 mA) See Figure 26, Figure 27, and Figure 28 16-bit LSB, 0 mA to 24 mA range Measured at 10 kHz, midscale output, 0 mA to 24 mA range Guaranteed by design and characterization; not production tested. TIMING CHARACTERISTICS AVDD = VBOOST_x= 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V; REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1, 2, 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 Limit at TMIN, TMAX 33 13 13 13 13 198 5 5 20 5 10 500 See the AC Performance Characteristics section 10 5 40 21 5 500 800 20 5 Unit ns min ns min ns min ns min ns min ns min ns min ns min μs min μs min ns min ns max μs max ns min μs max ns max μs min μs min ns min ns min μs min μs min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th/32nd SCLK falling edge to SYNC rising edge (see Figure 54) SYNC high time Data setup time Data hold time SYNC rising edge to LDAC falling edge (all DACs updated or any channel has digital slew rate control enabled) SYNC rising edge to LDAC falling edge (single DAC updated) LDAC pulse width low LDAC falling edge to DAC output response time DAC output settling time CLEAR high time CLEAR activation time SCLK rising edge to SDO valid SYNC rising edge to DAC output response time (LDAC = 0) (all DACs updated) SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated) LDAC falling edge to SYNC rising edge RESET pulse width SYNC high to next SYNC low (digital slew rate control enabled) (all DACs updated) SYNC high to next SYNC low (digital slew rate control disabled) (single DAC updated) t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 4 1 2 Guaranteed by design and characterization; not production tested. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V. 3 See Figure 3, Figure 4, Figure 5, and Figure 6. 4 This specification applies if LDAC is held low during the write cycle; otherwise, see t9. Rev. A | Page 6 of 44 AD5757 Timing Diagrams t1 SCLK 1 2 24 t6 t4 SYNC t3 t2 t5 t7 SDIN MSB t8 LSB t19 t10 LDAC t9 t10 t17 IOUT_x t12 t11 LDAC = 0 t12 IOUT_x t16 t13 CLEAR t14 IOUT_x Figure 3. Serial Interface Timing Diagram SCLK 1 24 1 24 t6 SYNC SDIN MSB LSB MSB LSB INPUT WORD SPECIFIES REGISTER TO BE READ SDO MSB LSB MSB NOP CONDITION LSB 09225-002 RESET t18 UNDEFINDED t15 SELECTED REGISTER DATA CLOCKED OUT Figure 4. Readback Timing Diagram Rev. A | Page 7 of 44 09225-003 AD5757 1 SCLK 2 MSB SYNC SDIN R/W DUT_ AD1 DUT_ AD0 X X X DB15 DB14 DB1 DB0 SDO SDO DISABLED SDO_ ENAB STATUS STATUS STATUS STATUS Figure 5. Status Readback During Write 200µA IOL TO OUTPUT PIN CL 50pF 200µA IOH VOH (MIN) OR VOL (MAX) 09225-005 Figure 6. Load Circuit for SDO Timing Diagram Rev. A | Page 8 of 44 09225-004 AD5757 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Parameter AVDD, VBOOST_x to AGND, DGND AVCC to AGND DVDD to DGND Digital Inputs to DGND Digital Outputs to DGND REFIN, REFOUT to AGND IOUT_x to AGND SWx to AGND AGND, GNDSWx to DGND Operating Temperature Range (TA) Industrial1 Storage Temperature Range Junction Temperature (TJ max) 64-Lead LFCSP θJA Thermal Impedance2 Power Dissipation Lead Temperature Soldering 1 Rating −0.3 V to +33 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to DVDD + 0.3 V or +7 V (whichever is less) −0.3 V to DVDD + 0.3 V or +7 V (whichever is less) −0.3 V to AVDD + 0.3 V or +7 V (whichever is less) AGND to VBOOST_x or 33 V if using the dc-to-dc circuitry −0.3 V to +33 V −0.3 V to +0.3 V −40°C to +105°C −65°C to +150°C 125°C 20°C/W (TJ max – TA)/θJA JEDEC industry standard J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 2 Power dissipated on chip must be derated to keep the junction temperature below 125°C. Based on a JEDEC 4-layer test board. Rev. A | Page 9 of 44 AD5757 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RSET_C RSET_D REFOUT REFIN NC CHARTD IGATED COMPDCDC_D VBOOST_D NC IOUT_D AGND NC CHARTC NC IGATEC PIN 1 INDICATOR RSET_B RSET_A REFGND REFGND AD0 AD1 SYNC SCLK SDIN SDO DVDD DGND LDAC CLEAR ALERT FAULT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AD5757 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 COMPDCDC_C IOUT_C VBOOST_C AVCC SWC GNDSWC GNDSWD SWD AGND SWA GNDSWA GNDSWB SWB AGND VBOOST_B IOUT_B Figure 7. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3, 4 5 6 7 8 9 10 11 12, 17 13 Mnemonic RSET_B RSET_A REFGND AD0 AD1 SYNC SCLK SDIN SDO DVDD DGND LDAC Description An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_B temperature drift performance. See the Device Features section. An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_A temperature drift performance. See the Device Features section. Ground Reference Point for Internal Reference. Address Decode for the Device Under Test (DUT) on the Board. Address Decode for the DUT on the Board. Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the rising edge of SCLK. This pin operates at clock speeds of up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 5. Digital Supply. The voltage range is from 2.7 V to 5.5 V. Digital Ground. Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at the falling edge of LDAC (see Figure 3). Using this mode, all analog outputs can be updated simultaneously. The LDAC pin must not be left unconnected. Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more information. When CLEAR is active, the DAC output register cannot be written to. Rev. A | Page 10 of 44 14 CLEAR 09225-006 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PAD SHOULD BE CONNECTED TO AGND, OR ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT THE PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. DGND RESET AVDD NC CHARTA IGATEA COMPDCDC_A VBOOST_A NC IOUT_A AGND NC CHARTB NC IGATEB COMPDCDC_B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AD5757 Pin No. 15 16 Mnemonic ALERT FAULT Description Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a predetermined time. See the Device Features section for more information. Active Low Output. This pin is asserted low when an open circuit in current mode is detected, a short circuit in voltage mode is detected, a PEC error is detected, or an overtemperature is detected (see the Device Features section). Open-drain output. Hardware Reset. Active Low Input. Positive Analog Supply. The voltage range is from 10.8 V to 33 V. No Connect. Do not connect to this pin. 18 19 20, 25, 28, 30, 50, 52, 55, 60 21 22 23 RESET AVDD NC CHARTA IGATEA COMPDCDC_A 24 26 27, 40, 53 29 31 32 VBOOST_A IOUT_A AGND CHARTB IGATEB COMPDCDC_B 33 34 35 36 37 38 39 41 42 43 44 45 46 47 48 IOUT_B VBOOST_B AGND SWB GNDSWB GNDSWA SWA SWD GNDSWD GNDSWC SWC AVCC VBOOST_C IOUT_C COMPDCDC_C 49 IGATEC HART Input Connection for DAC Channel A. Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter. See the External PMOS Mode section for more information. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and the AICC Supply Requirements—Slewing sections in the Device Features section for more information). Supply for Channel A Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as shown in Figure 56. Current Output Pin for DAC Channel A. Ground Reference Point for Analog Circuitry. This must be connected to 0 V. HART Input Connection for DAC Channel B. Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter. See the External PMOS Mode section for more information. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more information). Current Output Pin for DAC Channel B. Supply for Channel B Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as shown in Figure 56. Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 56. Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 56. Switching Output for Channel D DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 56. Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground. Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground. Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 56. Supply for DC-to-DC Circuitry. Supply for Channel C Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as shown in Figure 56. Current Output Pin for DAC Channel C. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more information). Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter. See the External PMOS Mode section for more information. Rev. A | Page 11 of 44 AD5757 Pin No. 51 54 56 57 Mnemonic CHARTC IOUT_D VBOOST_D COMPDCDC_D Description HART Input Connection for DAC Channel C. Current Output Pin for DAC Channel D. Supply for Channel D Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as shown in Figure 56. DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more information). Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter. See the External PMOS Mode section for more information. HART Input Connection for DAC Channel D. External Reference Voltage Input. Internal Reference Voltage Output. It is recommended to place a 0.1 μF capacitor between REFOUT and REFGND. An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_D temperature drift performance. See the Device Features section. An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the IOUT_C temperature drift performance. See the Device Features section. Exposed Pad. This exposed pad should be connected to AGND, or, alternatively, it can be left electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance. 58 59 61 62 63 64 IGATED CHARTD REFIN REFOUT RSET_D RSET_C EPAD Rev. A | Page 12 of 44 AD5757 TYPICAL PERFORMANCE CHARACTERISTICS CURRENT OUTPUTS 0.0025 0.0020 0.0015 AV DD = 15V TA = 25°C 0.0010 0.0008 0.0006 INL ERROR (%FSR) INL ERROR (%FSR) 0.0010 0.0005 0 –0.0005 –0.0010 –0.0015 –0.0020 –0.0025 0 10000 4mA TO 4mA TO 4mA TO 4mA TO 4mA TO 20mA, 20mA, 20mA, 20mA, 20mA, EXTERNAL R SET EXTERNAL R SET , WITH DC-TO-DC CONVERTER INTERNAL R SET INTERNAL R SET, WITH DC-TO-DC CONVERTER EXTERNAL R SET , EXTERNAL PMOS MODE 09225-149 0.0004 0.0002 0 –0.0002 –0.0004 –0.0006 –0.0008 09225-152 4mA TO 0mA TO 0mA TO 0mA TO 4mA TO 0mA TO 20mA RANGE MAX INL 24mA RANGE MAX INL 20mA RANGE MIN INL 20mA RANGE MAX INL 20mA RANGE MAX INL 24mA RANGE MIN INL AVDD = 15V 20000 30000 CODE 40000 50000 60000 –0.0010 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 8. Integral Nonlinearity vs. Code 1.0 0.8 0.6 DNL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 10000 20000 30000 CODE 40000 50000 60000 AV DD = 15V TA = 25°C 09225-150 Figure 11. Integral Nonlinearity vs. Temperature, Internal RSET 0.0020 4mA TO 4mA TO 4mA TO 4mA TO 4mA TO 20mA, 20mA, 20mA, 20mA, 20mA, EXTERNAL R SET EXTERNAL R SET , WITH DC-TO-DC CONVERTER INTERNAL R SET INTERNAL R SET, WITH DC-TO-DC CONVERTER EXTERNAL R SET , EXTERNAL PMOS MODE 0.0015 0.0010 INL ERROR (%FSR) 4mA TO 20mA RANGE MAX INL 0mA TO 24mA RANGE MAX INL 0mA TO 20mA RANGE MIN INL 0.0005 0 –0.0005 –0.0010 –0.0015 –0.0020 –40 AVDD = 15V 0mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL 0mA TO 24mA RANGE MIN INL –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 9. Differential Nonlinearity vs. Code 0.035 AV DD = 15V 0.030 TA = 25°C ALL CHANNELS ENABLED 0.025 Figure 12. Integral Nonlinearity vs. Temperature, External RSET 1.0 0.8 0.6 AVDD = 15V ALL RANGES INTERNAL AND EXTERNAL R SET TOTAL UNADJUSTED ERROR (%FSR) 0.015 0.010 0.005 0 –0.005 –0.010 4mA TO 4mA TO 4mA TO 4mA TO 4mA TO 20mA, 20mA, 20mA, 20mA, 20mA, EXTERNAL R SET EXTERNAL R SET , WITH DC-TO-DC CONVERTER INTERNAL R SET INTERNAL R SET , WITH DC-TO-DC CONVERTER EXTERNAL R SET , EXTERNAL PMOS MODE DNL ERROR (%FSR) 0.020 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 DNL ERROR MAX DNL ERROR MIN 0 10000 20000 30000 CODE 40000 50000 60000 09225-151 –20 0 20 40 60 TEMPERATURE (°C) 80 100 Figure 10. Total Unadjusted Error vs. Code Figure 13. Differential Nonlinearity vs. Temperature Rev. A | Page 13 of 44 09225-154 –0.015 –1.0 –40 09225-153 AD5757 0.03 0.02 TOTAL UNADJSUTED ERROR (%FSR) 0.02 0.01 0 GAIN ERROR (%FSR) 0.01 0 –0.01 –0.02 –0.03 –0.04 –0.05 –0.06 –0.07 –0.08 –40 –20 AVDD = 15V 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO 0 20mA INTERNAL RSET 20mA INTERNAL RSET 24mA INTERNAL RSET 20mA EXTERNAL R SET 20mA EXTERNAL R SET 24mA EXTERNAL R SET 09225-155 –0.01 –0.02 –0.03 –0.04 –0.05 –0.06 –40 AVDD = 15V 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO –20 0 20mA INTERNAL RSET 20mA INTERNAL RSET 24mA INTERNAL RSET 20mA EXTERNAL R SET 20mA EXTERNAL R SET 24mA EXTERNAL R SET 80 100 09225-159 09225-057 09225-056 20 40 60 TEMPERATURE (°C) 80 100 20 40 60 TEMPERATURE (°C) Figure 14. Total Unadjusted Error vs. Temperature 0.03 0.02 0.01 FULL-SCALE ERROR (%FSR) Figure 17. Gain Error vs. Temperature 0.0025 0.0020 0.0015 INL ERROR (%FSR) 4mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL TA = 25°C 0 –0.01 –0.02 –0.03 –0.04 –0.05 –0.06 –0.07 –0.08 –40 –20 AVDD = 15V 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO 0 20mA INTERNAL RSET 20mA INTERNAL RSET 24mA INTERNAL RSET 20mA EXTERNAL R SET 20mA EXTERNAL R SET 24mA EXTERNAL R SET 09225-157 0.0010 0.0005 0 –0.0005 –0.0010 –0.0015 –0.0020 10 20 40 60 TEMPERATURE (°C) 80 100 15 20 SUPPLY (V) 25 30 Figure 15. Full-Scale Error vs. Temperature 0.020 0.015 0.010 0.005 0 –0.005 –0.010 –0.015 –0.020 –40 AVDD = 15V 4mA TO 0mA TO 0mA TO 4mA TO 0mA TO 0mA TO –20 0 20mA INTERNAL RSET 20mA INTERNAL RSET 24mA INTERNAL RSET 20mA EXTERNAL RSET 20mA EXTERNAL RSET 24mA EXTERNAL RSET 09225-158 Figure 18. Integral Nonlinearity Error vs. AVDD, Over Supply, External RSET 0.0015 0.0010 0.0005 INL ERROR (%FSR) OFFSET ERROR (%FSR) 0 –0.0005 –0.0010 –0.0015 –0.0020 –0.0025 10 4mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL TA = 25°C 20 40 60 TEMPERATURE (°C) 80 100 15 20 SUPPLY (V) 25 30 Figure 16. Offset Error vs. Temperature Figure 19. Integral Nonlinearity Error vs. AVDD, Over Supply, Internal RSET Rev. A | Page 14 of 44 AD5757 1.0 0.8 0.6 DNL ERROR (%FSR) TOTAL UNADJUSTED ERROR (%FSR) ALL RANGES INTERNAL AND EXTERNAL R SET TA = 25°C 0.006 0.004 0.002 0 –0.002 –0.004 –0.006 –0.008 –0.010 –0.012 MIN OF TUE TA = 25°C EXTERNAL PMOS (NTLJS4149) 4mA TO 20mA RANGE RLOAD = 300Ω MAX OF TUE 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 09225-162 DNL ERROR MAX DNL ERROR MIN 15 20 SUPPLY (V) 25 30 10 15 20 25 30 VBOOST_X SUPPLY (V) Figure 20. Differential Nonlinearity Error vs. AVDD 0.012 Figure 23. Total Unadjusted Error vs. VBOOST_X, Using External PMOS Mode 6 AVDD = 15V TA = 25°C RLOAD = 300Ω TOTAL UNADJUSTED ERROR (%FSR) 0.010 5 0.008 CURRENT (µA) 4 0.006 3 0.004 4mA TO 20mA RANGE MAX TUE 4mA TO 20mA RANGE MIN TUE TA = 25°C 2 0.002 1 09225-060 15 20 SUPPLY (V) 25 30 0 5 10 TIME (µs) 15 20 Figure 21. Total Unadjusted Error vs. AVDD, External RSET 0 –0.002 4 2 0 Figure 24. Output Current vs. Time on Power-Up TOTAL UNADJUSTED ERROR (%FSR) –0.004 –0.006 –0.008 –0.010 –0.012 –0.014 –0.016 –8 VOLTAGE (µA) 4mA TO 20mA RANGE MAX TUE 4mA TO 20mA RANGE MIN TUE TA = 25°C –2 –4 –6 –0.018 09225-061 AVDD = 15V TA = 25°C RLOAD = 300Ω INT_ENABLE 15 20 SUPPLY (V) 25 30 0 1 2 3 TIME (µs) 4 5 6 Figure 22. Total Unadjusted Error vs. AVDD, Internal RSET Figure 25. Output Current vs. Time on Output Enable Rev. A | Page 15 of 44 09225-063 –0.020 10 –10 09225-062 0 10 0 09225-188 –1.0 10 AD5757 30 30 25 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) 25 20 20 15 IOUT VBOOST 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) AVCC = 5V TA = 25°C 09225-167 15 IOUT, AVCC = 4.5V IOUT, AVCC = 5.0V IOUT, AVCC = 5.5V 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 09225-169 10 10 5 5 0 –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 –0.25 TIME (ms) TIME (ms) Figure 26. Output Current and VBOOST_x Settling Time with DC-to-DC Converter (See Figure 56) 30 Figure 28. Output Current Settling with DC-to-DC Converter vs. Time and AVCC (See Figure 56) 25 TOTAL UNADJUSTED ERROR (%FSR) 25 IOUT (4mA TO 20mA STEP) 20 OUTPUT CURRENT (mA) 20 15 15 IOUT, IOUT, IOUT, TA = –40°C TA = +25°C TA = +105°C 10 TA = 25°C EXTERNAL PMOS (NTLJS4149) 4mA TO 20mA RANGE RLOAD = 300Ω VBOOST_X = 24V 10 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) AVCC = 5V 09225-168 5 5 IOUT (20mA TO 4mA STEP) 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 0 5 TIME (µs) 10 15 20 TIME (ms) Figure 27. Output Current Settling with DC-to-DC Converter vs. Time and Temperature (See Figure 56) Figure 29. Output Current Settling Time with External PMOS Transistor Rev. A | Page 16 of 44 09225-189 0 –0.25 0 –5 AD5757 10 8 20mA OUTPUT 10mA OUTPUT 0 AVDD = 15V VBOOST = 15V TA = 25°C CURRENT (AC COUPLED) (µA) 6 4 2 0 –2 –4 –6 –8 –10 AVCC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL R SET TA = 25°C –20 IOUT_x PSRR (dB) –40 –60 –80 –100 0 2 4 6 8 TIME (µs) 10 12 14 09225-170 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 30. Output Current vs. Time with DC-to-DC Converter (See Figure 56) 8 7 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C Figure 32. IOUT_x PSRR vs. Frequency HEADROOM VOLTAGE (V) 6 5 4 3 2 1 0 0 5 10 CURRENT (mA) 15 20 Figure 31. DC-to-DC Converter Headroom vs. Output Current (See Figure 56) 09225-067 Rev. A | Page 17 of 44 09225-068 –120 10 AD5757 DC-TO-DC BLOCK 90 85 AVCC = 4.5V AVCC = 5V AVCC = 5.5V IOUT_x EFFICIENCY (%) 80 20mA 70 VBOOST_x EFFICIENCY (%) 80 75 70 65 60 55 50 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 09225-016 60 50 40 30 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET AVCC = 5V fSW = 410 kHz INDUCTOR = 10µH (XAL4040-103) –20 0 20 40 60 80 100 09225-019 0 4 8 12 CURRENT (mA) 16 20 24 20 –40 TEMPERATURE (°C) Figure 33. Efficiency at VBOOST_x vs. Output Current (See Figure 56) 90 20mA 85 VBOOST_x EFFICIENCY (%) Figure 36. Output Efficiency vs. Temperature (See Figure 56) 0.6 0.5 SWITCH RESISTANCE (Ω) 09225-017 80 75 70 65 60 55 50 –40 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET AVCC = 5V fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) 0.4 0.3 0.2 0.1 –20 0 20 40 60 80 100 –20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 34. Efficiency at VBOOST_x vs. Temperature (See Figure 56) 80 AVCC = 4.5V AVCC = 5V AVCC = 5.5V Figure 37. Switch Resistance vs. Temperature 70 IOUT_x EFFICIENCY (%) 60 50 40 30 0mA TO 24mA RANGE 1kΩ LOAD EXTERNAL RSET fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 0 4 8 12 CURRENT (mA) 16 20 24 09225-018 20 Figure 35. Output Efficiency vs. Output Current (See Figure 56) Rev. A | Page 18 of 44 09225-123 0 –40 AD5757 REFERENCE 16 14 12 10 VOLTAGE (V) 5.0050 AVDD REFOUT TA = 25°C 5.0045 5.0040 5.0035 REFOUT (V) 30 DEVICES SHOWN AVDD = 15V 8 6 4 2 0 09225-010 5.0030 5.0025 5.0020 5.0015 5.0010 5.0005 0 0.2 0.4 0.6 TIME (ms) 0.8 1.0 1.2 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 38. REFOUT Turn-On Transient Figure 41. REFOUT vs. Temperature (When the AD5757 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is –4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. This second shift is due to the relaxation of stress incurred during soldering.) 5.002 4 3 2 AVDD = 15V TA = 25°C 5.001 5.000 AVDD = 15V TA = 25°C REFOUT (µV) REFOUT (V) 1 0 –1 –2 –3 4.999 4.998 4.997 4.996 4.995 09225-011 0 2 4 TIME (s) 6 8 10 0 2 4 6 8 10 LOAD CURRENT (mA) Figure 39. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth) 150 AVDD = 15V TA = 25°C 100 5.00000 Figure 42. REFOUT vs. Load Current TA = 25°C 4.99995 4.99990 50 REFOUT (µV) 0 REFOUT (V) 4.99985 4.99980 4.99975 4.99970 –50 –100 4.99965 4.99960 10 09225-012 0 5 10 TIME (ms) 15 20 15 20 AVDD (V) 25 30 Figure 40. REFOUT Output Noise (100 kHz Bandwidth) Figure 43. REFOUT vs. Supply Rev. A | Page 19 of 44 09225-015 –150 09225-014 09225-163 –2 5.0000 –40 AD5757 GENERAL 450 400 350 DVCC = 5V TA = 25°C 13.4 13.3 13.2 FREQUENCY (MHz) 300 DICC (µA) 13.1 13.0 12.9 12.8 12.7 12.6 –40 DVCC = 5.5V 09225-020 250 200 150 100 50 09225-007 0 0 1 2 3 4 5 –20 0 20 40 60 80 100 SDIN VOLTAGE (V) TEMPERATURE (°C) Figure 44. DICC vs. Logic Input Voltage 8 7 6 5 4 3 2 1 0 10 AIDD TA = 25°C IOUT = 0mA 09225-009 Figure 46. Internal Oscillator Frequency vs. Temperature 14.4 14.2 14.0 FREQUENCY (MHz) CURRENT (mA) 13.8 13.6 13.4 13.2 13.0 2.5 DVCC = 5.5V TA = 25°C 3.0 3.5 4.0 VOLTAGE (V) 4.5 5.0 5.5 09225-021 15 20 VOLTAGE (V) 25 30 Figure 45. AIDD vs. AVDD Figure 47. Internal Oscillator Frequency vs. DVCC Supply Voltage Rev. A | Page 20 of 44 AD5757 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity, is a measure of the maximum deviation, in LSBs, from the best fit line through the DAC transfer function. A typical INL vs. code plot is shown in Figure 8. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot is shown in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5757 is monotonic over its full operating temperature range. Offset Error Offset error is the deviation of the analog output from the ideal zero-scale output when all DAC registers are loaded with 0x0000. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed in % FSR. Gain TC This is a measure of the change in gain error with changes in temperature. Gain TC is expressed in ppm FSR/°C. Full-Scale Error Full-Scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output should be full-scale − 1 LSB. Full-scale error is expressed in percent of full-scale range (% FSR). Full-Scale TC Full-scale TC is a measure of the change in full-scale error with changes in temperature and is expressed in ppm FSR/°C. Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error taking all the various errors into account, including INL error, offset error, gain error, temperature, and time. TUE is expressed in % FSR. DC Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC, which is at midscale. Current Loop Compliance Voltage The maximum voltage at the IOUT_x pin for which the output current is equal to the programmed value. Voltage Reference Thermal Hysteresis Voltage reference thermal hysteresis is the difference in output voltage measured at +25°C compared to the output voltage measured at +25°C after cycling the temperature from +25°C to −40°C to +105°C and back to +25°C. The hysteresis is specified for the first and second temperature cycles and is expressed in ppm. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5757 is powered-on. It is specified as the area of the glitch in nV-sec. See Figure 24. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Reference TC Reference TC is a measure of the change in the reference output voltage with a change in temperature. It is expressed in ppm/°C. Line Regulation Line regulation is the change in reference output voltage due to a specified change in supply voltage. It is expressed in ppm/V. Load Regulation Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/mA. DC-to-DC Converter Headroom This is the difference between the voltage required at the current output and the voltage supplied by the dc-to-dc converter. See Figure 31. Output Efficiency I 2 × R LOAD OUT AVCC × AI CC This is defined as the power delivered to a channel’s load vs. the power delivered to the channel’s dc-to-dc input. Efficiency at VBOOST_x I OUT × V BOOST _ x AVCC × AI CC This is defined as the power delivered to a channel’s VBOOST_x supply vs. the power delivered to the channel’s dc-to-dc input. The VBOOST_x quiescent current is considered part of the dc-todc converter’s losses. Rev. A | Page 21 of 44 AD5757 THEORY OF OPERATION The AD5757 is a quad, precision digital-to-current loop converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost, single-chip solution for generating current loop outputs. The current ranges available are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. The desired output configuration is user selectable via the DAC control register. On-chip dynamic power control minimizes package power dissipation in current mode. POWER-ON STATE OF THE AD5757 On power-up of the AD5757, the IOUT_x pins are in tristate mode. SERIAL INTERFACE The AD5757 is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP standards. Data coding is always straight binary. Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If packet error checking, or PEC (see the Device Features section), is enabled, an additional eight bits must be written to the AD5757, creating a 32-bit serial interface. There are two ways in which the DAC outputs can be updated: individual updating or simultaneous updating of all DACs. DAC ARCHITECTURE The DAC core architecture of the AD5757 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 48. The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either ground or the reference buffer output. The remaining 12 bits of the data-word drive Switch S0 to Switch S11 of a 12-bit voltage mode R-2R ladder network. VOUT 2R 2R S0 2R S1 2R S7/S11 2R E1 2R E2 2R E15 Individual DAC Updating In this mode, LDAC is held low while data is being clocked into the DAC data register. The addressed DAC output is updated on the rising edge of SYNC. See Table 3 and Figure 3 for timing information. 8-/12-BIT R-2R LADDER FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS 09225-069 Simultaneous Updating of All DACs In this mode, LDAC is held high while data is being clocked into the DAC data register. Only the first write to each channel’s DAC data register is valid after LDAC is brought high. Any subsequent writes while LDAC is still held high are ignored, although they are loaded into the DAC data register. All the DAC outputs are updated by taking LDAC low after SYNC is taken high. OUTPUT I/V AMPLIFIER VREFIN 16-BIT DAC VOUT_x Figure 48. DAC Ladder Structure The voltage output from the DAC core is converted to a current (see Figure 49), which is then mirrored to the supply rail so that the application simply sees a current source output. The current outputs are supplied by VBOOST_x. VBOOST_x R2 T2 A2 16-BIT DAC T1 A1 R3 LDAC DAC REGISTER IOUT_x DAC INPUT REGISTER 09225-071 RSET OFFSET AND GAIN CALIBRATION DAC DATA REGISTER Figure 49. Voltage-to-Current Conversion Circuitry INTERFACE LOGIC SDO 09225-072 Reference Buffers The AD5757 can operate with either an external or internal reference. The reference input requires a 5 V reference for specified performance. This input voltage is then buffered before it is applied to the DAC. SCLK SYNC SDIN Figure 50. Simplified Serial Interface of Input Loading Circuitry for One DAC Channel Rev. A | Page 22 of 44 AD5757 TRANSFER FUNCTION For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA current output ranges, the output current is respectively expressed as ⎡ 20 mA ⎤ I OUT = ⎢ N ⎥ × D ⎣2 ⎦ ⎡ 24 mA ⎤ I OUT = ⎢ N ⎥ × D ⎦ ⎣2 ⎡ 16 mA ⎤ I OUT = ⎢ N ⎥ × D + 4 mA ⎦ ⎣2 where: D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC. Rev. A | Page 23 of 44 AD5757 REGISTERS Table 6 shows an overview of the registers for the AD5757. Table 6. Data, Control, and Readback Registers for the AD5757 Register Data DAC Data Register (×4) Gain Register (×4) Offset Register (×4) Clear Code Register (×4) Control Main Control Register Description Used to write a DAC code to each DAC channel. AD5757 data bits = D15 to D0. There are four DAC data registers, one per DAC channel. Used to program gain trim, on a per channel basis. AD5757 data bits = D15 to D0. There are four gain registers, one per DAC channel. Used to program offset trim, on a per channel basis. AD5757 data bits = D15 to D0. There are four offset registers, one per DAC channel. Used to program clear code on a per channel basis. AD5757 data bits = D15 to D0. There are four clear code registers, one per DAC channel. Used to configure the part for main operation. Sets functions such as status readback during write, enables output on all channels simultaneously, powers on all dc-to-dc converter blocks simultaneously, and enables and sets conditions of the watchdog timer. See the Device Features section for more details. Has three functions. Used to perform a reset, to toggle the user bit and, as part of the watchdog timer feature, to verify correct data communication operation. Used to program the slew rate of the output. There are four slew rate control registers, one per channel. These registers are used to control the following: Set the output range, for example, 4 mA to 20 mA. Set whether an internal/external sense resistor is used. Enable/disable a channel for CLEAR. Enable/disable internal circuitry on a per channel basis. Enable/disable output on a per channel basis. Power on dc-to-dc converters on a per channel basis. There are four DAC control registers, one per DAC channel. Use to set the dc-to-dc control parameters. Can control dc-to-dc maximum voltage, phase, and frequency. This contains any fault information, as well as a user toggle bit. Software Register Slew Rate Control Register (×4) DAC Control Register (×4) DC-to-DC Control Register Readback Status Register Rev. A | Page 24 of 44 AD5757 PROGRAMMING SEQUENCE TO WRITE/ENABLE THE OUTPUT CORRECTLY To correctly write to and set up the part from a power-on condition, use the following sequence: 1. 2. Perform a hardware or software reset after initial power-on. The dc-to-dc converter supply block must be configured. Set the dc-to-dc switching frequency, maximum output voltage allowed, and the phase that the four dc-to-dc channels clock at. Configure the DAC control register on a per channel basis. The output range is selected, and the dc-to-dc converter block is enabled (DC_DC bit). Other control bits can be configured at this point. Set the INT_ENABLE bit; however, the output enable bit (OUTEN) should not be set. Write the required code to the DAC data register. This implements a full DAC calibration internally. Allow at least 200 μs before Step 5 for reduced output glitch. Write to the DAC control register again to enable the output (set the OUTEN bit). CHANGING AND REPROGRAMMING THE RANGE When changing between ranges, the same sequence as described in the Programming Sequence to Write/Enable the Output Correctly section should be used. It is recommended to set the range to zero scale prior to disabling the output. Because the dc-to-dc switching frequency, maximum voltage, and phase have already been selected, there is no need to reprogram these. A flowchart of this sequence is shown in Figure 52. CHANNEL’S OUTPUT IS ENABLED. 3. STEP 1: WRITE TO CHANNEL’S DAC DATA REGISTER. SET THE OUTPUT TO 0V (ZERO OR MIDSCALE). 4. STEP 2: WRITE TO DAC CONTROL REGISTER. DISABLE THE OUTPUT (OUTEN = 0), AND SET THE NEW OUTPUT RANGE. KEEP THE DC_DC BIT AND THE INT_ENABLE BIT SET. 5. STEP 3: WRITE VALUE TO THE DAC DATA REGISTER. A flowchart of this sequence is shown in Figure 51. POWER ON. Figure 52. Steps for Changing the Output Range STEP 1: PERFORM A SOFTWARE/HARDWARE RESET. STEP 2: WRITE TO DC-TO-DC CONTROL REGISTER TO SET DC-TO-DC CLOCK FREQUENCY, PHASE, AND MAXIMUM VOLTAGE. STEP 3: WRITE TO DAC CONTROL REGISTER. SELECT THE DAC CHANNEL AND OUTPUT RANGE. SET THE DC_DC BIT AND OTHER CONTROL BITS AS REQUIRED. SET THE INT_ENABLE BIT BUT DO NOT SELECT THE OUTEN BIT. STEP 4: WRITE TO EACH/ALL DAC DATA REGISTERS. ALLOW AT LEAST 200µs BETWEEN STEP 3 AND STEP 5 FOR REDUCED OUTPUT GLITCH. Figure 51. Programming Sequence for Enabling the Output Correctly 09225-073 STEP 5: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 3 ABOVE. THIS TIME SELECT THE OUTEN BIT TO ENABLE THE OUTPUT. Rev. A | Page 25 of 44 09225-074 STEP 4: WRITE TO DAC CONTROL REGISTER. RELOAD SEQUENCE AS IN STEP 2 ABOVE. THIS TIME SELECT THE OUTEN BIT TO ENABLE THE OUTPUT. AD5757 DATA REGISTERS The input register is 24 bits wide. When PEC is enabled, the input register is 32 bits wide, with the last eight bits corresponding to the PEC code (see the Packet Error Checking section for more information on PEC). When writing to a data register, the format in Table 7 must be used. DAC Data Register When writing to the AD5757 DAC data registers, D15 to D0 are used for the DAC data bits. Table 9 shows the register format and Table 8 describes the function of Bit D23 to Bit D16. Table 7. Writing to a Data Register MSB D23 R/W D22 DUT_AD1 D21 DUT_AD0 D20 DREG2 D19 DREG1 D18 DREG0 D17 DAC_AD1 D16 DAC_AD0 LSB D15 to D0 Data Table 8. Input Register Decode Bit R/W DUT_AD1, DUT_AD0 Description Indicates a read from or a write to the addressed register. Used in association with the external pins, AD1 and AD0, to determine which AD5757 device is being addressed by the system controller. DUT_AD1 DUT_AD0 Function 0 0 Addresses part with Pin AD1 = 0, Pin AD0 = 0 0 1 Addresses part with Pin AD1 = 0, Pin AD0 = 1 1 0 Addresses part with Pin AD1 = 1, Pin AD0 = 0 1 1 Addresses part with Pin AD1 = 1, Pin AD0 = 1 Selects whether a data register or a control register is written to. If a control register is selected, a further decode of CREG bits (see Table 16) is required to select the particular control register, as follows. DREG2 DREG1 DREG0 Function 0 0 0 1 1 1 1 DAC_AD1, DAC_AD0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 Write to DAC data register (individual channel write) Write to gain register Write to gain register (all DACs) Write to offset register Write to offset register (all DACs) Write to clear code register Write to a control register DREG2, DREG1, DREG0 These bits are used to decode the DAC channel. DAC_AD1 DAC_AD0 DAC Channel/Register Address 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D X X These are don’t cares if they are not relevant to the operation being performed. Table 9. Programming the DAC Data Registers MSB D23 R/W D22 DUT_AD1 D21 DUT_AD0 D20 DREG2 D19 DREG1 D18 DREG0 D17 DAC_AD1 D16 DAC_AD0 LSB D15 to D0 DAC data Rev. A | Page 26 of 44 AD5757 Gain Register The 16-bit gain register, as shown in Table 10, allows the user to adjust the gain of each channel in steps of 1 LSB. This is done by setting the DREG[2:0] bits to 010. It is possible to write the same gain code to all four DAC channels at the same time by setting the DREG[2:0] bits to 011. The gain register coding is straight binary as shown in Table 11. The default code in the gain register is 0xFFFF. In theory, the gain can be tuned across the full range of the output. In practice, the maximum recommended gain trim is about 50% of programmed range to maintain accuracy. See the Digital Offset and Gain Control section for more information. Offset Register The 16-bit offset register, as shown in Table 12, allows the user to adjust the offset of each channel by −32,768 LSBs to +32,767 LSBs in steps of 1 LSB. This is done by setting the DREG[2:0] bits to 100. It is possible to write the same offset code to all four DAC channels at the same time by setting the DREG[2:0] bits to 101. The offset register coding is straight binary as shown in Table 13. The default code in the offset register is 0x8000, which results in zero offset programmed to the output. See the Digital Offset and Gain Control section for more information. Clear Code Register The 16-bit clear code register allows the user to set the clear value of each channel as shown in Table 14. It is possible, via software, to enable or disable on a per channel basis which channels are cleared when the CLEAR pin is activated. The default clear code is 0x0000. See the Asynchronous Clear section for more information. Table 10. Programming the Gain Register R/W 0 DUT_AD1 DUT_AD0 Device address DREG2 0 DREG1 1 DREG0 0 DAC_AD1 DAC_AD0 DAC channel address D15 to D0 Gain adjustment Table 11. Gain Register Gain Adjustment +65,535 LSBs +65,534 LSBs … 1 LSB 0 LSBs G15 1 1 … 0 0 G14 1 1 … 0 0 G13 1 1 … 0 0 G12 to G4 1 1 … 0 0 G3 1 1 … 0 0 G2 1 1 … 0 0 G1 1 0 … 0 0 G0 1 0 … 1 0 Table 12. Programming the Offset Register R/W 0 DUT_AD1 DUT_AD0 Device address DREG2 1 DREG1 0 DREG0 0 DAC_AD1 DAC_AD0 DAC channel address D15 to D0 Offset adjustment Table 13. Offset Register Options Offset Adjustment +32,767 LSBs +32,766 LSBs … No Adjustment (Default) … −32,767 LSBs −32,768 LSBs OF15 1 1 … 1 … 0 0 OF14 1 1 … 0 … 0 0 OF13 1 1 … 0 … 0 0 OF12 to OF4 1 1 … 0 … 0 0 OF3 1 1 … 0 … 0 0 OF2 1 1 … 0 … 0 0 OF1 1 0 … 0 … 0 0 OF0 1 0 … 0 … 0 0 Table 14. Programming the Clear Code Register R/W 0 DUT_AD1 DUT_AD0 Device address DREG2 1 DREG1 1 DREG0 0 DAC_AD1 DAC_AD0 DAC channel address D15 to D0 Clear code Rev. A | Page 27 of 44 AD5757 CONTROL REGISTERS When writing to a control register, the format shown in Table 15 must be used. See Table 8 for information on the configuration of Bit D23 to Bit D16. The control registers are addressed by setting the DREG[2:0] bits to 111 and then setting the CREG[2:0] bits to the appropriate decode address for that register, according to Table 16. These CREG bits select among the various control registers. Table 15. Writing to a Control Register MSB D23 R/W D22 DUT_AD1 D21 DUT_AD0 D20 1 D19 1 D18 1 D17 DAC_AD1 D16 DAC_AD0 D15 CREG2 D14 CREG1 D13 CREG0 LSB D12 to D0 Data Main Control Register The main control register options are shown in Table 17 and Table 18. See the Device Features section for more information on the features controlled by the main Control Register. Table 16. Register Access Decode CREG2 (D15) 0 0 0 0 1 CREG1 (D14) 0 0 1 1 0 CREG0 (D13) 0 1 0 1 0 Function Slew rate control register (one per channel) Main control register DAC control register (one per channel) DC-to-dc control register Software register (one per channel) Table 17. Programming the Main Control Register MSB D15 0 1 D14 0 D13 1 D12 0 D11 STATREAD D10 EWD D9 WD1 D8 WD0 D7 X1 D6 X1 D5 OUTEN_ALL D4 DCDC_ALL LSB D3 to D0 X1 X = don’t care. Table 18. Main Control Register Functions Bit STATREAD Description Enable status readback during a write. See the Device Features section. STATREAD = 1, enable. STATREAD = 0, disable (default). Enable watchdog timer. See the Device Features section for more information. EWD = 1, enable watchdog. EWD = 0, disable watchdog (default). Timeout select bits. Used to select the timeout period for the watchdog timer. WD1 WD0 Timeout Period (ms) 0 0 5 0 1 10 1 0 100 1 1 200 Enables the output on all four DACs simultaneously. Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register. When set, powers up the dc-to-dc converter on all four channels simultaneously. To power down the dc-to-dc converters, all channel outputs must first be disabled. Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register. EWD WD1, WD0 OUTEN_ALL DCDC_ALL Rev. A | Page 28 of 44 AD5757 DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 19 and Table 20. Table 19. Programming DAC Control Register D15 0 1 D14 1 D13 0 D12 X1 D11 X1 D10 X1 D9 X1 D8 INT_ENABLE D7 CLR_EN D6 OUTEN D5 RSET D4 DC_DC D3 X1 D2 R2 D1 R1 D0 R0 X = don’t care. Table 20. DAC Control Register Functions Bit INT_ENABLE Description Powers up the dc-to-dc converter, DAC, and internal amplifiers for the selected channel. Does not enable the output. Can only be done on a per channel basis. It is recommended to set this bit and allow a >200 μs delay before enabling the output because this results in a reduced output enable glitch. Plots of this glitch can be found in Figure 25. Per channel clear enable bit. Selects if this channel clears when the CLEAR pin is activated. CLR_EN = 1, channel clears when the part is cleared. CLR_EN = 0, channel does not clear when the part is cleared (default). Enables/disables the selected output channel. OUTEN = 1, enables the channel. OUTEN = 0, disables the channel (default). Selects an internal or external current sense resistor for the selected DAC channel. RSET = 0, selects the external resistor (default). RSET = 1, selects the internal resistor. Powers the dc-to-dc converter on the selected channel. DC_DC = 1, power up the dc-to-dc converter. DC_DC = 0, power down the dc-to-dc converter (default). This allows per channel dc-to-dc converter power-up/power-down. To power down the dc-to-dc converter, the OUTEN and INT_ENABLE bits must also be set to 0. All dc-to-dc converters can also be powered up simultaneously using the DCDC_ALL bit in the main control register. Selects the output range to be enabled. R2 R1 R0 Output Range Selected 1 0 0 4 mA to 20 mA current range 1 0 1 0 mA to 20 mA current range 1 1 0 0 mA to 24 mA current range CLR_EN OUTEN RSET DC_DC R2, R1, R0 Rev. A | Page 29 of 44 AD5757 Software Register The software register has three functions. It allows the user to perform a software reset to the part. It can be used to set the user toggle bit, D11, in the status register. It is also used as part of the watchdog feature when it is enabled. This feature is useful to ensure that communication has not been lost between the MCU and the AD5757 and that the datapath lines are working properly (that is, SDIN, SCLK, and SYNC). When the watchdog feature is enabled, the user must write 0x195 to the software register within the timeout period. If this command is not received within the timeout period, the ALERT pin signals a fault condition. This is only required when the watchdog timer function is enabled. DC-to-DC Control Register The dc-to-dc control register allows the user control over the dc-to-dc switching frequency and phase, as well as the maximum allowable dc-to-dc output voltage. The dc-to-dc control register options are shown in Table 23 and Table 24. LSB D11 to D0 Reset code/SPI code Table 21. Programming the Software Register MSB D15 1 D14 0 D13 0 D12 User program Table 22. Software Register Functions Bit User Program Description This bit is mapped to Bit D11 of the status register. When this bit is set to 1, Bit D11 of the status register is set to 1. Likewise, when D12 is set to 0, Bit D11 of the status register is also set to zero. This feature can be used to ensure that the SPI pins are working correctly by writing a known bit value to this register and reading back the corresponding bit from the status register. Option Description Reset code Writing 0x555 to D[11:0] performs a reset of the AD5757. SPI code If the watchdog timer feature is enabled, 0x195 must be written to the software register (D11 to D0) within the programmed timeout period. Reset Code/SPI Code Table 23. Programming the DC-to-DC Control Register MSB D15 0 1 D14 1 D13 1 D12 to D7 X1 D6 DC-DC Comp D5 to D4 DC-DC phase D3 to D2 DC-DC Freq LSB D1 to D0 DC-DC MaxV X = don’t care. Table 24. DC-to-DC Control Register Options Bit DC-DC Comp Description Selects between an internal and external compensation resistor for the dc-to-dc converter. See the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more information. 0 = selects the internal 150 kΩ compensation resistor (default). 1 = bypasses the internal compensation resistor for the dc-to-dc converter. In this mode, an external dc-to-dc compensation resistor must be used; this is placed at the COMPDCDC_x pin in series with the 10 nF dc-to-dc compensation capacitor to ground. Typically, a ~50 kΩ resistor is recommended. User programmable dc-to-dc converter phase (between channels). 00 = all dc-to-dc converters clock on the same edge (default). 01 = Channel A and Channel B clock on the same edge, Channel C and Channel D clock on opposite edges. 10 = Channel A and Channel C clock on the same edge, Channel B and Channel D clock on opposite edges. 11 = Channel A, Channel B, Channel C, and Channel D clock 90° out of phase from each other. DC-to-dc switching frequency; these are divided down from the internal 13 MHz oscillator (see Figure 46 and Figure 47). 00 = 250 ± 10% kHz. 01 = 410 ± 10% kHz (default). 10 = 650 ± 10% kHz. Maximum allowed VBOOST_x voltage supplied by the dc-to-dc converter. 00 = 23 V + 1 V/−1.5 V (default). 01 = 24.5 V ± 1 V. 10 = 27 V ± 1 V. 11 = 29.5 V ± 1V. Rev. A | Page 30 of 44 DC-DC Phase DC-DC Freq DC-DC MaxV AD5757 Slew Rate Control Register This register is used to program the slew rate control for the selected DAC channel. The slew rate control is enabled/ disabled and programmed on a per channel basis. See Table 25 and the Digital Slew Rate Control section for more information. request to read yet another register on a third data transfer or 0x1CE000, which is the no operation command. Readback Example To read back the gain register of Device 1, Channel A on the AD5757, implement the following sequence: 1. Write 0xA80000 to the AD5757 input register. This configures the AD5757 Device Address 1 for read mode with the gain register of Channel A selected. All the data bits, D15 to D0, are don’t cares. Follow with another read command or a no operation command (0x1CE000). During this command, the data from the Channel A gain register is clocked out on the SDO line. READBACK OPERATION Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. See Table 26 for the bits associated with a readback operation. The DUT_AD1 and DUT_AD0 bits, in association with Bits RD[4:0], select the register to be read. The remaining data bits in the write sequence are don’t cares. During the next SPI transfer (see Figure 4), the data appearing on the SDO output contains the data from the previously addressed register. This second SPI transfer should either be a Table 25. Programming the Slew Rate Control Register D15 0 1 2. D14 0 D13 0 D12 SE D11 to D7 X1 D6 to D3 SR_CLOCK D2 to D0 SR_STEP X = don’t care. Table 26. Input Shift Register Contents for a Read Operation D23 R/W 1 D22 DUT_AD1 D21 DUT_AD0 D20 RD4 D19 RD3 D18 RD2 D17 RD1 D16 RD0 D15 to D0 X1 X = don’t care. Table 27. Read Address Decoding RD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 RD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 RD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 RD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 RD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Function Read DAC A data register Read DAC B data register Read DAC C data register Read DAC D data register Read DAC A control register Read DAC B control register Read DAC C control register Read DAC D control register Read DAC A gain register Read DAC B gain register Read DAC C gain register Read DAC D gain register Read DACA offset register Read DAC B offset register Read DAC C offset register Read DAC D offset register Clear DAC A code register Clear DAC B code register Clear DAC C code register Clear DAC D code register DAC A slew rate control register DAC B slew rate control register DAC C slew rate control register DAC D slew rate control register Read status register Read main control register Read dc-to-dc control register Rev. A | Page 31 of 44 AD5757 Status Register The status register is a read only register. This register contains any fault information as a well as a ramp active bit and a user toggle bit. When the STATREAD bit in the main control Table 28. Decoding the Status Register MSB D15 DCDCD 1 register is set, the status register contents can be read back on the SDO pin during every write sequence. Alternatively, if the STATREAD bit is not set, the status register can be read using the normal readback operation. D14 DCDCC D13 DCDCB D12 DCDCA D11 User toggle D10 PEC error D9 Ramp active D8 Over TEMP D7 X1 D6 X1 D5 X1 D4 X1 D3 IOUT_D fault D2 IOUT_C fault D1 IOUT_B fault LSB D0 IOUT_A fault X = don’t care. Table 29. Status Register Options Bit DC-DCD Description This bit is set on Channel D if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX voltage). In this case, the IOUT_D fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information on this bit’s operation under this condition. This bit is set on Channel C if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX voltage). In this case, the IOUT_C fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information on this bit’s operation under this condition. This bit is set on Channel B if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX voltage). In this case, the IOUT_B fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information on this bit’s operation under this condition. This bit is set on Channel A if the dc-to-dc converter cannot maintain compliance (it may be reaching its VMAX voltage). In this case, the IOUT_A fault bit is also set. See the DC-to-DC Converter VMAX Functionality section for more information on this bit’s operation under this condition. User toggle bit. This bit is set or cleared via the software register. This can be used to verify data communications if needed. Denotes a PEC error on the last data-word received over the SPI interface. This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel). This bit is set if the AD5757 core temperature exceeds approximately 150°C. This bit is set if a fault is detected on the IOUT_D pin. This bit is set if a fault is detected on the IOUT_C pin. This bit is set if a fault is detected on the IOUT_B pin. This bit is set if a fault is detected on the IOUT_A pin. DC-DCC DC-DCB DC-DCA User toggle PEC Error Ramp Active Over TEMP IOUT_D Fault IOUT_C Fault IOUT_B Fault IOUT_A Fault Rev. A | Page 32 of 44 AD5757 DEVICE FEATURES OUTPUT FAULT The AD5757 is equipped with a FAULT pin, an active low opendrain output allowing several AD5757 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the following fault scenarios: • Theory of Operation section. Both the gain register and the offset register have 16 bits of resolution. The correct method to calibrate the gain/offset is to first calibrate out the gain and then calibrate the offset. The value (in decimal) that is written to the DAC input register can be calculated by • • The voltage at IOUT_x attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a comparator with windowed limits because this requires an actual output error before the FAULT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability. Thus, the FAULT output activates slightly before the compliance limit is reached. An interface error is detected due to a PEC failure. See the Packet Error Checking section. If the core temperature of the AD5757 exceeds approximately 150°C. Code DACRegister = D × ( M + 1) 216 + C − 215 (1) where: D is the code loaded to the DAC channel’s input register. M is the code in the gain register (default code = 216 – 1). C is the code in the offset register (default code = 215). STATUS READBACK DURING A WRITE The AD5757 has the ability to read back the status register contents during every write sequence. This feature is enabled via the STATREAD bit in the main control register. This allows the user to continuously monitor the status register and act quickly in the case of a fault. When status readback during a write is enabled, the contents of the 16-bit status register (see Table 29) are output on the SDO pin, as shown in Figure 5. The AD5757 powers up with this feature disabled. When this is enabled, the normal readback feature is not available, except for the status register. To read back any other register, clear the STATREAD bit first before following the readback sequence. STATREAD can be set high again after the register read. The IOUT_x fault, PEC error, and over TEMP bits of the status register are used in conjunction with the FAULT output to inform the user which one of the fault conditions caused the FAULT output to be activated. DIGITAL OFFSET AND GAIN CONTROL Each DAC channel has a gain (M) and offset (C) register, which allow trimming out of the gain and offset errors of the entire signal chain. Data from the DAC data register is operated on by a digital multiplier and adder controlled by the contents of the M and C registers. The calibrated DAC data is then stored in the DAC input register. INPUT REGISTER DAC REGISTER DAC ASYNCHRONOUS CLEAR CLEAR is an active high, edge-sensitive input that allows the output to be cleared to a preprogrammed 16-bit code. This code is user programmable via a per channel 16-bit clear code register. For a channel to clear, that channel must be enabled to be cleared via the CLR_EN bit in the channel’s DAC control register. If the channel is not enabled to be cleared, the output remains in its current state independent of the CLEAR pin level. M REGISTER C REGISTER 09225-075 When the CLEAR signal is returned low, the relevant outputs remain cleared until a new value is programmed. Figure 53. Digital Offset and Gain control PACKET ERROR CHECKING To verify that data has been received correctly in noisy environments, the AD5757 offers the option of packet error checking based on an 8-bit cyclic redundancy check (CRC-8). The device controlling the AD5757 should generate an 8-bit frame check sequence using the polynomial C(x) = x8 + x2 + x1 + 1 Although Figure 53 indicates a multiplier and adder for each channel, there is only one multiplier and one adder in the device, and they are shared among all four channels. This has implications for the update speed when several channels are updated at once (see Table 3). Each time data is written to the M or C register, the output is not automatically updated. Instead, the next write to the DAC channel uses these M and C values to perform a new calibration and automatically updates the channel. The output data from the calibration is routed to the DAC input register. This is then loaded to the DAC as described in the This is added to the end of the data-word, and 32 bits are sent to the AD5757 before taking SYNC high. If the AD5757 sees a 32-bit frame, it performs the error check when SYNC goes high. If the check is valid, the data is written to the selected register. Rev. A | Page 33 of 44 AD5757 If the error check fails, the FAULT pin goes low and the PEC error bit in the status register is set. After reading the status register, FAULT returns high (assuming there are no other faults), and the PEC error bit is cleared automatically. UPDATE ON SYNC HIGH SYNC INTERNAL REFERENCE The AD5757 contains an integrated 5 V voltage reference with initial accuracy of ±5 mV maximum and a temperature drift coefficient of ±10 ppm maximum. The reference voltage is buffered and externally available for use elsewhere within the system. SCLK MSB D23 SDIN 24-BIT DATA 24-BIT DATA TRANSFER—NO ERROR CHECKING LSB D0 EXTERNAL CURRENT SETTING RESISTOR Referring to Figure 49, RSET is an internal sense resistor as part of the voltage to current conversion circuitry. The stability of the output current value over temperature is dependent on the stability of the value of RSET. As a method of improving the stability of the output current over temperature, an external 15 kΩ low drift resistor can be connected to the RSET_x pin of the AD5757 to be used instead of the internal resistor, R1. The external resistor is selected via the DAC control register (see Table 19). Table 1 outlines the performance specifications of the AD5757 with both the internal RSET resistor and an external, 15 kΩ RSET resistor. Using an external RSET resistor allows for improved performance over the internal RSET resistor option. The external RSET resistor specification assumes an ideal resistor; the actual performance depends on the absolute value and temperature coefficient of the resistor used. This directly affects the gain error of the output, and thus the total unadjusted error. To arrive at the gain/TUE error of the output with a particular external RSET resistor, add the percentage absolute error of the RSET resistor directly to the gain/TUE error of the AD5757 with the external RSET resistor, shown in Table 1 (expressed in % FSR). SYNC UPDATE AFTER SYNC HIGH ONLY IF ERROR CHECK PASSED SCLK MSB D31 SDIN 24-BIT DATA LSB D8 D7 8-BIT CRC D0 32-BIT DATA TRANSFER WITH ERROR CHECKING Figure 54. PEC Timing The PEC can be used for both transmit and receive of data packets. If status readback during a write is enabled, the PEC values returned during the status readback during a write operation should be ignored. If status readback during a write is disabled, the user can still use the normal readback operation to monitor status register activity with PEC. 09225-180 FAULT FAULT PIN GOES HIGH IF ERROR CHECK FAILS HART The AD5757 has four CHART pins, one corresponding to each output channels. A HART signal can be coupled into these pins. The HART signal appears on the corresponding current output, if the output is enabled. Table 30 shows the recommended input voltages for the HART signal at the CHART pin. If these voltages are used, the current output should meet the HART amplitude specifications. Figure 55 shows the recommended circuit for attenuating and coupling in the HART signal. Table 30. CHART Input Voltage to HART Output Current RSET Internal RSET External RSET CHART Input Voltage 150 mV p-p 170 mV p-p C1 CHARTx HART MODEM OUTPUT C2 09225-076 WATCHDOG TIMER When enabled, an on-chip watchdog timer generates an alert signal if 0x195 has not been written to the software register within the programmed timeout period. This feature is useful to ensure that communication has not been lost between the MCU and the AD5757 and that these datapath lines are working properly (that is, SDIN, SCLK, and SYNC). If 0x195 is not received by the software register within the timeout period, the ALERT pin signals a fault condition. The ALERT signal is active high and can be connected directly to the CLEAR pin to enable a CLEAR in the event that communication from the MCU is lost. The watchdog timer is enabled, and the timeout period (5 ms, 10 ms, 100 ms, or 200 ms) is set in the main control register (see Table 17 and Table 18). Current Output (HART) 1 mA p-p 1 mA p-p OUTPUT ALERT The AD5757 is equipped with an ALERT pin. This is an active high CMOS output. The AD5757 also has an internal watchdog timer. When enabled, it monitors SPI communications. If 0x195 is not received by the software register within the timeout period, the ALERT pin goes active. Figure 55. Coupling HART Signal A minimum capacitance of C1 + C2 is required to ensure that the 1.2 kHz and 2.2 kHz HART frequencies are not significantly attenuated at the output. The recommended values are C1 = 22 nF, C2 = 47 nF. Rev. A | Page 34 of 44 AD5757 Digitally controlling the slew rate of the output is necessary to meet the analog rate of change requirements for HART. The following equation describes the slew rate as a function of the step size, the update clock frequency, and the LSB size: DIGITAL SLEW RATE CONTROL The slew rate control feature of the AD5757 allows the user to control the rate at which the output value changes. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load. To reduce the slew rate, this can be achieved by enabling the slew rate control feature. With the feature enabled via the SREN bit of the slew rate control register (see Table 25), the output, instead of slewing directly between two values, steps digitally at a rate defined by two parameters accessible via the slew rate control register, as shown in Table 25. The parameters are SR_CLOCK and SR_STEP. SR_CLOCK defines the rate at which the digital slew is updated, for example, if the selected update rate is 8 kHz, the output updates every 125 μs. In conjunction with this, SR_STEP defines by how much the output value changes at each update. Together, both parameters define the rate of change of the output value. Table 31 and Table 32 outline the range of values for both the SR_CLOCK and SR_STEP parameters. Table 31. Slew Rate Update Clock Options SR_CLOCK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 Slew Time = Output Change Step Size × Update Clock Frequency × LSB Size where: Slew Time is expressed in seconds. Output Change is expressed in amps for IOUT_x. When the slew rate control feature is enabled, all output changes occur at the programmed slew rate (see the DC-to-DC Converter Settling Time section for additional information). For example, if the CLEAR pin is asserted, the output slews to the clear value at the programmed slew rate (assuming that the clear channel is enabled to be cleared). If a number of channels are enabled for slew, care must be taken when asserting the CLEAR pin. If one of the channels is slewing when CLEAR is asserted, other channels may change directly to their clear values not under slew rate control. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range. Update Clock Frequency (Hz)1 64 k 32 k 16 k 8k 4k 2k 1k 500 250 125 64 32 16 8 4 0.5 POWER DISSIPATION CONTROL The AD5757 contains integrated dynamic power control using a dc-to-dc boost converter circuit, allowing reductions in power consumption from standard designs. In standard current input module designs, the load resistor values can range from typically 50 Ω to 750 Ω. Output module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor values. For example, in a 4 mA to 20 mA loop when driving 20 mA, a compliance voltage of >15 V is required. When driving 20 mA into a 50 Ω load, only 1 V compliance is required. The AD5757 circuitry senses the output voltage and regulates this voltage to meet compliance requirements plus a small headroom voltage. The AD5757 is capable of driving up to 24 mA through a 1 kΩ load. DC-TO-DC CONVERTERS The AD5757 contains four independent dc-to-dc converters. These are used to provide dynamic control of the VBOOST supply voltage for each channel (see Figure 49). Figure 56 shows the discreet components needed for the dc-to-dc circuitry, and the following sections describe component selection and operation of this circuitry. AVCC CIN ≥10µF LDCDC 10µH SWx DDCDC CDCDC 4.7µF RFILTER 10Ω VBOOST_X 09225-077 These clock frequencies are divided down from the 13 MHz internal oscillator. See Table 1, Figure 46, and Figure 47. Table 32. Slew Rate Step Size Options SR_STEP 000 001 010 011 100 101 110 111 Step Size (LSBs) 1 2 4 16 32 64 128 256 CFILTER 0.1µF Figure 56. DC-to-DC Circuit Rev. A | Page 35 of 44 AD5757 Table 33. Recommended DC-to-DC Components Symbol LDCDC CDCDC DDCDC Component XAL4040-103 GRM32ER71H475KA88L PMEG3010BEA Value 10 μH 4.7 μF 0.38 VF Manufacturer Coilcraft® Murata NXP 29.6 29.5 29.4 VMAX DC_DC BIT 0mA TO 24mA RANGE, 24mA OUTPUT OUTPUT UNLOADED VBOOST VOLTAGE (mV) 29.3 29.2 29.1 29.0 28.9 28.8 28.7 DC-DCx BIT = 0 09225-183 It is recommended to place a 10 Ω, 100 nF low-pass RC filter after CDCDC. This consumes a small amount of power but reduces the amount of ripple on the VBOOST_x supply. DC-DCx BIT = 1 DC-DCMaxV = 29.5V DC-to-DC Converter Operation The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step up an AVCC input of 4.5 V to 5.5 V to drive the AD5757 output channel. These are designed to operate in discontinuous conduction mode (DCM) with a duty cycle of 3 μF under all operating conditions. The input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low ESR component. For the AD5757, a low ESR tantalum or ceramic capacitor of 10 μF is recommended for typical applications. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature. X5R or X7R dielectrics are preferred because these capacitors remain stable over wider operating voltage and temperature ranges. Care must be taken if selecting a tantalum capacitor to ensure a low ESR value. 25 0.5 0.4 0.3 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 20 15 10 0.2 0.1 0 AICC IOUT VBOOST 0 0.5 1.0 1.5 TIME (ms) 2.0 2.5 5 Figure 58. AICC Current vs. Time for 24 mA Slew with Internal Compensation Resistor Reducing AICC Current Requirements There are two main methods that can be used to reduce the AICC current requirements. One method is to add an external compensation resistor, and the other is to use slew rate control. Both of these methods can be used in conjunction. A compensation resistor can be placed at the COMPDCDC_x pin in series with the 10 nF compensation capacitor. A 51 kΩ external compensation resistor is recommended. This compensation increases the slew time of the current output but eases the AICC transient current requirements. Figure 59 shows a plot of AICC current for a 24 mA step through a 1 kΩ load when using a 51 kΩ compensation resistor. This method eases the current requirements through smaller loads even further, as shown in Figure 60. AICC SUPPLY REQUIREMENTS—STATIC The dc-to-dc converter is designed to supply a VBOOST_x voltage of VBOOST = IOUT × RLOAD + Headroom (2) See Figure 31 for a plot of headroom supplied vs. output voltage. This means that, for a fixed load and output voltage, the dc-to-dc converter output current can be calculated by the following formula: AI CC = Power Out Efficiency × AVCC = ηVBOOST × AVCC I OUT × VBOOST (3) where: IOUT is the output current from IOUT_x in amps. ηVBOOST is the efficiency at VBOOST_x as a fraction (see Figure 33 and Figure 34). Rev. A | Page 37 of 44 09225-184 0 IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V) DC-to-DC Converter Input and Output Capacitor Selection 30 AD5757 0.8 0.7 0.6 AICC CURRENT (A) 28 24 20 16 12 8 IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V) 0.7 0.6 AICC CURRENT (A) 28 24 20 16 12 8 4 0 0.5 0.4 0.3 0.2 0.1 0 AICC IOUT VBOOST 0 0.5 1.0 1.5 TIME (ms) 2.0 2.5 0.5 0.4 0.3 0.2 AICC IOUT VBOOST 4 0 0.1 0 0 1 2 0.8 0.7 0.6 AICC CURRENT (A) 32 AICC IOUT VBOOST 0mA TO 24mA RANGE 500Ω LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 28 24 20 16 12 8 4 0 IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V) 3 TIME (ms) 4 5 6 Figure 61. AICC Current vs. Time for 24 mA Slew with Slew Rate Control EXTERNAL PMOS MODE The AD5757 can also be used with an external PMOS transistor per channel, as shown in Figure 62. This mode can be used to limit the on-chip power dissipation of the AD5757, though this will not reduce the power dissipation of the total system. The IGATE functionality is not typically required when using the dynamic power control feature so Figure 62 shows the configuration of the device for a fixed VBOOST_x supply. In this configuration the SWx pin are left floating and the GNDSWx pin is grounded. The VBOOST_x pin is connected to a minimum supply of 7.5 V and a maximum supply of 33 V. This supply can be sized according to the maximum load required to be driven. The IGATE functionality works by holding the gate of the external PMOS transistor at (VBOOST_x − 5 V). This means that the majority of the channels power dissipation will take place in this external PMOS transistor. The external PMOS transistor should be chosen tolerate a VDS voltage of at least −VBOOST_x, as well as to handle the power dissipation required. This external PMOS transistor typically has minimal effect on the current output performance. 0.5 0.4 0.3 0.2 0.1 0 0 0.5 1.0 1.5 TIME (ms) 2.0 2.5 Figure 60. AICC Current vs. Time for 24 mA Through 500 Ω Slew with External 51 kΩ Compensation Resistor Using slew rate control can greatly reduce the AVCC supplies current requirements, as shown in Figure 61. When using slew rate control, attention should be paid to the fact that the output cannot slew faster than the dc-to-dc converter. The dc-to-dc converter slews slowest at higher currents through large (for example, 1 kΩ) loads. This slew rate is also dependent on the configuration of the dc-to-dc converter. Two examples of the dc-to-dc converter’s output slew are shown in Figure 59 and AVCC 5.0V SWA (LEFT FLOATING) VBOOST_A R2 DAC A 09225-186 R3 IOUT_A (VBOOST_A –5V) R1 RSET_A CHARTA DAC CHANNEL A SWGNDA 09225-190 IGATEA CURRENT OUTPUT RLOAD Figure 62. Configuration off a Particular Channel Using IGATE Rev. A | Page 38 of 44 09225-187 Figure 59. AICC Current vs. Time for 24 mA Through 1 kΩ Slew with External 51 kΩ Compensation Resistor IOUT_x CURRENT (mA)/VBOOST_x VOLTAGE (V) 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 32 Figure 60 (VBOOST corresponds to the dc-to-dc converter’s output voltage). 0.8 0mA TO 24mA RANGE 1kΩ LOAD fSW = 410kHz INDUCTOR = 10µH (XAL4040-103) TA = 25°C 32 09225-185 AD5757 APPLICATIONS INFORMATION CURRENT OUTPUT MODE WITH INTERNAL RSET When using the internal RSET resistor in current output mode, the output is significantly affected by how many other channels using the internal RSET are enabled and by the dc crosstalk from these channels. The internal RSET specifications in Table 1 are for all channels enabled with the internal RSET selected and outputting the same code. For every channel enabled with the internal RSET, the offset error decreases. For example, with one current output enabled using the internal RSET, the offset error is 0.075% FSR. This value decreases proportionally as more current channels are enabled; the offset error is 0.056% FSR on each of two channels, 0.029% on each of three channels, and 0.01% on each of four channels. Similarly, the dc crosstalk when using the internal RSET is proportional to the number of current output channels enabled with the internal RSET. For example, with the measured channel at 0x8000 and one channel going from zero to full scale, the dc crosstalk is −0.011% FSR. With two channels going from zero to full scale, it is −0.019% FSR, and with all three other channels going from zero to full scale, it is −0.025% FSR. For the full-scale error measurement in Table 1, all channels are at 0xFFFF. This means that, as any channel goes to zero scale, the full-scale error increases due to the dc crosstalk. For example, with the measured channel at 0xFFFF and three channels at zero scale, the full-scale error is 0.025%. Similarly, if only one channel is enabled in current output mode with the internal RSET, the full-scale error is 0.025% FSR + 0.075% FSR = 0.1% FSR. There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, longterm drift, and output voltage noise. Initial accuracy error on the output voltage of an external reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. The trim adjustment can be used at any temperature to trim out any error. Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. The temperature coefficient of a reference’s output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the DAC output voltage to ambient temperature. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise must be considered. Choosing a reference with as low an output noise voltage as practical for the system resolution required is important. Precision voltage references such as the ADR435 (XFET design) produce low output noise in the 0.1 Hz to 10 Hz region. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. PRECISION VOLTAGE REFERENCE SELECTION To achieve the optimum performance from the AD5757 over its full operating temperature range, a precision voltage reference must be used. Thought should be given to the selection of a precision voltage reference. The voltage applied to the reference inputs is used to provide a buffered reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the device. DRIVING INDUCTIVE LOADS When driving inductive or poorly defined loads, a capacitor may be required between IOUT_x and AGND to ensure stability. A 0.01 μF capacitor between IOUT_x and AGND ensures stability of a load of 50 mH. The capacitive component of the load may cause slower settling, although this may be masked by the settling time of the AD5757. There is no maximum capacitance limit for the current output of the AD5757. Table 34. Recommended Precision References Part No. ADR445 ADR02 ADR435 ADR395 AD586 Initial Accuracy (mV Maximum) ±2 ±3 ±2 ±5 ±2.5 Long-Term Drift (ppm Typical) 50 50 40 50 15 Temperature Drift (ppm/°C Maximum) 3 3 3 9 10 0.1 Hz to 10 Hz Noise (μV p-p Typical) 2.25 10 8 8 4 Rev. A | Page 39 of 44 AD5757 TRANSIENT VOLTAGE PROTECTION The AD5757 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5757 from excessively high voltage transients, external power diodes and a surge current limiting resistor are required, as shown in Figure 63. The two protection diodes and resistor must have appropriate power ratings. Further protection can be provided with transient voltage suppressors or transorbs; these are available as both unidirectional suppressors (protect against positive high voltage transients) and bidirectional suppressors (protect against both positive and negative high voltage transients) and are available in a wide range of standoff and breakdown voltage ratings. It is recommended that all field connected nodes be protected. VBOOST_x LAYOUT GUIDELINES Grounding In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5757 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5757 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The GNDSWx and ground connection for the AVCC supply are referred to as PGND. PGND should be confined to certain areas of the board, and the PGND-to-AGND connection should be made at one point only. Supply Decoupling VBOOST_x AD5757 IOUT_x GND RP RLOAD Figure 63. Output Transient Voltage Protection MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5757 is via a serial bus that uses a protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire minimum interface consisting of a clock signal, a data signal, and a latch signal. The AD5757 requires a 24-bit data-word with data valid on the falling edge of SCLK. The DAC output update is initiated on either the rising edge of LDAC or, if LDAC is held low, on the rising edge of SYNC. The contents of the registers can be read using the readback function. The AD5757 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESL), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. 09225-079 Traces The power supply lines of the AD5757 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separating the lines helps). It is essential to minimize noise on the REFIN line because it couples through to the DAC output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, whereas signal traces are placed on the solder side. AD5757-TO-ADSP-BF527 INTERFACE The AD5757 can be connected directly to the SPORT interface of the ADSP-BF527, an Analog Devices, Inc., Blackfin® DSP. Figure 64 shows how the SPORT interface can be connected to control the AD5757. AD5757 SPORT_TFS SPORT_TSCK SPORT_DTO SYNC SCLK SDIN GPIO0 LDAC Figure 64. AD5757-to-ADSP-BF527 SPORT Interface 09225-080 ADSP-BF527 Rev. A | Page 40 of 44 AD5757 DC-to-DC Converters To achieve high efficiency, good regulation, and stability, a welldesigned printed circuit board layout is required. Follow these guidelines when designing printed circuit boards (see Figure 56): • • • GALVANICALLY ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. Isocouplers provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5757 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 65 shows a 4-channel isolated interface to the AD5757 using an ADuM1400. For more information, visit www.analog.com. MICROCONTROLLER SERIAL CLOCK OUT SERIAL DATA OUT SYNC OUT • • • Keep the low ESR input capacitor, CIN, close to AVCC and PGND. Keep the high current path from CIN through the inductor, LDCDC, to SWX and PGND as short as possible. Keep the high current path from CIN through LDCDC and the rectifier, DDCDC, to the output capacitor, CDCDC, as short as possible. Keep high current traces as short and as wide as possible. The path from CIN through the inductor, LDCDC, to SWX and PGND should be able to handle a minimum of 1 A. Place the compensation components as close as possible to COMPDCDC_x. Avoid routing high impedance traces near any node connected to SWx or near the inductor to prevent radiated noise injection. ADuM1400* VIA ENCODE DECODE VOA TO SCLK VIB ENCODE DECODE VOB TO SDIN VIC ENCODE DECODE VOC TO SYNC *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 65. Isolated Interface Rev. A | Page 41 of 44 09225-081 CONTROL OUT VID ENCODE DECODE VOD TO LDAC AD5757 OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 0.60 MAX 48 PIN 1 INDICATOR 49 64 1 PIN 1 INDICATOR TOP VIEW 8.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 7.25 7.10 SQ 6.95 0.50 0.40 0.30 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF 33 32 16 17 7.50 REF 0.25 MIN 1.00 0.85 0.80 SEATING PLANE FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 66. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5757ACPZ AD5757ACPZ-REEL7 1 Resolution (Bits) 16 16 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Package Option CP-64-3 CP-64-3 Z = RoHS Compliant Part. Rev. A | Page 42 of 44 080108-C AD5757 NOTES Rev. A | Page 43 of 44 AD5757 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09225-0-5/11(A) Rev. A | Page 44 of 44