Multiple Range, 16-/12-Bit,
Bipolar/Unipolar, Voltage Output DACs
AD5761/AD5721
Data Sheet
FEATURES
GENERAL DESCRIPTION
8 software-programmable output ranges: 0 V to +5 V, 0 V to
+10 V, 0 V to +16 V, 0 V to +20 V, ±3 V, ±5 V, ±10 V, −2.5 V to
+7.5 V; 5% overrange
Total unadjusted error (TUE): 0.1% FSR maximum
16-bit resolution: ±2 LSB maximum INL
Guaranteed monotonicity: ±1 LSB maximum
Single channel, 16-/12-bit DACs
Settling time: 7.5 μs typical
Integrated reference buffers
Low noise: 35 nV/√Hz
Low glitch: 1 nV-sec
1.8 V logic compatibility
Asynchronous updating via LDAC
Asynchronous RESET to zero scale/midscale
DSP/microcontroller-compatible serial interface
Robust 4 kV HBM ESD rating
Available in 16-lead TSSOP and 16-lead LFCSP
Operating temperature range: −40°C to +125°C
The AD5761/AD5721 are single channel, 16-/12-bit serial input,
voltage output, digital-to-analog converters (DACs). They operate
from single supply voltages from +4.75 V to +30 V or dual
supply voltages from −16.5 V to 0 V VSS and +4.75 V to +16.5 V
VDD. The integrated output amplifier and reference buffer
provide a very easy to use, universal solution.
APPLICATIONS
The devices available in the 16-lead TSSOP and in the 16-lead
LFCSP offer guaranteed specifications over the −40°C to +125°C
industrial temperature range.
The devices offer guaranteed monotonicity, integral nonlinearity
(INL) of ±2 LSB maximum, 35 nV/√Hz noise, and 7.5 μs settling
time on selected ranges.
The AD5761/AD5721 use a serial interface that operates at
clock rates of up to 50 MHz and are compatible with DSP and
microcontroller interface standards. Double buffering allows
the asynchronous updating of the DAC output. The input
coding is user-selectable twos complement or straight binary.
The asynchronous reset function resets all registers to their
default state. The output range is user selectable, via the
RA[2:0] bits in the control register.
Industrial automation
Instrumentation, data acquisition
Open-/closed-loop servo control, process control
Programmable logic controllers
Table 1. Pin-Compatible Devices
Device
AD5761R/AD5721R
Description
AD5761/AD5721 with internal reference
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFIN
AD5761/AD5721
REFERENCE
BUFFERS
DVCC
ALERT
SDI
SCLK
SYNC
SDO
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
12/16
INPUT
REG
DAC
REG
12/16
12-BIT/
16-BIT
DAC
RESET
VOUT
0V TO 5V
0V TO 10V
0V TO 16V
0V TO 20V
±3V
±5V
±10V
−2.5V TO +7.5V
DNC
DGND
VSS
LDAC
AGND
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
12640-001
CLEAR
Figure 1.
Rev. C
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AD5761/AD5721
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register Details ............................................................................... 24
Applications ....................................................................................... 1
Input Shift Register .................................................................... 24
General Description ......................................................................... 1
Control Register ......................................................................... 24
Functional Block Diagram .............................................................. 1
Readback Control Register ....................................................... 26
Revision History ............................................................................... 2
Update DAC Register from Input Register ............................. 26
Specifications..................................................................................... 3
Readback DAC Register ............................................................ 26
AC Performance Characteristics ................................................ 5
Write and Update DAC Register .............................................. 27
Timing Characteristics ................................................................ 6
Readback Input Register............................................................ 27
Absolute Maximum Ratings............................................................ 8
Disable Daisy-Chain Functionality.......................................... 27
ESD Caution .................................................................................. 8
Software Data Reset ................................................................... 28
Pin Configurations and Function Descriptions ........................... 9
Software Full Reset ..................................................................... 28
Typical Performance Characterstics............................................. 10
No Operation Registers ............................................................. 28
Terminology .................................................................................... 20
Applications Information .............................................................. 29
Theory of Operation ...................................................................... 21
Typical Operating Circuit ......................................................... 29
Digital-to-Analog Converter .................................................... 21
Power Supply Considerations ................................................... 29
Transfer Function ....................................................................... 21
Evaluation Board ........................................................................ 29
DAC Architecture ....................................................................... 21
Outline Dimensions ....................................................................... 31
Serial Interface ............................................................................ 22
Ordering Guide .......................................................................... 31
Hardware Control Pins .............................................................. 22
REVISION HISTORY
1/2018—Rev. B to Rev. C
Changes to Transfer Function Section......................................... 21
Change to DB[15:11] Column, Table 11 ..................................... 24
Change to RA[2:0] Description, Table 12 ................................... 25
Change to DB[15:13] Column, Table 15 ..................................... 26
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
4/2016—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Typical Operating Circuit Section and Precision
Voltage Reference Section ............................................................. 29
5/2015—Rev. 0 to Rev. A
Added 16-Lead LFCSP Package ....................................... Universal
Added Grade A Parameter, Table 2 .................................................3
Added Figure 5, Renumbered Sequentially ...................................9
Changes to Table 6.............................................................................9
Changes to Figure 49...................................................................... 17
Changes to Power Supply Considerations Section .................... 30
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
1/2015—Revision 0: Initial Version
Rev. C | Page 2 of 31
Data Sheet
AD5761/AD5721
SPECIFICATIONS
VDD 1 = 4.75 V to 30 V, VSS1 = −16.5 V to 0 V, AGND = DGND = 0 V, VREFIN = 2.5 V external, DVCC = 1.7 V to 5.5 V, RLOAD = 1 kΩ for all
ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter 2
STATIC PERFORMANCE
Programmable Output Ranges
AD5761
Resolution
Relative Accuracy, INL
A Grade
B Grade 4
Differential Nonlinearity, DNL
AD5721
Resolution
Relative Accuracy, INL
B Grade
Differential Nonlinearity, DNL
Zero-Scale Error
Min
Typ
0
0
0
0
−2.5
−3
−5
−10
Max
Unit
5
10
16
20
+7.5
+3
+5
+10
V
V
V
V
V
V
V
V
16
Bits
−8
−2
+8
+2
LSB
LSB
−1
+1
LSB
12
−10
+0.5
+0.5
+6
LSB
LSB
mV
+10
mV
µV/°C
±5
±15
Bipolar Zero Error
−5
−7
Bipolar Zero TC5
Offset Error
+5
+7
±2
±5
−6
+6
−10
Offset Error TC5
Gain Error
Gain Error TC5
Total Unadjusted Error (TUE)
REFERENCE INPUT5
Reference Input Voltage (VREF)
Input Current
Reference Range
OUTPUT CHARACTERISTICS5
Output Voltage Range
+10
−0.1
+0.1
+2
3
V
µA
V
+0.1
±1.5
−0.1
2.5
±0.5
µV/°C
mV
mV
µV/°C
µV/°C
mV
mV
µV/°C
µV/°C
% FSR
ppm FSR/°C
% FSR
±5
±15
−2
2
External reference3
All ranges except 0 V to 16 V and 0 V to 20 V, VREFIN =
2.5 V external reference
Bits
−0.5
−0.5
−6
Zero-Scale Temperature
Coefficient (TC) 5
Test Conditions/Comments
External reference 3, outputs unloaded
−VOUT
+VOUT
−10
−10.5
+10
+10.5
V
V
Rev. C | Page 3 of 31
External reference3
All ranges except ±10 V and 0 V to 20 V, external
reference3
0 V to 20 V, ±10 V ranges, external reference3
Unipolar ranges, external reference3
Bipolar ranges, external reference3
All bipolar ranges except ±10 V
±10 V output range
±3 V range, external reference3
All bipolar ranges except ±3 V, external reference3
All ranges except ±10 V and 0 V to 20 V, external
reference3
0 V to 20 V, ±10 V ranges; external reference3
Unipolar ranges, external reference3
Bipolar ranges, external reference3
External reference3
External reference3
External reference3
±1% for specified performance
Refer to Table 7 for the different output voltage
ranges available
VDD/VSS = ±11 V, ±10 V output range
VDD/VSS = ±11 V, ±10 V output range with 5%
overrange
AD5761/AD5721
Parameter 2
Capacitive Load Stability
Headroom
Data Sheet
Min
Typ
0.5
Output Voltage TC
Short-Circuit Current
Resistive Load
±3
25
Load Regulation
DC Output Impedance
LOGIC INPUTS5
Input Voltage
High, VIH
Low, VIL
Input Current
Leakage Current
0.3
0.5
Pin Capacitance
LOGIC OUTPUTS (SDO, ALERT)5
Output Voltage
Low, VOL
High, VOH
High Impedance, SDO Pin
Leakage Current
Pin Capacitance
POWER REQUIREMENTS
VDD
VSS
DVCC
IDD
ISS
DICC
Power Dissipation
DC Power Supply Rejection
Ratio (PSRR)5
AC PSRR5
Max
1
1
Unit
nF
V
1
2
ppm FSR/°C
mA
kΩ
kΩ
mV/mA
Ω
0.7 × DVCC
0.3 × DVCC
−1
−1
−55
SDI, SCLK, SYNC
LDAC, CLEAR, RESET pins held high
LDAC, CLEAR, RESET pins held low
Per pin, outputs unloaded
0.4
V
V
DVCC = 1.7 V to 5.5 V, sinking 200 µA
DVCC = 1.7 V to 5.5 V, sourcing 200 µA
+1
µA
pF
30
0
5.5
6.5
3
1
V
V
V
mA
mA
µA
mW
mV/V
5
5.1
1
0.005
67.1
0.1
V
V
µA
µA
µA
pF
DVCC − 0.5
4.75
−16.5
1.7
RLOAD = 1 kΩ for all ranges except 0 V to16 V and 0 V
to 20 V ranges (RLOAD = 2 kΩ)
±10 V range, external reference
Short on the VOUT pin
All ranges except 0 V to16 V and 0 V to 20 V
0 V to16 V, 0 V to 20 V ranges
Outputs unloaded
Outputs unloaded
DVCC = 1.7 V to 5.5 V, JEDEC compliant
+1
+1
5
−1
Test Conditions/Comments
0.1
80
mV/V
dB
80
dB
Outputs unloaded, external reference
Outputs unloaded
VIH = DVCC, VIL = DGND
±11 V operation, outputs unloaded
VDD ± 10%, VSS = −15 V
VSS ±10%, VDD = +15 V
VDD ±200 mV, 50 Hz/60 Hz, VSS = −15 V; external
reference; CLOAD = unloaded
VSS ±200 mV, 50 Hz/60 Hz, VDD = +15 V; external
reference; CLOAD = unloaded
For specified performance, headroom requirement is 1 V.
Temperature range: −40°C to +125°C, typical at +25°C.
External reference means 2 V to 2.85 V with overrange and 2 V to 3 V without overrange.
4
Integral nonlinearity error is specified at ±4 LSB (minimum/maximum) for 0 V to 16 V and 0 V to 20 V ranges with VREFIN = 2.5 V external reference, and for all ranges
with VREFIN = 2 V to 2.85 V with overrange and 2 V to 3 V without overrange.
5
Guaranteed by design and characterization, not production tested.
1
2
3
Rev. C | Page 4 of 31
Data Sheet
AD5761/AD5721
AC PERFORMANCE CHARACTERISTICS
VDD 1 = 4.75 V to 30 V, VSS1= −16.5 V to 0 V, AGND = DGND = 0 V, VREFIN = 2.5 V external, DVCC = 1.7 V to 5.5 V, RLOAD = 1 kΩ for all
ranges except 0 V to 16 V and 0 V to 20 V for which RLOAD = 2 kΩ, CLOAD = 200 pF, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter 2
DYNAMIC PERFORMANCE 3
Output Voltage Settling Time
Digital-to-Analog Glitch Impulse
Glitch Impulse Peak Amplitude
Power-On Glitch
Digital Feedthrough
Output Noise
0.1 Hz to 10 Hz Bandwidth (BW)
100 kHz BW
Output Noise Spectral Density (at 10 kHz)
Total Harmonic Distortion (THD) 4
Signal-to-Noise Ratio (SNR)
Peak Harmonic or Spurious Noise (SFDR)
Signal-to-Noise-and-Distortion
(SINAD) Ratio
Min
Typ
Max
Unit
Test Conditions/Comments
9
7.5
12.5
8.5
5
8
1
15
10
100
0.6
µs
µs
µs
nV-sec
nV-sec
mV
mV
mV p-p
nV-sec
20 V step to 1 LSB at 16-bit resolution
10 V step to 1 LSB at 16-bit resolution
512 LSB step to 1 LSB at 16-bit resolution
±10 V range
0 V to 5 V range
±10 V range
0 V to 5 V range
15
45
35
µV p-p
µV rms
µV rms
25
15
80
35
70
µV rms
µV rms
nV/√Hz
nV/√Hz
nV/√Hz
110
90
45
−87
92
92
85
nV/√Hz
nV/√Hz
nV/√Hz
dB
dB
dB
dB
For specified performance, headroom requirement is 1 V.
Temperature range: −40°C to +125°C, typical at +25°C.
Guaranteed by design and characterization; not production tested.
4
Digitally generated sine wave at 1 kHz.
1
2
3
Rev. C | Page 5 of 31
0 V to 20 V and 0 V to 16 V ranges, 2.5 V external reference
0 V to 10 V, ±10 V, −2.5 V to +7.5 V ranges, 2.5 V external
reference
±5 V range, 2.5 V external reference
+5 V, ±3 V ranges; 2.5 V external reference
±10 V range, 2.5 V external reference
±3 V range, 2.5 V external reference
±5 V, 0 V to 10 V, and −2.5 V to +7.5 V ranges; 2.5 V external
reference
0 V to 20 V range, 2.5 V external reference
0 V to 16 V range, 2.5 V external reference
0 V to 5 V range, 2.5 V external reference
2.5 V external reference, 1 kHz tone
At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz
At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz
At ambient, 2.5 V external reference, BW = 20 kHz, fOUT = 1 kHz
AD5761/AD5721
Data Sheet
TIMING CHARACTERISTICS
DVCC = 1.7 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
t1 1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
Limit at TMIN to TMAX
20
10
10
15
10
20
5
5
10
20
20
9
7.5
20
200
10
40
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs typ
µs typ
ns min
ns typ
ns min
ns max
t17
50
ns min
1
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge time
Minimum SYNC high time (write mode)
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
DAC output settling time, 20 V step to 1 LSB at 16-bit resolution (see Table 3)
DAC output settling time, 10 V step to 1 LSB at 16-bit resolution
CLEAR pulse width low
CLEAR pulse activation time
SYNC rising edge to SCLK falling edge
SCLK rising edge to SDO valid (CL_SDO = 15 pF, where CL_SDO is the capacitive load on the SDO
output)
Minimum SYNC high time (readback/daisy-chain mode)
Maximum SCLK frequency is 50 MHz for write mode and 33 MHz for readback mode.
Timing Diagrams
t1
SCLK
1
2
24
t3
t6
t2
t5
t4
SYNC
t8
t7
SDI
DB0
DB23
t9
t11
t10
LDAC
t12
VOUT
t12
VOUT
CLEAR
t13
t14
12640-002
VOUT
Figure 2. Serial Interface Timing Diagram
Rev. C | Page 6 of 31
Data Sheet
AD5761/AD5721
t1
SCLK
24
t3
t17
48
t2
t5
t15
t4
SYNC
t7
t8
DB23
SDI
DB0
DB23
INPUT WORD FOR DAC N
DB0
t16
INPUT WORD FOR DAC N – 1
DB0
DB23
SDO
UNDEFINED
t10
INPUT WORD FOR DAC N
t11
12640-003
LDAC
Figure 3. Daisy-Chain Timing Diagram
SCLK
1
24
1
24
t17
SYNC
DB23
DB0
DB23
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
DB23
DB0
NOP CONDITION
DB0
DB23
UNDEFINED
DB0
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Readback Timing Diagram
Rev. C | Page 7 of 31
12640-004
SDI
AD5761/AD5721
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
200 mA do not cause silicon controlled rectifier (SCR) latch-up.
Table 5.
Parameter
VDD to AGND
VSS to AGND
VDD to VSS
DVCC to DGND
Digital Inputs 1 to DGND
Digital Outputs 2 to DGND
VREFIN to DGND
VOUT to AGND
AGND to DGND
Operating Temperature Range,
TA Industrial
Storage Temperature Range
Junction Temperature, TJ MAX
Thermal Impedance
16-Lead TSSOP
θJA
θJC
16-Lead LFCSP
θJA
θJC
Power Dissipation
Lead Temperature
Soldering
ESD (Human Body Model)
Rating
−0.3 V to +34 V
+0.3 V to −17 V
−0.3 V to +34 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
−0.3 V to +7 V
VSS to VDD
−0.3 V to +0.3 V
−40°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−65°C to +150°C
150°C
113°C/W 3
28°C/W
75°C/W3
4.5°C/W 4
(TJ MAX − TA)/θJA
JEDEC industry standard
J-STD-020
4 kV
The digital inputs include CLEAR, RESET, SCLK, SYNC, SDI, and LDAC.
The digital outputs include ALERT and SDO.
3
JEDEC 2S2P test board, still air (0 m/sec airflow).
4
Measured to exposed paddle, with infinite heat sink on package top surface.
1
2
Rev. C | Page 8 of 31
Data Sheet
AD5761/AD5721
RESET 1
VREFIN 2
AD5761/
AD5721
AGND 3
TOP VIEW
(Not to Scale)
ALERT
1
CLEAR
2
15 DVCC
RESET
3
12 SCLK
VREFIN
4
AD5761/
AD5721
14 SCLK
11 SYNC
AGND
5
TOP VIEW
(Not to Scale)
VSS
6
11
VOUT
7
10 SDO
VDD
8
10 SDI
9
13 SYNC
12 SDI
9
LDAC
DNC
DNC = DO NOT CONNECT. DO NOT
CONNECT TO THIS PIN.
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. EXPOSED PAD. ENSURE THAT THE EXPOSED PAD IS
MECHANICALLY CONNECTED TO A PCB COPPER PLANE
FOR OPTIMAL THERMAL PERFORMANCE. THE EXPOSED PAD
CAN BE LEFT ELECTRICALLY FLOATING.
12640-106
DNC 7
LDAC
SDO 8
VDD 6
VOUT 5
VSS 4
16 DGND
12640-006
13 DVCC
14 DGND
16 CLEAR
15 ALERT
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. LFCSP Pin Configuration
Figure 6. TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
LFCSP TSSOP
1
3
Mnemonic
RESET
2
3
4
4
5
6
VREFIN
AGND
VSS
5
6
7
8
VOUT
VDD
7
8
9
10
DNC
SDO
9
11
LDAC
10
11
12
13
SDI
SYNC
12
14
SCLK
13
15
DVCC
14
15
16
1
DGND
ALERT
16
2
CLEAR
17
N/A1
EPAD
1
Description
Active Low Reset Input. Asserting this pin returns the AD5761/AD5721 to their default power-on status
where the output is clamped to ground and the output buffer is powered down. This pin can be left
floating because there is an internal pull-up resistor.
External Reference Voltage Input. For specified performance, VREFIN = 2.5 V.
Ground Reference for Analog Circuitry.
Negative Analog Supply Connection. A voltage in the range of −16.5 V to 0 V can be connected to this pin.
For unipolar output ranges, connect this pin to 0 V. VSS must be decoupled to AGND.
Analog Output Voltage of the DAC. The output amplifier is capable of directly driving a 2 kΩ, 1 nF load.
Positive Analog Supply Connection. A voltage in the range of 4.75 V to 30 V can be connected to this pin
for unipolar output ranges. Bipolar output ranges accept a voltage in the range of 4.75 V to 16.5 V. VDD
must be decoupled to AGND.
Do Not Connect. Do not connect to this pin.
Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode. Data is
clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
Load DAC. This logic input updates the DAC register and, consequently, the analog output. When tied
permanently low, the DAC register is updated when the input register is updated. If LDAC is held high
during the write to the input register, the DAC output register is not updated, and the DAC output update is
held off until the falling edge of LDAC. This pin can be left floating because there is an internal pull-up resistor.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Active Low Synchronization Input. This pin is the frame synchronization signal for the serial interface. While
SYNC is low, data is transferred in on the falling edge of SCLK. Data is latched on the rising edge of SYNC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin
operates at clock speeds of up to 50 MHz.
Digital Supply. The voltage range is from 1.7 V to 5.5 V. The applied voltage sets the voltage at which the
digital interface operates.
Digital Ground.
Active Low Alert. This pin is asserted low when the die temperature exceeds approximately 150°C, or
when an output short circuit or a brownout occurs. This pin is also asserted low during power-up, a full
software reset, or a hardware reset, for which a write to the control register asserts the pin high.
Falling Edge Clear Input. Asserting this pin sets the DAC register to zero-scale, midscale, or full-scale code
(user selectable) and updates the DAC output. This pin can be left floating because there is an internal
pull-up resistor.
Exposed Pad. Ensure that the exposed pad is mechanically connected to a PCB copper plane for optimal
thermal performance. The exposed pad can be left electrically floating.
N/A means not applicable.
Rev. C | Page 9 of 31
AD5761/AD5721
Data Sheet
TYPICAL PERFORMANCE CHARACTERSTICS
2.0
0V TO 5V SPAN
0V TO 10V SPAN
0V TO 16V SPAN
0V TO 20V SPAN
1.5
0.5
VDD = +21V
VSS = –11V
±3V SPAN
±5V SPAN
±10V SPAN
–2.5V TO +7.5V SPAN
0.4
0.3
VDD = +21V
VSS = –11V
INL ERROR (LSB)
INL ERROR (LSB)
1.0
0.5
0
–0.5
0.2
0.1
0
–0.1
–0.2
–1.0
–0.3
–1.5
20000
30000
40000
50000
60000
DAC CODE
–0.5
0V TO 5V SPAN
0V TO 10V SPAN
0V TO 16V SPAN
0V TO 20V SPAN
0.4
VDD = +21V
VSS = –11V
0.6
DNL ERROR (LSB)
0.2
0.1
0
–0.1
–0.4
–0.8
2000
2500
3000
3500
4000
DAC CODE
–1.0
1.5
0
0.5
10000
20000
30000
40000
50000
0V TO 5V SPAN
0V TO 10V SPAN
0V TO 16V SPAN
0V TO 20V SPAN
0.4
0.3
DNL ERROR (LSB)
1.0
0.5
0
–0.5
–1.0
60000
VDD = +21V
VSS = –11V
0.2
0.1
0
–0.1
–0.2
–0.3
–1.5
0
10000
20000
30000
40000
50000
60000
DAC CODE
Figure 9. AD5761 INL Error vs. DAC Code, Bipolar Output
–0.5
0
500
1000
1500
2000
2500
3000
3500
4000
DAC CODE
Figure 12. AD5721 DNL Error vs. DAC Code, Unipolar Output
Rev. C | Page 10 of 32
12640-012
–0.4
–2.0
12640-009
INL ERROR (LSB)
VDD = +21V
VSS = –11V
Figure 11. AD5761 DNL Error vs. DAC Code, Unipolar Output
VDD = +21V
VSS = –11V
±3V SPAN
±5V SPAN
±10V SPAN
–2.5V TO +7.5V SPAN
4000
DAC CODE
Figure 8. AD5721 INL Error vs. DAC Code, Unipolar Output
2.0
3500
–0.2
–0.6
1500
3000
0
–0.3
1000
2500
0.2
–0.4
500
2000
0.4
–0.2
0
1500
0V TO 5V SPAN
0V TO 10V SPAN
0V TO 16V SPAN
0V TO 20V SPAN
0.8
12640-008
INL ERROR (LSB)
0.3
1000
Figure 10. AD5721 INL Error vs. DAC Code, Bipolar Output
1.0
0.5
500
DAC CODE
Figure 7. AD5761 INL Error vs. DAC Code, Unipolar Output
–0.5
0
12640-010
10000
12640-011
0
12640-007
–2.0
–0.4
Data Sheet
1.0
1.0
±3V SPAN
±5V SPAN
±10V SPAN
–2.5V TO +7.5V SPAN
0.8
0.6
0.8
0.6
0.4
DNL ERROR (LSB)
0.2
0
–0.2
–0.4
–0.6
VDD = +21V
VSS = –11V
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–0.8
VDD = +21V
VSS = –11V
0
10000
20000
30000
40000
50000
60000
DAC CODE
–1.0
–40
12640-013
–1.0
MAXIMUM DNL, 0V TO 5V SPAN
MAXIMUM DNL, ±10V SPAN
MINIMUM DNL, 0V TO 5V SPAN
MINIMUM DNL, ±10V SPAN
0.3
25
50
85
105
125
Figure 16. DNL Error vs. Temperature
2.0
VDD = +21V
VSS = –11V
±3V SPAN
±5V SPAN
±10V SPAN
–2.5V TO +7.5V SPAN
0.4
0
TEMPERATURE (°C)
Figure 13. AD5761 DNL Error vs. DAC Code, Bipolar Output
0.5
–20
12640-016
DNL ERROR (LSB)
AD5761/AD5721
1.5
VDD = +21V
VSS = –11V
TA = 25°C
NO LOAD
MAXIMUM INL, 0V TO 5V SPAN
MAXIMUM INL, ±10V SPAN
MINIMUM INL, 0V TO 5V SPAN
MINIMUM INL, ±10V SPAN
INL ERROR (LSB)
DNL ERROR (LSB)
1.0
0.2
0.1
0
–0.1
–0.2
0.5
0
–0.5
–1.0
–0.3
–1.5
0
500
1000
1500
2000
2500
3000
3500
4000
DAC CODE
–2.0
+5V SPAN AVDD/AVSS = +6V/–1V
±10V SPAN AVDD/AVSS = +11V/–11V
AVDD/AVSS = +10V/–1V
AVDD/AVSS = +13.5V/–13.5V
AVDD/AVSS = +7.5V/–1V
AVDD/AVSS = +12.5V/–12.5V
AVDD/AVSS = +16.5V/–1V
AVDD/AVSS = +16.5V/–16.5V
AVDD/AVSS = +12.5V/–1V
AVDD/AVSS = +14.5V/–14.5V
SUPPLY VOLTAGE (V)
Figure 14. AD5721 DNL Error vs. DAC Code, Bipolar Output
2.0
1.5
Figure 17. INL Error vs. Supply Voltage
1.0
VDD = +21V
VSS = –11V
MAXIMUM INL, 0V TO 5V SPAN
MAXIMUM INL, ±10V SPAN
MINIMUM INL, 0V TO 5V SPAN
MINIMUM INL, ±10V SPAN
0.8
0.6
DNL ERROR (LSB)
1.0
0.5
0
–0.5
VDD = +21V
VSS = –11V
TA = 25°C
NO LOAD
MAXIMUM DNL, 0V TO 5V SPAN
MAXIMUM DNL, ±10V SPAN
MINIMUM DNL, 0V TO 5V SPAN
MINIMUM DNL, ±10V SPAN
0.4
0.2
0
–0.2
–0.4
–1.0
–0.6
–1.5
–20
0
25
50
85
TEMPERATURE (°C)
105
125
–1.0
+5V SPAN AVDD/AVSS = +6V/–1V
±10V SPAN AVDD/AVSS = +11V/–11V
AVDD/AVSS = +10V/–1V
AVDD/AVSS = +13.5V/–13.5V
AVDD/AVSS = +7.5V/–1V
AVDD/AVSS = +12.5V/–12.5V
AVDD/AVSS = +16.5V/–1V
AVDD/AVSS = +16.5V/–16.5V
AVDD/AVSS = +12.5V/–1V
AVDD/AVSS = +14.5V/–14.5V
SUPPLY VOLTAGE (V)
Figure 18. DNL Error vs. Supply Voltage
Figure 15. INL Error vs. Temperature
Rev. C | Page 11 of 32
12640-018
–2.0
–40
–0.8
12640-015
INL ERROR (LSB)
12640-017
–0.5
12640-014
–0.4
AD5761/AD5721
3
Data Sheet
0.006
MAXIMUM INL, 0V TO 5V SPAN
MAXIMUM INL, ±10V SPAN
MINIMUM INL, 0V TO 5V SPAN
MINIMUM INL, ±10V SPAN
0
–1
–2
0.002
0
–0.002
–0.004
2.75
2.50
2.25
3.00
REFERENCE VOLTAGE (V)
–0.006
–40
12640-019
–3
2.00
0.6
0.006
50
105
85
125
VDD = +21V
VSS = –11V
0V TO 5V SPAN
±10V SPAN
0.004
FULL-SCALE ERROR (V)
0.8
25
Figure 22. Midscale Error vs. Temperature
VDD = +21V
VSS = –11V
MAXIMUM DNL, 0V TO 5V SPAN
MAXIMUM DNL, ±10V SPAN
MINIMUM DNL, 0V TO 5V SPAN
MINIMUM DNL, ±10V SPAN
0
TEMPERATURE (°C)
Figure 19. INL Error vs. Reference Voltage
1.0
–20
12640-022
INL ERROR (LSB)
1
DNL ERROR (LSB)
0V TO 5V SPAN
±10V SPAN
0.004
MIDSCALE ERROR (V)
2
VDD = +21V
VSS = –11V
VDD = +21V
VSS = –11V
0.4
0.2
0
–0.2
–0.4
0.002
0
–0.002
–0.6
–0.004
2.75
2.50
3.00
REFERENCE VOLTAGE (V)
–0.006
–40
0.08
0.004
0.04
GAIN ERROR (%FSR)
0.06
0.002
0
–0.002
–0.004
50
85
125
105
TEMPERATURE (°C)
125
VDD = +21V
VSS = –11V
0V TO 5V SPAN
±10V SPAN
–0.04
–0.08
25
105
0
–0.008
0
85
–0.02
–0.06
–20
50
0.02
–0.006
12640-021
ZERO-SCALE ERROR (V)
0.10
VDD = +21V
VSS = –11V
0.006
–0.010
–40
25
Figure 23. Full-Scale Error vs. Temperature
0.010
0V TO 5V SPAN
0V TO 10V SPAN
0
TEMPERATURE (°C)
Figure 20. DNL Error vs. Reference Voltage
0.008
–20
–0.10
–40
–20
0
25
50
85
TEMPERATURE (°C)
Figure 24. Gain Error vs. Temperature
Figure 21. Zero-Scale Error vs. Temperature
Rev. C | Page 12 of 31
105
125
12640-024
2.25
12640-020
–1.0
2.00
12640-023
–0.8
Data Sheet
0.0010
TA = 25°C
VREF = 2.5V
0.020
0V TO 5V SPAN
±10V SPAN
0.015
TA = 25°C
VREF = 2.5V
0V TO 5V SPAN
±10V SPAN
0.010
0
GAIN ERROR (%FSR)
ZERO-SCALE ERROR (V)
0.0005
AD5761/AD5721
–0.0005
–0.0010
–0.0015
–0.0020
0.005
0
–0.005
–0.010
–0.015
–0.020
–0.0025
–0.025
–0.0030
AVDD/AVSS = +7.5V/–1V
AVDD/AVSS = +12.5V/–12.5V
–0.030
AVDD/AVSS = +16.5V/–1V
AVDD/AVSS = +16.5V/–16.5V
AVDD/AVSS = +12.5V/–1V
AVDD/AVSS = +14.5V/–14.5V
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
0.0003
Figure 28. Gain Error vs. Supply Voltage
0.005
0V TO 5V SPAN
±10V SPAN
TA = 25°C
VREF = 2.5V
VDD = +21V
VSS = –11V
TA = 25⁰C
0V TO 5V SPAN
±10V SPAN
0.003
ZERO-SCALE ERROR (V)
0.0001
MIDSCALE ERROR (V)
AVDD/AVSS = +16.5V/–1V
AVDD/AVSS = +16.5V/–16.5V
AVDD/AVSS = +12.5V/–1V
AVDD/AVSS = +14.5V/–14.5V
AVDD/AVSS = +7.5V/–1V
AVDD/AVSS = +12.5V/–12.5V
Figure 25. Zero-Scale Error vs. Supply Voltage
0.0005
AVDD/AVSS = +10V/–1V
AVDD/AVSS = +13.5V/–13.5V
+5V SPAN AVDD/AVSS = +6V/–1V
±10V SPAN AVDD/AVSS = +11V/–11V
12640-028
AVDD/AVSS = +10V/–1V
AVDD/AVSS = +13.5V/–13.5V
12640-025
+5V SPAN AVDD/AVSS = +6V/–1V
±10V SPAN AVDD/AVSS = +11V/–11V
–0.0001
–0.0003
–0.0005
–0.0007
–0.0009
0.001
–0.001
–0.003
–0.0011
–0.005
2.0
–0.0015
AVDD/AVSS = +10V/–1V
AVDD/AVSS = +13.5V/–13.5V
AVDD/AVSS = +7.5V/–1V
AVDD/AVSS = +12.5V/–12.5V
AVDD/AVSS = +16.5V/–1V
AVDD/AVSS = +16.5V/–16.5V
AVDD/AVSS = +12.5V/–1V
AVDD/AVSS = +14.5V/–14.5V
SUPPLY VOLTAGE (V)
Figure 26. Midscale Error vs. Supply Voltage
0.0010
TA = 25°C
VREF = 2.5V
3.0
Figure 29. Zero-Scale Error vs. Reference Voltage
0.0010
0V TO 5V SPAN
±10V SPAN
0.0008
0.0005
0V TO 5V SPAN
±10V SPAN
VDD = +21V
VSS = –11V
TA = 25°C
0.0006
MIDSCALE ERROR (V)
FULL-SCALE ERROR (V)
2.5
REFERENCE VOLTAGE (V)
12640-026
+5V SPAN AVDD/AVSS = +6V/–1V
±10V SPAN AVDD/AVSS = +11V/–11V
12640-029
–0.0013
0
–0.0005
–0.0010
–0.0015
0.0004
0.0002
0
–0.0002
–0.0004
–0.0006
AVDD/AVSS = +7.5V/–1V
AVDD/AVSS = +12.5V/–12.5V
–0.0010
2.0
AVDD/AVSS = +16.5V/–1V
AVDD/AVSS = +16.5V/–16.5V
AVDD/AVSS = +12.5V/–1V
AVDD/AVSS = +14.5V/–14.5V
SUPPLY VOLTAGE (V)
12640-027
AVDD/AVSS = +10V/–1V
AVDD/AVSS = +13.5V/–13.5V
Figure 27. Full-Scale Error vs. Supply Voltage
2.5
REFERENCE VOLTAGE (V)
Figure 30. Midscale Error vs. Reference Voltage
Rev. C | Page 13 of 32
3.0
12640-030
–0.0008
–0.0020
+5V SPAN AVDD/AVSS = +6V/–1V
±10V SPAN AVDD/AVSS = +11V/–11V
AD5761/AD5721
Data Sheet
0.05
0V TO 5V SPAN
±10V SPAN
0.03
TUE (%FSR)
0.003
0.001
0.01
–0.001
–0.01
–0.003
–0.03
–0.005
2.0
2.5
–0.05
12640-031
FULL-SCALE ERROR (V)
±5V SPAN
±10V SPAN
–2.5V TO +7.5V SPAN
±3V SPAN
VDD = +21V
VSS = –11V
TA = 25°C
3.0
REFERENCE VOLTAGE (V)
TA = 25°C
0
10000
20000
30000
40000
50000
12640-034
0.005
60000
CODE
Figure 34. TUE vs. Code, Bipolar Output
Figure 31. Full-Scale Error vs. Reference Voltage
0.030
0.05
0V TO 5V SPAN
±10V SPAN
VDD = +21V
VSS = –11V
VDD = +21V
VSS = –11V
TA = 25°C
0V TO 5V SPAN
±10V SPAN
0.025
0.020
TUE (%FSR)
0.01
–0.01
0.015
0.010
–0.03
0.005
3.0
2.5
REFERENCE VOLTAGE (V)
0
–40
12640-032
–0.05
2.0
–20
0V TO
0V TO
0V TO
0V TO
0.03
25
50
85
105
TEMPERATURE (°C)
Figure 32. Gain Error vs. Reference Voltage
0.05
0
125
12640-135
GAIN ERROR (%FSR)
0.03
Figure 35. TUE vs. Temperature
0.020
5V SPAN
10V SPAN
16V SPAN
20V SPAN
0.018
TA = 25°C
VREF = 2.5V
0V TO 5V SPAN
±10V SPAN
0.016
TUE (%FSR)
0.01
–0.01
0.012
0.010
0.008
0.006
0.004
–0.03
0.002
0
10000
20000
30000
40000
50000
CODE
60000
0
+5V SPAN AVDD/AVSS = +6V/–1V
±10V SPAN AVDD/AVSS = +11V/–11V
AVDD/AVSS = +10V/–1V
AVDD/AVSS = +13.5V/–13.5V
AVDD/AVSS = +7.5V/–1V
AVDD/AVSS = +12.5V/–12.5V
SUPPLY VOLTAGE (V)
Figure 36. TUE vs. Supply Voltage
Figure 33. TUE vs. Code, Unipolar Output
Rev. C | Page 14 of 31
AVDD/AVSS = +16.5V/–1V
AVDD/AVSS = +16.5V/–16.5V
AVDD/AVSS = +12.5V/–1V
AVDD/AVSS = +14.5V/–14.5V
12640-036
–0.05
TA = 25°C
12640-033
TUE (%FSR)
0.014
Data Sheet
30000
6
VDD = +21V
VSS = –11V
TA = 25°C
4
20000
15000
2
VOUT (V)
10000
5000
±10V
0V TO 10V
±5V
0V TO 5V
–2.5V TO +7.5V
±3V
0V TO 16V
0V TO 20V
–5000
–10000
–15000
–30
–20
–10
10
0
20
30
VDD = +21V
VSS = –11V
TA = 25°C
LOAD = 2kΩ||200pF
0
–2
–4
SYNC
±5V, FULL SCALE
TO ZERO SCALE
40
SOURCE/SINK CURRENT (mA)
–6
–8.0 –6.0 –4.0 –2.0
0
2.0
4.0
6.0
8.0 10.0 12.0 14.0
TIME (µs)
Figure 37. Source and Sink Capability of Output Amplifier with Positive Full
Scale Loaded
Figure 40. Full-Scale Settling Time (Falling Voltage Step), ±5 V Range
12
15000
VDD = +21V
VSS = –11V
TA = 25°C
SYNC
±10V, ZERO SCALE
TO FULL SCALE
10
8
6
5000
VOUT (V)
4
0
–5000
–10
–20
0
10
20
VDD = +21V
VSS = –11V
TA = 25°C
LOAD = 2kΩ||200pF
–8
–10
30
SOURCE/SINK CURRENT (mA)
–12
–3 –2 –1 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
TIME (µs)
12640-052
–20000
–30
0
–2
–6
12640-144
–15000
2
–4
±10V
0V TO 10V
±5V
0V TO 5V
–2.5V TO +7.5V
±3V
0V TO 16V
0V TO 20V
–10000
Figure 41. Full-Scale Settling Time (Rising Voltage Step), ±10 V Range
Figure 38. Source and Sink Capability of Output Amplifier
with Negative Full Scale Loaded
12
6
SYNC
±5V, ZERO SCALE
TO FULL SCALE
SYNC
±10V, FULL SCALE
TO ZERO SCALE
10
8
4
6
4
VOUT (V)
2
VOUT (V)
0
2
0
–2
–4
–2
–6
–6
–8.0 –6.0 –4.0 –2.0
0
2.0
4.0
TIME (µs)
6.0
8.0
10.0 12.0 14.0
–8
–10
Figure 39. Full-Scale Settling Time (Rising Voltage Step), ±5 V Range
VDD = +21V
VSS = –11V
TA = 25°C
LOAD = 2kΩ||200pF
–12
–3.0
–1.0
1.0
3.0
5.0
7.0
TIME (µs)
9.0
11.0
13.0
15.0
12640-053
VDD = +21V
VSS = –11V
TA = 25°C
LOAD = 2kΩ||200pF
–4
12640-050
OUTPUT VOLTAGE DELTA (µV)
10000
12640-051
0
12640-143
OUTPUT VOLTAGE DELTA (µV)
25000
AD5761/AD5721
Figure 42. Full-Scale Settling Time (Falling Voltage Step), ±10 V Range
Rev. C | Page 15 of 31
AD5761/AD5721
Data Sheet
6.0
0.10
SYNC
500-CODE STEP, ±5V SPAN
0.09
5.0
0.08
4.5
0.07
4.0
VOUT (V)
0.05
0.04
0.03
3.5
3.0
2.5
2.0
0.02
–0.01
–2
–1
0
1
2
3
4
0.5
5
TIME (µs)
0
–3 –2 –1
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
TIME (µs)
Figure 43. 500-Code Step Settling Time, ±5 V Range
0.20
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
–0.01
–2
VDD = +21V
VSS = –11V
TA = 25°C
LOAD = 2kΩ
1.0
12640-150
0
12640-057
1.5
VDD = +21V
VSS = –11V
TA = 25°C
LOAD = 2kΩ||200pF
0.01
Figure 46. Settling Time vs. Capacitive Load, 0 V to 5 V Range
0.005
SYNC
500-CODE STEP, ±10V SPAN
0.004
0.003
0.002
0.001
VOUT (V)
0
–0.001
–0.002
–0.003
–0.004
–0.005
–0.006
–0.007
VDD = +21V
VSS = –11V
TA = 25°C
LOAD = 2kΩ||200pF
1
2
4
3
–0.009
5
TIME (µs)
–0.010
12640-151
0
–1
VDD = +21V
VSS = –11V
LOAD = 2kΩ||200pF
TA = 25°C
–0.008
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
Figure 44. 500-Code Step Settling Time, ±10 V Range
12640-354
VOUT (V)
0.06
VOUT (V)
0nF
1nF
5nF
7nF
10nF
5.5
Figure 47. Digital-to-Analog Glitch Energy, 0 V to 5 V Range
12
0nF
1nF
5nF
7nF
10nF
10
8
6
0.004
0.002
0
2
VOUT (V)
VOUT (V)
4
0
–2
–0.002
–0.004
–4
–0.006
VDD =+21V
VSS = –11V
TA = 25°C
LOAD = 2kΩ
–10
–12
–5
0
5
10
15
TIME (µs)
20
VDD = +21V
VSS = –11V
LOAD = 2kΩ||200pF
TA = 25°C
–0.008
12640-056
–8
Figure 45. Settling Time vs. Capacitive Load, ±10 V Range
–0.010
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TIME (µs)
Figure 48. Digital-to-Analog Glitch Energy, ±10 V Range
Rev. C | Page 16 of 31
12640-355
–6
Data Sheet
AD5761/AD5721
5V
SCLK
10V
VDD
5V
10V
5V
SYNC
5V
VSS
SDI
VREFIN
200mV
VOUT
20mV
2
20ms/DIV
200µs/DIV
Figure 52. Software Full Reset Glitch from Zero Scale with Output Loaded,
0 V to 5 V Range
Figure 49. Power-Up Glitch
5V
5V
12640-359
12640-060
VOUT
5V
SCLK
SYNC
SCLK
5V
5V
SYNC
5V
SDI
SDI
2V
1V
12640-357
200µs/DIV
200µs/DIV
Figure 50. Software Full Reset Glitch from Full Scale with Output Loaded, 0 V
to 5 V Range
5V
5V
Figure 53. Software Full Reset Glitch from Full Scale with Output Loaded,
±10 V Range
SCLK
SYNC
SDI
5V
12640-360
VOUT
VOUT
5V
SCLK
5V
SYNC
5V
SDI
500mV
500mV
VOUT
200µs/DIV
Figure 51. Software Full Reset Glitch from Midscale with Output Loaded,
0 V to 5 V Range
12640-361
200µs/DIV
12640-358
VOUT
Figure 54. Software Full Reset Glitch from Midscale with Output Loaded,
±10 V Range
Rev. C | Page 17 of 31
AD5761/AD5721
Data Sheet
10
5V
SCLK
8
5V
SYNC
VDD = +21V
VSS = –11V
VREFIN = 2.5V
TA = 25°C
6
5V
NOISE (µV p-p)
SDI
2V
4
2
0
12640-362
200µs/DIV
–4
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
TIME (Seconds)
Figure 55. Software Full Reset Glitch from Zero Scale with Output Loaded,
±10 V Range
12640-161
–2
VOUT
Figure 58. Peak-to-Peak Noise (Voltage Output Noise), 0.1 Hz to 10 Hz
Bandwidth
30
5V
SCLK
20
5V
SYNC
NOISE (µV RMS)
SDI
VOUT
0
–10
12640-058
–20
200µs/DIV
–30
–2.0
VDD = +21V
VSS = –11V
TA = 25°C
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
TIME (Seconds)
Figure 59. Peak-to-Peak Noise (Voltage Output Noise), 100 kHz Bandwidth
Figure 56. Output Range Change Glitch, 0 V to 5 V Range
5V
VDD = +21V
VSS = –11V
TA = 25°C
SYNC
5V
NSD (nV/√Hz)
SDI
VOUT
200mV
200µs/DIV
Figure 57. Output Range Change Glitch, ±10 V Range
12640-059
5V
DAC OUTPUT NSD (nV/√Hz), EXT REF, ZS
DAC OUTPUT NSD (nV/√Hz), EXT REF, MS
DAC OUTPUT NSD (nV/√Hz), EXT REF, FS
SCLK
FREQUENCY (Hz)
12640-163
1V
10
12640-139
5V
Figure 60. DAC Output Noise Spectral Density vs. Frequency, ±10 V Range
Rev. C | Page 18 of 32
Data Sheet
AD5761/AD5721
0
0.0015
–80
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
FREQUENCY (kHz)
18
20
0.0010
0.0005
0
–0.0005
–0.0010
TA = 25°C
AVDD = +21V
AVSS = –11V
DVCC = 5V
2.5V EXT REF
LOAD = 2kΩ||200pF
TIME (µs)
Figure 61. Total Harmonic Distortion at 1 kHz
Figure 62. Digital Feedthrough
Rev. C | Page 19 of 32
12640-165
–60
12640-460
THD (dBV)
–40
24.1
24.1
24.2
24.3
24.4
24.5
24.5
24.6
24.7
24.8
24.9
24.9
25.0
25.1
25.2
25.3
25.3
25.4
25.5
25.6
25.7
25.7
25.8
25.9
DIGITAL FEEDTHROUGH (V p-p)
–20
AD5761/AD5721
Data Sheet
TERMINOLOGY
Total Unadjusted Error (TUE)
Total unadjusted error is a measure of the output error taking
all the various errors into account, namely INL error, offset
error, gain error, and output drift over supplies, temperature,
and time. TUE is expressed in % FSR.
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy, or integral nonlinearity, is a
measure of the maximum deviation, in LSB, from a straight line
passing through the endpoints of the DAC transfer function. A
typical INL error vs. DAC code plot is shown in Figure 7.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic. A
typical DNL error vs. code plot is shown in Figure 11.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5761/AD5721
are monotonic over their full operating temperature range.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (straight binary coding) or 0x0000 (twos complement
coding) for the AD5761/AD5721.
Bipolar Zero Temperature Coefficient (TC)
Bipolar zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in µV/°C.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when
0x0000 (straight binary coding) or 0x8000 (twos complement
coding) is loaded to the DAC register. Ideally, the output voltage
is negative full scale. A plot of zero-scale error vs. temperature is
shown in Figure 21.
Zero-Scale Error Temperature Coefficient (TC)
Zero-scale error TC is a measure of the change in zero-scale
error with a change in temperature. It is expressed in µV/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function.
Offset Error Temperature Coefficient (TC)
Offset error TC is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed in % FSR. A plot of gain error vs. temperature is
shown in Figure 24.
Gain Error Temperature Coefficient (TC)
Gain error TC is a measure of the change in gain error with
changes in temperature. It is expressed in ppm FSR/°C.
DC Power Supply Rejection Ratio (DC PSRR)
DC power supply rejection ratio is a measure of the rejection of
the output voltage to dc changes in the power supplies applied
to the DAC. It is measured for a given dc change in power supply
voltage and is expressed in mV/V.
AC Power Supply Rejection Ratio (AC PSRR)
AC power supply rejection ratio is a measure of the rejection of
the output voltage to ac changes in the power supplies applied
to the DAC. It is measured for a given amplitude and frequency
change in power supply voltage and is expressed in decibels.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
change. Full-scale settling time is shown in Figure 39 to Figure 42.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by 1 LSB at
the major carry transition (see Figure 47 and Figure 48).
Glitch Impulse Peak Amplitude
Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in
the DAC register changes state. It is specified as the amplitude
of the glitch in mV and is measured when the digital input code
is changed by 1 LSB at the major carry transition.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC but is
measured when the DAC output is not updated. It is specified in
nV-sec and measured with a full-scale code change on the data bus.
Noise Spectral Density
Noise spectral density is a measurement of the internally generated
random noise characterized as a spectral density (nV/√Hz). It is
measured by loading the DAC to full scale and measuring noise
at the output. It is measured in nV/√Hz. A plot of noise spectral
density is shown in Figure 60.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental.
For the AD5761/AD5721, it is defined as
THD (dB) = 20 × log
V22 + V32 + V42 + V52 + V62
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Rev. C | Page 20 of 31
Data Sheet
AD5761/AD5721
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
VREFIN
The AD5761/AD5721 are single channel 16-bit/12-bit voltage
output DACs. The AD5761/AD5721 output ranges are software
selectable and can be configured as follows:
VOUT
Data is written to the AD5761/AD5721 in a 24-bit word format
via a 4-wire digital interface that is serial peripheral interface
(SPI) compatible. The devices also offer an SDO pin to facilitate
daisy-chaining and readback.
TRANSFER FUNCTION
The input coding to the DAC can be straight binary or twos
complement (bipolar ranges case only). Therefore, the transfer
function is given by
D
VOUT = VREF × M × N − C
2
where:
VREF is 2.5 V.
M is the slope for a given output range (see Table 7).
D is the decimal equivalent of the code loaded to the DAC
register as follows:
0 to 4095 for the 12-bit device.
0 to 65,535 for the 16-bit device.
N is the number of bits. N is 12 for the AD5721 and 16 for the
AD5761.
C is the offset for a given output range (see Table 7).
M
8
4
2.4
4
8
6.4
4
2
AGND
OUTPUT
RANGE CONTROL
Figure 63. DAC Architecture
R-2R DAC
The architecture of the AD5761/AD5721 consists of two
matched DAC sections. A simplified circuit diagram is shown
in Figure 64. The six MSBs of the 16-bit data-word are decoded
to drive 63 switches, E0 to E62, whereas the remaining 10 bits of
the data-word drive the S0 to S9 switches of a 10-bit voltage
mode R-2R ladder network.
The code loaded into the DAC register determines which arms
of the ladder are switched between VREFIN and ground (AGND).
The output voltage is taken from the end of the ladder and
amplified afterwards to provide the selected output voltage.
R
2R
R
R
VOUT
2R
2R ...
2R
2R
2R ...
2R
S0
S1 ...
S9
E62
E61 ...
E0
VREFIN
AGND
10-BIT R-2R LADDER
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
Figure 64. DAC Ladder Structure
Table 7. M and C Values for Various Output Ranges
Range
±10 V
±5 V
±3 V
−2.5 V to +7.5 V
0 V to 20 V
0 V to 16 V
0 V to 10 V
0 V to 5 V
CONFIGURABLE
OUTPUT
AMPLIFIER
12640-061
•
DAC REGISTER
Unipolar output voltage: 0 V to 5 V, 0 V to 10 V, 0 V to 16 V,
0 V to 20 V
Bipolar output voltage: −2.5 V to +7.5 V, ±3 V, ±5 V, ±10 V
12640-062
•
REFIN
Reference Buffer
C
4
2
1.2
1
0
0
0
0
The AD5761/AD5721 operate with an external reference. The
reference input has an input range of 2 V to 3 V with 2.5 V for
specified performance. This input voltage is then buffered
before it is applied to the DAC core.
DAC Output Amplifier
The output amplifier is capable of generating both unipolar and
bipolar output voltages. It is capable of driving a load of 2 kΩ in
parallel with 1 nF to AGND. The source and sink capabilities of
the output amplifier are shown in Figure 37.
DAC ARCHITECTURE
The DAC architecture consists of an R-2R DAC followed by an
output buffer amplifier. Figure 63 shows a block diagram of the
DAC architecture. Note that the reference input is buffered
prior to being applied to the DAC.
The output voltage range obtained from the configurable output
amplifier is selected by writing to the 3 LSBs, (RA[2:0]), in the
control register.
Rev. C | Page 21 of 31
AD5761/AD5721
Data Sheet
The AD5761/AD5721 4-wire (SYNC, SCLK, SDI, and SDO)
digital interface is SPI compatible. The write sequence begins
after bringing the SYNC line low, maintaining this line low until
the complete data-word is loaded from the SDI pin. Data is
loaded in at the SCLK falling edge transition (see Figure 2).
When SYNC is brought high again, the serial data-word is
decoded according to the instructions in Table 10. The
AD5761/AD5721 contain an SDO pin to allow the user to
daisy-chain multiple devices together or to read back the
contents of the registers.
By connecting the SDO of the first device to the SDI input of
the next device in the chain, a multidevice interface is constructed.
Each device in the system requires 24 clock pulses. Therefore,
the total number of clock cycles must equal 24 × N, where N is
the total number of AD5761/AD5721 devices in the chain. When
the serial transfer to all devices is complete, SYNC is taken high,
which latches the input data in each device in the daisy chain
and prevents any further data from being clocked into the input
shift register.
CONTROLLER
DATA OUT
Standalone Operation
The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only when
SYNC is held low for the correct number of clock cycles.
SCLK
CONTROL OUT
SYNC
DATA IN
SDI
SCLK
SYNC
SDO
SDI
AD5761/
AD5721*
SCLK
SYNC
SDO
Readback Operation
*ADDITIONAL
For systems that contain several devices, use the SDO pin to
daisy-chain several devices together. Daisy-chain mode is useful
in system diagnostics and in reducing the number of serial
interface lines. The first falling edge of SYNC starts the write
cycle. SCLK is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied, the
data ripples out of the shift register and appears on the SDO line.
This data is clocked out on the rising edge of SCLK and is valid
on the falling edge.
SDO
AD5761/
AD5721*
The input shift register is updated on the rising edge of SYNC.
For another serial transfer to take place, SYNC must be brought
low again. After the end of the serial data transfer, data is
automatically transferred from the input shift register to the
addressed register. When the write cycle is complete, the output
can be updated by taking LDAC low while SYNC is high.
Daisy-Chain Operation
SDI
SERIAL CLOCK
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high
after the final clock to latch the data. The first falling edge of
SYNC starts the write cycle. Exactly 24 falling clock edges must
be applied to SCLK before SYNC is brought high again. If SYNC is
brought high before the 24th falling SCLK edge, the data written is
invalid. If more than 24 falling SCLK edges are applied before
SYNC is brought high, the input data is also invalid.
The contents of the input, DAC, and control registers can be
read back via the SDO pin. Figure 4 shows how the registers are
decoded. After a register has been addressed for a read, the next
24 clock cycles clock the data out on the SDO pin. The clocks
must be applied while SYNC is low. When SYNC is returned high,
the SDO pin is placed in tristate. For a read of a single register,
the no operation (NOP) function clocks out the data. Alternatively,
if more than one register is to be read, the data of the first register
to be addressed clocks out at the same time that the second register
to be read is being addressed. The SDO pin must be enabled to
complete a readback operation. The SDO pin is enabled by default.
AD5761/
AD5721*
PINS OMITTED FOR CLARITY.
12640-063
SERIAL INTERFACE
Figure 65. Daisy-Chain Block Diagram
HARDWARE CONTROL PINS
Load DAC Function (LDAC)
After data transfers into the input register of the DAC, there are
two ways to update the DAC register and DAC output. Depending on the status of both SYNC and LDAC, one of two update
modes is selected: synchronous DAC update or asynchronous
DAC update.
Synchronous DAC Update
In synchronous DAC update mode, LDAC is held low while
data is being clocked into the input shift register. The DAC
output is updated on the rising edge of SYNC.
Rev. C | Page 22 of 31
Data Sheet
AD5761/AD5721
Asynchronous DAC Update
Alert Function (ALERT)
In asynchronous DAC update mode, LDAC is held high while
data is being clocked into the input shift register. The DAC output
is asynchronously updated by taking LDAC low after SYNC is
taken high. The update then occurs on the falling edge of LDAC.
When the ALERT pin is asserted low, a readback from the
control register is required to clarify whether a short-circuit
or brownout condition occurred, depending on the values of
Bit 12 and Bit 11, SC and BO bits, respectively (see Table 15
and Table 16). If neither of these conditions occurred, the
temperature exceeded approximately 150°C.
Reset Function (RESET)
The AD5761/AD5721 can be reset to its power-on state by two
means: either by asserting the RESET pin or by using the software
full reset registers (see Table 26).
Asynchronous Clear Function (CLEAR)
The CLEAR pin is a falling edge active input that allows the output
to be cleared to a user defined value. The clear code value is
programmed by writing to Bit 10 and Bit 9 in the control register
(see Table 11 and Table 12). It is necessary to maintain CLEAR low
for a minimum amount of time to complete the operation (see
Figure 2). When the CLEAR signal is returned high, the output
remains at the clear value until a new value is loaded to the
DAC register.
The ALERT pin is low during power-up, a software full reset, or
a hardware reset. After the first write to the control register to
configure the DAC, the ALERT pin is asserted high.
In the event of the die temperature exceeding approximately 150°C,
the ALERT pin is low and the value of the ETS bit determines the
state of the digital supply of the device, whether the internal
digital supply is powered on or powered down. If the ETS bit is
set to 0, the internal digital supply is powered on when the internal
die temperature exceeds approximately 150°C. If the ETS bit is
set to 1, the internal digital supply is powered down when the
internal die temperature exceeds approximately 150°C and the
device becomes nonfunctional (see Table 11 and Table 12).
The AD5761/AD5721 temperature at power-up must be less
than 150°C for proper operation of the devices.
Rev. C | Page 23 of 31
AD5761/AD5721
Data Sheet
REGISTER DETAILS
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input,
SCLK, which can operate at rates of up to 50 MHz. The input shift register consists of three don’t care bits, one fixed value bit (DB20 = 0),
four address bits, and a 16-bit or 12-bit data-word as shown in Table 8 and Table 9, respectively.
Table 8. AD5761 16-Bit Input Shift Register Format
MSB
DB23
X1
1
LSB
DB22
X1
DB21
X1
DB20
0
DB19
DB18
DB17
Register address
DB16
DB15 to DB0
Register data
DB16
DB15 to DB4
Register data
X means don’t care.
Table 9. AD5721 12-Bit Input Shift Register Format
MSB
DB23
X1
1
LSB
DB22
X1
DB21
X1
DB20
0
DB19
DB18
DB17
Register address
DB3 to DB0
XXXX1
X means don’t care.
Table 10. Input Shift Register Commands
DB19
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Register Address
DB18 DB17
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
DB16
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Command
No operation
Write to input register (no update)
Update DAC register from input register
Write and update DAC register
Write to control register
No operation
No operation
Software data reset
Reserved
Disable daisy-chain functionality
Readback input register
Readback DAC register
Readback control register
No operation
No operation
Software full reset
CONTROL REGISTER
The control register controls the mode of operation of the AD5761/AD5721. The control register options are shown in Table 11 and Table 12.
On power-up, after a full reset, or after a hardware reset, the output of the DAC is clamped to ground through a 1 kΩ resistor and the
output buffer remains in power-down mode. A write to the control register is required to configure the device, remove the clamp to
ground, and power up the output buffer.
When the DAC output range is reconfigured during operation, a software full reset command (see Table 26) must be written to the device
before writing to the control register.
Table 11. Write to Control Register
MSB
DB[23:21]
XXX 1
XXX1
1
DB20
0
0
DB[19:16]
Register address
0100
DB[15:11]
DB[10:9]
DB8
XXXXX1
CV[1:0]
OVR
X means don’t care.
Rev. C | Page 24 of 31
DB7
DB6
Register data
B2C
ETS
DB5
DB[4:3]
LSB
DB[2:0]
0
PV[1:0]
RA[2:0]
Data Sheet
AD5761/AD5721
Table 12. Control Register Functions
Bit Name
CV[1:0]
OVR
B2C
ETS
PV[1:0]
RA[2:0]
Description
CLEAR voltage selection.
00: zero scale.
01: midscale.
10, 11: full scale.
5% overrange.
0: 5% overrange disabled.
1: 5% overrange enabled.
Bipolar range.
0: DAC input for bipolar output range is straight binary coded.
1: DAC input for bipolar output range is twos complement coded.
Thermal shutdown alert. The alert may not work correctly if the device powers on with temperature conditions >150°C
(greater than the maximum rating of the device).
0: internal digital supply does not power down if die temperature exceeds 150°C.
1: internal digital supply powers down if die temperature exceeds 150°C.
Power-up voltage.
00: zero scale.
01: midscale.
10, 11: full scale.
Output range. Before an output range configuration, the device must be reset.
000: −10 V to +10 V.
001: 0 V to +10 V.
010: −5 V to +5 V.
011: 0 V to 5 V.
100: −2.5 V to +7.5 V.
101: −3 V to +3 V.
110: 0 V to 16 V.
111: 0 V to 20 V.
Table 13. Bipolar Output Range Possible Codes
Straight Binary
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Decimal Code
+7
+6
+5
+4
+3
+2
+1
0
−1
−2
−3
−4
−5
−6
−7
−8
Rev. C | Page 25 of 31
Twos Complement
0111
0110
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000
AD5761/AD5721
Data Sheet
READBACK CONTROL REGISTER
The readback control register operation provides the contents of the control register by setting the register address to 1100. Table 14
outlines the 24-bit shift register for this command, where the last 16 bits are don’t care bits.
During the next command, the control register contents are shifted out of the SDO pin with the MSB shifted out first. Table 15 outlines
the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out.
Table 14. Readback Control Register, 24-Bit Shift Register to the SDI Pin
MSB
DB[23:21]
XXX1
XXX1
1
LSB
DB20
0
0
DB[19:16]
Register address
1100
DB[15:10]
Register data
Don’t care
X means don’t care.
Table 15. Readback Control Register, 24-Bit Data Read from the SDO Pin
MSB
DB[23:21]
XXX1
XXX1
1
DB20
0
0
DB[19:16]
Register address
1100
DB[15:13]
DB12
DB11
XXXXX1
SC
BO
DB[10:9] DB8 DB7
Register data
CV[1:0]
OVR B2C
DB6
DB5
DB[4:3]
LSB
DB[2:0]
ETS
X1
PV[1:0]
RA[2:0]
X means don’t care.
Table 16. Readback Control Register Bit Descriptions
Bit Name
SC
Description
Short-circuit condition. The SC bit is reset at every control register write.
0: no short-circuit condition detected.
1: short-circuit condition detected.
Brownout condition. The BO bit is reset at every control register write.
0: no brownout condition detected.
1: brownout condition detected.
BO
UPDATE DAC REGISTER FROM INPUT REGISTER
The update DAC register function loads the DAC register with the data saved in the input register, and updates the DAC output voltage.
This operation is equivalent to a software LDAC. Table 17 outlines how data is written to the DAC register.
Table 17. Update DAC Register from Input Register
MSB
DB23
X1
X1
1
LSB
DB22
X1
X1
DB21
X1
X1
DB20
0
0
DB19
DB18
DB17
Register address
0010
DB16
DB15 to DB0
Register data
Don’t care
X means don’t care.
READBACK DAC REGISTER
The readback DAC register operation provides the contents of the DAC register by setting the register address to 1011. Table 18 outlines
the 24-bit shift register for this command. During the next command, the DAC register contents are shifted out of the SDO pin with the
MSB shifted out first. Table 19 outlines the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out.
Table 18. Readback DAC Register, 24-Bit Shift Register to SDI Pin
MSB
DB23
X1
X1
1
LSB
DB22
X1
X1
DB21
X1
X1
DB20
0
0
DB19
DB18
DB17
Register address
1011
X means don’t care.
Rev. C | Page 26 of 31
DB16
DB15 to DB0
Register data
Don’t care
Data Sheet
AD5761/AD5721
Table 19. Readback DAC Register, 24-Bit Data Read from SDO Pin
MSB
DB23
X1
X1
1
LSB
DB22
X1
X1
DB21
X1
X1
DB20
0
0
DB19
DB18
DB17
Register address
1011
DB16
DB15 to DB0
Register data
Data read from DAC register
X means don’t care.
WRITE AND UPDATE DAC REGISTER
The write and update DAC register (Register Address 0011) updates the input register and the DAC register with the entered data-word
from the input shift register, irrespective of the state of LDAC.
Setting the register address to 0001 writes the input register with the data from the input shift register, clocked in MSB first on the SDI
pin.
Table 20. Write and Update DAC Register
MSB
DB23
X1
X1
X1
1
LSB
DB22
X1
X1
X1
DB21
X1
X1
X1
DB20
0
0
0
DB19
DB18
DB17
Register address
0001
0011
DB16
DB15 to DB0
Register data
Data loaded
Data loaded
X means don’t care.
READBACK INPUT REGISTER
The readback input register operation provides the contents of the input register by setting the register address to 1010. Table 21 outlines
the 24-bit shift register for this command. During the next command, the input register contents are shifted out of the SDO pin with MSB
shifted out first. Table 22 outlines the 24-bit data read from the SDO pin, where DB23 is the first bit shifted out.
Table 21. Read Back Input Register, 24-Bit Shift Register to the SDI Pin
MSB
DB23
X1
X1
1
LSB
DB22
X1
X1
DB21
X1
X1
DB20
0
0
DB19
DB18
DB17
Register address
1010
DB16
DB15 to DB0
Register data
Don’t care
X means don’t care.
Table 22. Readback Input Register, 24-Bit Data Read from the SDO Pin
MSB
DB23
X1
X1
1
LSB
DB22
X1
X1
DB21
X1
X1
DB20
0
0
DB19
DB18
DB17
DB16
Register address
1010
DB15 to DB0
Register data
Data read from input register
X means don’t care.
DISABLE DAISY-CHAIN FUNCTIONALITY
The daisy-chain feature can be disabled to save the power consumed by the SDO buffer when this functionality is not required (see Table 23).
When disabled, a readback request is not accepted because the SDO pin remains in tristate.
Table 23. Disable Daisy-Chain Functionality Register
MSB
DB23
X1
X1
1
DB22
X1
X1
DB21
X1
X1
DB20
0
0
DB19
DB18
DB17
Register address
1001
DB16
X means don’t care.
Rev. C | Page 27 of 31
DB15 to DB1
Register data
Don’t care
LSB
DB0
DDC
AD5761/AD5721
Data Sheet
Table 24. Disable Daisy-Chain Bit Description
Bit Name
DDC
Description
DDC decides whether daisy-chain functionality is enabled or disabled for the device. By default, daisy-chain functionality is
enabled.
0: daisy-chain functionality is enabled for the device.
1: daisy-chain functionality is disabled for the device.
SOFTWARE DATA RESET
The AD5761/AD5721 can be reset via software to zero scale, midscale, or full scale (see Table 25). The value to which the device is reset is
specified by the PV1 and PV0 bits, which are set in the write to control register command (see Table 11 and Table 12).
Table 25. Software Data Reset Register
MSB
DB23
X1
X1
1
LSB
DB22
X1
X1
DB21
X1
X1
DB20
0
0
DB19
DB18
DB17
Register address
0111
DB16
DB15 to DB0
Register data
Don’t care
X means don’t care.
SOFTWARE FULL RESET
The device can also be reset completely via software (see Table 26). When the register address is set to 1111, the device behaves in a
power-up state, where the output is clamped to AGND and the output buffer is powered down. The user must write to the control register
to configure the device, remove the 1 kΩ resistor clamp to ground, and power up the output buffer.
The software full reset command is also issued when the DAC output range is reconfigured during normal operation.
Table 26. Software Full Reset Register
MSB
DB23
X1
X1
1
LSB
DB22
X1
X1
DB21
X1
X1
DB20
0
0
DB19
DB18
DB17
Register address
1111
DB16
DB15 to DB0
Register data
Don’t care
X means don’t care.
NO OPERATION REGISTERS
The no operation registers are ignored and do not vary the state of the device (see Table 27).
Table 27. No Operation Registers
MSB
DB23
X1
X1
1
LSB
DB22
X1
X1
DB21
X1
X1
DB20
0
0
DB19
DB18
DB17
DB16
Register address
0000/0101/0110/1101/1110
X means don’t care.
Rev. C | Page 28 of 31
DB15 to DB0
Register data
Don’t care
Data Sheet
AD5761/AD5721
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
AD5761/
AD5721
Figure 66 shows the typical operating circuit for the AD5761/
AD5721. The only external components needed for these precision
16-/12-bit DACs are decoupling capacitors, supply voltage, and an
external reference. The integration of a reference buffer in the
AD5761/AD5721 results in overall savings in both cost and board
space.
100nF
DGND 16
CLEAR
2
CLEAR
DVCC 15
RESET
3
RESET
SCLK 14
SCLK
VREFIN
4
VREFIN
SYNC 13
SYNC
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise must be considered. It is
important to choose a reference with as low an output noise
voltage as practical for the system resolution that is required.
Precision voltage references, such as the ADR4525, produce low
output noise in the 0.1 Hz to 10 Hz region. However, as the circuit
bandwidth increases, filtering the output of the reference may
be required to minimize the output noise.
AGND
6
VSS
7
VOUT
SDO 10
8
VDD
DNC
SDI 12
10µF
+5V
+15V
100nF
10µF
LDAC 11
SDI
LDAC
SDO
9
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
12640-064
10µF
VOUT
Figure 66. Typical Operating Circuit
POWER SUPPLY CONSIDERATIONS
The AD5761/AD5721 must be powered by the following three
supplies to provide any of the eight output voltage ranges available
on the DAC: VDD = +21 V, VSS = −11 V, and DVCC = +5 V.
For applications requiring optimal high power efficiency and
low noise performance, it is recommended that the ADP5070
switching regulator be used to convert the 5 V input rail into
two intermediate rails (+23 V and −13 V). These intermediate
rails are then postregulated by very low noise, low dropout (LDO)
regulators (ADP7142 and ADP7182). Figure 67 shows the
recommended method.
ADP5070
5V INPUT
Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
The temperature coefficient of a reference output voltage affects
gain error and TUE. Choose a reference with a tight temperature
coefficient specification to reduce the dependence of the DAC
output voltage on ambient conditions.
5
+
DC-TO-DC
+23V
ADP7142
LDO
SWITCHING
REGULATOR
ADP7142
LDO
ADP5070
5V INPUT
DC-TO-DC
SWITCHING
REGULATOR
–13V
ADP7182
LDO
+21V: VDD
+5V: DVCC
–11V: VSS
12640-070
Initial accuracy error on the output voltage of an external
reference may lead to a full-scale error in the DAC. Therefore,
to minimize these errors, a reference with low initial accuracy
error specification is preferred. Choosing a reference with an
output trim adjustment, such as the ADR421, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim adjustment
can also be used at ambient temperature to trim out any error.
ALERT
100nF
Precision Voltage Reference Selection
There are four possible sources of error to consider when choosing
a voltage reference for high accuracy applications: initial accuracy,
temperature coefficient of the output voltage, long-term drift,
and output voltage noise.
1
–15V
In Figure 66, VDD is connected to 15 V and VSS is connected to
−15 V, but VDD and VSS can operate with supplies from 4.75 V to
30 V and from −16.5 V to 0 V, respectively.
An external reference is required for the AD5761/AD5721. Take
care in the selection of the same because any error in the voltage
reference is reflected in the output of the device.
ALERT
Figure 67. Postregulation by ADP7142 and ADP7182
EVALUATION BOARD
An evaluation board is available for the AD5761R to aid designers
in evaluating the high performance of the device with minimum
effort. This evaluation board can be used to evaluate the AD5761/
AD5721. The AD5761R evaluation kit includes a populated and
tested AD5761R printed circuit board (PCB). The evaluation
board interfaces to the USB port of a PC. Software is available
with the evaluation board to allow the user to easily program
the AD5761R. The EVAL-AD5761RSDZ user guide gives full
details on the operation of the evaluation board.
Rev. C | Page 29 of 31
AD5761/AD5721
Data Sheet
Table 28. Precision References Recommended for Use with the AD5761/AD5721
Part No.
ADR03
ADR421
ADR431
ADR441
ADR4525
Initial Accuracy
(mV Maximum)
±2.5
±1
±1
±1
1
Long-Term Drift
(ppm Typical)
50
50
40
50
25
Temperature Drift
(ppm/°C Maximum)
3
3
3
3
2
Rev. C | Page 30 of 31
0.1 Hz to 10 Hz Noise
(μV p-p Typical)
6
1.75
3.5
1.2
1.25
Data Sheet
AD5761/AD5721
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.50
BSC
13
PIN 1
INDICATOR AREA OPTIONS
16
(SEE DETAIL A)
12
1
1.75
1.60 SQ
1.45
EXPOSED
PAD
9
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
8
5
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-005138
4
0.50
0.40
0.30
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-23-2017-E
PIN 1
INDICATOR
DETAIL A
(JEDEC 95)
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
8°
0°
SEATING
PLANE
COPLANARITY
0.10
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 69. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5721BCPZ-RL7
AD5721BRUZ
AD5721BRUZ-RL7
AD5761ACPZ-RL7
AD5761BCPZ-RL7
AD5761ARUZ
AD5761ARUZ-RL7
AD5761BRUZ
AD5761BRUZ-RL7
1
Resolution (Bits)
12
12
12
16
16
16
16
16
16
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
INL (LSB)
±0.5
±0.5
±0.5
±8
±2
±8
±8
±2
±2
Package Description
16-Lead LFCSP
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP
16-Lead LFCSP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Z = RoHS Compliant Part.
©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12640-0-1/18(C)
Rev. C | Page 31 of 31
Package Option
CP-16-22
RU-16
RU-16
CP-16-22
CP-16-22
RU-16
RU-16
RU-16
RU-16
Marking Code
DHP
DN8
DHQ
工商网监
湘ICP备2023018690号
