AD629BR-REEL

High Common-Mode Voltage, Difference Amplifier AD629 FEATURES Improved replacement for: INA117P and INA117KU ±270 V common-mode voltage range Input protection to ±500 V common mode ±500 V differential mode Wide power supply range (±2.5 V to ±18 V) ±10 V output swing on ±12 V supply 1 mA maximum power supply current HIGH ACCURACY DC PERFORMANCE 3 ppm maximum gain nonlinearity (AD629B) 20 μV/°C maximum offset drift (AD629A) 10 μV/°C maximum offset drift (AD629B) 10 ppm/°C maximum gain drift EXCELLENT AC SPECIFICATIONS 77 dB minimum CMRR @ 500 Hz (AD629A) 86 dB minimum CMRR @ 500 Hz (AD629B) 500 kHz bandwidth FUNCTIONAL BLOCK DIAGRAM REF(–) 1 –IN 2 21.1kΩ 380kΩ 380kΩ 380kΩ 8 NC 7 +VS 6 OUTPUT +IN 3 –VS 4 20kΩ NC = NO CONNECT Figure 1. GENERAL DESCRIPTION The AD629 is a difference amplifier with a very high input, common-mode voltage range. It is a precision device that allows the user to accurately measure differential signals in the presence of high common-mode voltages up to ±270 V. The AD629 can replace costly isolation amplifiers in applications that do not require galvanic isolation. The device operates over a ±270 V common-mode voltage range and has inputs that are protected from common-mode or differential mode transients up to ±500 V. The AD629 has low offset, low offset drift, low gain error drift, low common-mode rejection drift, and excellent CMRR over a wide frequency range. The AD629 is available in low cost, 8-lead PDIP and 8-lead SOIC packages. For all packages and grades, performance is guaranteed over the industrial temperature range of −40°C to +85°C. APPLICATIONS High voltage current sensing Battery cell voltage monitors Power supply current monitors Motor controls Isolation 100 COMMON-MODE REJECTION RATIO (dB) 95 2mV/DIV 85 80 75 70 65 60 00783-002 OUTPUT ERROR (2mV/DIV) 90 00783-001 AD629 5 REF(+) 55 50 20 100 1k FREQUENCY (Hz) 10k 60V/DIV –240 –120 0 120 COMMON-MODE VOLTAGE (V) 240 20k Figure 2. Common-Mode Rejection Ratio vs. Frequency Figure 3. Error Voltage vs. Input Common-Mode Voltage Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1999-2007 Analog Devices, Inc. All rights reserved. 00783-003 AD629 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Typical Performance Characteristics ............................................. 5 Theory of Operation ........................................................................ 9 Applications..................................................................................... 10 Basic Connections...................................................................... 10 Single-Supply Operation ........................................................... 10 System-Level Decoupling and Grounding.............................. 10 Using a Large Sense Resistor..................................................... 11 Output Filtering.......................................................................... 11 Output Current and Buffering.................................................. 12 A Gain of 19 Differential Amplifier......................................... 12 Error Budget Analysis Example 1 ............................................ 12 Error Budget Analysis Example 2 ............................................ 13 Outline Dimensions ....................................................................... 14 Ordering Guide............................................................................... 15 REVISION HISTORY 3/07—Rev. A to Rev. B Updated Format and Layout .............................................Universal Changes to Ordering Guide .......................................................... 15 3/00—Rev. 0 to Rev. A 10/99—Revision 0: Initial Version Rev. B | Page 2 of 16 AD629 SPECIFICATIONS TA = 25°C, VS = ±15 V, unless otherwise noted. Table 1. Parameter GAIN Nominal Gain Gain Error Gain Nonlinearity Gain vs. Temperature OFFSET VOLTAGE Offset Voltage vs. Temperature vs. Supply (PSRR) INPUT Common-Mode Rejection Ratio Condition VOUT = ±10 V, RL = 2 kΩ Min AD629A Typ Max 1 0.01 4 1 3 0.2 VS = ±5 V TA = TMIN to TMAX VS = ±5 V to ± 15 V VCM = ±250 V dc TA = TMIN to TMAX VCM = 500 V p-p, dc to 500 Hz VCM = 500 V p-p, dc to 1 kHz Common mode Differential Common mode Differential RL = 10 kΩ RL = 2 kΩ VS = ±12 V, RL = 2 kΩ Stable operation 6 100 88 Min AD629B Typ Max 1 0.01 4 1 3 0.1 3 110 96 Unit V/V % ppm ppm ppm/°C mV mV μV/°C dB dB dB dB dB V V kΩ kΩ V V V mA pF kHz V/μs kHz μs μs μs μV p-p nV/√Hz ±18 1 V mA mA °C 0.05 10 10 1 20 90 86 82 86 ±270 ±13 RL = 10 kΩ TA = TMIN to TMAX 0.03 10 3 10 0.5 1 10 84 77 73 77 88 90 ±270 ±13 200 800 ±13 ±12.5 ±10 Operating Voltage Range Input Operating Impedance OUTPUT Operating Voltage Range 200 800 ±13 ±12.5 ±10 ±25 1000 500 2.1 28 15 12 5 15 550 ±2.5 ±18 1 ±2.5 1000 Output Short-Circuit Current Capacitive Load DYNAMIC RESPONSE Small Signal –3 dB Bandwidth Slew Rate Full Power Bandwidth Settling Time ±25 1.7 VOUT = 20 V p-p 0.01%, VOUT = 10 V step 0.1%, VOUT = 10 V step 0.01%, VCM = 10 V step, VDIFF = 0 V 1.7 500 2.1 28 15 12 5 15 550 OUTPUT NOISE VOLTAGE 0.01 Hz to 10 Hz Spectral Density, ≥100 Hz 1 POWER SUPPLY Operating Voltage Range Quiescent Current TEMPERATURE RANGE For Specified Performance 1 VOUT = 0 V TMIN to TMAX TA = TMIN to TMAX −40 0.9 1.2 0.9 1.2 −40 +85 +85 See Figure 19. Rev. B | Page 3 of 16 AD629 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage, VS Internal Power Dissipation 1 8-Lead PDIP (N) 8-Lead SOIC (R) Input Voltage Range, Continuous Common-Mode and Differential, 10 sec Output Short-Circuit Duration Pin 1 and Pin 5 Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) 1 Rating ±18 V See Figure 4 See Figure 4 ±300 V ±500 V Indefinite –VS − 0.3 V to +VS + 0.3 V 150°C −55°C to +125°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.0 TJ = 150°C MAXIMUM POWER DISSIPATION (W) 8-LEAD PDIP 1.5 1.0 Specification is for device in free air: 8-Lead PDIP, θJA = 100°C/W; 8-Lead SOIC, θJA = 155°C/W. 8-LEAD SOIC 0.5 00783-004 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE (°C) 70 80 90 Figure 4. Maximum Power Dissipation vs. Temperature for SOIC and PDIP ESD CAUTION Rev. B | Page 4 of 16 AD629 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VS = ±15 V, unless otherwise noted. 100 COMMON-MODE REJECTION RATIO (dB) 400 360 COMMON-MODE VOLTAGE (±V) 90 80 70 60 50 40 30 20 00783-006 TA = +25°C 320 280 240 200 160 120 80 40 0 0 2 4 6 8 10 12 14 16 POWER SUPPLY VOLTAGE (±V) 18 00783-009 TA = +85°C TA = –40°C 10 0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 20 Figure 5. Common-Mode Rejection Ratio vs. Frequency Figure 8. Common-Mode Operating Range vs. Power Supply Voltage 2mV/DIV VS = ±18V RL = 10kΩ VS = ±18V RL = 2kΩ OUTPUT ERROR (2mV/DIV) OUTPUT ERROR (2mV/DIV) VS = ±15V VS = ±15V VS = ±12V VS = ±12V 00783-007 VS = ±10V –20 –16 –12 –8 –4 0 4 VOUT (V) 8 12 4V/DIV 16 VS = ±10V –20 –16 –12 –8 –4 0 4 VOUT (V) 8 12 4V/DIV 16 20 20 Figure 6. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage, RL = 10 kΩ (Curves Offset for Clarity) RL = 1kΩ Figure 9. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage, RL = 2 kΩ (Curves Offset for Clarity) OUTPUT ERROR (2mV/DIV) VS = ±15V OUTPUT ERROR (2mV/DIV) VS = ±18V VS = ±5V, RL = 10kΩ VS = ±5V, RL = 2kΩ VS = ±12V VS = ±5V, RL = 1kΩ 00783-008 VS = ±10V –20 –16 –12 –8 –4 0 4 VOUT (V) 8 12 4V/DIV 16 VS = ±2.5V, RL = 1kΩ –20 –16 –12 –8 –4 0 4 VOUT (V) 8 12 1V/DIV 16 20 20 Figure 7. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage, RL = 1 kΩ (Curves Offset for Clarity) Figure 10. Typical Gain Error Normalized @ VOUT = 0 V and Output Voltage Operating Range vs. Supply Voltage (Curves Offset for Clarity) Rev. B | Page 5 of 16 00783-011 00783-010 AD629 20µV/DIV VS = ±15V RL = 10kΩ 40µV/DIV VS = ±15V RL = 2kΩ ERROR (0.8ppm/DIV) 00783-012 ERROR (2ppm/DIV) 2.5V/DIV –10 –5 0 VOUT (V) 5 10 2V/DIV –10 –8 –6 –4 –2 0 2 VOUT (V) 4 6 8 10 Figure 11. Gain Nonlinearity; VS = ±15 V, RL = 10 kΩ 14.0 20µV/DIV VS = ±12V RL = 10kΩ Figure 14. Gain Nonlinearity; VS = ±15 V, RL = 2kΩ –40°C 13.0 12.0 OUTPUT VOLTAGE (V) –40°C ERROR (1ppm/DIV) 11.0 10.0 9.0 –11.5 –12.0 –12.5 VS= ±15V +85°C +25°C –40°C +25°C 16 18 00783-016 2V/DIV –10 –8 –6 –4 –2 0 2 VOUT (V) 4 6 8 10 00783-013 –13.0 –13.5 +85°C 0 2 4 6 8 10 12 14 OUTPUT CURRENT (mA) Figure 12. Gain Nonlinearity; VS = ±12 V, RL =10 kΩ Figure 15. Output Voltage Operating Range vs. Output Current; VS = ±15 V 11.5 40µV/DIV +85°C –40°C –40°C VS = ±5V RL = 1kΩ 10.5 9.5 OUTPUT VOLTAGE (V) ERROR (6.67ppm/DIV) 8.5 7.5 6.5 –9.0 –9.5 –10.0 VS= ±12V +25°C +85°C –40°C +25°C +85°C 0 2 4 6 8 10 12 14 OUTPUT CURRENT (mA) 16 18 00783-017 0.6V/DIV –3.0 –2.4 –1.8 –1.2 –0.6 0 0.6 VOUT (V) 1.2 1.8 2.4 3.0 00783-014 –10.5 –11.0 Figure 13. Gain Nonlinearity; VS = ±5 V, RL = 1 kΩ Figure 16. Output Voltage Operating Range vs. Output Current; VS = ±12 V Rev. B | Page 6 of 16 00783-015 20 20 AD629 4.5 3.5 2.5 OUTPUT VOLTAGE (V) +85°C –40°C –40°C +85°C VS= ±5V +85°C –40°C +25°C +85°C 4 6 8 10 12 14 OUTPUT CURRENT (mA) 16 18 00783-018 1.5 0.5 G = +1 RL = 2kΩ CL = 1000pF +25°C –2.0 –2.5 –3.0 –3.5 –4.0 +25°C 0 2 25mV/DIV 4µs/DIV 20 Figure 17. Output Voltage Operating Range vs. Output Current; VS = ±5 V 120 POWER SUPPLY REJECTION RATIO (dB) Figure 20. Small Signal Pulse Response +VS –VS 110 100 90 80 70 60 50 40 30 0.1 1.0 10 100 FREQUENCY (Hz) 1k 00783-019 G = +1 RL = 2kΩ CL = 1000pF 25mV/DIV 4µs/DIV 10k Figure 18. Power Supply Rejection Ratio vs. Frequency 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.01 0.1 1.0 10 100 FREQUENCY (Hz) 1k 10k 00783-020 Figure 21. Small Signal Pulse Response VOLTAGE NOISE SPECTRAL DENSITY (µV/ Hz) G = +1 RL = 2kΩ CL = 1000pF 5V/DIV 5µs/DIV 100k Figure 19. Voltage Noise Spectral Density vs. Frequency Figure 22. Large Signal Pulse Response Rev. B | Page 7 of 16 00783-023 00783-022 00783-021 AD629 5V/DIV +10V VOUT 0V 5V/DIV 0V VOUT –10V OUTPUT ERROR 1mV = 0.01% OUTPUT ERROR 1mV = 0.01% 00783-024 1mV/DIV 10µs/DIV 1mV/DIV 10µs/DIV Figure 23. Settling Time to 0.01%, for 0 V to 10 V Output Step; G = −1, RL = 2 kΩ 350 300 250 200 150 100 50 0 –150 N = 2180 n ≈ 200 PCS. FROM 10 ASSEMBLY LOTS Figure 26. Settling Time to 0.01% for 0 V to −10 V Output Step; G = −1, RL = 2kΩ 300 N = 2180 n ≈ 200 PCS. FROM 10 ASSEMBLY LOTS 250 NUMBER OF UNITS NUMBER OF UNITS 200 150 100 50 00783-025 00783-027 –100 –50 0 50 100 COMMON-MODE REJECTION RATIO (ppm) 150 0 –900 –600 –300 0 300 OFFSET VOLTAGE (µV) 600 900 Figure 24. Typical Distribution of Common-Mode Rejection; Package Option N-8 400 350 300 NUMBER OF UNITS Figure 27. Typical Distribution of Offset Voltage; Package Option N-8 400 N = 2180 n ≈ 200 PCS. FROM 10 ASSEMBLY LOTS NUMBER OF UNITS 350 300 250 200 150 100 00783-026 N = 2180 n ≈ 200 PCS. FROM 10 ASSEMBLY LOTS 250 200 150 100 50 0 –600 –400 –200 0 200 –1 GAIN ERROR (ppm) 400 600 0 –600 –400 –200 0 200 +1 GAIN ERROR (ppm) 400 600 Figure 25. Typical Distribution of −1 Gain Error; Package Option N-8 Figure 28. Typical Distribution of +1 Gain Error; Package Option N-8 Rev. B | Page 8 of 16 00783-029 50 00783-028 AD629 THEORY OF OPERATION The AD629 is a unity gain, differential-to-single-ended amplifier (diff amp) that can reject extremely high commonmode signals (in excess of 270 V with 15 V supplies). It consists of an operational amplifier (op amp) and a resistor network. To achieve high common-mode voltage range, an internal resistor divider (Pin 3 or Pin 5) attenuates the noninverting signal by a factor of 20. Other internal resistors (Pin 1, Pin 2, and the feedback resistor) restore the gain to provide a differential gain of unity. The complete transfer function equals VOUT = V (+IN) − V (−IN) Laser wafer trimming provides resistor matching so that common-mode signals are rejected while differential input signals are amplified. To reduce output drift, the op amp uses super beta transistors in its input stage. The input offset current and its associated temperature coefficient contribute no appreciable output voltage offset or drift, which has the added benefit of reducing voltage noise because the corner where 1/f noise becomes dominant is below 5 Hz. To reduce the dependence of gain accuracy on the op amp, the open-loop voltage gain of the op amp exceeds 20 million, and the PSRR exceeds 140 dB. REF(–) 1 –IN 2 +IN 3 –VS 4 21.1kΩ 380kΩ 380kΩ 20kΩ 380kΩ 8 7 6 5 NC +VS OUTPUT REF(+) 00783-001 AD629 NC = NO CONNECT Figure 29. Functional Block Diagram Rev. B | Page 9 of 16 AD629 APPLICATIONS BASIC CONNECTIONS Figure 30 shows the basic connections for operating the AD629 with a dual supply. A supply voltage of between ±3 V and ±18 V is applied between Pin 7 and Pin 4. Both supplies should be decoupled close to the pins using 0.1 μF capacitors. Electrolytic capacitors of 10 μF, also located close to the supply pins, may be required if low frequency noise is present on the power supply. While multiple amplifiers can be decoupled by a single set of 10 μF capacitors, each in amp should have its own set of 0.1 μF capacitors so that the decoupling point can be located right at the IC’s power pins. +VS REF (–) 1 REF (–) 1 21.1kΩ 380kΩ 380kΩ VY AD629 8 +VS NC –IN ISHUNT RSHUNT +IN 2 380kΩ VX 7 +VS 0.1µF 3 6 –VS 20kΩ 5 4 REF (+) OUTPUT = VOUT – VREF NC = NO CONNECT VREF Figure 31. Operation with a Single Supply 21.1kΩ 380kΩ 380kΩ AD629 8 +3V TO +18V NC –IN ISHUNT RSHUNT +IN 2 380kΩ 7 +VS 0.1µF (SEE TEXT) 3 6 VOUT = ISHUNT × RSHUNT REF (+) –VS (SEE TEXT) 0.1µF 20kΩ 4 5 Figure 30. Basic Connections 00783-030 NC = NO CONNECT –VS –3V TO –18V Applying a reference voltage to REF(+) and REF(–) and operating on a single supply reduces the input common-mode range of the AD629. The new input common-mode range depends upon the voltage at the inverting and noninverting inputs of the internal operational amplifier, labeled VX and VY in Figure 31. These nodes can swing to within 1 V of either rail. Therefore, for a (single) supply voltage of 10 V, VX and VY can range between 1 V and 9 V. If VREF is set to 5 V, the permissible common-mode range is +85 V to –75 V. The common-mode voltage ranges can be calculated by VCM (±) = 20 VX/VY(±) − 19 VREF The differential input signal, which typically results from a load current flowing through a small shunt resistor, is applied to Pin 2 and Pin 3 with the polarity shown to obtain a positive gain. The common-mode range on the differential input signal can range from −270 V to +270 V, and the maximum differential range is ±13 V. When configured as shown in Figure 30, the device operates as a simple gain-of-1, differential-to-singleended amplifier; the output voltage being the shunt resistance times the shunt current. The output is measured with respect to Pin 1 and Pin 5. Pin 1 and Pin 5 (REF(–) and REF(+)) should be grounded for a gain of unity and should be connected to the same low impedance ground plane. Failure to do this results in degraded commonmode rejection. Pin 8 is a no connect pin and should be left open. SYSTEM-LEVEL DECOUPLING AND GROUNDING The use of ground planes is recommended to minimize the impedance of ground returns (and therefore the size of dc errors). Figure 32 shows how to work with grounding in a mixed-signal environment, that is, with digital and analog signals present. To isolate low level analog signals from a noisy digital environment, many data acquisition components have separate analog and digital ground returns. All ground pins from mixed-signal components, such as ADCs, should return through a low impedance analog ground plane. Digital ground lines of mixed-signal converters should also be connected to the analog ground plane. Typically, analog and digital grounds should be separated; however, it is also a requirement to minimize the voltage difference between digital and analog grounds on a converter, to keep them as small as possible (typically