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AD664KNZ-BIP

AD664KNZ-BIP

  • 厂商:

    AD(亚德诺)

  • 封装:

    DIP-28

  • 描述:

    IC DAC 12BIT QUAD BIPOLAR 28DIP

  • 数据手册
  • 价格&库存
AD664KNZ-BIP 数据手册
Monolithic, 12-Bit Quad DAC AD664 Data Sheet FEATURES Four complete voltage-output DACs Data register readback feature Reset to zero override Multiplying operation Double buffered latches Surface-mount (LCC, PLCC, and JLCC) and PDIP and SBDIP packages MIL-STD-883 compliant versions available The functional completeness of the AD664 results from the combination of the Analog Devices, Inc., BiMOS II process, laser trimmed thin film resistors, and double level metal interconnects. APPLICATIONS Automatic test equipment Robotics Process control Disk drives Instrumentation Avionics PRODUCT HIGHLIGHTS 1. GENERAL DESCRIPTION The AD664 is four complete 12-bit, voltage-output digital-toanalog converters (DACs) on one monolithic IC chip. Each DAC has a double buffered input latch structure and a data readback function. All DAC read and write operations occur through a single microprocessor-compatible input/output (I/O) port. The I/O port accommodates 4-bit, 8-bit, or 12-bit parallel words allowing simple interfacing with a wide variety of microprocessors. A reset to zero control pin is provided to allow a user to simultaneously reset all DAC outputs to zero, regardless of the contents of the input latch. Any one or all of the DACs may be placed in a transparent mode allowing immediate response by the outputs to the input data. Rev. E The analog portion of the AD664 consists of four DAC cells, four output amplifiers, a control amplifier, and switches. Each DAC cell is an inverting R-2R type. The output current from each DAC is switched to the on-board application resistors and output amplifier. The output range of each DAC cell is programmed through the digital input/output port and may be set to unipolar (UNI) or bipolar (BIP) range, with a gain of one or two times the reference voltage. All DACs are operated from a single external reference. The AD664 provides four voltage-output DACs on one chip offering the highest density 12-bit DAC function available. 2. The output range of each DAC is fully and independently programmable. 3. Readback capability allows verification of contents of the internal data registers. 4. The asynchronous reset control returns all DAC outputs to 0 V. 5. DAC to DAC matching performance is specified and tested. 6. Linearity error is specified to be 1/2 LSB at room temperature and 3/4 LSB maximum for the K, B, and T grades. 7. DAC performance is guaranteed to be monotonic over the full operating temperature range. 8. Readback buffers have tristate outputs. 9. Multiplying mode operation allows use with fixed, variable, positive, or negative external references. 10. The AD664 is available in versions compliant with MILSTD-883. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD664 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Update Second Rank of a DAC ................................................ 19 Applications ....................................................................................... 1 Preload Multiple First Rank Registers ..................................... 19 General Description ......................................................................... 1 Load and Update Multiple DAC Outputs ............................... 19 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Selecting Gain Range and Modes (44-Lead Versions (JLCC and PLCC) and 44-Terminal Version (LCC)) ........................ 19 Functional Block Diagrams ............................................................. 4 Load and Update Mode of One DAC ...................................... 20 Specifications..................................................................................... 5 Preloading the Mode Select Register ....................................... 21 Absolute Maximum Ratings............................................................ 8 Transparent Operation (44-Lead Versions (JLCC and PLCC) and 44-Terminal Version (LCC)) ............................................. 22 ESD Caution .................................................................................. 8 Pin Configurations and Function Descriptions ........................... 9 Terminology .................................................................................... 12 Theory of Operation ...................................................................... 13 44-Lead (JLCC/PLCC) Version and 44-Terminal (LCC) Version ......................................................................................... 13 Output Data..................................................................................... 23 DAC Data Readback .................................................................. 23 Mode Data Readback ................................................................. 23 Output Loads .............................................................................. 24 Asynchronous Reset Operation ............................................... 24 28-Lead Versions ........................................................................ 13 Interfacing the AD664 to Microprocessors ................................ 25 Analog Circuit Considerations ..................................................... 14 MC6801 Interface ....................................................................... 25 Grounding Recommendations ................................................. 14 8051 Interface.............................................................................. 27 Power Supplies and Decoupling ............................................... 14 IBM PC Interface........................................................................ 28 Driving the Reference Input ..................................................... 14 Simple AD664 to MC68000 Interface ..................................... 31 Output Considerations .............................................................. 14 Applications Information .............................................................. 32 Multiplying Mode Performance ............................................... 15 Tester per Pin Automatic Test Equipment (ATE) Architecture ................................................................................ 32 Crosstalk ...................................................................................... 15 Output Noise ............................................................................... 15 Digital Interface .............................................................................. 16 Input Data ........................................................................................ 17 Timing Requirements .................................................................... 18 X-Axis and Y-Axis Plotters ....................................................... 33 Die Information .............................................................................. 34 Outline Dimensions ....................................................................... 36 Ordering Guide .......................................................................... 38 Load and Update One DAC Output ........................................ 18 Preloading the First Rank of One DAC ................................... 18 REVISION HISTORY 11/2018—Rev. D to Rev. E Updated Format .................................................................. Universal Reorganized Layout ............................................................ Universal Changed 28-Pin to 28-Lead .............................................. Universal Changed 44-Pin to 44-Lead and 44-Terminal ................ Universal Added 39-Pad Bare Die ..................................................... Universal Removed AD345 ................................................................. Universal Removed AD689 ................................................................. Universal Changed Product Description Section to General Description Section ................................................................................................ 1 Deleted Pin Configurations Section .............................................. 1 Changes to Product Highlights Section......................................... 1 Added Table of Contents Section ................................................... 2 Added Functional Block Diagrams Section ...................................4 Changes to Figure 1 and Figure 2 ....................................................4 Changes to Specifications Section ...................................................5 Changed Pin Configurations Section to Pin Configurations and Function Descriptions Section ........................................................9 Changes to Pin Configurations and Function Descriptions Section and Figure 3 ..........................................................................9 Added Figure 4, Figure 5, and Table 3; Renumbered Sequentially ........................................................................................9 Changes to Figure 6 ........................................................................ 11 Added Figure 7 and Table 4 .......................................................... 11 Changed Definitions of Specifications Section to Terminology Section.............................................................................................. 12 Rev. E | Page 2 of 39 Data Sheet AD664 Changed Functional Description Section to Theory of Operation Section ...........................................................................13 Changes to Theory of Operation Section and 28-Lead Versions Section ..............................................................................................13 Changes to Driving the Reference Input Section and Figure 10 ...........................................................................................14 Changes to Figure 11, Figure 12, and Figure 13 ..........................15 Changes to Digital Interface Section and Figure 14 ...................16 Changes to Table 6 ..........................................................................17 Added Timing Requirements Section ..........................................18 Changes to Figure 15, Figure 16, Table 7, Table 8, and Preloading the First Rank of One DAC Section..........................18 Changes to Figure 17 ......................................................................19 Change to Load and Update Multiple DAC Outputs Section ...19 Changes to Table 9 ..........................................................................20 Changes to Preloading the Mode Select Register Section, Figure 23, Figure 24, Table 10, and Table 11 ................................21 Changes to Figure 25, Figure 26, Table 12, and Table 13 ...........22 Change to Output Data Section, DAC Data Readback Section, and Mode Data Readback Section ................................................23 Changes to Figure 27, Table 14, and Table 15..............................23 Changes to Asynchronous Reset Operation Section and Table 16 .............................................................................................24 Changes to MC6801 Interface Section .........................................25 Change to Figure 32 ........................................................................ 25 Changes to Figure 33 ...................................................................... 26 Changes to Figure 35 ...................................................................... 27 Change to Figure 37 ........................................................................ 29 Changes to Table 17 ........................................................................ 29 Change to Simple AD664 to MC68000 Interface Section ......... 31 Changes to Figure 38 ...................................................................... 31 Changed Applications of the AD664 Section to Applications Information Section ........................................................................ 32 Changes to Tester per Pin Automatic Test Equipment (ATE) Architecture Section and Figure 39 .............................................. 32 Changed X-Y Plotters Section to X-Axis and Y-Axis Plotters Section .............................................................................................. 33 Changes to X-Axis and Y-Axis Plotters Section ......................... 33 Added Die Information Section, Figure 41, and Table 18 ......... 34 Updated Outline Dimensions........................................................ 36 Changes to Ordering Guide ........................................................... 38 2/2012—Rev. C to Rev. D Updated Outline Dimensions........................................................ 20 Changes to Ordering Guide ........................................................... 21 12/91—Rev. B to Rev. C Rev. E | Page 3 of 39 AD664 Data Sheet FUNCTIONAL BLOCK DIAGRAMS VCC (+12V/+15V) VREFIN VEE (–12V/–15V) AGND TO BIP OFF A TO D RF BIP OFF A TO VREF OFF A TO D LATCH A1 QS0, QS1, QS2 4 QS0 TO LATCHES A1 TO D1 DB7 DB5 I/O BUFFER TS VREF A TS VREF B 8 12 4 LATCH B1 LATCH B2 MODE LATCH 1 MODE LATCH 2 VOA U TS LATCH C1 ×1 BIP OFF A ×2 RF LATCH C2 U 12-BIT R/2R MDAC TS QS0, QS1, QS2 B RF RFC ×1 VOC VREF C DB3 DB1 RFB AD664 2RF QS1 4 B RF VOB 12 TO LATCHES A1 TO D1 ×2 RF 2RF 12-BIT R/2R MDAC TS 12 DB4 DB2 RFA ×1 BIP OFF A I/O BUFFER DB8 DB6 12-BIT R/2R MDAC B BIP OFF D I/O BUFFER QS0, QS1, QS2 LATCH D1 DB0 QS2 LATCH D2 U 12-BIT R/2R MDAC TO ALL LATCHES TO LATCHES A1 TO D1 ×2 RF 2RF VREF D TS B RF RFD ×1 VOD RESET CONTROL LOGIC RD CS LS TR MS DS1 DGND VLL (+5V) RST DS0 10590-003 DB9 U RF Figure 1. 44-Lead JLCC and PLCC and 44-Terminal LCC Functional Block Diagram VCC (+12V/+15V) VREFIN DB11 TO VREF A TO D DB10 LATCH A1 DB9 DB8 DB7 DB4 LATCH A2 TS LATCH B1 LATCH B2 RF VOA VREFA VREFB RF 12-BIT R/2R MDAC VOB 12 RF LATCH C1 LATCH C2 12-BIT R/2R MDAC DB3 TS DB2 TS DB1 AGND 12-BIT R/2R MDAC TS 12 TRISTATE I/O BUFFER DB6 DB5 VEE (–12V/–15V) LATCH D1 DB0 LATCH D2 VOC VREFC VREFD RF 12-BIT R/2R MDAC TO ALL LATCHES VOD RESET AD664 CONTROL LOGIC RD CS LS TR DS1 DS0 RST VLL (+5V) Figure 2. 28-Lead PDIP and SBDIP Functional Block Diagram Rev. E | Page 4 of 39 DGND 10590-004 DB10 LATCH A2 QS0, QS1, QS2 DB11 ×2 RF 2RF Data Sheet AD664 SPECIFICATIONS VLL = +5 V, VCC = +15 V, VEE = −15 V, VREF = +10 V, and TA = +25°C, unless otherwise noted. Table 1. Parameter RESOLUTION ANALOG OUTPUT Voltage Range1 UNI Versions BIP Versions Output Current Load Resistance Load Capacitance Short-Circuit Current ACCURACY Gain Error UNI Offset BIP Zero3 Linearity Error4 Linearity TMIN to TMAX Differential Linearity Differential Linearity TMIN to TMAX Gain Error Drift UNI 0 V to +10 V Mode AD664Jx/AD664Ax/AD664SD Min Typ Max 12 12 AD664Kx/AD664Bx/AD664TD/AD664TE Min Typ Max 12 12 0 0 VCC − 2.02 V VEE + 2.02 VCC − 2.02 V 500 40 mA kΩ pF mA +5 +1 +2 +1/2 +3/4 +1/2 LSB LSB LSB LSB LSB LSB ppm of FSR6/°C ppm of FSR/°C ppm of FSR/°C VCC − 2.02 VCC − 2.02 VEE + 2.02 5 5 2 25 −7 −2 −3 −3/4 −1 −3/4 ±3 ±1/2 ±3/4 ±1/2 ±3/4 2 500 40 +7 +2 +3 +3/4 +1 +3/4 25 −5 −1 −2 −1/2 −3/4 −1/2 Monotonic5 ±2 ±1/4 ±1/2 ±1/4 ±1/2 Unit Bits Monotonic5 −12 ±7 +12 −10 ±5 +10 BIP −5 V to +5 V Mode −12 ±7 +12 −10 ±5 +10 BIP −10 V to +10 V Mode −12 ±7 +12 −10 ±5 +10 UNI Offset Drift UNI 0 V to +10 V Mode −3 ±1.5 +3 −2 ±1 +2 ppm of FSR/°C BIP Zero Drift BIP −5 V to +5 V Mode −12 ±7 +12 −10 ±5 +10 −12 ±7 +12 −10 ±5 +10 ppm of FSR/°C ppm of FSR/°C 2.6 VCC − 2.02 1.3 VEE + 2.02 5.0 5.5 4.5 0.1 3 1 6 ±16.5 15 19 525 BIP −10 V to +10 V Mode REFERENCE INPUT Input Resistance Voltage Range7 POWER REOUIREMENTS VLL ILL At VIH, VIL = 5 V, 0 V At VIH, VIL = 2.4 V, 0.4 V VCC/VEE ICC IEE Total Power 1.3 VEE + 2.02 4.5 ±11.4 12 15 400 Rev. E | Page 5 of 39 2.6 VCC − 2.02 kΩ V 5.0 5.5 V 0.1 3 1 6 ±16.5 15 19 525 mA mA V mA mA mW ±11.4 12 15 400 AD664 Parameter ANALOG GROUND CURRENT8 MATCHING PERFORMANCE Gain Error9 Offset Error10 BIP Zero Error11 Linearity Error12 CROSSTALK Analog Digital DYNAMIC PERFORMANCE (RL = 2 kΩ, CL = 500 pF) Settling Time to ±1/2 LSB All Bits Switched from 0 to 1 or 1 to 0, Gain = 1, VREF = 10 Settling Time to ±1/2 LSB VREF (−10 V to 10 V), Gain = 1, Bits On Glitch Impulse MULTIPLYING MODE PERFORMANCE Reference Feedthrough at 1 kHz Reference −3 dB Bandwidth POWER SUPPLY GAIN SENSITIVITY VCC (11.4 V to 16.5 V) VEE (−16.5 V to −11.4 V) VLL (4.5 V to 5.5 V) DIGITAL INPUTS VIH VIL Data Inputs IIH at VIN = VLL IIL at VIN = DGND CS/DS0/DS1/RST/RD/LS IIH at VIN = VLL IIL at VIN = VLL MS/TR13 IIH at VIN = VLL IIL at VIN = DGND QS0/QS1/QS213 IIH at VIN = VLL IIL at VIN = DGND DIGITAL OUTPUTS VOL at 1.6 mA Sink VOH at 0.5 mA Source Data Sheet AD664Jx/AD664Ax/AD664SD Min Typ Max −600 ±400 +600 AD664Kx/AD664Bx/AD664TD/AD664TE Min Typ Max −600 ±400 +600 Unit μA −6 −2 −3 −1.5 −4 −1 −2 −1 +4 +1 +2 +1 LSB LSB LSB LSB −90 −60 dB dB 10 μs 500 μs nV-sec ±3 ±1/2 ±1 ±1/2 +6 +2 +3 +1.5 ±2 ±1/4 ±1 ±1/2 −90 −60 8 10 8 10 10 500 −75 70 ±2 ±2 ±2 2.0 0 −75 70 ±5 ±5 ±5 ±2 ±2 ±2 0.8 2.0 0 dB kHz ±5 ±5 ±5 ppm/% ppm/% ppm/% 0.8 V V −10 −10 ±1 ±1 +10 +10 −10 −10 ±1 ±1 +10 +10 μA μA −10 −10 ±1 ±1 +10 +10 −10 −10 ±1 ±1 +10 +10 μA μA −10 −10 +5 −5 +10 0 −10 −10 +5 −5 +10 0 μA μA −10 −10 +5 ±1 +10 +10 −10 −10 +5 ±1 +10 +10 μA μA 0.4 V V 0.4 2.4 2.4 Rev. E | Page 6 of 39 Data Sheet Parameter TEMPERATURE RANGE AD664Jx/AD664Kx AD664Ax/AD664Bx AD664SD/AD664TD/AD664TE/AD664TJ AD664 AD664Jx/AD664Ax/AD664SD Min Typ Max AD664Kx/AD664Bx/AD664TD/AD664TE Min Typ Max Unit 0 −40 −55 0 −40 −55 °C °C °C 70 +85 +125 70 +85 +125 A minimum power supply of ±12.0 V is required for 0 V to +10 V and ±10 V operation. A minimum power supply of ±11.4 V is required for −5 V to +5 V operation. For VCC < +12 V and VEE > −12 V. Voltage not to exceed 10 V maximum. BIP zero error is the difference from the ideal output (0 V) and the actual output voltage with code 100 000 000 000 applied to the inputs. 4 Linearity error is defined as the maximum deviation of the actual DAC output from the ideal output (a straight line drawn from zero scale to full-scale (FS) − 1 LSB). 5 Monotonic at all temperatures. Differential linearity specifications are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. 6 Full-scale range (FSR) is +20 V for a ±10 V range and +10 V for a ±5 V range. 7 A minimum power supply of ±12.0 V is required for a +10 V reference voltage. 8 Analog ground current is input code dependent. 9 Gain error matching is the largest difference in gain error between any two DACs in one package. 10 Offset error matching is the largest difference in offset error between any two DACs in one package. 11 BIP zero error matching is the largest difference in BIP zero error between any two DACs in one package. 12 Linearity error matching is the difference in the worst ease linearity error between any two DACs in one package. 13 44-lead (JLCC and PLCC) and 44-terminal (LCC) versions only. 1 2 3 Rev. E | Page 7 of 39 AD664 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VLL to DGND VCC to DGND VEE to DGND Soldering Power Dissipation AGND to DGND Reference Input VCC to VEE Digital Inputs Analog Inputs Rating 0 V to 7 V 0 V to 18 V −18 V to 0 V 300°C, 10 sec 1000 mW −1 V to +1 V VREFIN ≤ ±10 V and VREFIN ≤ (VCC – 2 V, VEE + 2 V) 0 V to 36 V −0.3 V to +7 V Indefinite shorts to VCC, VLL, VEE, and AGND Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. E | Page 8 of 39 Data Sheet AD664 25 QS2 NC 44 24 QS1 23 QS0 22 RST DGND 1 TOP VIEW (Not to Scale) LS 2 5 19 DS0 VEE (–12V/–15V) 6 18 CS 10 11 12 AD664 TOP VIEW (Not to Scale) 13 14 15 16 17 10590-103 DNC DNC RFD VOD 10 11 12 13 14 15 16 17 VOC 9 RFC 8 VREFIN 7 DNC = DO NOT CONNECT. 39 38 37 36 35 34 8 9 33 32 31 30 29 18 19 DS1 VCC (+12V/+15V) RFB 20 VOB 21 4 RFA 3 VOA DNC AGND VREFIN RFC VOC VOD RFD DNC DNC 7 DB10 DB9 DB8 DB7 DB6 DNC DB5 DB4 DB3 DB2 DB1 CS DS0 DS1 DGND RST QS0 QS1 QS2 TR MS (LSB) DB0 RD AD664 RFA VOA VOB RFB DNC = DO NOT CONNECT. 3 2 Figure 5. 44-Terminal LCC Pad Configuration DB11 (MSB) 4 DNC 5 DNC DNC VLL (+5V) AGND DNC 6 LS RD VEE (–12V/–15V) VCC (+12V/+15V) Figure 3. 44-Lead JLCC Pin Configuration 1 44 43 42 41 40 RFA 7 39 DB10 VOA 8 VOB 9 38 DB9 37 DB8 RFB 10 36 DB7 VREFIN 11 RFC 12 VOC 13 VOD 14 AD664 35 DB6 TOP VIEW (Not to Scale) 34 DNC 33 DB5 32 DB4 RFD 15 31 DB3 DNC 16 30 DB2 DNC 17 29 DB1 DNC = DO NOT CONNECT. 10590-104 TR MS (LSB) DB0 QS2 RST QS0 QS1 DGND DS1 CS DS0 18 19 20 21 22 23 24 25 26 27 28 Figure 4. 44-Lead PLCC Pin Configuration Table 3. 44-Lead JLCC, 44-Lead PLCC, and 44-Terminal LCC Pin Function Descriptions Pin No. 1 2 3, 16, 17, 34, 41, 43, 44 4 5 6 7 8 9 10 Mnemonic RD LS DNC AGND VCC (+12V/+15V) VEE (−12V/−15V) RFA VOA VOB RFB Description Readback Pin (Active Low). Latch Select Pin (Active Low). Do Not Connect. Analog Ground Pin. Positive Analog Supply Connection. Negative Analog Supply Connection. Feedback Connection for DAC A. Analog Output Voltage from DAC A. Analog Output Voltage from DAC B. Feedback Connection for DAC B. Rev. E | Page 9 of 39 10590-107 NC 43 27 28 TR 25 26 26 23 24 MS VLL (+5V) 42 20 21 22 27 6 5 4 3 2 1 (LSB) DB0 28 DNC 41 40 39 38 37 36 35 34 33 32 31 30 29 DB11 (MSB) 40 44 43 42 41 VEE (–12V/–15V) VCC (+12V/+15V) AGND DNC LS RD DNC DNC VLL (+5V) DNC DB11 (MSB) DB1 DB2 DB3 DB4 DB5 DNC DB6 DB7 DB8 DB9 DB10 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD664 Pin No. 11 12 13 14 15 18 19 20 21 22 23 24 25 26 27 28 to 33, 35 to 40 42 Data Sheet Mnemonic VREFIN RFC VOC VOD RFD CS DS0 DS1 DGND RST QS0 QS1 QS2 TR MS DB0 to DB11 VLL (+5V) Description Reference Input Voltage Pin. Feedback Connection for DAC C. Analog Output Voltage from DAC C. Analog Output Voltage from DAC D. Feedback Connection for DAC D. Chip Select Pin (Active Low). DAC Address Data 0. DAC Address Data 1. Digital Ground. Reset Pin (Active Low). 4-Bit Nibble Data. 8-Bit Nibble Data. 12-Bit Nibble Data. Transfer Register Pin (Active Low). Mode Select Pin (Active Low). Data Input/Outputs. DB11 is MSB. Digital Supply. Rev. E | Page 10 of 39 Data Sheet AD664 1 VOC 2 28 VOB 27 VOA VOD 3 26 VEE (–12V/–15V) CS 4 25 VCC (+12V/+15V) DS0 5 24 AGND VOC 2 27 VOD 3 26 VEE (–12V/–15V) CS 4 25 VCC (+12V/+15V) DS0 5 24 AGND DS1 6 DS1 6 23 LS DGND 7 AD664 22 RD RST 8 TOP VIEW (Not to Scale) DB0 (LSB) 9 DGND 7 AD664 VOA TOP VIEW 21 VLL (+5V) (Not to Scale) DB0 (LSB) 9 20 DB11 (MSB) RST 8 19 DB10 DB2 11 18 DB9 DB3 12 17 DB8 DB4 13 16 DB7 DB5 14 15 DB6 22 RD 21 VLL (+5V) 20 DB11 (MSB) DB1 10 19 DB10 DB2 11 18 DB9 DB3 12 17 DB8 DB4 13 16 DB7 DB5 14 15 DB6 Figure 7. 28-Lead PDIP Pin Configuration Table 4. 28-Lead SBDIP and 28-Lead PDIP Pin Function Descriptions Mnemonic VREFIN VOC VOD CS DS0 DS1 DGND RST DB0 to DB11 VLL (+5V) RD LS AGND VCC (+12V/+15V) VEE (−12 V/−15 V) VOA VOB 23 LS 10590-105 DB1 10 Figure 6. 28-Lead SBDIP Pin Configuration Pin No. 1 2 3 4 5 6 7 8 9 to 20 21 22 23 24 25 26 27 28 VREFIN 28 Description Reference Input Voltage Pin. Analog Output Voltage from DAC C. Analog Output Voltage from DAC D. Chip Select Pin (Active Low). DAC Address Data 0. DAC Address Data 1. Digital Ground. Reset Pin (Active Low). Data Input/Outputs. DB11 is MSB. Digital Supply. Readback Pin (Active Low). Latch Select Pin (Active Low). Analog Ground Pin. Positive Analog Supply Connection. Negative Analog Supply Connection. Analog Output Voltage from DAC A. Analog Output Voltage from DAC B. Rev. E | Page 11 of 39 10590-106 VOB VREFIN 1 AD664 Data Sheet TERMINOLOGY Linearity Error Analog Devices defines linearity error as the maximum deviation of the actual, adjusted DAC output from the ideal analog output (a straight line drawn from zero scale to fullscale − 1 LSB) for any bit combination. This is also referred to as relative accuracy. The AD664 is laser trimmed to typically maintain linearity errors at less than ±1/4 LSB. Monotonicity A DAC is said to be monotonic if the output either increases or remains constant for increasing digital inputs such that the output is always a nondecreasing function of input. All versions of the AD664 are monotonic over their full operating temperature range. Differential Linearity Monotonic behavior requires that the differential linearity error be less than 1 LSB both at 25°C as well as over the temperature range of interest. Differential nonlinearity is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. For example, for a 10 V full-scale output, a change of 1 LSB in digital input code results in a 2.44 mV change in the analog output (VREF = 10 V, Gain = 1, 1 LSB = 10 V × 1/4096 = 2.44 mV). If in actual use, a 1 LSB change in the input code results in a change of only 0.61 mV (1/4 LSB) in analog output, the differential nonlinearity error is −1.83 mV, or −3/4 LSB. Gain Error DAC gain error is a measure of the difference between the output span of an ideal DAC and an actual device. UNI Offset Error UNI offset error is the difference between the ideal output (0 V) and the actual output of a DAC when the input is loaded with all 0s and the mode is UNI. BIP Zero Error BIP zero error is the difference between the ideal output (0 V) and the actual output of a DAC when the input code is loaded with the MSB = 1 and the rest of the bits = 0 and the mode is BIP. Settling Time Settling time is the time required for the output to reach and remain within a specified error band about its final value, measured from the digital input transition. Crosstalk Crosstalk is the change in an output caused by a change in one or more of the other outputs. Crosstalk is due to capacitive and thermal coupling between outputs. Reference Feedthrough The portion of an ac reference signal that appears at an output when all input bits are low. Feedthrough is due to capacitive coupling between the reference input and the output, and is specified in decibels at a particular frequency. Reference 3 dB Bandwidth The frequency of the ac reference input signal at which the amplitude of the full-scale output response falls 3 dB from the ideal response. Glitch Impulse Glitch impulse is an undesired output voltage transient caused by asymmetrical switching times in the switches of a DAC. These transients are specified by their net area (in nV-sec) of the voltage vs. time characteristic. Rev. E | Page 12 of 39 Data Sheet AD664 THEORY OF OPERATION The AD664 combines four complete 12-bit voltage output DAC converters with a fast, flexible digital I/O port on one monolithic chip. The AD664 is available in three forms. The device is available in a 44-lead version (JLCC and PLCC), a 44-terminal version (LCC) (all shown in Figure 1), and a 28-lead version (shown in Figure 2). 44-LEAD (JLCC/PLCC) VERSION AND 44-TERMINAL (LCC) VERSION Each DAC offers flexibility, accuracy, and good dynamic performance. The R/2R structure is fabricated from thin film resistors, which are laser trimmed to achieve 1/2 LSB linearity and guaranteed monotonicity. The output amplifier combines the best features of the bipolar (BIP) and metal-oxide semiconductor (MOS) devices to achieve good dynamic performance and low offset. Settling time is under 10 µs and each output can drive a 5 mA, 500 pF load. Short-circuit protection allows indefinite shorts to VLL, VCC, VEE, and AGND. The output and span resistor pins are available separately. This feature allows a user to insert current boosting elements to increase the drive capability of the system, as well as to overcome parasitics. Digital circuitry is implemented in complementary metal-oxide semiconductor (CMOS) logic. The fast, low power, digital interface allows the AD664 to be interfaced with most microprocessors. Through this interface, the wide variety of features on each chip may be accessed. For example, the input data for each DAC is programmed by way of 4-bit, 8-bit, 12-bit, or 16-bit words. The double buffered input structure of this latch allows all four DACs to be updated simultaneously. A readback feature allows the internal registers to be read back through the same digital port, as either 4-bit, 8-bit, or 12-bit words. When disabled, the readback drivers are placed in a high impedance (tristate) mode. A transparent mode allows the input data to pass straight through both ranks of input registers and appear at the DAC with a minimum of delay. One DAC may be placed in the transparent mode at a time, or all four may be made transparent at once. The mode select feature allows the output range and mode of the DACs to be selected via the data bus inputs. An internal mode select register stores the selections. This register may also be read back to check its contents. A reset to zero feature allows all DACs to be reset to 0 V output by strobing a single pin. 28-LEAD VERSIONS The 28-lead versions are dedicated versions of the 44-lead (JLCC and PLCC) and 44-terminal (LCC) AD664. Each offers a reduced set of features from those offered in the 44-lead version (JLCC and PLCC) and 44-terminal version (LCC). This accommodates the reduced number of package pins available. Data is written and read with 12-bit words only. Output range and mode select functions are also not available in 28-lead versions. As an alternative, users specify either the UNI (zero scale to VREFIN) models or the BIP (−VREFIN to VREFIN) models depending on the application requirements. Finally, the transparent mode is not available on the 28-lead versions. Table 5. Transfer Functions Gain 1 2 Mode = UNI 000000000000 = 0 V 100000000000 = VREFIN/2 111111111111 = VREFIN − 1 LSB 000000000000 = 0 V 100000000000 = VREFIN 111111111111 = 2 × VREFIN − 1 LSB Mode = BIP 000000000000 = − VREFIN/2 100000000000 = 0 V 111111111111 = VREFIN/2 − 1 LSB 000000000000 = VREFIN 100000000000 = 0 V 111111111111 = +VREFIN − 1 LSB Rev. E | Page 13 of 39 AD664 Data Sheet ANALOG CIRCUIT CONSIDERATIONS V+ GROUNDING RECOMMENDATIONS SYSTEM SUPPLIES +15V –15V +5V The AD664 has two pins, designated analog and digital ground. The analog ground pin is the high quality ground reference point for the device. A unique internal design has resulted in low analog ground current, which greatly simplifies management of ground current and the associated induced voltage drops. The analog ground pin is connected to the analog ground point in the system. The external reference and any external loads are also returned to analog ground. REF VLL VCC VREF IN AD664 The digital ground pin is connected to the digital ground point in the circuit. This pin returns current from the logic portions of the AD664 circuitry to ground. DIGITAL ANALOG COMMON COMMON +5V RETURN –15V RETURN +15V RETURN 10590-007 Analog and digital grounds are connected at one point in the system. If there is a possibility that this connection be broken or otherwise disconnected, then two diodes are connected between the analog and digital ground pins of the AD664 to limit the maximum ground voltage difference. VEE Figure 8. Recommended Circuit Schematic POWER SUPPLIES AND DECOUPLING OUTPUT CONSIDERATIONS The AD664 requires three power supplies for proper operation. VLL powers the logic portions of the device and requires 5 V. VCC and VEE power the remaining portions of the circuitry and require +12 V to +15 V and −12 V to −15 V, respectively. VCC and VEE must also be a minimum of 2 V greater than the maximum reference and output voltages anticipated. Each DAC output can source or sink 5 mA of current to an external load. Short-circuit protection limits load current to a maximum load current of 40 mA. Load capacitance of up to 500 pF is accommodated with no effect on stability. When an application requires additional output current, a current boosting element is inserted into the output loop with no sacrifice in accuracy. Figure 9 details this method. Decoupling capacitors are used on all power supply pins. Good engineering practice dictates that the bypass capacitors be located as near as possible to the package pins. VLL is bypassed to digital ground. VCC and VEE are decoupled to analog ground. OUT SENSE OUT FORCE DAC DRIVING THE REFERENCE INPUT AD664 The architecture of the AD664 derives an inverted version of the reference voltage for some portions of the internal circuitry. This means that the power supplies must be at least 2 V greater than both the external reference and the inverted external reference. CURRENT BOOSTER EXTERNAL LOAD 10590-008 The reference input of the AD664 can have an impedance as low as 1.3 kΩ. The external reference voltage must be able to source up to 7.7 mA of load current. Suitable choices include the 5 V AD586 and the 10 V AD587. ANALOG COMMON Figure 9. Current Boosting Scheme Maximum AD664 output voltage settling time is 10 μs. Figure 10 shows the output voltage settling time with a fixed 10 V reference, gain = 1, and all bits switched from 1 to 0. 5V LARGE SCALE >2mV 100 90 +1LSB FINE SCALE 0V –1LSB 10 0% 5V 2µs Figure 10. Settling Time, All Bits Switched from 1 to 0 Rev. E | Page 14 of 39 10590-009 INPUT BITS Data Sheet AD664 Alternately, Figure 11 shows the settling characteristics when the reference is switched and the input bits remain fixed. In this case, all bits are on, the gain is 1, and the reference is switched from −5 V to +5 V. 5V 2V >2mV DAC A, C, D OUT 100 90 DAC B OUT 0V 0V –1LSB –1LSB 10 0% 5V 10590-010 10 0% REF INPUT 100 90 +1LSB +1LSB FINE SCALE 2µs 1µs Figure 11. Settling Time, Input Bits Fixed, Reference Switched DIGITAL CROSSTALK MULTIPLYING MODE PERFORMANCE OUTPUT NOISE 20 45 0 0 –5 10k 100k FREQUENCY (Hz) 1M 1mV 200µs 100 90 10 0% 10590-013 PHASE 5 Wideband output noise is shown in Figure 14. This measurement was made with a 7 MHz noise bandwidth, gain = 1, and all bits on. The total rms noise is approximately 1/5 the visual peak-to-peak noise. 10590-011 GAIN (dB) 90 PHASE MARGIN (Degrees) GAIN 10 ANALOG CROSSTALK Figure 13. Output Crosstalk Figure 12 illustrates the typical open-loop gain and phase performance of the output amplifiers of the AD664. 15 >2mV 10590-012 LARGE SCALE switch 2 kΩ loads from 10 V to 0 V. The first disturbance in the output of DAC B is caused by digital feedthrough from the input data lows. The second disturbance is caused by analog feedthrough from the other DAC outputs. Figure 12. Gain and Phase Performance of AD664 Outputs CROSSTALK Figure 14. Typical Output Noise Crosstalk is a spurious signal on one DAC output caused by a change in the output of one or more of the other DACs. Crosstalk is induced by capacitive, thermal, or load current induced feedthrough. Figure 13 shows typical crosstalk. DAC B is set to output 0 V. The outputs of DAC A, DAC C, and DAC D Rev. E | Page 15 of 39 AD664 Data Sheet DIGITAL INTERFACE Partial address decoding is performed by the DS0, DS1, QS0, QS1, and QS2 address bits. QS0, QS1, and QS2 allow the 44-lead versions (JLCC and PLCC) and the 44-terminal version (LCC) of the AD664 to be addressed in 4-bit nibble, 8-bit byte or 12-bit parallel words. As Table 6 shows, the AD664 makes a wide variety of operating modes available to the user. These modes are accessed or programmed through the high speed digital port of the quad DAC. On-board registers program and store the DAC input codes and the DAC operating mode data. All registers are double buffered to allow for simultaneous updating of all outputs. Register data may be read back to verify the respective contents. The digital port also allows transparent operation. Data from the input pins is sent directly through both ranks of latches to the DAC. The RST pin provides a simple method to reset all output voltages to 0. Its advantages are speed and low software overhead. Table 6. Digital Truth Table1 Function Load First Rank (Data) DACA DACB DACC DACD Load Second Rank (Data) Readback Second Rank (Data) Reset Transparent2 All DACs DACA DACB DACC DACD Mode Select2, 3 First Rank Second Rank Readback Mode2 Update Second Rank and Mode DS1, DS0 LS MS TR QS0, QS1, QS22 RD CS RST 00 01 10 11 X Select DAC X 0 0 0 0 1 X X 1 1 1 1 1 1 X 1 1 1 1 1 1 X Select quad Select quad Select quad Select quad X Select quad X 1 1 1 1 1 0 X 1 to 0 1 to 0 1 to 0 1 to 0 1 to 0 1 to 0 X 1 1 1 1 1 1 0 X 00 01 10 11 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 000 000 000 000 000 1 1 1 1 1 1 to 0 1 to 0 1 to 0 1 to 0 1 to 0 1 1 1 1 1 X X X X 0 1 X 1 0 0 0 0 1 1 1 0 00X X 00X X 1 1 0 1 1 to 0 1 to 0 1 to 0 1 to 0 1 1 1 1 X means don’t care. For 44-lead versions (JLCC and PLCC) and 44-terminal version (LCC) only. Allow the AD664 to be addressed in 4-bit nibble, 8-bit byte, or 12-bit parallel words. 3 For MS, TR, LS = 0, an MS first write occurs. 2 Rev. E | Page 16 of 39 Data Sheet AD664 INPUT DATA In general, two types of data are input to the registers of the AD664, input code data, and mode select data. Input code data sets the DAC inputs while the mode select data sets the gain and range of each DAC. The versatile I/O port of the AD664 allows many different types of data input schemes. For example, the input code for just one of the DACs may be loaded and the output may or may not be updated. Alternatively, the input codes for all four DACs may be written, and the outputs may or may not be updated. The same applies for mode selection. The mode of just one or many of the DACs may be rewritten and the user can choose to immediately update the outputs or wait until a later time to transfer the mode information to the outputs. A user may also write both input code and mode information into their respective first ranks and then update all second ranks at once. Finally, transparent operation allows data to be transferred from the inputs to the outputs using a single control line. This feature is useful, for example, in a situation where one of the DACs is used in an analog-to-digital converter (ADC). The successive approximation register (SAR) ADC is connected directly to a DAC by using the transparent mode of operation. Another use for this feature is during system calibration where the endpoints of the transfer function of each DAC is measured. For example, if the full-scale voltages of each DAC are measured, then by making all four DACs transparent and putting all ones on the input port, all four DACs are full-scale. This requires far less software overhead than loading each register individually. Rev. E | Page 17 of 39 AD664 Data Sheet TIMING REQUIREMENTS The following sections detail the timing requirements for various data loading schemes. All of the timing specifications shown assume VIH = +2.4 V, VIL = +0.4 V, VCC = +15 V, VEE = −15 V, and VLL = +5 V. DATA INPUT/ OUTPUT BITS DATA VALID tDS ADDRESS QS0, QS1, QS2 DS0, DS1 tDH ADDRESS VALID tAS LOAD AND UPDATE ONE DAC OUTPUT LS In this first example, the object is simply to change the output of one of the four DACs on the AD664 chip. The procedure is to select the address bits that indicate the DAC to be programmed, pull latch select (LS) low, pull chip select (CS) low, release LS and then release CS. When CS goes low, data enters the first rank of the input latch. As soon as LS goes high, the data is transferred into the second rank and produces the new output voltage. During this transfer, mode select (MS), transparent (TR), readback (RD), and reset (RST) are held high. tAH tLW tLS 10590-113 tCH CS Figure 15. Update Output of a Single DAC DATA INPUT/ OUTPUT BITS DATA VALID tDS tDH ADDRESS QS0, QS1, QS2 DS0, DS1 ADDRESS VALID tAS PRELOADING THE FIRST RANK OF ONE DAC tAH LS tLS tLH CS tCW 10590-014 In this case, the object is to load new data into the first rank of one of the DACs but not the output. As in the previous case, the address and data inputs are placed on the appropriate pins, LS is brought to 0, and CS is asserted. Note that in this situation, CS goes high before LS goes high. The input data is prevented from getting to the second rank and affecting the output voltage. Figure 16. Preload First Rank of a DAC This method shown in Figure 16 allows the user to preload the data to a DAC and strobe it into the output latch, which can be done by reproducing the sequence of signals illustrated in the Update Second Rank of a DAC section. Table 7. Update Output of a Single DAC Timing Parameter LS Falling Edge to CS Falling Edge (tLS1) Data Transition to CS Falling Edge (tDS) CS Rising Edge to Data Transition (tDH) LS Low Time (tLW) LS Rising Edge to CS Rising Edge (tCH) Address Transition to CS Falling Edge (tAS) CS Rising Edge to Address Transition (tAH) 1 25°C Minimum (ns) 0 0 0 60 30 0 0 TMIN to TMAX Minimum (ns) 0 0 0 80 50 0 0 For tLS > 0, the width of LS must be increased by the same amount that tLS is greater than 0 ns. Table 8. Preload First Rank of a DAC Timing Parameter LS Falling Edge to CS Falling Edge (tLS) CS Rising Edge to LS Rising Edge (tLH) CS Low Time (tCW) Data Transition to CS Falling Edge (tDS) CS Rising Edge to Data Transition (tDH) Address Transition to CS Falling Edge (tAS) CS Rising Edge to Address Transition (tAH) 25°C Minimum (ns) 0 15 80 0 15 0 15 Rev. E | Page 18 of 39 TMIN to TMAX Minimum (ns) 0 15 100 0 15 0 15 Data Sheet AD664 DATA INPUT/ OUTPUT BITS Assuming that a new input code had previously been placed into the first rank of the input latches, the user can update the output of the DAC by simply pulling CS low while keeping LS, MS, TR, RD, and RST high. Address data is not needed in this case. All second ranks are updated by this procedure, but only the second ranks that receive data differently from the data that was originally there manifest a change. Updating the second rank does not change the contents of the first rank. DAC4 WORD 70ns LS CS Figure 19. Update All DAC Outputs DON’T CARE 0 ADDRESS 1 QS0, QS1, QS2 DS0, DS1 0 DON’T CARE 1 0 DAC3 WORD ADDRESS QS0, QS1, QS2 DS0, DS1 1 LS DAC2 WORD tCW = 80ns MIN (100ns MIN AT TMIN TO TMAX) 10590-015 1 CS 0 Figure 17. Update Second Rank of a DAC The same options that exist for individual DAC input loading also exist for multiple DAC input loading. That is, the user can choose to update the first and second ranks of the registers or preload the first ranks and then update them at a future time. PRELOAD MULTIPLE FIRST RANK REGISTERS The second method involves doing a CS assertion (low) and an LS toggle separately for each DAC. This method is a series of preload operations (Figure 16 and Table 8). In this case, illustrated in Figure 20, two LS signals are shown. One, labeled LS, goes high before CS returns high. This transfers the new input word to the DAC outputs sequentially. The second LS signal, labeled alternate LS, stays low until CS returns high. Using this sequence loads the first ranks with each new input word but does not update the DAC outputs. Then, to update all DAC outputs simultaneously requires the signals illustrated in Figure 17. DATA INPUT/ OUTPUT BITS ADDRESS QS0, QS1, QS2 DS0, DS1 The first ranks of the DAC input registers may be preloaded with new input data without disturbing the second rank data. This is done by transferring the data into the first rank by bringing CS low while LS is low. CS must return high before LS. This prevents the data from the first rank from getting into the second rank. A simple second rank update cycle as shown in Figure 17 moves the preloaded information to the DACs. DATA INPUT/ OUTPUT BITS DATA1 VALID DATA2 VALID ADDRESS QS0, QS1, QS2 DS0, DS1 ADDRESS ONE ADDRESS TWO DATA3 VALID DATA4 VALID ADDRESS THREE ADDRESS FOUR ALTERNATE LS CS tW Figure 20. Load and Update Multiple DACs SELECTING GAIN RANGE AND MODES (44-LEAD VERSIONS (JLCC AND PLCC) AND 44-TERMINAL VERSION (LCC)) 10590-016 LS CS LS 10590-018 DATA INPUT/ OUTPUT BITS DAC1 WORD 10590-017 UPDATE SECOND RANK OF A DAC Figure 18. Preload First Rank Registers LOAD AND UPDATE MULTIPLE DAC OUTPUTS The following examples demonstrate two ways to update all DAC outputs. The first method involves doing all data transfers during one long CS low period. Note that in this case, shown in Figure 19, LS returns high before CS goes high. Data hold time, relative to an address change, is 70 ns. This updates the outputs of all DACs simultaneously. The mode select feature of the AD664 allows a user to configure the gain ranges and output modes of each of the four DACs. On-board switches take the place of up to eight external relays that are normally required to accomplish this task. The switches are programmed by the mode select word entered via the data I/O port. The mode select word is 8-bits wide and occupies the topmost eight bits of the input word. The last four bits of the input word are don’t care bits. Figure 21 shows the format of the mode select word. The first four bits determine the gain range of the DAC. When set to be a gain of 1, the output of the DAC spans a voltage of one times the reference. When set to a gain of 2, the output of the DAC spans a voltage of two times the reference. Rev. E | Page 19 of 39 AD664 Data Sheet The next four bits determine the mode of the DAC. When set to UNI, the output goes from 0 V to VREFIN, or 0 V to 2 V VREFIN. When the BIP mode is selected, the output goes from − VREFIN/2 to VREFIN/2 or − VREFIN to VREFIN. DB4 GB GC GD MA MB MC MD Gx = 0; GAIN = 1 Gx = 1; GAIN = 2 Mx = 0; UNIPOLAR Mx = 1; BIPOLAR MS tMS Figure 21. Mode Select Word Format DATA INPUT/ OUTPUT BITS LOAD AND UPDATE MODE OF ONE DAC tMH MODE SELECT DATA WORD tDH tDS In this next example, the object is to load new mode information for one of the DACs into the first rank of latches and then immediately update the second rank. This mode is done by putting the new mode information (8-bit word length) onto the data bus. Then MS and LS are pulled low. Following the MS and LS being pulled low, CS is pulled low. This loads the mode tLW LS tLS tCH 10590-020 GA In reality, this load cycle really updates the modes of all the DACs, but the effect is to only change the modes of those DACs whose mode select information has actually changed. 10590-019 DB11 information into the first rank of latches. LS is then brought high. This action updates the second rank of latches (and the DAC outputs). The load cycle ends when CS is brought high. CS Figure 22. Load and Update Mode of One DAC Table 9. Load and Update Mode of One DAC Timing Parameter MS Falling Edge to CS Falling Edge (tMS) LS Falling Edge to CS Falling Edge (tLS1) Data Transition to CS Falling Edge (tDS) LS Low Time (tLW) LS Rising Edge to CS Rising Edge (tCH) CS Rising Edge to Data Transition (tDH) CS Rising Edge to MS Rising Edge (tMH) 1 25°C Minimum (ns) 0 TMIN to TMAX Minimum (ns) 0 0 0 60 70 0 0 0 0 70 80 0 0 For tLS > 0, the width of LS must be increased by the same amount that tLS is greater than 0 ns. Rev. E | Page 20 of 39 Data Sheet AD664 PRELOADING THE MODE SELECT REGISTER 1 0 ADDRESS 1 QS0, QS1, QS2 DS0, DS1 0 MS tMH tMS CS tW Figure 24. Update Second Rank of Mode Select Latch MS tMH tMS DATA INPUT/ OUTPUT BITS MODE SELECT DATA WORD tDH tDS LS tLS CS tW 10590-021 tLH Figure 23. Preload Mode Select Register Table 10. Preload Mode Select Register Timing Parameter CS Rising Edge to MS Rising Edge (tMH) 25°C Minimum (ns) 15 TMIN to TMAX Minimum (ns) 15 MS Falling Edge to CS Falling Edge (tMS) 0 0 LS Falling Edge to CS Falling Edge (tLS) Data Transition to CS Falling Edge (tDS) CS Low Time (tW) CS Rising Edge to LS Rising Edge (tLH) CS Rising Edge to Data Transition (tDH) 0 0 80 15 15 0 0 100 15 15 Table 11. Update Second Rank of Mode Select Latch Timing Parameter MS Falling Edge to CS Falling Edge (tMS) 25°C Minimum (ns) 0 CS Rising Edge to MS Rising Edge (tMH) CS Low Time (tW) 0 0 80 100 Rev. E | Page 21 of 39 TMIN to TMAX Minimum (ns) 0 10590-022 Mode data is written into the first rank of the mode select latch without changing the modes currently being used. This feature is useful when a user wants to preload new mode information in anticipation of strobing it in at a future time. Figure 23 and Table 10 illustrate the correct sequence and timing of control signals to accomplish this task, which allows the user to preload the data to a DAC and strobe it into the output latch at some future time. The user can do this by reproducing the sequence of signals illustrated in Figure 24 and Table 11. DATA INPUT/ OUTPUT BITS AD664 Data Sheet TRANSPARENT OPERATION (44-LEAD VERSIONS (JLCC AND PLCC) AND 44-TERMINAL VERSION (LCC)) LS DATA INPUT/ OUTPUT BITS Transparent operation allows data from the inputs of the AD664 to be transferred into the DAC registers without the intervening step of being latched into the first rank of latches. Two modes of transparent operation exist, the partially transparent mode and a fully transparent mode. In the partially transparent mode, one of the DACs is transparent, while the remaining three continue to use the data latched into their respective input registers. Both modes require a 12-bit wide input word. Fully transparent operation is a simultaneous load of data from Figure 15, in which replacing LS with TR causes all four DACs to be loaded at once. The fully transparent mode is achieved by asserting lows on QS0, QS1, QS2, TR, and CS while keeping LS high, in addition to MS and RD. Figure 25 illustrates the necessary timing relationships. Fully transparent operation also works with TR tied low (enabled). DATA VALID tDS tDH QS1, QS2, AND QS3 tQS tQH tTW TR tCH 10590-023 tTS CS Figure 25. Fully Transparent Mode Partially transparent operation is preloading the first rank in Figure 16 without requiring the additional CS pulse from Figure 17. The partially transparent mode is achieved by setting CS, QS0, QS1, QS2, LS, and TR low while keeping RD and MS high. The address of the transparent DAC is asserted on DS0 and DS1. Figure 26 illustrates the necessary timing relationships. Partially transparent operation also works with TR tied low (enabled). DATA INPUT/ OUTPUT BITS DATA VALID tDS tDH ADDRESS QS0, QS1, QS2 DS0, DS1 ADDRESS VALID tAS tAH TR tW tTH 10590-024 tTS CS Figure 26. Partially Transparent Table 12. Fully Transparent Mode Timing Parameter Data Transition to CS Falling Edge (tDS) QS Falling Edge to CS Falling Edge (tQS) TR Falling Edge to CS Falling Edge (tTS1) TR Low Time (tTW) TR Rising Edge to CS Rising Edge (tCH) CS Rising Edge to Data Transition (tDH) CS Rising Edge to QS Rising Edge (tQH) 1 25°C Minimum (ns) 0 0 0 80 90 0 0 TMIN to TMAX Minimum (ns) 0 0 0 90 110 0 0 For tTS > 0, the width of TR must be increased by the same amount that tTS is greater than 0 ns. Table 13. Partially Transparent Mode Timing Parameter Data Transition to CS Falling Edge (tDS) Address Transition to CS Falling Edge (tAS) TR Falling Edge to CS Falling Edge (tTS) CS Low Time (tW) CS Rising Edge to Data Transition (tDH) CS Rising Edge to Address Transition (tAH) CS Rising Edge to TR Rising Edge (tTH) 25°C Minimum (ns) 0 0 0 90 15 15 15 Rev. E | Page 22 of 39 TMIN to TMAX Minimum (ns) 0 0 0 110 15 15 15 Data Sheet AD664 OUTPUT DATA Two types of outputs may be obtained from the internal data registers of the AD664 chip, mode select, and DAC input code data. Readback data may be in the same forms in which it is entered, namely, 4-bit, 8-bit, and 12-bit wide words (12 bits only for 28-lead versions). DAC DATA READBACK MODE DATA READBACK Mode data is read back in a similar fashion. By setting MS, QS0, QS1, RD, and CS low while setting TR and RST high, the mode select word is presented to the I/O port pins. Figure 28 and Table 15 show the timing diagram for a readback of the mode select data register. DAC input code readback data is obtained by setting the address of the DAC (DS0, DS1) and the quads (QS0, QS1, QS2) on the address pins and bringing the RD and CS pins low. The timing diagram for a DAC code readback operation appears in Figure 27 and Table 14. QS0, QS1 tAS tAH RD, MS tMS ADDRESS QS0, QS1, QS2 DS0, DS1 tMH CS DATA RD tRS HIGH Z tDV tRH DATA VALID HIGH Z tDF Figure 28. Mode Data Readback CS HIGH Z tDV OUTPUT DATA 0 HIGH Z tDF 10590-025 1 DATA INPUT/ OUTPUT BITS Figure 27. DAC Input Code Readback Table 14. DAC Input Code Readback Timing Parameter Address Transition to CS Falling Edge (tAS) RD Falling Edge to CS Falling Edge (tRS) CS Falling Edge to Data Transition (tDV) CS Rising Edge to Data Transition (tDF) CS Rising Edge to Address Transition (tAH) CS Rising Edge to RD Rising Edge (tRH) 25°C Minimum (ns) 0 0 150 60 0 0 TMIN to TMAX Minimum (ns) 0 0 180 75 0 0 Table 15. DAC Mode Readback Timing Parameter QS0, QS1 to CS Falling Edge (tAS) RD, MS Falling Edge to CS Falling Edge (tMS) CS Falling Edge to Data Transition (tDV) CS Rising Edge to Data Transition (tDF) CS Rising Edge to QS0, QS1 Rising Edge (tAH) CS Rising Edge to RD, MS Rising Edge (tMH) 25°C Minimum (ns) 0 0 150 60 0 0 Rev. E | Page 23 of 39 TMIN to TMAX Minimum (ns) 0 0 180 75 0 0 10590-026 tAH tAS AD664 Data Sheet tRW RST Readback timing is tested with the output loads shown in Figure 29. Figure 30. Asynchronous Reset Operation +5V 3kΩ OUTPUT PIN HIGH Z In the 28-lead versions of the AD664, the mode remains unchanged. The appropriate input code is rewritten to reset the output voltage to 0 V. As in the 44-lead versions (JLCC and PLCC) and the 44-terminal version (LCC), the previous input data is erased. OUTPUT PIN 3kΩ 100pF HIGH Z 0 100pF 1 At power-up, an AD664 may be activated in either the read or write modes. While at the device level this event does not produce any problems, at the system level, it may produce problems. Analog Devices recommends the addition of a simple power-on reset scheme to any system where the possibility of an unknown start-up state is a problem. The simplest version of this scheme is illustrated in Figure 31. +5V 10pF 0 HIGH Z OUTPUT PIN 3kΩ 1 10pF HIGH Z 10590-027 3kΩ OUTPUT PIN 10590-028 OUTPUT LOADS +5V Figure 29. Output Loads AD664 ASYNCHRONOUS RESET OPERATION 1 RST N RST 100nF Figure 31. Power-On Reset Figure 31 shows that the scheme is only appropriate for systems in which the RST is otherwise not used. To use the RST pin, an additional logic gate may be included to combine the power-on reset with the reset signal. Table 16. Asynchronous Reset Operation Timing Parameter Pulse Width (tRW) AD664 10590-029 The asynchronous reset signal shown in Figure 30 and Table 16 may be asserted at any time. A minimum pulse width (tRW) of 90 ns is required. The reset feature is designed to return all DAC outputs to 0 V, regardless of the mode or range selected. In the 44-lead versions (JLCC and PLCC) and the 44-terminal version (LCC), the modes are reset to UNI 10 V span (gain of 1), and the input codes are rewritten to be zeros. Previous DAC code and mode information is erased. 10kΩ 25°C Minimum (ns) 80 TMIN to TMAX Minimum (ns) 100 Rev. E | Page 24 of 39 Data Sheet AD664 INTERFACING THE AD664 TO MICROPROCESSORS The AD664 is easy to interface with a wide variety of popular microprocessors. Common architectures include processors with dedicated 8-bit data and address buses, an 8-bit bus over which data and address are multiplexed, an 8-bit data and 16-bit address partially muxed, and separate 16-bit data and address buses. of the AD664. The SC1 (IOS) and E pins are combined to produce an appropriate CS signal. This addressing scheme leaves the five most significant address bits and five I/O lines free for other tasks in the system. Figure 33 shows another way to interface an AD664 to the MC6801. Here, the six least significant address lines select AD664 features and registers. This interface configuration is a purely memory mapped scheme while the one illustrated in Figure 32 uses some memory mapping as well as some dedicated I/O pins. In Figure 33, two address lines and all eight I/O lines remain free for other system tasks. AD664 addressing is accomplished through either memory mapped or I/O techniques. In memory mapped schemes, the AD664 appears to the host microprocessor as random access memory (RAM). Standard memory addressing techniques are used to select the AD664. In the I/O schemes, the AD664 is treated as an external I/O device by the host. Dedicated I/O pins are used to address the AD664. Expansion of the scheme employed in Figure 32 results in that shown in Figure 34. Here, two AD664s are connected to an MC6801, providing a total of eight 12-bit, software programmable DACs. Again, the three LSBs of the address are used to select the on-chip registers of the AD664. The SC1 (IOS) and E pins, as well as a fourth address bit, are decoded to provide the appropriate CS signals. Four address and five I/O lines remain uncommitted. MC6801 INTERFACE Figure 32 to Figure 35 illustrate a few of the various methods that are used to connect the AD664 to the Motorola MC6801 microprocessor. In each of these cases, the MC6801 is intended to be configured in its expanded, nonmultiplexed mode of operation. In this mode, the MC6801 can address 256 bytes of external memory over 8-bit data (Port 3) and 8-bit address (Port 4) buses. Eight general-purpose I/O lines (Port 1) are also available. On-board RAM and read-only memory (ROM) provide program and data storage space. A slightly more sophisticated approach to system expansion is illustrated in Figure 35. Here, a 74LS138 (1-of-8 decoder) is used to address one of the eight AD664s connected to the MC6801. The three least significant address bits are used to select on-chip register and DAC. The next three address bits are used to select the appropriate AD664. The SC1 (IOS) and E pins gate the 74LS138 output. +5V FREE FOR OTHER INPUT/OUTPUT TASKS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 E VSS SC1 XTAL1 SC2 EXTAL2 P30 NMI P31 IRQ1 P32 RESET VCC P33 P34 P20 P35 P21 P36 P22 P23 MC6801 P37 P40 P24 P41 P10 P42 P11 P43 P12 P44 P13 P45 P14 P46 P15 P16 P47 P17 VCC STANDBY E 40 IOS 39 R/W 38 D0 37 36 35 34 33 32 31 D7 30 A0 29 28 27 26 25 24 23 A7 22 21 FREE FOR OTHER TASKS DS1 DS0 QS0 QS1 QS2 CS AD664 RD LS +5V Figure 32. Simple AD664 to MC6801 Interface Rev. E | Page 25 of 39 TR MS RST 10590-030 GND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 In Figure 32, the three least significant address bits (P40, P41, and P42) are employed to select the appropriate on-chip addresses for the various input registers of the AD664. Three I/O lines (P17, P16, and P15) are used to select various operating features AD664 Data Sheet FREE FOR OTHER INPUT/OUTPUT TASKS E VSS SC1 XTAL1 SC2 EXTAL2 P30 NMI P31 IRQ1 P32 RESET VCC P33 P34 P20 P35 P21 P36 P22 P23 MC6801 P37 P40 P24 P41 P10 P42 P11 P43 P12 P44 P13 P45 P14 P46 P15 P16 P47 P17 VCC STANDBY 40 IOS 39 R/W 38 D0 37 36 35 34 33 32 31 D7 30 A0 29 28 27 26 25 24 23 A7 22 21 DS1 DS0 QS0 QS1 QS2 CS AD664 RD LS TR MS RST +5V 10590-031 +5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 GND FREE FOR OTHER TASKS Figure 33. Alternate AD664 to MC6801 Interface TO CS 2 FREE FOR OTHER INPUT/OUTPUT TASKS E VSS SC1 XTAL1 SC2 EXTAL2 P30 NMI P31 IRQ1 P32 RESET VCC P33 P34 P20 P35 P21 P36 P22 P23 MC6801 P37 P40 P24 P41 P10 P42 P11 P43 P12 P44 P13 P45 P14 P46 P15 P47 P16 VCC P17 STANDBY 40 IOS 39 R/W 38 D0 37 36 35 34 33 32 31 D7 30 A0 29 28 27 26 25 24 23 A7 22 21 FREE FOR OTHER TASKS DS1 DS0 QS0 QS1 QS2 CS AD664 1 RD CS 1 LS TR MS RST +5V DS1 DS0 QS0 QS1 QS2 CS CS 2 AD664 2 RD LS TR MS RST +5V 10590-032 +5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 GND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 TO CS 1 Figure 34. Interfacing Two AD664s to an MC6801 Rev. E | Page 26 of 39 AD664 +5V FREE FOR OTHER INPUT/OUTPUT TASKS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 E VSS SC1 XTAL1 SC2 EXTAL2 P30 NMI P31 IRQ1 P32 RESET VCC P33 P34 P20 P35 P21 P36 P22 P23 MC6801 P37 P40 P24 P41 P10 P42 P11 P43 P12 P44 P13 P45 P14 P46 P15 P47 P16 VCC P17 STANDBY E 40 IOS 39 R/W 38 D0 37 36 35 34 33 32 31 D7 30 A0 29 28 27 26 25 24 23 A7 22 21 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 GND DS1 DS0 QS0 QS1 QS2 FREE FOR OTHER TASKS AD664 1 CS RD LS TR MS RST +5V DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 Data Sheet DS1 DS0 QS0 QS1 QS2 CS AD664 2 RD LS TR MS RST +5V 74LS138 A0 VCC 16 2 A1 O0 15 3 A2 O1 14 CS 2 4 E1 O2 13 CS 3 5 E2 O3 12 CS 4 6 E3 O4 11 CS 5 7 O7 O5 10 CS 6 8 GND O6 9 CS 7 +5V CS 1 10590-033 GND 1 Figure 35. Interfacing Eight AD664s to an MC6801 and a Motorola 74LS138 The schemes in Figure 32 to Figure 35 illustrate some of the trade-offs that a designer may make when configuring a system. For example, the designer may use I/O lines instead of address bits or vice versa. This decision may be influenced by other I/O tasks or system expansion requirements. The designer can also choose to implement only a subset of the features available. Perhaps the RST pin is not really needed. Tying that input pin to VLL (+5V) frees up another I/O or address bit. The same consideration applies to mode select. In all of these cases, TR is shown tied to VLL (+5V), because the MC6801 cannot provide the 12-bit wide input word required for the transparent mode. In situations where transparent operation is not required, and mode select is also not needed, the designer may consider specifying the dual in-line package (DIP) version of the device (either the UNI or the BIP version). Each of the schemes illustrated in Figure 32 to Figure 35 operates with an MC6801 at clock rates up to and including 1.5 MHz. Similar schemes are derived for other 8-bit microprocessors and microcontrollers such as the 8051/8086/8088/6502. One such scheme developed for the 8051 and AD664 is illustrated in Figure 36. 8051 INTERFACE Figure 36 shows the AD664 combined with an 8051 microcontroller chip. Three LSB addresses provide the quad and DAC select signals. Control signals from Port 1 select various operating modes such as readback, mode select, and reset as well as providing the LS signal. Read and write signals from the 8051 are decoded to provide the CS signal. Rev. E | Page 27 of 39 AD664 Data Sheet 8 38 9 37 P0.4 DB11 39 8 DB4 P0.2 P0.3 40 P0.1 NC VCC 41 P1.0 1 P0.0 P1.1 2 42 P1.2 3 43 P1.3 4 44 P1.4 5 7 P0.5 DB3 P0.6 P0.7 36 35 EA DB6 34 NC DS1 P3.1 13 33 ALE DS0 P3.2 14 32 PSEN QS0, QS1 P3.3 15 31 P2.7 P3.4 16 30 P2.6 P3.5 17 29 P2.5 AD664 RST CS QS2 P2.4 28 +5V 10590-034 P2.3 27 25 26 P2.2 P2.1 24 22 XTAL2 20 XTAL1 21 VSS 18 19 P3.7 P3.6 NC 23 P2.0 8051 NC 12 MS RST 10 P3.0 11 LS P1.7 4 TR P1.6 8 RD P1.5 6 +5V Figure 36. AD664 to 8051 Interface IBM PC INTERFACE Figure 37 illustrates a simple interface between an IBM® PC and an AD664. The three least significant address bits are used to select the quad and DAC. The next two address bits are used for LS and MS. In this scheme, a 12-bit input word requires two load cycles, an 8-bit word, and a 4-bit word. Another write is required to transfer the word or words previously written to the second rank. A 12-bit wide word again requires at least two read cycles, namely, one for the eight MSBs and four for the LSBs. The page select signal produces a CS strobe for any address from 300 hexadecimal to 31F hexadecimal. Rev. E | Page 28 of 39 Data Sheet AD664 D0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 D7 A2 DS1 A1 DS0 QS0 QS1 A0 AD664 QS2 +12V VCC –12V VEE +5V RST MS TR LS DCOM CS AD588 VREF RD VLOGIC ACOM A3 A4 IOR IOW A5 A6 A7 PAGE SELECT A8 A9 AEN 10590-035 GND RESET DRIVE Figure 37. AD664 to IBM PC Interface Table 17 details the memory locations and addresses used by this interface. Table 17. IBM PC Memory Map Hexadecimal 300 301 302 303 304 305 306 307 308 3091 30A 30B1 30C 30D1 30E 30F1 310 311 312 313 314 315 A9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 Rev. E | Page 29 of 39 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Register Selected Illegal address Mode select, first rank Illegal address Mode select, first rank Illegal address Mode select, first rank Illegal address Mode select, first rank Mode select, second rank Mode select, second rank Mode select, second rank Mode select, second rank Mode select, second rank Mode select, second rank Mode select, second rank Mode select, second rank DAC A, 4 LSBs, first rank DAC A, 8 MSBs, first rank DAC B, 4 LSBs, first rank DAC B, 8 MSBs, first rank DAC C, 4 LSBs, first rank DAC C, 8 MSBs, first rank AD664 Hexadecimal 316 317 3181 3191 31A1 31B1 31C1 31D1 31E1 31F1 1 Data Sheet A9 1 1 1 1 1 1 1 1 1 1 A8 1 1 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 A4 1 1 1 1 1 1 1 1 1 1 A3 0 0 1 1 1 1 1 1 1 1 A2 1 1 0 0 0 0 1 1 1 1 A1 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 Register Selected DAC D, 4 LSBs, first rank DAC D, 8 MSBs, first rank Second rank Second rank Second rank Second rank Second rank Second rank Second rank Second rank Registers are readable. The following IBM PC basic routine produces four output voltage ramps from one AD664. Line numbers 10 through 70 define the hardware addresses for the first and second ranks of DAC registers as well as the first and second ranks of the mode select register. Program variables are initialized in line numbers 110 through 130. Line number 170 writes 0s out to the first rank and, then, the second rank of the mode select register. Line numbers 200 through 320 calculate output voltages. Finally, line numbers 410 through 450 update the first, then the second ranks of the DAC input registers. Hardware registers may be read with the INP instruction. For example, the contents of the DAC A register may be accessed with the following command: Line#A = INP(DACA). 5 REM----AD664 LISSAJOUS PATTERNS---- 10 REM ---ASSIGN HARDWARE ADDRESSES--- 20 DACA = 785 30 DACB = 787 40 DACC = 789 50 DACD = 791 60 DAC2ND = 792 70 MODE1 = 769: MODE2 = 776 80 REM 90 REM 100 REM ---INITIALIZE VARIABLES--- 110 X = 0: Y1 = 128: Y2 = 64: Y3 = 32 120 CX = 1: CY1 = 1: CY2 = −1: CY3= 1 130 FX = 9: FY1 = 5: FY2 = 13: FY3 = 15 140 REM 150 REM 160 REM ---INITIALIZE MODES AND GAINS--- 170 OUT MODE1,0: OUT MODE2,0 180 REM 190 REM 200 REM ---CALCULATE VARIABLES--- 210 X = X + FX*CX 220 Y1 = Y1 + FY1*CY1 230 Y2 = Y2 + FY2*CY2 240 Y3 = Y3 + FY3*CY3 250 IF X > 255 THEN X = 255: CX = −1: GOTO 270 260 IF X < 0 THEN X = 0: CX = 1 270 IF Y1 > 255 THEN Y1 = 255: CY1 = −1: GOTO 290 280 IF Y1 < 0 THEN Y1 = 0: CY1 = 1 290 IF Y2 > 255 THEN Y2 = 255: CY2 = −1 GOTO 310 300 IF Y2 < 0 THEN Y2 = 0: CY2 = −1 310 IF Y3 > 255 THEN Y3 = 255: CY3 = −1: GOTO 400 320 IF Y3 < 0 THEN Y3 = 0: CY3 = 1 330 REM 340 REM 400 REM ---SEND DAC DATA--- 410 OUT DACA,X 420 OUT DACB,Yl 430 OUT DACC,Y2 440 OUT DACD,Y3 450 OUT DAC2ND,0 500 REM 510 REM 520 REM ---LOOP BACK--- 530 GOTO 210 Rev. E | Page 30 of 39 Data Sheet AD664 SIMPLE AD664 TO MC68000 INTERFACE This scheme is converted to write right justified data by connecting the data inputs to data bits DB0 through DB11. Other options include controlling the QS0, QS1, and QS2 pins with UDS and LDS to provide a way to write 8-bit input and read 8-bit output words. Figure 38 shows an AD664 connected to the NXP MC68000. In this memory mapped I/O scheme, the left justified data is written in one 12-bit input word. Four address bits are used to perform the on-chip DAC selection as well as the various operating features. The R/W signal controls the RD function and system reset controls RST. ADDRESS BUS VCC (2) GND (2) CLK DATA BUS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 MC68000 MICROPROCESSOR AS DS1 DS0 QS0 QS1 QS2 R/W UDS LDS CS AD664 RD LS TR MS RST DTACK VMA BG VPA BGACK BERR IPL0 RESET IPL1 HALT IPL1 +5V 270Ω BR 570pF 270Ω 10590-036 FC0 FC1 FC2 E 200pF Figure 38. AD664 to MC68000 Interface Rev. E | Page 31 of 39 AD664 Data Sheet APPLICATIONS INFORMATION or readback as the tester has pins. The AD664 is a particularly appropriate choice for a large scale system because the low power requirements (under 500 mW) ease power supply and cooling requirements. Analog ground currents of 600 μA or less make the ground current management task simpler. All DACs are driven from the same system reference and tracks over time and temperature. Finally, the small board area required by the AD664 (and AD96687) allows a high functional density. TESTER PER PIN AUTOMATIC TEST EQUIPMENT (ATE) ARCHITECTURE Figure 39 shows the AD664 used in a single channel of a digital test system. In this scheme, the AD664 supplies four individual output voltages. Two output voltages are provided to the VHIGH and VLOW inputs of the pin driver IC to set the digital output levels. Two others are routed to the inputs of the AD96687 dual comparator to supply reference levels of the readback features. This approach is replicated to give as many channels of stimulus DC PARAMETRICS D STORED DATA AND INHIBIT PATTERN DELAY PERIOD GENERATION AND DELAY TIMING VH INH 2 FORMATTER VL WIDTH INH PIN DRIVER IC 50Ω DUT DELAY 2 WIDTH STORED COMPARE DATA AND DON’T CARE DATA D 2 EXP DATA MASK COMPARE REGISTER 2 VH VL AD96687 10590-037 SYSTEM BUS AD664 Figure 39. AD664 in Tester per Pin Architecture Rev. E | Page 32 of 39 Data Sheet AD664 Figure 40 is a block diagram of the control section of a microprocessor controlled x-axis and y-axis pen plotter. In this conceptual exercise, two of the DACs are used for the X-channel drive and two are used for the Y-channel drive. Each DAC channel provides either the coarse or fine movement control for its respective channel. This approach offers increased resolution over some other approaches. A designer can take advantage of the reset feature of the AD664 in the following manner. If the system is designed such that the home position of the pen (or galvanometer, beam, head, or similar mechanism) results when the outputs of all of the DACs are at zero, no system software is required to home the pen. A simple reset signal is sufficient. the object. Conversely, a C size drawing created with gains of 2 is reduced to an A size simply by changing the gains to 1 and redrawing. The same principal applies for conversion from B size to D size or D size to B size. The multiplying capability of the AD664 provides another scaling option. Changing the reference voltage provides a proportional change in drawing size. Inverting the reference voltage inverts the drawing. Swapping digital input data from the X-channel to the Y-channel rotates the drawing 90°. VREF X COARSE X DRIVE Similarly, the transparent feature is used to the same end. One code is sent to all DACs at the same time to send the pen to the home position. Of course, this requires some software in which the previous example requires only a single reset strobe signal. Drawing scaling is achieved by taking advantage of the software programmable gain settings of the AD664. If, for example, an A size drawing is created with gain settings of 1, a C size drawing is created by simply resetting all DAC gains to 2 and redrawing Rev. E | Page 33 of 39 ÷N X FINE COARSE Y DRIVE ÷N FINE TR RST TRANS ADDRESS DATA RESET Figure 40. X-Axis and Y-Axis Plotter Block Diagram 10590-038 X-AXIS AND Y-AXIS PLOTTERS AD664 Data Sheet DIE INFORMATION VCC AGND AGND LS RD VLL VLL 6 5 4 3 2 1 39 38 DB11 DB10 37 36 DB9 35 34 DB8 8 33 DB7 VOB 9 32 DB6 RFB 10 31 DB5 VREFIN 11 RFC 12 30 DB4 VOC 13 VOD 14 29 DB3 RFD 15 28 DB2 RFA 7 VOA CS 16 27 17 18 19 20 21 22 23 24 25 DS0 DS1 DGND RST QS0 QS1 QS2 TR MS DB1 26 DB0 (LSB) Figure 41. Bond Pad Diagram Table 18. Bond Pad Coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Mnemonic RD LS AGND AGND VCC VEE RFA VOA VOB RFB VREFIN RFC VOC VOD RFD CS DS0 DS1 DGND RST QS0 Pad Coordinates X (μm) Y (μm) −98 +3403 −896 +3403 −1869 +3448 −2384 +3448 −2998 +3448 −3452 +2990 −3452 +2396 −3452 +1809 −3452 +1208 −3452 +611 −3452 −1 −3452 −596 −3452 −1190 −3452 −1808 −3452 −2385 −3405 −2988 −3015 −3403 −2421 −3403 −1825 −3456 −1222 −3403 −617 −3403 Description Readback Pin (Active Low). Latch Select Pin (Active Low). Analog Ground Pin. Analog Ground Pin. Positive Analog Supply Connection. Negative Analog Supply Connection. Feedback Connection for DAC A. Analog Output Voltage from DAC A. Analog Output Voltage from DAC B. Feedback Connection for DAC B. Reference Input Voltage Pin. Feedback Connection for DAC C. Analog Output Voltage from DAC C. Analog Output Voltage from DAC D. Feedback Connection for DAC D. Chip Select Pin (Active Low). DAC Address Data 0. DAC Address Data 1. Digital Ground. Reset Pin (Active Low). 4-Bit Nibble Data. Rev. E | Page 34 of 39 10590-043 VEE Data Sheet Pad No. 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 AD664 Mnemonic QS1 QS2 TR MS DB0 (LSB) DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 VLL VLL Pad Coordinates X (µm) Y (µm) −23 −3403 +574 −3403 +1181 −3403 +1775 −3403 +2294 −3321 +3463 −3321 +3463 −2633 +3463 −1922 +3463 −1195 +3463 −474 3463 488 3463 1202 3463 1925 3463 2636 3463 3324 2301 3324 1780 3448 1330 3448 Description 8-Bit Nibble Data. 12-Bit Nibble Data. Transfer Register Pin (Active Low). Mode Select Pin (Active Low). Data Input/Output. Data Input/Output. Data Input/Output. Data Input/Output. Data Input/Output. Data Input/Output. Data Input/Output. Data Input/Output. Data Input/Output. Data Input/Output. Data Input/Output. Data Input/Outputs. DB11 is MSB. Digital Supply. Digital Supply. Rev. E | Page 35 of 39 AD664 Data Sheet OUTLINE DIMENSIONS 0.005 (0.13) MIN 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.580 (12.73) PIN 1 1 4 1.490 (37.85) MAX 0.085 (2.16) MAX 0.200 (5.08) 0.125 (3.18) 0.620 (15.75) 0.590 (14.99) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.026 (0.66) 0.014 (0.36) 0.100 (2.54) 0.070 (1.78) 0.030 (0.76) 0.018 (0.46) 0.008 (0.20) SEATING PLANE CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 42. 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-28-2) Dimensions shown in inches and (millimeters) 0.055 (1.40) 0.045 (1.14) 0.075 (1.91) REF 6 40 39 0.662 (16.82) SQ 0.640 (16.27) 0.050 (1.27) BSC 44 1 7 0.028 (0.71) 0.022 (0.56) BOTTOM VIEW 29 28 0.020 (0.51) REF  45° 17 18 0.040 (1.02) REF  45° 3 PLACES CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 43. 44-Terminal Ceramic Leadless Chip Carrier [LCC] (E-44-1) Dimensions shown in inches and (millimeters) Rev. E | Page 36 of 39 022106-A 0.100 (2.54) 0.064 (1.63) Data Sheet AD664 0.662 (16.82) SQ 0.628 (15.95) PIN 1 INDICATOR 40 6 40 39 7 0.020 (0.51) REF × 45° 0.050 (1.27) BSC 6 39 7 0.500 (12.70) SQ 0.492 (12.50) 17 29 28 TOP VIEW BOTTOM VIEW 0.040 (1.02) REF × 45° 0.700 (17.78) SQ 0.680 (17.27) 0.078 (1.98) 0.054 (1.37) (3 PLACES) 0.135 (3.43) 0.100 (2.54) SIDE VIEW 0.032 (0.81) 0.020 (0.51) 0.023 (0.58) 0.013 (0.33) 0.650 (16.51) 0.610 (15.49) 11-16-2018-B 0.025 (0.64) MIN 17 29 28 18 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 44. 44-Lead Ceramic Leaded Chip Carrier, J-Formed Leads [JLCC] (J-44) Dimensions shown in inches and (millimeters) 1.565 (39.75) 1.380 (35.05) 28 15 0.580 (14.73) 0.485 (12.31) 1 14 0.625 (15.88) 0.600 (15.24) 0.100 (2.54) BSC 0.250 (6.35) MAX 0.195 (4.95) 0.125 (3.17) 0.015 (0.38) GAUGE PLANE 0.015 (0.38) MIN 0.200 (5.08) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.014 (0.36) 0.005 (0.13) MIN 0.700 (17.78) MAX 0.015 (0.38) 0.008 (0.20) COMPLIANT TO JEDEC STANDARDS MS-011 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS. Figure 45. 28-Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-28-2) Dimensions shown in inches and (millimeters) Rev. E | Page 37 of 39 071006-A 0.070 (1.78) 0.050 (1.27) AD664 Data Sheet 0.180 (4.57) 0.165 (4.19) 0.048 (1.22) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 6 0.048 (1.22) 0.042 (1.07) 0.020 (0.51) MIN 40 39 7 0.021 (0.53) 0.013 (0.33) PIN 1 IDENTIFIER 0.630 (16.00) 0.590 (14.99) 0.050 (1.27) BSC TOP VIEW (PINS DOWN) 17 (PINS UP) 0.032 (0.81) 0.026 (0.66) 29 28 18 BOTTOM VIEW 0.656 (16.66) SQ 0.650 (16.51) 0.045 (1.14) R 0.025 (0.64) 0.120 (3.05) 0.090 (2.29) 0.695 (17.65) SQ 0.685 (17.40) COMPLIANT TO JEDEC STANDARDS MO-047-AC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 46. 44-Lead Plastic Leaded Chip Carrier [PLCC] (P-44) Dimensions shown in inches and (millimeters) 7.366 SQ 0.350 0.090 × 0.090 (Pads 1-39) 6 5 4 3 2 1 39 37 38 36 35 7 34 8 33 9 32 10 31 11 30 12 13 14 29 15 28 17 27 18 19 20 21 22 23 24 25 26 TOP VIEW SIDE VIEW (CIRCUIT SIDE) 10-25-2018-A 16 Figure 47. 39-Pad Bare Die [Chip] (C-39-2) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 5962-8871901MXA 5962-8871902MXA 5962-8871903MYA AD664AD-BIP AD664AD-UNI AD664AJ AD664BD-BIP AD664BD-UNI Temperature Range −55°C to +125°C −55°C to +125°C −55°C to +125°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 44-Terminal Ceramic Leadless Chip Carrier [LCC] 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 44-Lead Ceramic Leaded Chip Carrier, J-Formed Leads [JLCC] 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] Rev. E | Page 38 of 39 Package Option D-28-2 D-28-2 E-44-1 D-28-2 D-28-2 J-44 D-28-2 D-28-2 Data Sheet Model1, 2 AD664BE AD664BJ AD664JNZ-BIP AD664JNZ-UNI AD664JPZ AD664KNZ-BIP AD664KNZ-UNI AD664KPZ AD664SD-BIP AD664SD-BIP/883B AD664SD-UNI/883B AD664TD-BIP AD664TD-BIP/883B AD664TD-UNI/883B AD664TE/883B AD664TJ/883B AD664CHIPS 1 2 AD664 Temperature Range −40°C to +85°C −40°C to +85°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C Package Description 44-Terminal Ceramic Leadless Chip Carrier [LCC] 44-Lead Ceramic Leaded Chip Carrier, J-Formed Leads [JLCC] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Dual In-Line Package [PDIP] 44-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Dual In-Line Package [PDIP] 44-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] 44-Terminal Ceramic Leadless Chip Carrier [LCC] 44-Lead Ceramic Leaded Chip Carrier, J-Formed Leads [JLCC] 39-Pad Bare Die [CHIP] Z = RoHS Compliant Part. The AD664AJ and AD664BE are also RoHS compliant parts. ©2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10590-0-11/18(E) Rev. E | Page 39 of 39 Package Option E-44-1 J-44 N-28-2 N-28-2 P-44 N-28-2 N-28-2 P-44 D-28-2 D-28-2 D-28-2 D-28-2 D-28-2 D-28-2 E-44-1 J-44 C-39-2
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AD664KNZ-BIP
    •  国内价格
    • 1000+1411.30000

    库存:2000