135 MHz BW IF Diversity Receiver
AD6679
Data Sheet
FEATURES
APPLICATIONS
Parallel LVDS (DDR) outputs
In-band SFDR = 82 dBFS at 340 MHz (500 MSPS)
In-band SNR = 67.8 dBFS at 340 MHz (500 MSPS)
1.1 W total power per channel at 500 MSPS (default settings)
Noise density = −153 dBFS/Hz at 500 MSPS
1.25 V, 2.50 V, and 3.3 V dc supply operation
Flexible input range
1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient automatic gain control
(AGC) implementation
Noise shaping requantizer (NSR) option for main receiver
function
Variable dynamic range (VDR) option for digital
predistortion (DPD) function
2 integrated wideband digital processors per channel
12-bit numerically controlled oscillator (NCO), up to
4 cascaded half-band filters
Differential clock inputs
Integer clock divide by 1, 2, 4, or 8
Energy saving power-down modes
Small signal dither
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
GENERAL DESCRIPTION
The AD6679 is a 135 MHz bandwidth mixed-signal intermediate
frequency (IF) receiver. It consists of two, 14-bit, 500 MSPS
analog-to-digital converters (ADCs) and various digital signal
processing blocks consisting of four wideband DDCs, an NSR,
and VDR monitoring. It has an on-chip buffer and a sample-andhold circuit designed for low power, small size, and ease of use.
This product is designed to support communications applications
capable of sampling wide bandwidth analog signals of up to 2 GHz.
The AD6679 is optimized for wide input bandwidth, high sampling
rates, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
FUNCTIONAL BLOCK DIAGRAM
AVDD1
(1.25V)
AVDD2
(2.50V)
AVDD3
(3.3V)
DVDD
(1.25V)
DRVDD
(1.25V)
SPIVDD
(1.22V TO 3.4V)
BUFFER
VIN+A
SIGNAL PROCESSING
ADC
VIN–A
DIGITAL DOWNCONVERSION
(×4)
FD_A
SIGNAL
MONITOR
FAST
DETECT
FD_B
DATA
ROUTER
MUX
16
LVDS
OUTPUT
STAGING
NOISE SHAPING
REQUANTIZER
(×2)
LVDS
OUTPUTS
V_1P0
BUFFER
VARIABLE
DYNAMIC RANGE
(×2)
VIN+B
ADC
D0±
D1±
D2±
D3±
D4±
D5±
D6±
D7±
D8±
D9±
D10±
D11±
D12±
D13±
DCO±
STATUS±
VIN–B
CLK–
FAST
DETECT
CLOCK
GENERATION
AND ADJUST
CLK+
AD6679
÷2
SPI CONTROL
÷4
SIGNAL
MONITOR
PDWN/STBY
AGND
SYNC±
SDIO
SCLK
CSB
DGND
DRGND
13059-001
÷8
Figure 1.
Rev. B
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AD6679
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ................................................................... 46
Applications ....................................................................................... 1
DDC NCO Plus Mixer Loss and SFDR ................................... 47
General Description ......................................................................... 1
Numerically Controlled Oscillator .......................................... 47
Functional Block Diagram .............................................................. 1
FIR Filters ........................................................................................ 49
Revision History ............................................................................... 3
Overview ..................................................................................... 49
Product Highlights ........................................................................... 4
Half-Band Filters ........................................................................ 49
Specifications..................................................................................... 5
DDC Gain Stage ......................................................................... 51
DC Specifications ......................................................................... 5
DDC Complex to Real Conversion ......................................... 51
AC Specifications.......................................................................... 6
DDC Example Configurations ................................................. 52
Digital Specifications ................................................................... 7
Noise Shaping Requantizer (NSR) ............................................... 56
Switching Specifications .............................................................. 8
Decimating Half-Band Filter .................................................... 56
Timing Specifications .................................................................. 9
NSR Overview ............................................................................ 56
Absolute Maximum Ratings .......................................................... 18
Variable Dynamic Range (VDR) .................................................. 59
Thermal Characteristics ............................................................ 18
VDR Real Mode.......................................................................... 60
ESD Caution ................................................................................ 18
VDR Complex Mode ................................................................. 60
Pin Configurations and Function Descriptions ......................... 19
Digital Outputs ............................................................................... 62
Typical Performance Characteristics ........................................... 25
Timing.......................................................................................... 62
Equivalent Circuits ......................................................................... 28
Data Clock Output ..................................................................... 62
Theory of Operation ...................................................................... 30
ADC Overrange .......................................................................... 62
ADC Architecture ...................................................................... 30
Multichip Synchronization............................................................ 64
Analog Input Considerations.................................................... 30
SYNC± Setup and Hold Window Monitor ............................. 65
Voltage Reference ....................................................................... 32
Test Modes ....................................................................................... 67
Clock Input Considerations ...................................................... 33
ADC Test Modes ........................................................................ 67
Power-Down/Standby Mode..................................................... 35
Serial Port Interface (SPI) .............................................................. 68
Temperature Diode .................................................................... 35
Configuration Using the SPI ..................................................... 68
Virtual Converter Mapping ........................................................... 36
Hardware Interface ..................................................................... 68
ADC Overrange and Fast Detect .................................................. 38
SPI Accessible Features .............................................................. 68
ADC Overrange (OR) ................................................................ 38
Memory Map .................................................................................. 69
Fast Threshold Detection (FD_A and FD_B) ........................ 38
Reading the Memory Map Register Table............................... 69
Signal Monitor ................................................................................ 39
Memory Map Register Table ..................................................... 70
Digital Downconverter (DDC) ..................................................... 40
Applications Information .............................................................. 80
DDC I/Q Input Selection .......................................................... 40
Power Supply Recommendations............................................. 80
DDC I/Q Output Selection ....................................................... 40
Outline Dimensions ....................................................................... 81
DDC General Description ........................................................ 40
Ordering Guide .......................................................................... 81
Frequency Translation ................................................................... 46
Rev. B | Page 2 of 81
Data Sheet
AD6679
REVISION HISTORY
4/16—Rev. A to Rev. B
Changes to Table 4 ............................................................................ 8
Changes to Table 5 and Figure 3 ..................................................... 9
Changes to Figure 4 Caption .........................................................10
Changes to Figure 5 Caption .........................................................11
Changes to Figure 6 Caption .........................................................12
Changes to Figure 7 Caption .........................................................13
Changes to Figure 8 Caption .........................................................14
Changes to Figure 10 ......................................................................16
Changes to Table 6 ..........................................................................18
Changes to Input Clock Divider Section .....................................34
Added Virtual Converter Mapping Section and Table 12;
Renumbered Sequentially ..............................................................36
Added Figure 60; Renumbered Sequentially ...............................37
Changes to Table 35 ........................................................................62
Changes to Datapath Soft Reset Section ......................................69
Changes to Table 41 ........................................................................70
9/15—Rev. 0 to Rev. A
Changes to General Description Section ....................................... 3
Changes to Figure 12 ...................................................................... 18
Changes to Figure 13 ...................................................................... 20
Changes to Figure 14 ...................................................................... 22
Changes to ADC Test Modes......................................................... 63
5/15—Revision 0: Initial Version
Rev. B | Page 3 of 81
AD6679
Data Sheet
The analog input and clock signals are differential inputs. The
ADC data outputs are internally connected to four DDCs
through a crossbar mux. Each DDC consists of up to five
cascaded signal processing stages: a 12-bit frequency translator
(NCO) and up to four half-band decimation filters.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows improved SNR performance in
a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes, selectable via the
serial port interface (SPI). With the NSR feature enabled, the
outputs of the ADCs are processed such that the AD6679 supports
enhanced SNR performance within a limited portion of the
Nyquist bandwidth while maintaining a 9-bit output resolution.
incoming signal power using the fast detect control bits in
Register 0x245 of the ADC. If the input signal level exceeds the
programmable threshold, the fast detect indicator goes high.
Because this threshold indicator has low latency, the user can
quickly reduce the system gain to avoid an overrange condition
at the ADC input. In addition to the fast detect outputs, the
AD6679 also offers signal monitoring capability. The signal
monitoring block provides additional information about the
signal that the ADC digitized.
The output data is routed directly to the one external
14-bit LVDS output port, supporting double data rate (DDR)
formatting. An external data clock and a clock status bit are offered
for data capture flexibility.
Each ADC output is also connected internally to a VDR block.
This optional mode allows full dynamic range for defined input
signals. Inputs that are within a defined mask (based on DPD
applications) pass unaltered. Inputs that violate this defined
mask result in the reduction of the output resolution.
The AD6679 has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using a 1.8 V capable 3-wire SPI.
With VDR, the dynamic range of the observation receiver is
determined by a defined input frequency mask. For signals
falling within the mask, the outputs are presented at the
maximum resolution allowed. For signals exceeding defined
power levels within this frequency mask, the output resolution
is truncated. This mask is based on DPD applications and
supports tunable real IF sampling, and zero IF or complex IF
receive architectures.
PRODUCT HIGHLIGHTS
Operation of the AD6679 between the DDC, NSR, and VDR
modes is selectable via SPI-programmable profiles.
The AD6679 is available in a Pb-free, 196-ball BGA_ED, and is
specified over the −40°C to +85°C industrial temperature range.
1.
2.
3.
4.
5.
In addition to the DDC blocks, the AD6679 has several functions
that simplify the AGC function in a communications receiver.
The programmable threshold detector allows monitoring of the
6.
7.
Rev. B | Page 4 of 81
Wide full power bandwidth IF sampling of signals up to
2 GHz.
Buffered inputs with programmable input termination
eases filter design and implementation.
Four integrated wideband decimation filters and NCO
blocks support multiband receivers.
Flexible SPI controls various product features and
functions to meet specific system requirements.
Programmable fast overrange detection and signal
monitoring.
Programmable fast overrange detection.
12 mm × 12 mm, 196-ball BGA_ED.
Data Sheet
AD6679
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate, 1.0 V internal reference (VREF), AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Voltage
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUTS
Differential Input Voltage Range (Internal VREF = 1.0 V)
Common-Mode Voltage (VCM)
Differential Input Capacitance1
Analog Full Power Bandwidth
POWER SUPPLY
AVDD1
AVDD2
AVDD3
DVDD
DRVDD
SPIVDD
IAVDD1
IAVDD2
IAVDD32
IDVDD (Default SPI—NSR Mode)
IDVDD (VDR Mode)
IDRVDD3
ISPIVDD
POWER CONSUMPTION
Total Power Dissipation
Default SPI—NSR Mode3
VDR Mode3
Power-Down Dissipation
Standby4
Temperature
Full
Full
Full
Full
Full
Full
Full
Min
14
−0.3
−6.5
−0.6
−4.5
Typ
Max
Guaranteed
0
+0.3
0
0.3
0
+6.5
0
5.0
±0.5
+0.7
±2.5
+5.0
Unit
Bits
% FSR
% FSR
% FSR
% FSR
LSB
LSB
Full
Full
±3
−39
ppm/°C
ppm/°C
Full
1.0
V
25°C
2.04
LSB rms
Full
Full
Full
Full
1.46
2.06
2.05
1.5
2
2.06
V p-p
V
pF
GHz
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.22
2.44
3.2
1.22
1.22
1.22
1.25
2.50
3.3
1.25
1.25
1.8
464
396
89
141
117
110
5
1.28
2.56
3.4
1.28
1.28
3.4
503
455
100
164
138
123
6
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
2.2
2.16
0.71
1.4
2.37
2.34
W
W
W
W
Full
Full
Full
Full
1
Differential capacitance is measured between the VIN+x and VIN−x pins (x = A, B).
AVDD3 current changes based on the Buffer Control 1 setting (see Figure 46).
Parallel interleaved LVDS mode. The power dissipation on DRVDD changes with the output data mode used.
4
Standby can be controlled by the SPI.
2
3
Rev. B | Page 5 of 81
AD6679
Data Sheet
AC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.
Table 2.
Parameter 1
ANALOG INPUT FULL SCALE
NOISE DENSITY 2
SIGNAL-TO-NOISE RATIO (SNR) 3
VDR Mode (Input Mask Not Triggered)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
NSR Enabled (21% Bandwidth (BW) Mode)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
NSR Enabled (28% BW Mode)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)3
VDR Mode (Input Mask Not Triggered)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
EFFECTIVE NUMBER OF BITS (ENOB)3
VDR Mode (Input Mask Not Triggered)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
Temperature
Full
Full
2.06
−153
Unit
V p-p
dBFS/Hz
68.9
68.6
67.8
67.3
63.9
62.8
59.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
25°C
25°C
25°C
75.0
74.8
74.0
73.1
69.7
68.1
64.6
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
25°C
25°C
25°C
72.4
72.3
71.6
71.0
67.7
66.8
63.1
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
68.7
68.5
67.6
67.2
63.8
62.5
58.3
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
11.1
10.9
10.8
10.8
10.3
10.1
9.5
Bits
Bits
Bits
Bits
Bits
Bits
Bits
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Rev. B | Page 6 of 81
Min
67.5
67
10.8
Typ
Max
Data Sheet
AD6679
Parameter 1
SPURIOUS FREE DYNAMIC RANGE (SFDR), SECOND OR THIRD HARMONIC3
VDR Mode (Input Mask Not Triggered)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
WORST OTHER (EXCLUDING SECOND OR THIRD HARMONIC)3
VDR Mode (Input Mask Not Triggered)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)3, AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 185 MHz, fIN2 = 188 MHz
fIN1 = 338 MHz, fIN2 = 341 MHz
CROSSTALK 4
FULL POWER BANDWIDTH
Temperature
25°C
Full
25°C
25°C
25°C
25°C
25°C
Min
Typ
Unit
Max
83
85
82
86
81
76
69
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
Full
25°C
25°C
25°C
25°C
25°C
−93
−94
−90
−92
−89
−89
−85
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
−88
−87
95
2
dBFS
dBFS
dB
GHz
76
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Noise density is measured at a low analog input frequency (30 MHz).
3
See Table 11 for the recommended settings for full-scale voltage and buffer control settings.
4
Crosstalk is measured at 185 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel.
1
2
DIGITAL SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.
Table 3.
Parameter
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
SYSTEM REFERENCE INPUTS (SYNC+, SYNC−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Differential)
LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. B | Page 7 of 81
Min
600
Typ
LVDS/LVPECL
1200
0.85
35
Max
Unit
1800
mV p-p
V
kΩ
pF
2.5
400
0.6
LVDS/LVPECL
1200
0.85
35
1800
2.0
2.5
0
CMOS
0.8 × SPIVDD
0.2 × SPIVDD
30
mV p-p
V
kΩ
pF
V
V
kΩ
AD6679
Parameter
LOGIC OUTPUT (SDIO)
Logic Compliance
Logic 1 Voltage (IOH = 800 µA)
Logic 0 Voltage (IOL = 50 µA)
LOGIC OUTPUTS (FD_A, FD_B)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
DIGITAL OUTPUTS (D0± to D13±, A Dx/Dy± and B Dx/Dy±,
DATA0± to DATA7±, DCO±, OVR±, FCO±, and STATUS±)
Logic Compliance
ANSI Mode
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Reduced Swing Mode
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Data Sheet
Temperature
Min
Full
Full
Full
Full
Full
Full
Full
0.8
0
Typ
Max
Unit
CMOS
0.8 × SPIVDD
0.2 × SPIVDD
V
V
CMOS
SPIVDD
0
30
V
V
kΩ
Full
LVDS
Full
Full
230
0.58
350
0.70
430
0.85
mV
V
Full
Full
120
0.59
200
0.70
235
0.83
mV
V
SWITCHING SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling
rate, 1.0 V internal reference, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, unless otherwise noted.
Table 4.
Parameter
CLOCK
Clock Rate (at CLK+/CLK− Pins)
Sample Rate
Maximum 1
Minimum 2
Clock Pulse Width
High
Low
LVDS DATA OUTPUT
Data Propagation Delay (tPD) 3
DCO± Propagation Delay (tDCO)3
DCO± to Data Skew—Rising Edge Data (tSKEWR)3
DCO± to Data Skew—Falling Edge Data (tSKEWF)3
DCO± and Data Duty Cycle
FCO± Propagation Delay (tFCO) 4
DCO± to FCO± Skew (tFRAME)4
DCO Output Frequency
Output Date Rate
LATENCY
Pipeline Latency
NSR Latency 5
NSR HB Filter Latency5
VDR Latency5
HB1 Filter Latency5
HB1 + HB2 Filter Latency5
HB1 + HB2 + HB3 Filter Latency5
HB1 + HB2 + HB3 + HB4 Filter Latency5
Fast Detect Latency
Temperature
Min
Full
0.3
Full
Full
500
250
MSPS
MSPS
Full
Full
1000
1000
ps
ps
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. B | Page 8 of 81
−150
−150
44
−150
Typ
2.225
2.2
−25
−25
50
2.2
−25
33
8
24
8
50
101
217
433
28
Max
Unit
4
GHz
+100
+100
56
+100
500
1000
ns
ns
ps
ps
%
ns
ps
MHz
Mbps
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Data Sheet
AD6679
Parameter
Wake-Up Time 6
Standby
Power-Down6
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Out of Range Recovery Time
Temperature
Min
Typ
25°C
25°C
1
Full
Full
Full
530
55
1
Max
Unit
4
ms
ms
ps
fs rms
Clock cycles
The maximum sample rate is the clock rate after the divider.
The minimum sample rate operates at 300 MSPS with L = 2 or L = 1.
This specification is valid for parallel interleaved, channel multiplexed, and byte mode output modes.
4
This specification is valid for byte mode output mode only.
5
Add this value to the pipeline latency specification to achieve total latency through the AD6679.
6
Wake-up time is defined as the time required to return to normal operation from power-down mode or standby mode.
1
2
3
TIMING SPECIFICATIONS
Table 5.
Parameter
CLK± to SYNC± TIMING REQUIREMENTS
tSU_SR
tH_SR
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tACCESS
Test Conditions/Comments
Min
Device clock to SYNC± setup time
Device clock to SYNC± hold time
See Figure 3
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK is in a logic high state
Minimum period that SCLK is in a logic low state
Maximum time delay between falling edge of SCLK and output
data valid for a read operation
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge (not shown in Figure 3)
tDIS_SDIO
Typ
Max
Unit
117
−96
ps
ps
6
ns
ns
ns
ns
ns
ns
ns
ns
2
2
40
2
2
10
10
10
10
ns
Timing Diagrams
CLK–
CLK+
tSU_SR
tH_SR
13059-002
SYNC–
SYNC+
Figure 2. SYNC± Setup and Hold Timing
tHIGH
tDS
tS
tCLK
tDH
tACCESS
tH
tLOW
CSB
SDIO DON’T CARE
DON’T CARE
R/W
A14
A13
A12
A11
A10
A9
A8
A7
D7
Figure 3. Serial Port Interface Timing Diagram
Rev. B | Page 9 of 81
D6
D3
D2
D1
D0
DON’T CARE
13059-003
SCLK DON’T CARE
AD6679
Data Sheet
APERTURE DELAY
N + 33
N
VIN±x
N + 37
N + 34
N + 38
N–1
N+x
N + 35
N+y
N + 36
N + 39
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET
SYNC+
SYNC–
CLK+
CLK–
tCLK
tCH
FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE
tDCO
tPD
2 × tCLK
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST
DCO± ((DATA CLOCK OUTPUT)
90° PHASE ADJUST 1
DCO± (DATA CLOCK OUTPUT)
180° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
270° PHASE ADJUST 2
STATUS BIT SELECTED BY
OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0]
IN THE REGISTER MAP
tSKEWF
tSKEWR
OVR+
(OVERRANGE/STATUS BIT)
CONVERTER 0 CONVERTER 0 CONVERTER 0 CONVERTER 0 CONVERTER 0
SAMPLE
SAMPLE
SAMPLE
SAMPLE
SAMPLE
[N + 4]
[N + 3]
[N + 2]
[N + 1]
[N]
OVR
OVR
OVR
OVR
OVR
OVR
OVR
D13±
D13
D13
D13
D13
D13
D13
D13
D0±
D0
D0
D0
D0
D0
D0
D0
190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
Figure 4. Parallel Interleaved Mode—One Virtual Converter (Decimate by 1)
Rev. B | Page 10 of 81
13059-004
OVR–
Data Sheet
AD6679
APERTURE DELAY
N + 33
N
VIN±x
N + 35
N+x
N + 34
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET
SYNC+
SYNC–
CLK+
CLK–
tCLK
tDCO
tPD
tCH
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
180° PHASE ADJUST
STATUS BIT SELECTED BY
OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0]
IN THE REGISTER MAP
tSKEWR
OVR+
(OVERRANGE/STATUS BIT)
tSKEWF
CONVERTER 0
SAMPLE
[N]
CONVERTER 1
SAMPLE
[N]
CONVERTER 0
SAMPLE
[N + 1]
CONVERTER 1
SAMPLE
[N + 1]
CONVERTER 0
SAMPLE
[N + 2]
OVR
OVR
OVR
OVR
OVR
OVR
OVR
OVR
D13±
D13
D13
D13
D13
D13
D13
D13
D13
D0±
D0
D0
D0
D0
D0
D0
D0
D0
Figure 5. Parallel Interleaved Mode—Two Virtual Converters (Decimate by 1)
Rev. B | Page 11 of 81
13059-005
OVR–
AD6679
Data Sheet
APERTURE DELAY
N + 33
N
VIN±x
N + 35
N+x
N + 34
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYSREF SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET
SYNC+
SYNC–
CLK+
CLK–
tDCO
tPD
tCH
tCLK
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
180° PHASE ADJUST
STATUS BIT SELECTED BY
OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0]
IN THE REGISTER MAP
OVR+
(OVERRANGE/STAUS BIT)
OVR
OVR
S[N – y]
(ODD BITS)
S[N – x]
(EVEN BITS)
tSKEWR
OVR
tSKEWF
CONVERTERS
SAMPLE
[N]
CONVERTERS
SAMPLE
[N]
CONVERTERS
SAMPLE
[N + 1]
CONVERTERS
SAMPLE
[N + 1]
CONVERTERS
SAMPLE
[N + 2]
OVR
OVR
OVR
OVR
OVR
S[N]
(ODD BITS)
S[N + 1]
(EVEN BITS)
S[N + 1]
(ODD BITS)
S[N + 2]
(EVEN BITS)
OVR–
S[N]
S[N – 1]
(ODD BITS) (EVEN BITS)
A D0/D1±
Figure 6. Channel Multiplexed (Even/Odd) Mode—One Virtual Converter (Decimate by 1)
Rev. B | Page 12 of 81
13059-006
A D12/D13±
Data Sheet
AD6679
APERTURE DELAY
N + 33
N
VIN±x
N + 35
N+x
N + 34
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET
SYNC+
SYNC–
CLK+
CLK–
tDCO
tPD
tCLK
tCH
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
180° PHASE ADJUST
STATUS BIT SELECTED BY
OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0]
IN THE REGISTER MAP
tSKEWR
OVR+
(OVERRANGE/STATUS BIT)
OVR
tSKEWF
CONVERTERS
SAMPLE
[N]
CONVERTERS
SAMPLE
[N]
CONVERTERS
SAMPLE
[N + 1]
CONVERTERS
SAMPLE
[N + 1]
CONVERTERS
SAMPLE
[N + 2]
OVR
OVR
OVR
OVR
OVR
OVR
OVR
S[N – y]
(ODD BITS)
S[N – x]
(EVEN BITS)
S[N]
S[N – 1]
(ODD BITS) (EVEN BITS)
S[N]
(ODD BITS)
S[N + 1]
(EVEN BITS)
S[N + 1]
(ODD BITS)
S[N + 2]
(EVEN BITS)
S[N – y]
(ODD BITS)
S[N – x]
(EVEN BITS)
S[N]
S[N – 1]
(ODD BITS) (EVEN BITS)
S[N]
(ODD BITS)
S[N + 1]
(EVEN BITS)
S[N + 1]
(ODD BITS)
S[N + 2]
(EVEN BITS)
OVR–
A D12/D13±
B D12/D13±
B D0/D1±
Figure 7. Channel Multiplexed (Even/Odd) Mode—Two Virtual Converters (Decimate by 1)
Rev. B | Page 13 of 81
13059-007
A D0/D1±
AD6679
Data Sheet
APERTURE DELAY
N+z
N
VIN±x
N–1
N + 36
N + 33
N + 37
N + 39
N+x
N + 34
N + 35
N+y
N + 38
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO/FCO DIVIDERS TO BE RESET
SYNC+
SYNC–
CLK+
CLK–
tCLK
FIXED DELAY FROM SYNC EVENT
TO DCO KNOWN PHASE
tCH
tDCO
tPD
tFCO
2 × tCLK
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
90° PHASE ADJUST 1
DCO± (DATA CLOCK OUTPUT)
180° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
270° PHASE ADJUST 2
tFRAME
tSKEWF
tSKEWR
FCO–
(FRAME CLOCK OUTPUT)3
FRAME 0
FRAME 1
FRAME 2
FRAME 3
FCO+
STATUS+
(OVERRANGE STATUS BIT)
I0[N]
EVEN
I0[N]
ODD
I1[N]
EVEN
I1[N]
ODD
I2[N + 1]
EVEN
I2[N + 1]
ODD
I3[N + 1]
EVEN
I3[N + 1]
ODD
PAR4
PAR
OVR
PAR
OVR
PAR
OVR
PAR
OVR
PAR
DATA7±
D15
D15
D14
D15
D14
D15
D14
D15
D14
D15
DATA0±
D1
D1
D0
D1
D0
D1
D0
D1
D0
D1
STATUS–
1) ENABLED (ALWAYS ON)
2) DISABLED (ALWAYS OFF)
3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDORANDOM BIT)
4STATUS BIT SELECTED BY THE OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP.
Figure 8. LVDS Byte Mode—One Virtual Converter, One DDC (I Only, Decimate by 2)
Rev. B | Page 14 of 81
13059-100
190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
3FRAME CLOCK OUTPUT SUPPORTS THREE MODES OF OPERATION:
Data Sheet
AD6679
APERTURE DELAY
N+z
N
VIN±x
N–1
N + 36
N + 33
N + 37
N + 39
N+x
N + 34
N + 35
N+y
N + 38
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF
THE CLK SIGNAL CAUSES THE DCO/FCO DIVIDERS TO BE RESET
SYNC+
SYNC–
CLK+
CLK–
tCLK
FIXED DELAY FROM SYNC EVENT
TO DCO KNOWN PHASE
tCH
tDCO
tPD
tFCO
2 × tCLK
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
90° PHASE ADJUST 1
DCO± (DATA CLOCK OUTPUT)
180° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
270° PHASE ADJUST 2
tFRAME
FCO–
(FRAME CLOCK OUTPUT)3
FRAME 0
FCO+
STATUS+
(OVERRANGE STATUS BIT)
FRAME 1
tSKEWF
tSKEWR
I0[N]
EVEN
I0[N]
ODD
Q 0[N]
EVEN
Q 0[N]
ODD
I0[N + 1]
EVEN
I0[N + 1] Q 0[N + 1] Q 0[N + 1]
ODD
EVEN
ODD
PAR 4
PAR
OVR
PAR
OVR
PAR
OVR
PAR
OVR
PAR
DATA7±
D15
D15
D14
D15
D14
D15
D14
D15
D14
D15
DATA0±
D1
D1
D0
D1
D0
D1
D0
D1
D0
D1
STATUS–
1) ENABLED (ALWAYS ON)
2) DISABLED (ALWAYS OFF)
3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDORANDOM BIT)
4STATUS BIT SELECTED BY THE OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP.
Figure 9. LVDS Byte Mode—Two Virtual Converters, One DDC (I/Q Decimate by 4)
Rev. B | Page 15 of 81
13059-008
190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
3FRAME CLOCK OUTPUT SUPPORTS THREE MODES OF OPERATION:
Rev. B | Page 16 of 81
Figure 10. LVDS Byte Mode—Four Virtual Converters, Two DDCs (I/Q Decimate by 8)
D1
DATA0±
N+y
N+z
N + 33
N + 34
N + 35
N + 36
N + 37
N + 38
N + 39
tCH
tDCO
tPD
tFCO
D0
D14
OVR
I0[N]
EVEN
D1
D15
PAR
D0
D14
OVR
Q0[N]
EVEN
tSKEWF
I0[N]
ODD
1) ENABLED (ALWAYS ON)
2) DISABLED (ALWAYS OFF)
3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDO-RANDOM BIT)
4STATUS BIT SELECTED BY OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP.
D1
D15
PAR
tSKEWR
tFRAME
2 × tCLK
D1
D15
PAR
Q0[N]
ODD
D0
D14
OVR
I1[N]
EVEN
FRAME 0
FRAME 0
D1
D15
PAR
I1[N]
ODD
D0
D14
OVR
Q1[N]
EVEN
FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE
D1
D15
PAR
Q1[N]
ODD
D0
D14
OVR
I0[N+1]
EVEN
D1
D15
PAR
I0[N+1]
ODD
D0
D14
OVR
Q0[N+1]
EVEN
D1
D15
PAR
Q0[N+1]
ODD
D0
D14
OVR
I1[N + 1]
EVEN
D1
D15
PAR
I1[N+1]
ODD
FRAME 1
FRAME 1
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO/FCO DIVIDERS TO BE RESET
N+x
APERTURE DELAY
190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
3FRAME CLOCK OUTPUT SUPPORTS THREE MODES OF OPERATION:
D15
PAR4
tCLK
N–1
DATA7±
STATUS–
STATUS+
(OVERRANGE STATUS BIT)
FCO+
FCO–
(FRAME CLOCK OUTPUT)3
DCO± (DATA CLOCK OUTPUT)
270° PHASE ADJUST 2
DCO± (DATA CLOCK OUTPUT)
180° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
90° PHASE ADJUST 1
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST
CLK–
CLK+
SYNC–
SYNC+
VIN±x
N
D0
D14
OVR
Q1[N+1]
EVEN
D1
D15
PAR
Q1[N+1]
ODD
AD6679
Data Sheet
13059-009
tCLK
Rev. B | Page 17 of 81
D1
DATA0±
N+x
N+y
APERTURE DELAY
N+z
Figure 11. LVDS Byte Mode—Eight Virtual Converters, Four DDCs (I/Q Decimate by 16)
N + 34
N + 35
tDCO
tPD
tFCO
N + 36
N + 37
N + 38
N + 39
D14
D0
D1
OVR
I0[N]
EVEN
D15
PAR
tSKEWR
tFRAME
D1
D15
PAR
I0[N]
ODD
D0
D14
OVR
Q0[N]
EVEN
tSKEWF
2 × tCLK
D1
D15
PAR
Q0[N]
ODD
D0
D14
OVR
I1[N]
EVEN
FRAME 0
D1
D15
PAR
I1[N]
ODD
D0
D14
OVR
Q1[N]
EVEN
FIXED DELAY FROM SYSNC EVENT TO DCO KNOWN PHASE
CLOCK OUTPUT SUPPORTS THREE MODES OF OPERATION:
1) ENABLED (ALWAYS ON)
2) DISABLED (ALWAYS OFF)
3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDORANDOM BIT)
4STATUS BIT SELECTED BY OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP.
3FRAME
N + 33
D1
D15
PAR
Q1[N]
ODD
D0
D14
OVR
I2[N]
EVEN
FRAME 0
D1
D15
PAR
I2[N]
ODD
D0
D14
OVR
Q2[N]
EVEN
D1
D15
PAR
Q2[N]
ODD
D0
D14
OVR
I3[N]
EVEN
D1
D15
PAR
I3[N]
ODD
SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO/FCO DIVIDERS TO BE RESET
tCH
N
190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±.
D15
PAR 4
N–1
DATA7±
STATUS–
STATUS+
(OVERRANGE STATUS BIT)
FCO+
FCO–
(FRAME CLOCK OUTPUT) 3
DCO± (DATA CLOCK OUTPUT)
270° PHASE ADJUST 2
DCO± (DATA CLOCK OUTPUT)
180° PHASE ADJUST
DCO± (DATA CLOCK OUTPUT)
90° PHASE ADJUST 1
DCO± (DATA CLOCK OUTPUT)
0° PHASE ADJUST
CLK–
CLK+
SYNC–
SYNC+
VIN±x
D0
D14
OVR
Q3[N]
EVEN
D1
D15
PAR
Q3[N]
ODD
Data Sheet
AD6679
13059-010
AD6679
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD1 to AGND
AVDD2 to AGND
AVDD3 to AGND
DVDD to DGND
DRVDD to DRGND
SPIVDD to AGND
AGND to DRGND
VIN±x to AGND
SCLK, SDIO, CSB to AGND
PDWN/STBY to AGND
Environmental
Operating Temperature Range
Maximum Junction Temperature
Storage Temperature Range
(Ambient)
THERMAL CHARACTERISTICS
Rating
1.32 V
2.75 V
3.63 V
1.32 V
1.32 V
3.63 V
−0.3 V to +0.3 V
3.2 V
−0.3 V to SPIVDD + 0.3 V
−0.3 V to SPIVDD + 0.3 V
−40°C to +85°C
+125°C
−65°C to +150°C
Typical θJA, ΨJB, and ΨJT are specified vs. the number of printed
circuit board (PCB) layers in different airflow velocities (in
m/sec). Airflow increases heat dissipation, effectively reducing
θJA and ΨJB. In addition, metal in direct contact with the package
leads from metal traces, through holes, ground, and power planes
reduces the θJA. Thermal performance for actual applications
requires careful inspection of the conditions in an application.
The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does
not exceed the limits shown in Table 6.
Table 7. Thermal Resistance
PCB Type
JEDEC 2s2p
Board
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
1
2
3
Airflow Velocity
(m/sec)
0.0
θJA
27.01, 2
ΨJT
0.71, 3
Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per JEDEC JESD51-8 (still air).
ESD CAUTION
Rev. B | Page 18 of 81
ΨJB
7.31, 3
Unit
°C/W
Data Sheet
AD6679
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
AGND
AGND
AGND
AVDD2
AVDD1
AGND
CLK+
CLK–
AGND
AVDD1
AVDD2
AGND
AGND
AGND
A
B
AVDD3
AGND
AGND
AVDD2
AVDD1
AGND
AGND
AGND
AGND
AVDD1
AVDD2
AGND
AGND
AVDD3
B
C
AVDD3
AGND
AGND
AVDD2
AVDD1
AGND
SYNC+
SYNC–
AGND
AVDD1
AVDD2
AGND
AGND
AVDD3
C
D
AGND
AGND
AGND
AVDD2
AVDD1
AGND
AVDD1
AGND
AGND
AVDD1
AVDD2
AGND
AGND
AGND
D
E
VIN–B
AGND
AGND
AVDD2
AVDD1
AGND
AGND
AGND
AGND
AVDD1
AVDD2
AGND
AGND
VIN–A
E
F
VIN+B
AGND
AGND
AVDD2
AGND
AGND
AGND
AGND
AGND
AGND
AVDD2
AGND
AGND
VIN+A
F
G
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD2
AGND
AGND
AGND
G
H
AGND
AGND
AGND
CSB
AGND
AGND
AGND
AGND
AGND
V_1P0
AGND
AGND
AGND
AGND
H
FD_A
J
J
FD_B
AGND
AGND
SCLK
SPIVDD
AGND
AGND
AGND
AGND
AVDD2
SPIVDD
AGND
PDWN/
STBY
K
DGND
DGND
AGND
SDIO
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DCO–
DCO+
K
L
DVDD
DVDD
DGND
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
OVR–
OVR+
L
M
D1+
D1–
DVDD
DVDD
DRVDD
DRVDD
DRVDD
DRGND
DRGND
DRGND
DRGND
DRGND
D13–
D13+
M
N
D2–
D3–
D4–
D5–
D6–
D0–
DRVDD
DRGND
D7–
D8–
D9–
D10–
D11–
D12–
N
P
D2+
D3+
D4+
D5+
D6+
D0+
DRVDD
DRGND
D7+
D8+
D9+
D10+
D11+
D12+
P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1.25V ANALOG SUPPLY
2.50V ANALOG SUPPLY
3.3V ANALOG SUPPLY
1.25V DIGITAL SUPPLY
1.25V LVDS DRIVER SUPPLY
1.22V TO 3.4V SPI SUPPLY
ANALOG GROUND
DIGITAL GROUND
LVDS DRIVER GROUND
ADC I/O
LVDS INTERFACE
SPI INTERFACE
Figure 12. Pin Configuration—Parallel Interleaved LVDS Mode (Top View)
Table 8. Pin Function Descriptions—Parallel Interleaved LVDS Mode
Pin No.
Power Supplies
A5, A10, B5, B10, C5, C10, D5, D7, D10, E5, E10
A4, A11, B4, B11, C4, C11, D4, D11, E4, E11, F4,
F11, G11, J10
B1, B14, C1, C14
L1, L2, M3, M4
M5 to M7, N7, P7
J5, J11
K1, K2, L3, L4
M8 to M12, N8, P8
A1 to A3, A6, A9, A12 to A14, B2, B3, B6 to B9,
B12, B13, C2, C3, C6, C9, C12, C13, D1 to D3,
D6, D8, D9, D12 to D14, E2, E3, E6 to E9, E12,
E13, F2, F3, F5 to F10, F12, F13, G1 to G10, G12
to G14, H1 to H3, H5 to H9, H11 to H14, J2, J3,
J6 to J9, J12, K3, K5 to K12, L5 to L12
Analog
E14, F14
E1, F1
Mnemonic
Type
Description
AVDD1
AVDD2
Supply
Supply
Analog Power Supply (1.25 V Nominal).
Analog Power Supply (2.50 V Nominal).
AVDD3
DVDD
DRVDD
SPIVDD
DGND
DRGND
AGND
Supply
Supply
Supply
Supply
Ground
Ground
Ground
Analog Power Supply (3.3 V Nominal)
Digital Power Supply (1.25 V Nominal).
Digital Driver Power Supply (1.25 V Nominal).
Digital Power Supply for SPI (1.22 V to 3.4 V).
Ground Reference for DVDD.
Ground Reference for DRVDD.
Analog Ground.
VIN−A,
VIN+A
VIN−B,
VIN+B
Input
ADC A Analog Input Complement/True.
Input
ADC B Analog Input Complement/True.
Rev. B | Page 19 of 81
13059-011
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD6679
Data Sheet
Pin No.
H10
Mnemonic
V_1P0
Type
Input/DNC
A7, A8
CMOS Outputs
J14, J1
Digital Inputs
C7, C8
CLK+, CLK−
Input
Description
1.0 V Reference Voltage Input/Do Not Connect. This pin
is configurable through the SPI as a no connect or as an
input. Do not connect this pin if using the internal
reference. This pin requires a 1.0 V reference voltage
input if using an external voltage reference source.
Clock Input True/Complement.
FD_A, FD_B
Output
Fast Detect Outputs for Channel A and Channel B.
SYNC+,
SYNC−
Input
Active High LVDS Sync Input—True/Complement.
D0−, D0+
D1−, D1+
D2−, D2+
D3−, D3+
D4−, D4+
D5−, D5+
D6−, D6+
D7−, D7+
D8−, D8+
D9−, D9+
D10−, D10+
D11−, D11+
D12−, D12+
D13−, D13+
OVR−, OVR+
DCO−, DCO+
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
LVDS Lane 0 Output Data—Complement/True.
LVDS Lane 1 Output Data—Complement/True.
LVDS Lane 2 Output Data—Complement/True.
LVDS Lane 3 Output Data—Complement/True.
LVDS Lane 4 Output Data—Complement/True.
LVDS Lane 5 Output Data—Complement/True.
LVDS Lane 6 Output Data—Complement/True.
LVDS Lane 7 Output Data—Complement/True.
LVDS Lane 8 Output Data—Complement/True.
LVDS Lane 9 Output Data—Complement/True.
LVDS Lane 10 Output Data—Complement/True.
LVDS Lane 11 Output Data—Complement/True.
LVDS Lane 12 Output Data—Complement/True.
LVDS Lane 13 Output Data—Complement/True.
LVDS Overrange Output Data—Complement/True.
LVDS Digital Clock Output Data—Complement/True.
SDIO
SCLK
CSB
PDWN/STBY
Input/output
Input
Input
Input
SPI Serial Data Input/Output.
SPI Serial Clock.
SPI Chip Select (Active Low).
Power-Down Input (Active High)/Standby. The
operation of this pin depends on the SPI mode and can
be configured in power-down or standby mode.
Data Outputs
N6, P6
M2, M1
N1, P1
N2, P2
N3, P3
N4, P4
N5, P5
N9, P9
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
M13, M14
L13, L14
K13, K14
Device Under Test (DUT) Controls
K4
J4
H4
J13
Rev. B | Page 20 of 81
Data Sheet
AD6679
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
AGND
AGND
AGND
AVDD2
AVDD1
AGND
CLK+
CLK–
AGND
AVDD1
AVDD2
AGND
AGND
AGND
A
B
AVDD3
AGND
AGND
AVDD2
AVDD1
AGND
AGND
AGND
AGND
AVDD1
AVDD2
AGND
AGND
AVDD3
B
C
AVDD3
AGND
AGND
AVDD2
AVDD1
AGND
SYNC+
SYNC–
AGND
AVDD1
AVDD2
AGND
AGND
AVDD3
C
D
AGND
AGND
AGND
AVDD2
AVDD1
AGND
AVDD1
AGND
AGND
AVDD1
AVDD2
AGND
AGND
AGND
D
E
VIN–B
AGND
AGND
AVDD2
AVDD1
AGND
AGND
AGND
AGND
AVDD1
AVDD2
AGND
AGND
VIN–A
E
F
VIN+B
AGND
AGND
AVDD2
AGND
AGND
AGND
AGND
AGND
AGND
AVDD2
AGND
AGND
VIN+A
F
G
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD2
AGND
AGND
AGND
G
H
AGND
AGND
AGND
CSB
AGND
AGND
AGND
AGND
AGND
V_1P0
AGND
AGND
AGND
AGND
H
J
FD_B
AGND
AGND
SCLK
SPIVDD
AGND
AGND
AGND
AGND
AVDD2
SPIVDD
AGND
PDWN/
STBY
FD_A
J
K
DGND
DGND
AGND
SDIO
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DCO–
DCO+
K
L
DVDD
DVDD
DGND
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
OVR–
OVR+
L
M
B D2/D3 +
B D2/D3 –
DVDD
DVDD
DRVDD
DRVDD
DRVDD
DRGND
DRGND
DRGND
DRGND
DRGND
N
B D4/D5–
B D6/D7 –
B D8/D9 –
B D10/D11 – B D12/D13 –
B D0/D1 –
DRVDD
DRGND
A D0/D1 –
A D2/D3 –
A D4/D5–
A D6/D7–
A D8/D9–
A D10/D11– N
P
B D4/D5 +
B D6/D7+
B D8/D9 +
B D10/D11 + B D12/D13 +
B D0/D1 +
DRVDD
DRGND
A D0/D1 +
A D2/D3 +
A D4/D5 +
A D6/D7 +
A D8/D9 +
A D10/D11 + P
1
2
3
6
7
8
9
10
11
12
13
1.25V ANALOG SUPPLY
2.50V ANALOG SUPPLY
3.3V ANALOG SUPPLY
5
1.25V DIGITAL SUPPLY
1.25V LVDS DRIVER SUPPLY
1.22V TO 3.4V SPI SUPPLY
ANALOG GROUND
DIGITAL GROUND
LVDS DRIVER GROUND
14
ADC I/O
LVDS INTERFACE
SPI INTERFACE
13059-012
4
A D12/D13– A D12/D13+ M
Figure 13. Pin Configuration—Channel Multiplexed (Even/Odd) LVDS Mode (Top View)
Table 9. Pin Function Descriptions—Channel Multiplexed (Even/Odd) LVDS Mode 1
Pin No.
Power Supplies
A5, A10, B5, B10, C5, C10, D5, D7, D10, E5,
E10
A4, A11, B4, B11, C4, C11, D4, D11, E4, E11,
F4, F11, G11, J10
B1, B14, C1, C14
L1, L2, M3, M4
M5 to M7, N7, P7
J5, J11
K1, K2, L3, L4
M8 to M12, N8, P8
A1 to A3, A6, A9, A12 to A14, B2, B3, B6 to
B9, B12, B13, C2, C3, C6, C9, C12, C13, D1 to
D3, D6, D8, D9, D12 to D14, E2, E3, E6 to E9,
E12, E13, F2, F3, F5 to F10, F12, F13, G1 to
G10, G12 to G14, H1 to H3, H5 to H9, H11 to
H14, J2, J3, J6 to J9, J12, K3, K5 to K12, L5 to
L12
Analog
E14, F14
E1, F1
H10
A7, A8
Mnemonic
Type
Description
AVDD1
Supply
Analog Power Supply (1.25 V Nominal).
AVDD2
Supply
Analog Power Supply (2.50 V Nominal).
AVDD3
DVDD
DRVDD
SPIVDD
DGND
DRGND
AGND
Supply
Supply
Supply
Supply
Ground
Ground
Ground
Analog Power Supply (3.3 V Nominal)
Digital Power Supply (1.25 V Nominal).
Digital Driver Power Supply (1.25 V Nominal).
Digital Power Supply for SPI (1.22 V to 3.4 V).
Ground Reference for DVDD.
Ground Reference for DRVDD.
Analog Ground.
VIN−A, VIN+A
VIN−B, VIN+B
V_1P0
Input
Input
Input/DNC
CLK+, CLK−
Input
ADC A Analog Input Complement/True.
ADC B Analog Input Complement/True.
1.0 V Reference Voltage Input/Do Not Connect. This pin
is configurable through the SPI as a no connect or as an
input. Do not connect this pin if using the internal
reference. This pin requires a 1.0 V reference voltage
input if using an external voltage reference source.
Clock Input True/Complement.
Rev. B | Page 21 of 81
AD6679
Pin No.
CMOS Outputs
J14, J1
Digital Inputs
C7, C8
Data Outputs
N9, P9
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
M13, M14
N6, P6
M2, M1
N1, P1
N2, P2
N3, P3
N4, P4
N5, P5
L13, L14
K13, K14
DUT Controls
K4
J4
H4
J13
1
Data Sheet
Mnemonic
Type
Description
FD_A, FD_B
Output
Fast Detect Outputs for Channel A and Channel B.
SYNC+,
SYNC−
Input
Active High LVDS Sync Input—True/Complement.
A D0/D1−,
A D0/D1+
A D2/D3−,
A D2/D3+
A D4/D5−,
A D4/D5+
A D6/D7−,
A D6/D7+
A D8/D9−,
A D8/D9+
A D10/D11−,
A D10/D11+
A D12/D13−,
A D12/D13+
B D0/D1−,
B D0/D1+
B D2/D3−,
B D2/D3+
B D4/D5−,
B D4/D5+
B D6/D7−,
B D6/D7+
B D8/D9−,
B D8/D9+
B D10/D11−,
B D10/D11+
B D12/D13−,
B D12/D13+
OVR−, OVR+
DCO−, DCO+
Output
LVDS Channel A Data 0/Data 1 Output Data—
Complement/True.
LVDS Channel A Data 2/Data 3 Output Data—
Complement/True.
LVDS Channel A Data 4/Data 5 Output Data—
Complement/True.
LVDS Channel A Data 6/Data 7 Output Data—
Complement/True.
LVDS Channel A Data 8/Data 9 Output Data—
Complement/True.
LVDS Channel A Data 10/Data 11 Output Data—
Complement/True.
LVDS Channel A Data 12/Data 13 Output Data—
Complement/True.
LVDS Channel B Data 0/Data 1 Output Data—
Complement/True.
LVDS Channel B Data 2/Data 3 Output Data—
Complement/True.
LVDS Channel B Data 4/Data 5 Output Data—
Complement/True.
LVDS Channel B Data 6/Data 7 Output Data—
Complement/True.
LVDS Channel B Data 8/Data 9 Output Data—
Complement/True.
LVDS Channel B Data 10/Data 11 Output Data—
Complement/True.
LVDS Channel B Data 12/Data 13 Output Data—
Complement/True.
LVDS Overrange Output Data—Complement/True.
LVDS Digital Clock Output Data—Complement/True.
SDIO
SCLK
CSB
PDWN/STBY
Input/output
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
SPI Serial Data Input/Output.
SPI Serial Clock.
SPI Chip Select (Active Low).
Power-Down Input (Active High). The operation of this
pin depends on the SPI mode and can be configured in
power-down or standby mode.
When using channel multiplexed (even/odd) LVDS mode for one converter, the Channel B outputs are disabled and can be left unconnected.
Rev. B | Page 22 of 81
Data Sheet
AD6679
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
AGND
AGND
AGND
AVDD2
AVDD1
AGND
CLK+
CLK–
AGND
AVDD1
AVDD2
AGND
AGND
AGND
A
B
AVDD3
AGND
AGND
AVDD2
AVDD1
AGND
AGND
AGND
AGND
AVDD1
AVDD2
AGND
AGND
AVDD3
B
C
AVDD3
AGND
AGND
AVDD2
AVDD1
AGND
SYNC+
SYNC–
AGND
AVDD1
AVDD2
AGND
AGND
AVDD3
C
D
AGND
AGND
AGND
AVDD2
AVDD1
AGND
AVDD1
AGND
AGND
AVDD1
AVDD2
AGND
AGND
AGND
D
E
VIN–B
AGND
AGND
AVDD2
AVDD1
AGND
AGND
AGND
AGND
AVDD1
AVDD2
AGND
AGND
VIN–A
E
F
VIN+B
AGND
AGND
AVDD2
AGND
AGND
AGND
AGND
AGND
AGND
AVDD2
AGND
AGND
VIN+A
F
G
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD2
AGND
AGND
AGND
G
H
AGND
AGND
AGND
CSB
AGND
AGND
AGND
AGND
AGND
V_1P0
AGND
AGND
AGND
AGND
H
FD_A
J
J
FD_B
AGND
AGND
SCLK
SPIVDD
AGND
AGND
AGND
AGND
AVDD2
SPIVDD
AGND
PDWN/
STBY
K
DGND
DGND
AGND
SDIO
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DCO–
DCO+
K
L
DVDD
DVDD
DGND
DGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
FCO–
FCO+
L
M
DNC
DNC
DVDD
DVDD
DRVDD
DRVDD
DRVDD
DRGND
DRGND
DRGND
DRGND
DRGND
STATUS–
STATUS+
M
N
DNC
DNC
DNC
DATA0 –
DATA1 –
DNC
DRVDD
DRGND
DATA2–
DATA3 –
DATA4–
DATA5–
DATA 6–
DATA7 –
N
P
DNC
DNC
DNC
DATA0 +
DATA1 +
DNC
DRVDD
DRGND
DATA2+
DATA3 +
DATA4 +
DATA5 +
DATA6 +
DATA7 +
P
1
2
3
4
5
6
7
8
9
10
11
12
13
1.25V DIGITAL SUPPLY
1.25V LVDS DRIVER SUPPLY
1.22V TO 3.4V SPI SUPPLY
ANALOG GROUND
DIGITAL GROUND
LVDS DRIVER GROUND
ADC I/O
LVDS INTERFACE
SPI INTERFACE
14
DO NOT CONNECT
13059-013
1.25V ANALOG SUPPLY
2.50V ANALOG SUPPLY
3.3V ANALOG SUPPLY
Figure 14. Pin Configuration—LVDS Byte Mode (Top View)
Table 10. Pin Function Descriptions—LVDS Byte Mode
Pin No.
Power Supplies
A5, A10, B5, B10, C5, C10, D5, D7, D10, E5, E10
A4, A11, B4, B11, C4, C11, D4, D11, E4, E11, F4,
F11, G11, J10
B1, B14, C1, C14
L1, L2, M3, M4
M5 to M7, N7, P7
J5, J11
K1, K2, L3, L4
M8 to M12, N8, P8
A1 to A3, A6, A9, A12 to A14, B2, B3, B6 to B9,
B12, B13, C2, C3, C6, C9, C12, C13, D1 to D3,
D6, D8, D9, D12 to D14, E2, E3, E6 to E9, E12,
E13, F2, F3, F5 to F10, F12, F13, G1 to G10,
G12 to G14, H1 to H3, H5 to H9, H11 to H14,
J2, J3, J6 to J9, J12, K3, K5 to K12, L5 to L12
Analog
E14, F14
Mnemonic
Type
Description
AVDD1
AVDD2
Supply
Supply
Analog Power Supply (1.25 V Nominal).
Analog Power Supply (2.50 V Nominal).
AVDD3
DVDD
DRVDD
SPIVDD
DGND
DRGND
AGND
Supply
Supply
Supply
Supply
Ground
Ground
Ground
Analog Power Supply (3.3 V Nominal)
Digital Power Supply (1.25 V Nominal).
Digital Driver Power Supply (1.25 V Nominal).
Digital Power Supply for SPI (1.22 V to 3.4 V).
Ground Reference for DVDD.
Ground Reference for DRVDD.
Analog Ground.
Input
ADC A Analog Input Complement/True.
Input
ADC B Analog Input Complement/True.
H10
VIN−A,
VIN+A
VIN−B,
VIN+B
V_1P0
Input/DNC
A7, A8
CLK+, CLK−
Input
1.0 V Reference Voltage Input/Do Not Connect. This pin is
configurable through the SPI as a no connect or an input.
Do not connect this pin if using the internal reference.
This pin requires a 1.0 V reference voltage input if using
an external voltage reference source.
Clock Input True/Complement.
E1, F1
Rev. B | Page 23 of 81
AD6679
Pin No.
CMOS Outputs
J14, J1
Digital Inputs
C7, C8
Data Sheet
Mnemonic
Type
Description
FD_A, FD_B
Output
Fast Detect Outputs for Channel A and Channel B.
SYNC+,
SYNC−
Input
Active High LVDS Sync Input—True/Complement.
DATA0−,
DATA0+
DATA1−,
DATA1+
DATA2−,
DATA2+
DATA3−,
DATA3+
DATA4−,
DATA4+
DATA5−,
DATA5+
DATA6−,
DATA6+
DATA7−,
DATA7+
STATUS−,
STATUS+
FCO−, FCO+
DCO−,
DCO+
Output
LVDS Byte Data 0—Complement/True.
Output
LVDS Byte Data 1—Complement/True.
Output
LVDS Byte Data 2—Complement/True.
Output
LVDS Byte Data 3—Complement/True.
Output
LVDS Byte Data 4—Complement/True.
Output
LVDS Byte Data 5—Complement/True.
Output
LVDS Byte Data 6—Complement/True.
Output
LVDS Byte Data 7—Complement/True.
Output
LVDS Status Output Data—Complement/True.
Output
Output
LVDS Frame Clock Output Data—Complement/True.
LVDS Digital Clock Output Data—Complement/True.
DUT Controls
K4
J4
H4
J13
SDIO
SCLK
CSB
PDWN/STBY
Input/output
Input
Input
Input
SPI Serial Data Input/Output.
SPI Serial Clock.
SPI Chip Select (Active Low).
Power-Down Input (Active High). The operation of this
pin depends on the SPI mode and can be configured in
power-down or standby mode.
No Connects
M1, M2, N1 to N3, N6, P1 to P3, P6
DNC
DNC
Do Not Connect. Do not connect to these pins.
Data Outputs
N4, P4
N5, P5
N9, P9
N10, P10
N11, P11
N12, P12
N13, P13
N14, P14
M13, M14
L13, L14
K13, K14
Rev. B | Page 24 of 81
Data Sheet
AD6679
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, AIN = −1.0 dBFS, VDR mode
(no violation of VDR mask), clock divider = 2, otherwise default SPI settings, TA = 25°C, 128k FFT sample, unless otherwise noted.
0
0
AIN = −1dBFS
SNR = 68.9dBFS
ENOB = 10.9 BITS
SFDR = 83dBFS
BUFFER CONTROL 1 = 2.0×
–20
–40
AMPLITUDE (dBFS)
–40
–60
–80
–100
–80
–100
–120
0
25
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
–140
13059-014
–140
0
75
100
125
150
175
200
225
250
225
250
225
250
Figure 18. Single-Tone FFT with fIN = 450.3 MHz
0
0
AIN = −1dBFS
SNR = 68.7dBFS
ENOB = 10.9 BITS
SFDR = 84dBFS
BUFFER CONTROL 1 = 2.0×
–20
AIN = −1dBFS
SNR = 63.9dBFS
ENOB = 10.3 BITS
SFDR = 81dBFS
BUFFER CONTROL 1 = 5.0×
–20
–40
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–60
–80
–100
–120
0
25
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
–140
13059-015
–140
0
25
50
75
100
125
150
175
200
FREQUENCY (MHz)
Figure 16. Single-Tone FFT with fIN = 170.3 MHz
13059-018
AMPLITUDE (dBFS)
50
FREQUENCY (MHz)
Figure 15. Single Tone FFT with fIN = 10.3 MHz
Figure 19. Single-Tone FFT with fIN = 765.3 MHz
0
0
AIN = −1dBFS
SNR = 67.8dBFS
ENOB = 10.8 BITS
SFDR = 82dBFS
BUFFER CONTROL 1 = 4.5×
–20
AIN = −1dBFS
SNR = 62.8dBFS
ENOB = 10.1 BITS
SFDR = 76dBFS
BUFFER CONTROL 1 = 5.0×
–20
–40
AMPLITUDE (dBFS)
–40
–60
–80
–100
–60
–80
–100
–120
–120
–140
0
25
50
75
100
125
150
175
200
FREQUENCY (MHz)
225
250
13059-016
AMPLITUDE (dBFS)
25
13059-017
–120
–60
Figure 17. Single-Tone FFT with fIN = 340.3 MHz
–140
0
25
50
75
100
125
150
175
200
FREQUENCY (MHz)
Figure 20. Single-Tone FFT with fIN = 985.3 MHz
Rev. B | Page 25 of 81
13059-019
AMPLITUDE (dBFS)
AIN = −1dBFS
SNR = 67.3dBFS
ENOB = 10.8 BITS
SFDR = 86dBFS
BUFFER CONTROL 1 = 4.5×
–20
AD6679
Data Sheet
95
0
AIN = −1dBFS
SNR = 61.7dBFS
ENOB = 9.9 BITS
SFDR = 70dBFS
BUFFER CONTROL 1 = 8.0×
–20
90
SFDR
SNR/SFDR (dBFS)
–60
–80
85
80
75
–100
70
0
25
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
65
200
13059-020
–140
Figure 21. Single-Tone FFT with fIN = 1205.3 MHz
SFDR, 2.0×
SNRFS, 2.0×
SFDR, 3.0×
SNRFS, 3.0×
SFDR, 4.0×
SNRFS, 4.0×
90
85
SNR/SFDR (dBFS)
–60
–80
–100
80
75
70
–120
–140
0
25
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
13059-021
65
60
50
150
200
250
300
350
400
450
500
ANALOG INPUT FREQUENCY (MHz)
Figure 22. Single-Tone FFT with fIN = 1630.3 MHz
Figure 25. SNR/SFDR vs. Analog Input Frequency (fIN);
fIN < 500 MHz; Buffer Control 1 Setting = 2.0×, 3.0×, and 4.0×
0
0
AIN = −1dBFS
SNR = 59.0dBFS
ENOB = 9.5 BITS
SFDR = 69dBFS
BUFFER CONTROL 1 = 8.0×
–20
100
13059-024
AMPLITUDE (dBFS)
500
450
95
AIN = −1dBFS
SNR = 60.1dBFS
ENOB = 9.7 BITS
SFDR = 71dBFS
BUFFER CONTROL 1 = 8.0×
–40
AIN1 AND AIN2 = –7dBFS
SFDR = 88dBFS
IMD2 = 95dBFS
IMD3 = 88dBFS
BUFFER CONTROL 1 = 2.0×
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–40
–60
–80
–100
–120
–140
0
25
50
75
100
125
150
175
200
225
FREQUENCY (MHz)
250
13059-022
AMPLITUDE (dBFS)
400
300
350
SAMPLE RATE (MHz)
250
Figure 24. SNR/SFDR vs. Sample Rate (fS); fIN = 170.3 MHz;
0
–20
SNR
13059-023
–120
Figure 23. Single-Tone FFT with fIN = 1950.3 MHz
–120
0
50
100
150
200
FREQUENCY (MHz)
Figure 26. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz
Rev. B | Page 26 of 81
250
13059-025
AMPLITUDE (dBFS)
–40
Data Sheet
AD6679
100
0
80
SNR (dBc)
SNR/SFDR (dBc AND dBFS)
–20
–40
–60
–80
–100
60
SFDR (dBFS)
40
SNR (dBc)
20
0
0
–6
–12
–18
–24
–30
–36
–42
–48
FREQUENCY (MHz)
–40
–60
250
–54
200
–66
150
–72
100
–78
50
–90
0
13059-026
–120
INPUT AMPLITUDE (dBFS)
13059-029
–20
–84
AMPLITUDE (dBFS)
SFDR (dBc)
AIN1 AND AIN2 = –7dBFS
SFDR = 87dBFS
IMD2 = 94dBFS
IMD3 = 87dBFS
BUFFER CONTROL 1 = 2.0×
Figure 30. SNR/SFDR vs. Input Amplitude, fIN = 170.3 MHz
Figure 27. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz
90
0
SFDR
–20
85
SNR/SFDR (dBFS)
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
80
75
–100
70
IMD3 (dBFS)
–140
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
INPUT AMPLITUDE (dBFS)
SNR
65
–40
–25
–10
0
15
25
TEMPERATURE (°C)
40
55
70
85
13059-030
–120
13059-027
SFDR/IMD3 (dBc AND dBFS)
SFDR (dBc)
Figure 31. SNR/SFDR vs. Temperature, fIN = 170.3 MHz
Figure 28. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz
and fIN2 = 187 MHz
2.30
0
2.25
–20
2.20
2.15
–40
IMD3 (dBc)
POWER (W)
SFDR/IMD3 (dBc AND dBFS)
SFDR (dBc)
–60
–80
SFDR (dBFS)
2.10
2.05
2.00
1.95
–100
1.90
–120
1.85
IMD3 (dBFS)
Figure 29. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 338 MHz
and fIN2 = 341 MHz
Rev. B | Page 27 of 81
500
480
460
440
420
400
380
360
340
320
300
SAMPLE RATE (MSPS)
Figure 32. Power Dissipation vs. Sample Rate (fS), Default SPI
13059-031
INPUT AMPLITUDE (dBFS)
13059-028
1.80
–140
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
AD6679
Data Sheet
EQUIVALENT CIRCUITS
AVDD3
AVDD3
AVDD3
3pF 1.5pF
200Ω
SWING CONTROL
(SPI)
VCM
BUFFER
200Ω
67Ω
28Ω
10pF
200Ω
400Ω
DRVDD
AVDD3
D0+ TO D13+;
A Dx/Dy+ AND B Dx/Dy+;
DATA0+ TO DATA7+
DATA+
AVDD3
OUTPUT
DRIVER
VIN–x
D0– TO D13–;
A Dx/Dy– AND B Dx/Dy–;
DATA0– TO DATA7–
DATA–
13059-032
AIN
CONTROL
(SPI)
3pF 1.5pF
DRGND
Figure 36. Digital Outputs
Figure 33. Analog Inputs
SPIVDD
AVDD1
25Ω
ESD
PROTECTED
SCLK
30kΩ
AVDD1
ESD
PROTECTED
20kΩ
20kΩ
VCM = 0.85V
13059-033
25Ω
CLK–
SPIVDD
1kΩ
13059-036
CLK+
DRGND
DRVDD
Figure 34. Clock Inputs
Figure 37. SCLK Inputs
AVDD1
1kΩ
ESD
PROTECTED
20kΩ
LEVEL
TRANSLATOR
AVDD1
VCM = 0.85V
ESD
PROTECTED
20kΩ
1kΩ
13059-034
SYNC–
CSB
30kΩ
1kΩ
13059-037
SYNC+
SPIVDD
Figure 35. SYNC± Inputs
Figure 38. CSB Input
Rev. B | Page 28 of 81
13059-035
67Ω
200Ω
28Ω
VIN+x
Data Sheet
AD6679
SPIVDD
SPIVDD
ESD
PROTECTED
SDO
1kΩ
SDIO
ESD
PROTECTED
SPIVDD
SDI
30kΩ
1kΩ
PDWN/
STBY
30kΩ
ESD
PROTECTED
Figure 39. SDIO
PDWN
CONTROL (SPI)
Figure 41. PDWN/STBY Input
AVDD2
SPIVDD
ESD
PROTECTED
FD
V_1P0
FD_A/FD_B
TEMPERATURE DIODE
(FD_A ONLY)
FD_x PIN CONTROL (SPI)
ESD
PROTECTED
13059-039
ESD
PROTECTED
V_1P0 PIN
CONTROL (SPI)
Figure 42. V_1P0 Input/Output
Figure 40. FD_A/FD_B Outputs
Rev. B | Page 29 of 81
13059-041
ESD
PROTECTED
13059-040
13059-038
ESD
PROTECTED
AD6679
Data Sheet
THEORY OF OPERATION
The AD6679 has several functions that simplify the AGC
function in a communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect bits of the ADC output data stream,
which are enabled and programmed via Register 0x245 through
Register 0x24C. If the input signal level exceeds the programmable
threshold, the fast detect indicator goes high. Because this
threshold indicator has low latency, the user can quickly reduce
the system gain to avoid an overrange condition at the ADC input.
The LVDS outputs can be configured depending on the decimation
ratio. Multiple device synchronization is supported through the
SYNC± input pins.
ADC ARCHITECTURE
The architecture consists of an input buffered pipelined ADC.
The input buffer provides a termination impedance to the
analog input signal. This termination impedance can be
changed using the SPI to meet the termination needs of the
driver/amplifier. The default termination value is set to 400 Ω. The
equivalent circuit diagram of the analog input termination is
shown in Figure 33. The input buffer is optimized for high
linearity, low noise, and low power.
The input buffer provides a linear high input impedance (for
ease of drive) and reduces the kickback from the ADC. The
quantized outputs from each stage are combined into a final
16-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate with a new input
sample while the remaining stages operate with the preceding
samples. Sampling occurs on the rising edge of the clock.
For best dynamic performance, match the source impedances
driving VIN+x and VIN−x such that common-mode settling
errors are symmetrical. These errors are reduced by the commonmode rejection of the ADC. An internal reference buffer creates
a differential reference that defines the span of the ADC core.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD6679, the available span is programmable through the SPI
port from 1.46 V p-p to 2.06 V p-p differential with 2.06 V p-p
differential being the default.
Differential Input Configurations
There are several ways to drive the AD6679, either actively or
passively. However, optimum performance is achieved by
driving the analog input differentially.
For applications in which SNR and SFDR are key parameters,
differential transformer coupling is the recommended input
configuration (see Figure 43 and Figure 44) because the noise
performance of most amplifiers is not adequate to achieve the
true performance of the AD6679.
For low to midrange frequencies, it is recommended to use a
double balun or double transformer network (see Figure 43) for
optimum performance from the AD6679. For higher
frequencies in the second or third Nyquist zone, it is better to
remove some of the front-end passive components to ensure
wideband operation (see Figure 44).
ETC1-11-13/
MABA007159
1:1Z
10Ω
10Ω
0.1µF
25Ω
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6679 is a differential buffer. The
internal common-mode voltage of the buffer is 2.05 V. The
clock signal alternately switches the input circuit between
sample mode and hold mode. When the input circuit is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within one-half of a clock cycle.
A small resistor, in series with each input, can help reduce the
peak transient current inserted from the output stage of the
driving source. In addition, low Q inductors or ferrite beads can
be placed on each section of the input to reduce high differential capacitance at the analog inputs and, thus, achieve the
4pF
2pF
0.1µF
25Ω
10Ω
ADC
10Ω
0.1µF
13059-042
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
maximum bandwidth of the ADC. Such use of low Q inductors
or ferrite beads is required when driving the converter front end
at high IF frequencies. Place either a differential capacitor or
two single-ended capacitors on the inputs to provide a matching
passive network. This ultimately creates a low-pass filter (LPF)
at the input, which limits unwanted broadband noise. For more
information, refer to the AN-742 Application Note, the AN-827
Application Note, and the Analog Dialogue article “TransformerCoupled Front-End for Wideband A/D Converters” (Volume 39,
April 2005) at www.analog.com. In general, the precise values
depend on the application.
4pF
Figure 43. Differential Transformer Coupled Configuration for First and
Second Nyquist Frequencies
25Ω
MARKI
BAL-0006
OR
BAL-0006SMG
25Ω
25Ω
0.1µF
0.1µF
25Ω
0.1µF
ADC
13059-043
The AD6679 has two analog input channels and 14 LVDS
output lane pairs. The AD6679 is designed to sample wide
bandwidth analog signals of up to 2 GHz. The AD6679 is
optimized for wide input bandwidth, high sampling rates,
excellent linearity, and low power in a small package.
Figure 44. Differential Transformer Coupled Configuration for Second and
Third Nyquist Frequencies
Rev. B | Page 30 of 81
Data Sheet
AD6679
Input Common Mode
250
The analog inputs of the AD6679 are internally biased to the
common mode, as shown in Figure 45. The common-mode
buffer has a limited range in that the performance suffers
greatly if the common-mode voltage drops by more than
100 mV. Therefore, in dc-coupled applications, set the
common-mode voltage to 2.05 V ± 100 mV to ensure proper
ADC operation.
230
210
IAVDD3 (mA)
190
170
150
130
110
Analog Input Controls and SFDR Optimization
90
The AD6679 offers flexible controls for the analog inputs such
as input termination, buffer current, and input full-scale
adjustment. All of the available controls are shown in Figure 45.
50
1.5×
AVDD3
2.5×
3.5×
4.5×
5.5×
6.5×
7.5×
8.5×
BUFFER CURRENT SETTING
13059-045
70
Figure 46. Typical IAVDD3 vs. Buffer Current Setting in Register 0x018
VIN+x
Register 0x019, Register 0x01A, Register 0x11A, and Register 0x935
offer secondary bias controls for the input buffer for frequencies
>500 MHz. Use Register 0x934 to reduce input capacitance to
achieve wider signal bandwidth but doing so may result in
slightly lower linearity and noise performance. These register
settings do not affect the AVDD3 power as much as Register 0x018
does. For frequencies 1000 MHz) but is not necessary. Using Register 0x11A
can help the ADC sampling network to optimize the sampling
and settling times internal to the ADC for high frequency operation. For frequencies greater than 500 MHz, it is recommended
to operate the ADC core at a 1.46 V full-scale setting. This setting
offers better SFDR without any significant decrease in SNR.
Figure 47, Figure 48, and Figure 49 show the SFDR vs. input
frequency for various buffer settings for the AD6679. The
recommended settings shown in Table 11 were used to collect
the data while changing the contents of register 0x018 only.
95
4.5×
85
3.0×
75
2.0×
65
1.5×
55
1.0×
45
35
50
100
150
200
250
300
350
INPUT FREQUENCY (MHz)
400
450
500
13059-046
200Ω
67Ω
28Ω
10pF
200Ω
400Ω
SFDR (dBFS)
AVDD3
200Ω
67Ω
200Ω
28Ω
3pF
Figure 47. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF);
10 MHz < fIN < 500 MHz; Front-End Network Shown in Figure 43
Rev. B | Page 31 of 81
AD6679
Data Sheet
Absolute Maximum Input Swing
90
VOLTAGE REFERENCE
80
75
65
500
550
600
650
700
750
800
850
900
950
1000
INPUT FREQUENCY (MHz)
13059-047
70
Figure 48. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF);
500 MHz < fIN < 1000 MHz; Front-End Network Shown in Figure 44
A stable and accurate 1.0 V voltage reference is built into the
AD6679. This internal 1.0 V reference sets the full-scale input
range of the ADC. The full-scale input range can be adjusted via
Register 0x025. For more information on adjusting the input
swing, see Table 41. Figure 50 shows the block diagram of the
internal 1.0 V reference controls.
VIN+A/
VIN+B
VIN–A/
VIN–B
80
INTERNAL
V_1P0
GENERATOR
75
FULL-SCALE
VOLTAGE
ADJUST
INPUT FULL-SCALE
RANGE ADJUST
SPI REGISTER
(REG 0x025 AND REG 0x024)
70
V_1P0
65
V_1P0 PIN
CONTROL SPI
REGISTER
(REG 0x025 AND
REG 0x024)
60
55
50
4.5×
5.0×
6.0×
7.0×
8.0×
8.0×
Figure 50. Internal Reference Configuration and Controls
45
1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000
INPUT FREQUENCY (MHz)
13059-048
SFDR (dBFS)
ADC
CORE
13059-049
SFDR (dBFS)
The absolute maximum input swing allowed at the inputs of the
AD6679 is 4.3 V p-p differential. Signals operating near or at
this level can cause permanent damage to the ADC.
4.5×
5.0×
6.0×
7.0×
8.0×
85
Figure 49. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF);
1 GHz < fIN < 2 GHz; Front-End Network Shown in Figure 44
Table 11. SFDR Optimization for Input Frequencies
Frequency
DC to 250 MHz
250 MHz to
500 MHz
500 MHz to
1 GHz
1 GHz to 2 GHz
1
2
Buffer
Control 1
(Register
0x018)
0x20
(2.0×)
0x70
(4.5×)
0x80
(5.0×)
0xF0
(8.5×)
Buffer
Control 2
(Register
0x019)
0x60
(Setting 3)
0x60
(Setting 3)
0x40
(Setting 1)
0x40
(Setting 1)
Buffer
Control 3
(Register
0x01A)
0x0A
(Setting 3)
0x0A
(Setting 3)
0x08
(Setting 1)
0x08
(Setting 1)
Buffer
Control 4
(Register
0x11A)
0x00 (off)
Buffer
Control 5
(Register
0x935)
0x04 (on)
0x00 (off)
0x04 (on)
0x00 (off)
0x00 (off)
0x00 (off)
0x00 (off)
Input FullScale
Range
(Register
0x025)
0x0C
(2.06 V p-p)
0x0C
(2.06 V p-p)
0x08
(1.46 V p-p)
0x08
(1.46 V p-p)
Input FullScale
Control
(Register
0x030)
0x04
Input
Capacitance
(Register
0x934)
0x1F
Input
Termination
(Register
0x016) 1
0x0C/0x1C/0x6C
0x04
0x1F
0x0C/0x1C/0x6C
0x18
0x1F/0x00 2
0x0C/0x1C/0x6C
0x18
0x1F/0x002
0x0C/0x1C/0x6C
The input termination can be changed to accommodate the application with little or no impact to ac performance.
The input capacitance can be set to 1.5 pF to achieve wider input bandwidth but doing so results in slightly lower ac performance.
Rev. B | Page 32 of 81
Data Sheet
AD6679
The use of an external reference may be necessary, in some
applications, to enhance the gain accuracy of the ADC or
improve thermal drift characteristics. Figure 51 shows the
typical drift characteristics of the internal 1.0 V reference.
0.1µF
CLOCK
INPUT
1:1Z
CLK+
100Ω
50Ω
0.1µF
Figure 52. Transformer Coupled Differential Clock
Another option is to ac couple a differential CML or LVDS
signal to the sample clock input pins as shown in Figure 53 and
Figure 54.
3.3V
71Ω
1.0010
1.0009
10pF
33Ω
Z0 = 50Ω
1.0008
33Ω
0.1µF
ADC
1.0006
CLK–
Z0 = 50Ω
1.0005
0.1µF
13059-052
CLK+
1.0007
Figure 53. Differential CML Sample Clock
1.0004
1.0003
1.0002
0.1µF
0.1µF
CLK+
CLOCK INPUT
1.0000
0.1µF
0.9999
0
25
90
TEMPERATURE (°C)
13059-050
–50
Figure 51. Typical V_1P0 Drift
CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD6679 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled to the CLK+ and CLK− pins via a
transformer or clock drivers. These pins are biased internally
and require no additional biasing.
Figure 52 shows one preferred method for clocking the
AD6679. The low jitter clock source is converted from a singleended signal to a differential signal using an RF transformer.
1
NC
2
GND SET 5
3
VIN
CLK–
0.1µF
50Ω1
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance
is required on the clock duty cycle to maintain dynamic
performance characteristics. In applications where the clock
duty cycle cannot be guaranteed to be 50%, a higher multiple
frequency clock can be supplied to the AD6679. For example,
the AD6679 can be clocked at 2 GHz with the internal clock
divider set to 4. This ensures a 50% duty cycle, high slew rate
internal clock for the ADC. See the Memory Map section for
more details on using this feature.
FULL-SCALE
VOLTAGE
ADJUST
NC 6
VOUT 4
ADC
Figure 54. Differential LVDS Sample Clock
INTERNAL
V_1P0
GENERATOR
ADR130
0.1µF
50Ω1
150Ω RESISTORS ARE OPTIONAL.
The external reference must be a stable 1.0 V reference. The
ADR130 is a good option for providing the 1.0 V reference.
Figure 55 shows how the ADR130 can be used to provide the
external 1.0 V reference to the AD6679. The gray areas show
unused blocks within the AD6679 while the ADR130 provides
the external reference.
INPUT
100Ω
CLK–
CLOCK INPUT
0.9998
CLK+
LVDS
DRIVER
13059-053
1.0001
V_1P0
0.1µF
FULL-SCALE
CONTROL
Figure 55. External Reference Using the ADR130
Rev. B | Page 33 of 81
13059-054
V_1P0 VOLTAGE (V)
ADC
CLK–
13059-051
Register 0x024 enables the user to use either this internal 1.0 V
reference, or to provide an external 1.0 V reference. When using
an external voltage reference, provide a 1.0 V reference. The
full-scale adjustment is made using the SPI, irrespective of the
reference voltage. For more information on adjusting the fullscale level of the AD6679, refer to the Memory Map Register
Table section.
AD6679
Data Sheet
Input Clock Divider
Clock Jitter Considerations
The AD6679 contains an input clock divider with the ability to
divide the Nyquist input clock by 1, 2, 4, or 8. The divide ratio
can be selected using Register 0x10B. This is shown in Figure 56.
The maximum frequency at the output of the divider is 500 MHz.
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) is calculated by
The maximum frequency at the CLK± inputs is 4 GHz. This is
the limit of the divider. In applications where the clock input is
a multiple of the sample clock, take care to program the
appropriate divider ratio into the clock divider before applying
the clock signal. This ensures that the current transients during
device startup are controlled.
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 57).
SNR = 20 × log10(2 × π × fA × tJ)
130
RMS CLOCK JITTER REQUIREMENT
120
CLK+
110
÷2
100
16 BITS
÷4
90
14 BITS
SNR (dB)
REG 0x10B
13059-055
÷8
80
12 BITS
70
10 BITS
60
Figure 56. Clock Divider Circuit
8 BITS
50
The AD6679 clock divider can be synchronized using the
external SYNC± input. A valid SYNC± input causes the clock
divider to reset to a programmable state. This feature is enabled
by setting Bit 7 of Register 0x10D. This synchronization feature
allows multiple devices to have their clock dividers aligned to
guarantee simultaneous input sampling.
After programming the desired clock divider settings, changing
the input clock frequency or glitching the input clock a datapath
soft reset is recommended by writing 0x02 to Register 0x001.
This reset function restarts all the datapath and clock generation
circuitry in the device. The reset occurs on the first clock cycle
after the register is programmed, and the device requires 5 ms
to recover. This reset does not affect the contents of the memory
map registers.
Input Clock Divider ½ Period Delay Adjustment
The input clock divider inside the AD6679 provides phase delay
in increments of ½ the input clock cycle. Program Register 0x10C
to enable this delay independently for each channel.
40
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
30
1
10
100
ANALOG INPUT FREQUENCY (MHz)
1000
13059-056
CLK–
Figure 57. Ideal SNR vs. Analog Input Frequency and Jitter
Treat the clock input as an analog signal when aperture jitter
may affect the dynamic range of the AD6679. Separate the power
supplies for the clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
If the clock is generated from another type of source (by gating,
dividing, or other methods), retime it using the original clock at
the last step. See the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
Figure 58 shows the estimated SNR of the AD6679 across input
frequency for different clock induced jitter values. Estimate the
SNR by using the following equation:
Clock Fine Delay Adjustment
To adjust the AD6679 sampling edge instant, write to Register
0x117 and Register 0x118. Setting Bit 0 of Register 0x117 enables
the fine delay feature, and Register 0x118, Bits[7:0], set the value
of the delay. This value can be programmed individually for each
channel. The clock delay can be adjusted from −151.7 ps to
+150 ps in ~1.7 ps increments. The clock delay adjustment
takes effect immediately when it is enabled via SPI writes.
Enabling the clock fine delay adjustment in Register 0x117
causes a datapath reset.
Rev. B | Page 34 of 81
− SNR JITTER
− SNR ADC
10
SNR(dBFS) = 10log 10
+ 10 10
Data Sheet
AD6679
The temperature diode voltage can be output to the FD_A pin
using the SPI. Use Register 0x028, Bit 0, to enable or disable the
diode. Register 0x028 is a local register. Channel A must be
selected in the device index register (Register 0x008) to enable
the temperature diode readout. Configure the FD_A pin to
output the diode voltage by programming Register 0x040,
Bits[2:0]. See Table 41 for more information.
75
70
25fs
50fs
75fs
100fs
125fs
150fs
175fs
200fs
60
55
The voltage response of the temperature diode (with SPIVDD =
1.8 V) is shown in Figure 59.
0.90
100M
10M
1G
10G
INPUT FREQUENCY (Hz)
Figure 58. Estimated SNR Degradation for the AD6679 vs.
Input Frequency and Jitter
POWER-DOWN/STANDBY MODE
The AD6679 has a PDWN/STBY pin that configures the device
in power-down or standby mode. The default operation is the
power-down function. The PDWN/STBY pin is a logic high
pin. The power-down option can also be set via Register 0x03F
and Register 0x040.
TEMPERATURE DIODE VOLTAGE (V)
45
1M
13059-057
50
TEMPERATURE DIODE
0.85
0.80
0.75
0.70
0.65
0.60
–55 –45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105 115 125
TEMPERATURE (°C)
The AD6679 contains a diode-based temperature sensor for
measuring the temperature of the die. This diode can output a
voltage and serve as a coarse temperature sensor to monitor the
internal die temperature.
Rev. B | Page 35 of 81
Figure 59. Temperature Diode Voltage vs. Temperature
13059-058
SNR (dBFS)
65
AD6679
Data Sheet
VIRTUAL CONVERTER MAPPING
To support the different application layer modes, the AD6679
treats each sample stream (real or I or Q) as originating from
separate virtual converters. Table 12 shows the number of
virtual converters required for each chip mode.
The AD6679 contains a configurable signal path that allows
different features to be enabled for different applications. These
features are controlled through the chip application mode
register (0x200). The chip operating mode is controlled by
Bits[3:0] and the Chip Q ignore is controlled by Bit 5.
The AD6679 supports up to four digital DDC blocks. Each
DDC block outputs either two sample streams (I/Q) for the
complex data components (real + imaginary) or one sample
stream for real (I) data. The AD6679 can be configured to use up
to eight virtual converters depending on the DDC configuration.
Figure 60 shows the virtual converters and their relationship to
DDC outputs when complex outputs are used.
The AD6679 contains the following digital features:
•
•
•
•
Two analog-to-digital converter (ADC) cores
Four digital downconverter (DDC) channels
Two noise shaped requantizer (NSR) blocks with optional
decimate by two blocks
Two variable dynamic range (VDR) blocks
Table 12 shows the virtual converter mapping for each chip
operating mode when channel swapping is disabled.
After the chip application mode has been selected, the output
decimation ratio is set using the chip decimation ratio in
Register 0x201, Bits[2:0]. The output sample rate is the ADC
sample rate divided by the chip decimation ratio.
Table 12. Virtual Converter Mapping
No. of
Virtual
Converters
Supported
1
Chip
Operating
Mode
(Register
0x200[3:0])
One DDC
mode (0x1)
2
One DDC
mode (0x1)
2
Two DDC
mode (0x2)
4
Two DDC
mode (0x2)
4
Four DDC
mode (0x3)
8
Four DDC
mode (0x3)
1 to 2
NSR mode
(0x7)
1 to 2
VDR mode
(0x8)
1
Chip Q
Ignore
(Register
0x200[5])
Real
(I only)
(0x1)
Complex
(I/Q)
(0x0)
Real
(I only)
(0x1)
Complex
(I/Q)
(0x0)
Real
(I only)
(0x1)
Complex
(I/Q)
(0x0)
Real or
complex
(0x0)
Real or
complex
(0x0)
Virtual Converter Mapping1
0
DDC 0
I samples
1
N/A
2
N/A
3
N/A
4
N/A
5
N/A
6
N/A
7
N/A
DDC 0
I samples
DDC 0
Q samples
N/A
N/A
N/A
N/A
N/A
N/A
DDC 0
I samples
DDC 1
I samples
N/A
N/A
N/A
N/A
N/A
N/A
DDC 0
I samples
DDC 0
Q samples
DDC 1
I samples
DDC 1
Q samples
N/A
N/A
N/A
N/A
DDC 0
I samples
DDC 1
I samples
DDC 2
I samples
DDC 3
I samples
N/A
N/A
N/A
N/A
DDC 0
I samples
DDC 0
Q samples
DDC 1
I samples
DDC 1
Q samples
DDC 2
I samples
DDC 2
Q samples
DDC 3
I samples
DDC 3
Q samples
ADC A
samples
ADC B
samples
N/A
N/A
N/A
N/A
N/A
N/A
ADC A
samples
ADC B
samples
N/A
N/A
N/A
N/A
N/A
N/A
N/A means not applicable.
Rev. B | Page 36 of 81
Data Sheet
AD6679
ADC A
SAMPLING
AT fS
REAL/I
REAL/Q
REAL/I
REAL/Q
I/Q
CROSSBAR
MUX
REAL/I
REAL/Q
REAL/Q
ADC B
SAMPLING
AT fS
REAL/I
REAL/Q
DDC 0
I
I
Q
Q
DDC 1
I
I
Q
Q
DDC 2
I
I
Q
Q
DDC 3
I
I
Q
Q
REAL/I
CONVERTER 0
Q
CONVERTER 1
REAL/I
CONVERTER 2
Q
CONVERTER 3
REAL/I
CONVERTER 4
Q
CONVERTER 5
REAL/I
CONVERTER 6
Q
CONVERTER 7
Figure 60. DDCs and Virtual Converter Mapping
Rev. B | Page 37 of 81
OUTPUT
INTERFACE
13059-159
REAL/I
AD6679
Data Sheet
ADC OVERRANGE AND FAST DETECT
The operation of the upper threshold and lower threshold registers,
along with the dwell time registers, is shown in Figure 61.
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overrange bit, available via the STATUS±/OVR±
pins, provides information on the state of the analog input
that is of limited usefulness. Therefore, it is helpful to have a
programmable threshold below full scale that allows time to
reduce the gain before the clip actually occurs. In addition,
because input signals can have significant slew rates, the latency
of this function is of major concern. Highly pipelined converters
can have significant latency. The AD6679 contains fast detect
circuitry for individual channels to monitor the threshold and
assert the FD_A and FD_B pins.
The FD_x indicator is asserted if the input magnitude exceeds
the value programmed in the fast detect upper threshold
registers, located in Register 0x247 and Register 0x248. The
selected threshold register is compared with the signal
magnitude at the output of the ADC. The fast upper threshold
detection has a latency of 28 clock cycles. The approximate
upper threshold magnitude is defined by
Upper Threshold Magnitude (dBFS) = 20log(Threshold
Magnitude/213)
The FD_x indicators are not cleared until the signal drops
below the lower threshold for the programmed dwell time. The
lower threshold is programmed in the fast detect lower threshold registers, located in Register 0x249 and Register 0x24A. The
fast detect lower threshold register is a 13-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to the ADC pipeline latency but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange indicator can
be output via the STATUS± pins. The latency of this overrange
indicator matches the sample latency.
The AD6679 constantly monitors the analog input level and
records any overrange condition in any of the eight virtual
converters. For more information on the virtual converters,
refer to Figure 63. The overrange status of each virtual converter
is registered as a sticky bit (that is, it is set until cleared) in
Register 0x563. The contents of Register 0x563 can be cleared
using Register 0x562 by toggling the bits corresponding to the
virtual converter to set and reset the position.
Lower Threshold Magnitude (dBFS) = 20log(Threshold
Magnitude/213)
For example, to set an upper threshold of −6 dBFS, write
0x0FFF to Register 0x247 and Register 0x248; and to set a lower
threshold of −10 dBFS, write 0x0A1D to Register 0x249 and
Register 0x24A.
FAST THRESHOLD DETECTION (FD_A AND FD_B)
The fast detect (FD) bit (enabled in the control bits via
Register 0x559) is set whenever the absolute value of the input
signal exceeds the programmable upper threshold level. The FD
bit is cleared only when the absolute value of the input signal
drops below the lower threshold level for greater than the
programmable dwell time. This feature provides hysteresis and
prevents the FD bit from excessively toggling.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located in Register 0x24B and Register 0x24C.
See the Memory Map section (Register 0x245 to Register 0x24C in
Table 41) for more details.
UPPER THRESHOLD
DWELL TIME
TIMER RESET BY
RISE ABOVE
LOWER
THRESHOLD
DWELL TIME
FD_A OR FD_B
Figure 61. Threshold Settings for FD_A and FD_B Signals
Rev. B | Page 38 of 81
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE
LOWER THRESHOLD
13059-059
MIDSCALE
LOWER THRESHOLD
Data Sheet
AD6679
SIGNAL MONITOR
The signal monitor block provides additional information about
the signal being digitized by the ADC. The signal monitor
computes the peak magnitude of the digitized signal. This
information can be used to drive an AGC loop to optimize the
range of the ADC in the presence of real-world signals.
The results of the signal monitor block can be obtained by
reading back the internal values from the SPI port. A global, 24bit programmable period controls the duration of the measurement. Figure 62 shows the simplified block diagram of the
signal monitor block.
The peak detector captures the largest signal within the
observation period. This period observes only the magnitude of
the signal. The resolution of the peak detector is a 13-bit value
and the observation period is 24 bits and represents converter
output samples. The peak magnitude is derived by using the
following equation:
Peak Magnitude (dBFS) = 20 log(Peak Detector Value/213)
The magnitude of the input port signal is monitored over a
programmable time period that is determined by the signal
monitor period registers (SMPRs). Only even values of the
SIGNAL MONITOR
PERIOD REGISTER
(SMPR)
REG 0x271, REG 0x272, REG 0x273
After enabling this mode, the value in the SMPR is loaded into a
monitor period timer that decrements at the decimated clock
rate. The magnitude of the input signal is compared with the
value in the internal magnitude storage register (not accessible
to the user), and the greater of the two is updated as the current
peak level. The initial value of the magnitude storage register is
set to the current ADC input signal magnitude. This comparison
continues until the monitor period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding
register, which can be read through the memory map. The
monitor period timer is reloaded with the value in the SMPR,
and the countdown is restarted. In addition, the magnitude of
the first input sample is updated in the internal magnitude
storage register, and the comparison and update procedure, as
explained previously, continues.
DOWN
COUNTER
IS
COUNT = 1?
LOAD
CLEAR
FROM
INPUT
MAGNITUDE
STORAGE
REGISTER
LOAD
LOAD
SIGNAL
MONITOR
HOLDING
REGISTER
COMPARE
A>B
Figure 62. Signal Monitor Block
Rev. B | Page 39 of 81
TO STATUS± PINS
AND MEMORY MAP
13059-060
FROM
MEMORY
MAP
SMPR are supported. The peak detector function is enabled by
setting Bit 1 of Register 0x270 in the signal monitor control
register. The 24-bit SMPR must be programmed before
activating this mode.
AD6679
Data Sheet
DIGITAL DOWNCONVERTER (DDC)
The AD6679 includes four digital downconverters (DDCs) that
provide filtering and reduce the output data rate. This digital
processing section includes an NCO, up to four half-band
decimating filter, a finite impulse response (FIR) filter, a gain
stage, and a complex to real conversion stage. Each of these
processing blocks has control lines that allow it to be
independently enabled and disabled to provide the desired
processing function. The DDC can be configured to output
either real data or complex output data.
DDC I/Q INPUT SELECTION
The AD6679 has two ADC channels and four DDC channels.
Each DDC channel has two input ports that can be paired to
support both real and complex inputs through the I/Q crossbar
mux. For real signals, both DDC input ports must select the
same ADC channel (that is, DDC Input Port I = ADC Channel A
and DDC Input Port Q = ADC Channel A). For complex signals,
each DDC input port must select different ADC channels (that
is, DDC Input Port I = ADC Channel A and DDC Input Port Q
= ADC Channel B).
The inputs to each DDC are controlled by the DDC input selection registers (Register 0x311, Register 0x331, Register 0x351, and
Register 0x371). See Table 41 for information on how to
configure the DDCs.
DDC I/Q OUTPUT SELECTION
Each DDC channel has two output ports that can be paired to
support both real and complex outputs. For real output signals,
only the DDC Output Port I is used (the DDC Output Port Q is
invalid). For complex I/Q output signals, both DDC Output
Port I and DDC Output Port Q are used.
The I/Q outputs to each DDC channel are controlled by the
DDC complex to real enable bit, Bit 3, in the DDC control
registers (Register 0x310, Register 0x330, Register 0x350, and
Register 0x370).
The Chip Q ignore bit in the chip mode register (Register 0x200,
Bit 5) controls the chip output muxing of all the DDC channels.
When all DDC channels use real outputs, set this bit high to
ignore all DDC Q output ports. When any of the DDC channels
are set to use complex I/Q outputs, the user must clear this bit
to use both DDC Output Port I and DDC Output Port Q. For
more information, see Figure 71.
DDC GENERAL DESCRIPTION
The four DDC blocks extract a portion of the full digital
spectrum captured by the ADC(s). They are intended for IF
sampling or oversampled baseband radios requiring wide
bandwidth input signals.
Each DDC block contains the following signal processing
stages:
Frequency translation stage (optional)
Filtering stage
Gain stage (optional)
Complex to real conversion stage (optional)
Frequency Translation Stage (Optional)
This stage consists of a 12-bit complex NCO and quadrature
mixers that can be used for frequency translation of both real
and complex input signals. This stage shifts a portion of the
available digital spectrum down to baseband.
Filtering Stage
After shifting down to baseband, this stage decimates the
frequency spectrum using a chain of up to four half-band lowpass filters for rate conversion. The decimation process lowers
the output data rate, which, in turn, reduces the output interface
rate.
Gain Stage (Optional)
Due to losses associated with mixing a real input signal down to
baseband, this stage compensates by adding an additional 0 dB
or 6 dB of gain.
Complex to Real Conversion Stage (Optional)
When real outputs are necessary, this stage converts the
complex outputs back to real outputs by performing an fS/4
mixing operation together with a filter to remove the complex
component of the signal.
Figure 63 shows the detailed block diagram of the DDCs
implemented in the AD6679.
Rev. B | Page 40 of 81
Data Sheet
AD6679
GAIN = 0dB
OR 6dB
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
HB1 FIR
DCM = 2
GAIN = 0dB
OR 6dB
ADC
SAMPLING
AT fS
GAIN = 0dB
OR 6dB
REAL/I
GAIN = 0dB
OR 6dB
REAL/Q Q
HB2 FIR
DCM = BYPASS OR 2
NCO
+
MIXER
(OPTIONAL)
HB3 FIR
DCM = BYPASS OR 2
I
HB4 FIR
DCM = BYPASS OR 2
DDC 0
REAL/I
REAL/I
CONVERTER 0
Q CONVERTER 1
SYNC±
Q CONVERTER 3
HB1 FIR
DCM = 2
SYNC±
REAL/Q Q
ADC
SAMPLING
AT fS
HB1 FIR
DCM = 2
HB2 FIR
DCM = BYPASS OR 2
I
HB3 FIR
DCM = BYPASS OR 2
DDC 2
REAL/I
NCO
+
MIXER
(OPTIONAL)
REAL/I
REAL/I
CONVERTER 2
REAL/I
CONVERTER 4
OUTPUT INTERFACE
REAL/Q Q
HB2 FIR
DCM = BYPASS OR 2
NCO
+
MIXER
(OPTIONAL)
HB3 FIR
DCM = BYPASS OR 2
I
HB4 FIR
DCM = BYPASS OR 2
I/Q CROSSBAR MUX
REAL/I
HB4 FIR
DCM = BYPASS OR 2
DDC 1
Q CONVERTER 5
SYNC±
SYNC±
SYNCHRONIZATION
CONTROL CIRCUITS
HB1 FIR
DCM = 2
REAL/I
CONVERTER 6
Q CONVERTER 7
13059-061
REAL/Q Q
HB2 FIR
DCM = BYPASS OR 2
NCO
+
MIXER
(OPTIONAL)
HB3 FIR
DCM = BYPASS OR 2
I
HB4 FIR
DCM = BYPASS OR 2
DDC 3
REAL/I
SYNC
Figure 63. DDC Detailed Block Diagram
Figure 64 shows an example usage of one of the four DDC
blocks with a real input signal and four half-band filters (HB4 +
HB3 + HB2 + HB1). It shows both complex (decimate by 16)
and real (decimate by 8) output options.
When DDCs have different decimation ratios, the chip
decimation ratio (Register 0x201) must be set to the lowest
decimation ratio of all the DDC blocks. In this scenario,
samples of higher decimation ratio DDCs are repeated to match
the chip decimation ratio sample rate. Whenever the NCO
frequency is set or changed, the DDC soft reset must be issued.
If the DDC soft reset is not issued, the output may potentially
show amplitude variations.
Table 13 through Table 17 show the DDC samples when the
chip decimation ratio is set to 1, 2, 4, 8, or 16, respectively.
When DDCs have different decimation ratios, the chip decimation
ratio must be set to the lowest decimation ratio of all the DDC
channels. In this scenario, samples of higher decimation ratio
DDCs are repeated to match the chip decimation ratio sample
rate.
Rev. B | Page 41 of 81
AD6679
Data Sheet
ADC
ADC
SAMPLING
AT fS
REAL
REAL INPUT—SAMPLED AT fS
BANDWIDTH OF
INTEREST IMAGE
–fS/2
–fS/3
–fS/4
REAL
BANDWIDTH OF
INTEREST
–fS/32
fS/32
DC
fS/16
–fS/16
–fS/8
FREQUENCY TRANSLATION STAGE (OPTIONAL)
DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY
TUNING WORD = ROUND ((fS/3)/fS × 4096) = +1365 (0x555)
fS/8
fS/4
fS/3
fS/2
I
NCO TUNES CENTER OF
BANDWIDTH OF INTEREST
TO BASEBAND
cos(wt)
REAL
12-BIT
NCO
90°
0°
–sin(wt)
Q
DIGITAL FILTER
RESPONSE
–fS/2
–fS/3
–fS/4
–fS/32
fS/32
DC
fS/16
–fS/16
–fS/8
BANDWIDTH OF
INTEREST IMAGE
(–6dB LOSS DUE TO
NCO + MIXER)
BANDWIDTH OF INTEREST
(–6dB LOSS DUE TO
NCO + MIXER)
fS/8
fS/4
fS/3
fS/2
FILTERING STAGE
HB4 FIR
4 DIGITAL HALF-BAND FILTERS
(HB4 + HB3 + HB2 + HB1)
I
HALFBAND
FILTER
Q
HALFBAND
FILTER
HB3 FIR
2
HALFBAND
FILTER
2
HALFBAND
FILTER
HB4 FIR
HB2 FIR
2
HALFBAND
FILTER
2
HALFBAND
FILTER
HB3 FIR
HB1 FIR
2
HB2 FIR
HALFBAND
FILTER
I
HB1 FIR
2
HALFBAND
FILTER
Q
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
COMPLEX (I/Q) OUTPUTS
GAIN STAGE (OPTIONAL)
DIGITAL FILTER
RESPONSE
I
GAIN STAGE (OPTIONAL)
Q
0dB OR 6dB GAIN
COMPLEX TO REAL
CONVERSION STAGE (OPTIONAL)
fS/4 MIXING + COMPLEX FILTER TO REMOVE Q
–fS/32
fS/32
DC
fS/16
–fS/16
–fS/8
I
REAL (I) OUTPUTS
+6dB
+6dB
fS/8
2
+6dB
2
+6dB
I
Q
–fS/32
fS/32
DC
–fS/16
fS/16
DOWNSAMPLE BY 2
I
DECIMATE BY 8
Q
DECIMATE BY 16
0dB OR 6dB GAIN
Q
COMPLEX REAL/I
TO
REAL
–fS/8
–fS/32
fS/32
DC
–fS/16
fS/16
fS/8
Figure 64. DDC Theory of Operation Example (Real Input, Decimate by 16)
Rev. B | Page 42 of 81
13059-062
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
Data Sheet
AD6679
Table 13. DDC Samples When Chip Decimation Ratio = 1
HB1 FIR
(DCM 1 =
1)
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 16
N + 17
N + 18
N + 19
N + 20
N + 21
N + 22
N + 23
N + 24
N + 25
N + 26
N + 27
N + 28
N + 29
N + 30
N + 31
1
Real (I) Output (Complex to Real Enabled)
HB3 FIR + HB2
HB4 FIR + HB3 FIR +
HB2 FIR +
FIR + HB1 FIR
HB2 FIR + HB1 FIR
HB1 FIR
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 2)
N
N
N
N+1
N+1
N+1
N
N
N
N+1
N+1
N+1
N+2
N
N
N+3
N+1
N+1
N+2
N
N
N+3
N+1
N+1
N+4
N+2
N
N+5
N+3
N+1
N+4
N+2
N
N+5
N+3
N+1
N+6
N+2
N
N+7
N+3
N+1
N+6
N+2
N
N+7
N+3
N+1
N+8
N+4
N+2
N+9
N+5
N+3
N+8
N+4
N+2
N+9
N+5
N+3
N + 10
N+4
N+2
N + 11
N+5
N+3
N + 10
N+4
N+2
N + 11
N+5
N+3
N + 12
N+6
N+2
N + 13
N+7
N+3
N + 12
N+6
N+2
N + 13
N+7
N+3
N + 14
N+6
N+2
N + 15
N+7
N+3
N + 14
N+6
N+2
N + 15
N+7
N+3
Complex (I/Q) Outputs (Complex to Real Disabled)
HB2 FIR +
HB3 FIR + HB2
HB4 FIR + HB3 FIR +
HB1 FIR
HB1 FIR
FIR + HB1 FIR
HB2 FIR + HB1 FIR
(DCM1 = 2) (DCM1 = 4)
(DCM1 = 8)
(DCM1 = 16)
N
N
N
N
N+1
N+1
N+1
N+1
N
N
N
N
N+1
N+1
N+1
N+1
N+2
N
N
N
N+3
N+1
N+1
N+1
N+2
N
N
N
N+3
N+1
N+1
N+1
N+4
N+2
N
N
N+5
N+3
N+1
N+1
N+4
N+2
N
N
N+5
N+3
N+1
N+1
N+6
N+2
N
N
N+7
N+3
N+1
N+1
N+6
N+2
N
N
N+7
N+3
N+1
N+1
N+8
N+4
N+2
N
N+9
N+5
N+3
N+1
N+8
N+4
N+2
N
N+9
N+5
N+3
N+1
N + 10
N+4
N+2
N
N + 11
N+5
N+3
N+1
N + 10
N+4
N+2
N
N + 11
N+5
N+3
N+1
N + 12
N+6
N+2
N
N + 13
N+7
N+3
N+1
N + 12
N+6
N+2
N
N + 13
N+7
N+3
N+1
N + 14
N+6
N+2
N
N + 15
N+7
N+3
N+1
N + 14
N+6
N+2
N
N + 15
N+7
N+3
N+1
DCM means decimation.
Table 14. DDC Samples When Chip Decimation Ratio = 2
Real (I) Output (Complex to Real Enabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
(DCM 1 = 2)
(DCM1 = 4)
(DCM1 = 8)
N
N
N
N+1
N+1
N+1
N+2
N
N
N+3
N+1
N+1
N+4
N+2
N
N+5
N+3
N+1
N+6
N+2
N
N+7
N+3
N+1
N+8
N+4
N+2
N+9
N+5
N+3
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 16)
N
N
N
N
N+1
N+1
N+1
N+1
N+2
N
N
N
N+3
N+1
N+1
N+1
N+4
N+2
N
N
N+5
N+3
N+1
N+1
N+6
N+2
N
N
N+7
N+3
N+1
N+1
N+8
N+4
N+2
N
N+9
N+5
N+3
N+1
Rev. B | Page 43 of 81
AD6679
Data Sheet
Real (I) Output (Complex to Real Enabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
(DCM 1 = 2)
(DCM1 = 4)
(DCM1 = 8)
N + 10
N+4
N+2
N + 11
N+5
N+3
N + 12
N+6
N+2
N + 13
N+7
N+3
N + 14
N+6
N+2
N + 15
N+7
N+3
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 16)
N + 10
N+4
N+2
N
N + 11
N+5
N+3
N+1
N + 12
N+6
N+2
N
N + 13
N+7
N+3
N+1
N + 14
N+6
N+2
N
N + 15
N+7
N+3
N+1
DCM means decimation.
Table 15. DDC Samples When Chip Decimation Ratio = 4
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR +
HB3 FIR + HB2 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 8)
HB1 FIR (DCM 1 = 4)
N
N
N+1
N+1
N+2
N
N+3
N+1
N+4
N+2
N+5
N+3
N+6
N+2
N+7
N+3
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
HB3 FIR + HB2 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 4)
HB1 FIR (DCM1 = 8)
(DCM1 = 16)
N
N
N
N+1
N+1
N+1
N+2
N
N
N+3
N+1
N+1
N+4
N+2
N
N+5
N+3
N+1
N+6
N+2
N
N+7
N+3
N+1
DCM means decimation.
Table 16. DDC Samples When Chip Decimation Ratio = 8
Real (I) Output (Complex to Real Enabled)
Complex (I/Q) Outputs (Complex to Real Disabled)
HB3 FIR + HB2 FIR + HB1 FIR
HB4 FIR + HB3 FIR + HB2 FIR +
(DCM1 = 8)
HB1 FIR (DCM1 = 16)
N
N
N+1
N+1
N+2
N
N+3
N+1
N+4
N+2
N+5
N+3
N+6
N+2
N+7
N+3
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 8)
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
1
DCM means decimation.
Table 17. DDC Samples When Chip Decimation Ratio = 16
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 16)
Not applicable
Not applicable
Not applicable
Not applicable
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)
N
N+1
N+2
N+3
DCM means decimation.
Rev. B | Page 44 of 81
Data Sheet
AD6679
For example, if the chip decimation ratio is set to decimate by 4,
DDC 0 is set to use HB2 + HB1 filters (complex outputs, decimate
by 4) and DDC 1 is set to use HB4 + HB3 + HB2 + HB1 filters
(real outputs, decimate by 8). DDC 1 repeats its output data two
times for every one DDC 0 output. The resulting output samples
are shown in Table 18.
Table 18. DDC Output Samples When Chip DCM 1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real)
DDC Input Samples
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
1
Output Port I
I0 (N)
DDC 0
Output Port Q
Q0 (N)
I0 (N + 1)
Q0 (N + 1)
I0 (N + 2)
Q0 (N + 2)
I0 (N + 3)
Q0 (N + 3)
DCM means decimation.
Rev. B | Page 45 of 81
Output Port I
I1 (N)
I1 (N + 1)
DDC 1
Output Port Q
Not applicable
Not applicable
AD6679
Data Sheet
FREQUENCY TRANSLATION
GENERAL DESCRIPTION
Variable IF Mode
Frequency translation is accomplished by using a 12-bit
complex NCO with a digital quadrature mixer. This stage
translates either a real or complex input signal from an IF to a
baseband complex digital output (carrier frequency = 0 Hz).
The NCO and the mixers are enabled. The NCO output
frequency can be used to digitally tune the IF frequency.
0 Hz IF (ZIF) Mode
The mixers are bypassed, and the NCO is disabled.
The frequency translation stage of each DDC can be controlled
individually and supports four different IF modes using Bits[5:4]
of the DDC control registers (Register 0x310, Register 0x330,
Register 0x350, and Register 0x370). These IF modes are
The mixers and the NCO are enabled in a special downmixing
by fS/4 mode to save power.
Test Mode
Variable IF mode
0 Hz IF, or zero IF (ZIF), mode
fS/4 Hz IF mode
Test mode
The input samples are forced to 0.999 to positive full scale. The
NCO is enabled. This test mode allows the NCOs to drive the
decimation filters directly.
Figure 65 and Figure 66 show examples of the frequency
translation stage for both real and complex inputs.
NCO FREQUENCY TUNING WORD (FTW) SELECTION
12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096
I
ADC + DIGITAL MIXER + NCO
REAL INPUT—SAMPLED AT fS
REAL
cos(wt)
ADC
SAMPLING
AT fS
REAL
12-BIT
NCO
90°
0°
COMPLEX
–sin(wt)
Q
BANDWIDTH OF
INTEREST
BANDWIDTH OF
INTEREST IMAGE
–fS/2
–fS/3
–fS/4
–fS/8
fS/32
–fS/32
DC
–fS/16
fS/16
fS/8
fS/4
fS/3
fS/2
–6dB LOSS DUE TO
NCO + MIXER
12-BIT NCO FTW =
ROUND ((fS/3)/fS × 4096) = +1365 (0x555)
POSITIVE FTW VALUES
–fS/32
DC
fS/32
12-BIT NCO FTW =
ROUND ((fS/3)/fS × 4096) = –1365 (0xAAB)
–fS/32
NEGATIVE FTW VALUES
DC
fS/32
Figure 65. DDC NCO Frequency Tuning Word Selection—Real Inputs
Rev. B | Page 46 of 81
13059-063
fS/4 Hz IF Mode
Data Sheet
AD6679
NCO FREQUENCY TUNING WORD (FTW) SELECTION
12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096
QUADRATURE ANALOG MIXER +
2 ADCs + QUADRATURE DIGITAL REAL
MIXER + NCO
COMPLEX INPUT—SAMPLED AT fS
QUADRATURE MIXER
ADC
SAMPLING
AT fS
I
+
I
I
Q
Q
90°
PHASE
12-BIT
NCO
90°
0°
Q
Q
ADC
SAMPLING
AT fS
Q
Q
I
I
–
–sin(wt)
I
I
+
COMPLEX
Q
+
BANDWIDTH OF
INTEREST
IMAGE DUE TO
ANALOG I/Q
MISMATCH
–fS/3
–fS/4
–fS/32
fS/32
–fS/16
fS/16
DC
–fS/8
fS/8
fS/4
fS/3
fS/2
12-BIT NCO FTW =
ROUND ((fS/3)/fS × 4096) = +1365 (0x555)
POSITIVE FTW VALUES
–fS/32
fS/32
13059-064
–fS/2
DC
Figure 66. DDC NCO Frequency Tuning Word Selection—Complex Inputs
DDC NCO PLUS MIXER LOSS AND SFDR
Setting Up the NCO FTW and POW
When mixing a real input signal down to baseband, 6 dB of loss
is introduced in the signal due to filtering of the negative image.
The NCO introduces an additional 0.05 dB of loss. The total
loss of a real input signal mixed down to baseband is 6.05 dB.
For this reason, it is recommended to compensate for this loss
by enabling the 6 dB of gain in the gain stage of the DDC to
recenter the dynamic range of the signal within the full scale of
the output bits.
The NCO frequency value is given by the 12-bit, twos
complement number entered in the NCO FTW. Frequencies
between −fS/2 and +fS/2 (fS/2 excluded) are represented using
the following frequency words:
When mixing a complex input signal down to baseband, the
maximum value each I/Q sample can reach is 1.414 × full scale
after it passes through the complex mixer. To avoid an
overrange of the I/Q samples and to keep the data bit-widths
aligned with real mixing, 3.06 dB of loss is introduced in the
mixer for complex signals. The NCO introduces an additional
0.05 dB of loss. The total loss of a complex input signal mixed
down to baseband is −3.11 dB.
The worst case spurious signal from the NCO is greater than
102 dBc SFDR for all output frequencies.
NUMERICALLY CONTROLLED OSCILLATOR
The AD6679 has a 12-bit NCO for each DDC that enables the
frequency translation process. The NCO allows the input
spectrum to be tuned to dc, where it can be effectively filtered
by the subsequent filter blocks to prevent aliasing. The NCO
can be set up by providing a frequency tuning word (FTW) and
a phase offset word (POW).
0x800 represents a frequency of −fS/2.
0x000 represents dc (frequency is 0 Hz).
0x7FF represents a frequency of +fS/2 − fS/212.
Calculate the NCO frequency tuning word using the following
equation:
mod f C , f S
NCO _ FTW round 2 12
fS
where:
NCO_FTW is a 12-bit, twos complement number representing
the NCO FTW.
fC is the desired carrier frequency in Hz.
fS is the AD6679 sampling frequency (clock rate) in Hz.
mod( ) is a remainder function. For example, mod(110,100) =
10 and for negative numbers, mod(−32,10) = −2.
round( ) is a rounding function. For example, round(3.6) = 4
and for negative numbers, round(−3.4) = −3.
Note that this equation applies to the aliasing of signals in the
digital domain (that is, aliasing introduced when digitizing
analog signals).
Rev. B | Page 47 of 81
AD6679
Data Sheet
For example, if the ADC sampling frequency (fS) is 500 MSPS
and the carrier frequency (fC) is 140.312 MHz, then
Use the following two methods to synchronize multiple PAWs
within the chip:
mod140.312,500
NCO _ FTW round 212
1149 MHz
500
This, in turn, converts to 0x47D in the 12-bit twos complement
representation for NCO_FTW. Calculate the actual carrier
frequency, fC_ACTUAL, based on the following equation:
fC _ ACTUAL
NCO_ FTW f S
140.26 MHz
212
A 12-bit POW is available for each NCO to create a known
phase relationship between multiple AD6679 chips or
individual DDC channels inside one AD6679 chip.
The following procedure must be followed to update the FTW
and/or POW registers to ensure proper operation of the NCO:
1.
2.
3.
Write to the FTW registers for all the DDCs.
Write to the POW registers for all the DDCs.
Synchronize the NCOs either through the DDC NCO soft
reset bit (Register 0x300, Bit 4), accessible through the SPI
or through the assertion of the SYNC± pin.
It is important to note that the NCOs must be synchronized
either through the SPI or through the SYNC± pin after all
writes to the FTW or POW registers are complete. This
synchronization is necessary to ensure the proper operation
of the NCO.
NCO Synchronization
Each NCO contains a separate phase accumulator word (PAW)
that determines the instantaneous phase of the NCO. The initial
reset value of each PAW is determined by the POW. The phase
increment value of each PAW is determined by the FTW. See
the Setting Up the NCO FTW and POW section for more
information.
Using the SPI. Use the DDC NCO soft reset bit in the DDC
synchronization control register (Register 0x300, Bit 4) to
reset all the PAWs in the chip. This is accomplished by
setting the DDC NCO soft reset bit high and then setting
this bit low. Note that this method synchronizes DDC
channels within the same AD6679 chip only.
Using the SYNC± pins. When the SYNC± pins are
enabled in the SYNC± control registers (Register 0x120
and Register 0x121) and the DDC synchronization is
enabled in the DDC synchronization control register
(Register 0x300, Bits[1:0]), any subsequent SYNC± event
resets all the PAWs in the chip. Note that this method
synchronizes DDC channels within the same AD6679 chip
or DDC channels within separate AD6679 chips.
Mixer
The NCO is accompanied by a mixer. Its operation is similar to
an analog quadrature mixer. It performs the downconversion of
input signals (real or complex) by using the NCO frequency as a
local oscillator. For real input signals, this mixer performs a real
mixer operation (with two multipliers). For complex input
signals, the mixer performs a complex mixer operation (with
four multipliers and two adders). The mixer adjusts its
operation based on the input signal (real or complex) provided
to each individual channel. The selection of real or complex
inputs can be controlled individually for each DDC block using
Bit 7 of the DDC control registers (Register 0x310, Register 0x330,
Register 0x350, and Register 0x370).
Rev. B | Page 48 of 81
Data Sheet
AD6679
FIR FILTERS
There are four sets of decimate by 2, low-pass, half-band, FIR
filters (labeled HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR in
Figure 63) following the frequency translation stage. After the
carrier of interest is tuned down to dc (carrier frequency =
0 Hz), these filters efficiently lower the sample rate, while
providing sufficient alias rejection from unwanted adjacent
carriers around the bandwidth of interest.
HB1 FIR is always enabled and cannot be bypassed. The HB2,
HB3, and HB4 FIR filters are optional and can be bypassed for
higher output sample rates.
Table 20 shows the different bandwidths selectable by including
different half-band filters. In all cases, the DDC filtering stage
on the AD6679 provides 100 dB of stop band alias rejection.
Table 21 shows the amount of stop-band alias rejection for
multiple pass-band ripple/cutoff points. The decimation ratio of
the filtering stage of each DDC can be controlled individually
through Bits[1:0] of the DDC control registers (Register 0x310,
Register 0x330, Register 0x350, and Register 0x370).
HALF-BAND FILTERS
tion that is optimized for low power consumption. The HB4
filter is used only when complex outputs (decimate by 16) or
real outputs (decimate by 8) are enabled; otherwise, it is
bypassed. Table 19 and Figure 67 show the coefficients and
response of the HB4 filter.
Table 19. HB4 Filter Coefficients
HB4 Coefficient
Number
C1, C11
C2, C10
C3, C9
C4, C8
C5, C7
C6
Normalized
Coefficient
0.006042
0
−0.049316
0
0.293273
0.500000
Decimal
Coefficient (15-Bit)
99
0
−808
0
4805
8192
0
–20
MAGNITUDE (dB)
OVERVIEW
The AD6679 offers four half-band filters to enable digital signal
processing of the ADC converted data. These half-band filters
are bypassable and can be individually selected.
–40
–60
–80
–100
0
0.1
The first decimate by 2, half-band, low-pass, FIR filter (HB4)
uses an 11-tap, symmetrical, fixed coefficient filter implementa-
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
NORMALIZED FREQUENCY (× π RAD/SAMPLE)
13059-065
–120
HB4 Filter
Figure 67. HB4 Filter Response
Table 20. DDC Filter Characteristics
ADC
Sample
Rate
(MSPS)
500
1
Half Band Filter
Selection
HB1
HB1 + HB2
HB1 + HB2 + HB3
HB1 + HB2 + HB3
+ HB4
Real Output
Output
DecimaSample Rate
(MSPS)
tion Ratio
1
500
2
250
4
125
8
62.5
Complex (I/Q) Output
DecimaOutput Sample
tion
Ratio
Rate (MSPS)
2
250 (I) + 250 (Q)
4
125 (I) + 125 (Q)
8
62.5 (I) + 62.5 (Q)
16
31.25 (I) + 31.25 (Q)
Alias
Protected
Bandwidth
(MHz)
192.5
96.3
48.1
24.1
Ideal SNR
Improvement 1 (dB)
1
4
7
10
PassBand
Ripple
(dB)
100
Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)).
Table 21. DDC Filter Alias Rejection
Alias Rejection
(dB)
>100
90
85
63.3
25
19.3
10.7
1
Pass-Band Ripple/Cutoff
Point (dB)
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