AD7224LR-18

a FEATURES 8-Bit CMOS DAC with Output Amplifiers Operates with Single or Dual Supplies Low Total Unadjusted Error: Less Than 1 LSB Over Temperature Extended Temperature Range Operation P-Compatible with Double Buffered Inputs Standard 18-Pin DIPs, and 20-Terminal Surface Mount Package and SOIC Package LC2MOS 8-Bit DAC with Output Amplifiers AD7224 FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7224 is a precision 8-bit voltage-output, digital-toanalog converter, with output amplifier and double buffered interface logic on a monolithic CMOS chip. No external trims are required to achieve full specified performance for the part. The double buffered interface logic consists of two 8-bit registers–an input register and a DAC register. Only the data held in the DAC registers determines the analog output of the converter. The double buffering allows simultaneous update in a system containing multiple AD7224s. Both registers may be made transparent under control of three external lines, CS, WR and LDAC. With both registers transparent, the RESET line functions like a zero override; a useful function for system calibration cycles. All logic inputs are TTL and CMOS (5 V) level compatible and the control logic is speed compatible with most 8-bit microprocessors. Specified performance is guaranteed for input reference voltages from +2 V to +12.5 V when using dual supplies. The part is also specified for single supply operation using a reference of +10 V. The output amplifier is capable of developing +10 V across a 2 kΩ load. The AD7224 is fabricated in an all ion-implanted high speed Linear Compatible CMOS (LC2MOS) process which has been specifically developed to allow high speed digital logic circuits and precision analog circuits to be integrated on the same chip. 1. DAC and Amplifier on CMOS Chip The single-chip design of the 8-bit DAC and output amplifier is inherently more reliable than multi-chip designs. CMOS fabrication means low power consumption (35 mW typical with single supply). 2. Low Total Unadjusted Error The fabrication of the AD7224 on Analog Devices Linear Compatible CMOS (LC2MOS) process coupled with a novel DAC switch-pair arrangement, enables an excellent total unadjusted error of less than 1 LSB over the full operating temperature range. 3. Single or Dual Supply Operation The voltage-mode configuration of the AD7224 allows operation from a single power supply rail. The part can also be operated with dual supplies giving enhanced performance for some parameters. 4. Versatile Interface Logic The high speed logic allows direct interfacing to most microprocessors. Additionally, the double buffered interface enables simultaneous update of the AD7224 in multiple DAC systems. The part also features a zero override function. R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD7224–SPECIFICATIONS DUAL SUPPLY Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error Relative Accuracy Differential Nonlinearity Full-Scale Error Full-Scale Temperature Coefficient Zero Code Error Zero Code Error Temperature Coefficient REFERENCE INPUT Voltage Range Input Resistance Input Capacitance3 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current Input Capacitance3 Input Coding DYNAMIC PERFORMANCE Voltage Output Slew Rate3 Voltage Output Settling Time3 Positive Full-Scale Change Negative Full-Scale Change Digital Feedthrough Minimum Load Resistance POWER SUPPLIES VDD Range VSS Range IDD @ 25°C TMIN to TMAX ISS @ 25°C TMIN to TMAX SWITCHING CHARACTERISTICS3, 4 t1 @ 25°C TMIN to TMAX t2 @ 25°C TMIN to TMAX t3 @ 25°C TMIN to TMAX t4 @ 25°C TMIN to TMAX t5 @ 25°C TMIN to TMAX t6 @ 25°C TMIN to TMAX (VDD = 11.4 V to 16.5 V, VSS = –5 V 10%; AGND = DGND = O V; VREF = +2 V to (VDD – 4 V)1 unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.) K, B, T Versions2 8 ±2 ±1 ±1 ± 3/2 ± 20 ± 30 ± 50 2 to (VDD – 4) 8 100 2.4 0.8 ±1 8 Binary 2.5 5 7 50 2 11.4/16.5 4.5/5.5 4 6 3 5 L, C, U Versions2 8 ±1 ± 1/2 ±1 ±1 ± 20 ± 20 ± 30 2 to (VDD – 4) 8 100 2.4 0.8 ±1 8 Binary 2.5 5 7 50 2 11.4/16.5 4.5/5.5 4 6 3 5 Units Bits LSB max LSB max LSB max LSB max ppm/°C max mV max µV/°C typ V min to V max kΩ min pF max V min V max µA max pF max Conditions/Comments VDD = +15 V ± 5%, VREF = +10 V Guaranteed Monotonic VDD = 14 V to 16.5 V, VREF = +10 V Occurs when DAC is loaded with all 1s. VIN = 0 V or VDD V/µs min µs max µs max nV secs typ kΩ min V min/V max V min/V max mA max mA max mA max mA max VREF = +10 V; Settling Time to ± 1/2 LSB VREF = +10 V; Settling Time to ± 1/2 LSB VREF = 0 V VOUT = +10 V For Specified Performance For Specified Performance Outputs Unloaded; VIN = VINL or VINH Outputs Unloaded; VIN = VINL or VINH Outputs Unloaded; VIN = VINL or VINH Outputs Unloaded; VIN = VINL or VINH 90 90 90 90 0 0 0 0 90 90 10 10 90 90 90 90 0 0 0 0 90 90 10 10 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Chip Select/Load DAC Pulse Width Write/Reset Pulse Width Chip Select/Load DAC to Write Setup Time Chip Select/Load DAC to Write Hold Time Data Valid to Write Setup Time Data Valid to Write Hold Time NOTES 1 Maximum possible reference voltage. 2 Temperature ranges are as follows: K, L Versions: –40°C to +85°C B, C Versions: –40 °C to +85°C T, U Versions: –55°C to +125°C 3 Sample Tested at 25 °C by Product Assurance to ensure compliance. 4 Switching characteristics apply for single and dual supply operation. Specifications subject to change without notice. –2– REV. B AD7224 SINGLE SUPPLY Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error Differential Nonlinearity REFERENCE INPUT Input Resistance Input Capacitance3 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current Input Capacitance3 Input Coding DYNAMIC PERFORMANCE Voltage Output Slew Rate4 Voltage Output Settling Time4 Positive Full-Scale Change Negative Full-Scale Change Digital Feedthrough3 Minimum Load Resistance POWER SUPPLIES VDD Range IDD @ 25°C TMIN to TMAX SWITCHING CHARACTERISTICS3, 4 t1 @ 25°C TMIN to TMAX t2 @ 25°C TMIN to TMAX t3 @ 25°C TMIN to TMAX t4 @ 25°C TMIN to TMAX t5 @ 25°C TMIN to TMAX t6 @ 25°C TMIN to TMAX (VDD = +15 V 5%; VSS = AGND = DGND = O V; VREF = +10 V unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.) K, B, T Versions2 8 ±2 ±1 8 100 2.4 0.8 ±1 8 Binary 2 5 20 50 2 14.25/15.75 4 6 L, C, U Versions2 8 ±2 ±1 8 100 2.4 0.8 ±1 8 Binary 2 5 20 50 2 14.25/15.75 4 6 Units Bits LSB max LSB max kΩ min pF max V min V max µA max pF max Conditions/Comments 1 Guaranteed Monotonic Occurs when DAC is loaded with all 1s. VIN = 0 V or VDD V/µs min µs max µs max nV secs typ kΩ min V min/V max mA max mA max Settling Time to ± 1/2 LSB Settling Time to ± 1/2 LSB VREF = 0 V VOUT = +10 V For Specified Performance Outputs Unloaded; VIN = VINL or VINH Outputs Unloaded; VIN = VINL or VINH 90 90 90 90 0 0 0 0 90 90 10 10 90 90 90 90 0 0 0 0 90 90 10 10 ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Chip Select/Load DAC Pulse Width Write/Reset Pulse Width Chip Select/Load DAC to Write Setup Time Chip Select/Load DAC to Write Hold Time Data Valid to Write Setup Time Data Valid to Write Hold Time NOTES 1 Maximum possible reference voltage. 2 Temperature ranges are as follows: AD7224KN, LN: 0 °C to +70 °C AD7224BQ, CQ: –25 °C to +85°C AD7224TD, UD: –55 °C to +125°C 3 See Terminology. 4 Sample tested at 25 °C by Product Assurance to ensure compliance. Specifications subject to change without notice. REV. B –3– AD7224 ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C Operating Temperature Commercial (K, L Versions) . . . . . . . . . . . –40°C to +85°C Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C Extended (T, U Versions) . . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 The outputs may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit current to AGND is 60 mA. Model1 AD7224KN AD7224LN AD7224KP AD7224LP AD7224KR-1 AD7224LR-1 AD7224KR-18 AD7224LR-18 AD7224BQ AD7224CQ AD7224TQ AD7224UQ AD7224TE AD7224UE Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C Total Unadjusted Error (LSB) ± 2 max ± 1 max ± 2 max ± 1 max ± 2 max ± 1 max ± 2 max ± 1 max ± 2 max ± 1 max ± 2 max ± 1 max ± 2 max ± 1 max Package Option2 N-18 N-18 P-20A P-20A R-20 R-20 R-18 R-18 Q-18 Q-18 Q-18 Q-18 E-20A E-20A NOTES 1 To order MIL-STD-883 processed parts, add /883B to part number. Contact your local sales office for military data sheet. 2 E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7224 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN CONFIGURATIONS DIP and SOIC VSS VOUT VREF AGND DGND (MSB) DB7 DB6 DB5 DB4 1 2 3 4 5 6 7 8 9 18 17 VDD RESET VSS VOUT VREF AGND DGND (MSB) DB7 DB6 DB5 DB4 1 2 3 4 5 6 7 8 9 WARNING! ESD SENSITIVE DEVICE (SOIC) 18 17 VDD RESET (SOIC) VSS VOUT VREF AGND DGND (MSB) DB7 DB6 DB5 DB4 1 2 3 4 5 6 7 8 9 20 VDD 19 RESET 18 LDAC 16 LDAC 16 LDAC AD7224 15 WR CS DB0 (LSB) AD7224 R-18 15 WR CS DB0 (LSB) AD7224 R-20 17 WR 14 TOP VIEW (Not to Scale) 13 14 TOP VIEW (Not to Scale) 13 16 CS TOP VIEW (Not to Scale) 15 DB0 (LSB) 14 DB1 13 DB2 12 DB3 11 NC 12 DB1 11 DB2 10 DB3 12 DB1 11 DB2 10 DB3 NC 10 LCCC RESET VOUT VOUT VSS VDD PLCC RESET VSS NC VDD NC = NO CONNECT 3 VREF 4 AGND 5 DGND 6 (MSB) DB7 7 DB6 8 9 DB5 2 NC 1 20 19 18 LDAC VREF AGND DGND (MSB) DB7 DB6 4 5 6 7 8 3 2 1 20 19 18 LDAC AD7224 TOP VIEW (Not to Scale) 17 WR 16 CS 15 DB0 (LSB) 14 DB1 AD7224 TOP VIEW (Not to Scale) 17 WR 16 CS 15 DB0 (LSB) 14 DB1 10 11 12 13 DB4 DB3 DB2 NC 9 10 11 12 13 DB4 NC = NO CONNECT NC = NO CONNECT –4– DB5 DB3 DB2 NC REV. B AD7224 TERMINOLOGY TOTAL UNADJUSTED ERROR VOUT = D • VREF where D is a fractional representation of the digital input code and can vary from 0 to 255/256. OP-AMP SECTION Total Unadjusted Error is a comprehensive specification which includes full-scale error, relative accuracy and zero code error. Maximum output voltage is VREF – 1 LSB (ideal), where 1 LSB (ideal) is VREF/256. The LSB size will vary over the VREF range. Hence the zero code error, relative to the LSB size, will increase as VREF decreases. Accordingly, the total unadjusted error, which includes the zero code error, will also vary in terms of LSBs over the VREF range. As a result, total unadjusted error is specified for a fixed reference voltage of +10 V. RELATIVE ACCURACY The voltage-mode D/A converter output is buffered by a unity gain noninverting CMOS amplifier. This buffer amplifier is capable of developing +10 V across a 2 kΩ load and can drive capacitive loads of 3300 pF. The AD7224 can be operated single or dual supply resulting in different performance in some parameters from the output amplifier. In single supply operation (VSS = 0 V = AGND) the sink capability of the amplifier, which is normally 400 µA, is reduced as the output voltage nears AGND. The full sink capability of 400 µA is maintained over the full output voltage range by tying VSS to –5 V. This is indicated in Figure 2. 500 VSS = –5V 400 Relative Accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after allowing for zero code error and full-scale error and is normally expressed in LSBs or as a percentage of full-scale reading. DIFFERENTIAL NONLINEARITY ISINK – µA Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB max over the operating temperature range ensures monotonicity. DIGITAL FEEDTHROUGH 300 VSS = 0V 200 VDD = +15V TA = 25°C Digital Feedthrough is the glitch impulse transferred to the output due to a change in the digital input code. It is specified in nV secs and is measured at VREF = 0 V. FULL-SCALE ERROR 100 0 0 2 4 6 VOUT – Volts 8 10 Full-Scale Error is defined as: Measured Value – Zero Code Error – Ideal Value Figure 2. Variation of ISINK with VOUT CIRCUIT INFORMATION D/A SECTION The AD7224 contains an 8-bit voltage-mode digital-to-analog converter. The output voltage from the converter has the same polarity as the reference voltage, allowing single supply operation. A novel DAC switch pair arrangement on the AD7224 allows a reference voltage range from +2 V to +12.5 V. The DAC consists of a highly stable, thin-film, R-2R ladder and eight high speed NMOS single pole, double-throw switches. The simplified circuit diagram for this DAC is shown in Figure 1. R 2R VREF AGND 2R DB0 R 2R DB0 R 2R DB0 2R DB0 SHOWN FOR ALL 1's ON DAC VOUT Settling-time for negative-going output signals approaching AGND is similarly affected by VSS. Negative-going settling-time for single supply operation is longer than for dual supply operation. Positive-going settling-time is not affected by VSS. Additionally, the negative VSS gives more headroom to the output amplifier which results in better zero code performance and improved slew-rate at the output, than can be obtained in the single supply mode. DIGITAL SECTION The AD7224 digital inputs are compatible with either TTL or 5 V CMOS levels. All logic inputs are static-protected MOS gates with typical input currents of less than 1 nA. Internal input protection is achieved by an on-chip distributed diode between DGND and each MOS gate. To minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (VDD and DGND) as practically possible. INTERFACE LOGIC INFORMATION Figure 1. D/A Simplified Circuit Diagram The input impedance at the VREF pin is code dependent and can vary from 8 kΩ minimum to infinity. The lowest input impedance occurs when the DAC is loaded with the digital code 01010101. Therefore, it is important that the reference presents a low output impedance under changing load conditions. The nodal capacitance at the reference terminals is also code dependent and typically varies from 25 pF to 50 pF. The VOUT pin can be considered as a digitally programmable voltage source with an output voltage of: REV. B Table I shows the truth table for AD7224 operation. The part contains two registers, an input register and a DAC register. CS and WR control the loading of the input register while LDAC and WR control the transfer of information from the input register to the DAC register. Only the data held in the DAC register will determine the analog output of the converter. All control signals are level-triggered and therefore either or both registers may be made transparent; the input register by keeping CS and WR “LOW”, the DAC register by keeping LDAC and WR “LOW”. Input data is latched on the rising edge of WR. –5– AD7224 Table I. AD7224 Truth Table RESET LDAC H H H H H H H L L X H H H L L X H L WR L H X L CS L X H L L H H X H L Function Both Registers are Transparent Both Registers are Latched Both Registers are Latched Input Register Transparent Input Register Latched DAC Register Transparent DAC Register Latched Both Registers Loaded With All Zeros Both Register Latched With All Zeros and Output Remains at Zero Both Registers are Transparent and Output Follows Input Data a +2.5 V bandgap reference and the AD584, a precision +10 V reference. Note that in order to achieve an output voltage range of 0 V to +10 V, a nominal +15 V ± 5% power supply voltage is required by the AD7224. GROUND MANAGEMENT g L g X H L g g AC or transient voltages between AGND and DGND can cause noise at the analog output. This is especially true in microprocessor systems where digital noise is prevalent. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7224. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7224 AGND and DGND pins (IN914 or equivalent). H = High State, L = Low State, X = Don’t Care. All control inputs are level triggered. The contents of both registers are reset by a low level on the RESET line. With both registers transparent, the RESET line functions like a zero override with the output brought to 0 V for the duration of the RESET pulse. If both registers are latched, a “LOW” pulse on RESET will latch all 0s into the registers and the output remains at 0 V after the RESET line has returned “HIGH”. The RESET line can be used to ensure power-up to 0 V on the AD7224 output and is also useful, when used as a zero override, in system calibration cycles. Figure 3 shows the input control logic for the AD7224. LDAC WR CS RESET INPUT DATA INPUT REGISTER DAC REGISTER Applying the AD7224 UNIPOLAR OUTPUT OPERATION This is the basic mode of operation for the AD7224, with the output voltage having the same positive polarity as VREF. The AD7224 can be operated single supply (VSS = AGND) or with positive/negative supplies (see op-amp section which outlines the advantages of having negative VSS). Connections for the unipolar output operation are shown in Figure 5. The voltage at VREF must never be negative with respect to DGND. Failure to observe this precaution may cause parasitic transistor action and possible device destruction. The code table for unipolar output operation is shown in Table II. VREF DB7 DATA (8-BIT) DB0 CS WR LDAC DAC VOUT 3 VDD Figure 3. Input Control Logic CS t1 t3 t2 t4 t3 t2 t1 t4 AD7224 VSS AGND DGND RESET WR LDAC t5 DATA IN t6 Figure 5. Unipolar Output Circuit Table III. Unipolar Code Table DAC Register Contents MSB LSB 1111 1000 1000 0111 0000 0000 1111 0001 0000 1111 0001 0000 Analog Output  255  +V REF    256  DATA VALID NOTES: 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF VDD . t r = tf = 20ns OVER V DD RANGE VINH + V INL 2. TIMING MEASUREMENT REFERENCE LEVEL IS 2 Figure 4. Write Cycle Timing Diagram SPECIFICATION RANGES For the DAC to maintain specified accuracy, the reference voltage must be at least 4 V below the VDD power supply voltage. This voltage differential is required for correct generation of bias voltages for the DAC switches. With dual supply operation, the AD7224 has an extended VDD range from +12 V ± 5% to +15 V ± 10% (i.e., from +11.4 V to +16.5 V). Operation is also specified for a single VDD power supply of +15 V ± 5%. Performance is specified over a wide range of reference voltages from 2 V to (VDD – 4 V) with dual supplies. This allows a range of standard reference generators to be used such as the AD580, –6–  129  +V REF    256   128  V REF +V REF   =+ 2  256   127  +V REF    256  1 +V REF    256  0V 1 Note : 1 LSB = (V REF ) 2−8 = V REF    256  () REV. B AD7224 BIPOLAR OUTPUT OPERATION VIN The AD7224 can be configured to provide bipolar output operation using one external amplifier and two resistors. Figure 6 shows a circuit used to implement offset binary coding. In this case   R2  R2  V O = 1 +  • ( D V REF ) –   • (V REF )   R1  R1  VREF VDD AGND VIN VBIAS VSS DAC VOUT AD7224 DGND With R1 = R2 VO = (2 D – 1) • VREF where D is a fractional representation of the digital word in the DAC register. Mismatch between R1 and R2 causes gain and offset errors; therefore, these resistors must match and track over temperature. Once again, the AD7224 can be operated in single supply or from positive/negative supplies. Table III shows the digital code versus output voltage relationship for the circuit of Figure 6 with R1 = R2. VREF DB7 DATA (8-BIT) DB0 CS WR LDAC RESET VSS AGND DGND DAC VOUT +15V A15 Figure 7. AGND Bias Circuit MICROPROCESSOR INTERFACE A15 A8 ADDRESS BUS 8085A 8088 WR ADDRESS DECODE CS LDAC AD7224* WR LATCH EN DB7 DB0 ADDRESS DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY VREF 3 VDD R1 R2 +15V VOUT ALE AD7 AD0 Figure 8. AD7224 to 8085A/8088 Interface ADDRESS BUS A0 6809 6502 R/W ADDRESS DECODE EN CS LDAC AD7224 R1, R2 = 10kΩ ±0.1% Figure 6. Bipolar Output Circuit E OR φ2 AD7224* WR DB7 DB0 DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY D7 E OR φ2 D0 D7 Table III. Bipolar (Offset Binary) Code Table DAC Register Contents MSB LSB 1111 1000 1000 0111 0000 0000 1111 0001 0000 1111 0001 0000 Analog Output  127  +V REF    128  1 +V REF    128  D0 Figure 9. AD7224 to 6809/6502 Interface A15 ADDRESS BUS A0 0V Z-80 CS ADDRESS DECODE LDAC 1 –V REF    128   127  –V REF    128   128  –V REF   = –V REF  128  AD7224* WR WR DB7 DB0 D7 D0 DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY AGND BIAS Figure 10. AD7224 to Z-80 Interface A23 ADDRESS BUS A1 68008 ADDRESS DECODE CS LDAC WR The AD7224 AGND pin can be biased above system GND (AD7224 DGND) to provide an offset “zero” analog output voltage level. Figure 7 shows a circuit configuration to achieve this. The output voltage, VOUT, is expressed as: VOUT = VBIAS + D • (VIN) where D is a fractional representation of the digital word in DAC register and can vary from 0 to 255/256. For a given VIN, increasing AGND above system GND will reduce the effective VDD–VREF which must be at least 4 V to ensure specified operation. Note that VDD and VSS for the AD7224 must be referenced to DGND. REV. B –7– R/W DTACK AD7224* DB7 DB0 D7 D0 DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 11. AD7224 to 68008 Interface AD7224 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 18-Pin Plastic (Suffix N) 18-Pin Cerdip (Suffix Q) 18-Pin Ceramic (Suffix D) 18-Lead SOIC (R-18) 18 10 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) PIN 1 1 9 0.4625 (11.75) 0.4469 (11.35) 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) x 45 ° 0.0098 (0.25) PLCC Package P-20A 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 19 PIN 1 IDENTIFIER TOP VIEW 18 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 8 9 0.020 (0.50) R 13 0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.02) SQ 0.385 (9.78) 0.110 (2.79) 0.085 (2.16) PIN 1 1 10 0.180 (4.57) 0.165 (4.19) 0.025 (0.63) 0.015 (0.38) 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0125 (0.32) 0.0091 (0.23) 8° 0° 0.0500 (1.27) 0.0157 (0.40) 0.048 (1.21) 0.042 (1.07) 4 3 20-Lead SOIC (R-20) 0.050 (1.27) BSC 14 0.040 (1.01) 0.025 (0.64) 20 11 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) LCCC Package E-20A 0.100 (2.54) 0.064 (1.63) 0.075 (1.91) REF 0.200 (5.08) BSC 0.100 (2.54) BSC 0.015 (0.38) MIN 0.5118 (13.00) 0.4961 (12.60) 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) x 45 ° 0.0098 (0.25) 0.358 (9.09) 0.342 (8.69) SQ 0.358 (9.09) MAX SQ 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 13 20 1 BOTTOM VIEW 9 0.028 (0.71) 0.022 (0.56) 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0125 (0.32) 0.0091 (0.23) 8° 0° 0.0500 (1.27) 0.0157 (0.40) 0.050 (1.27) BSC 45 ° TYP 0.088 (2.24) 0.054 (1.37) 0.055 (1.40) 0.045 (1.14) 0.150 (3.81) BSC –8– REV. B PRINTED IN U.S.A. C836a–10–10/84