AD7273BUJZ-REEL7

3 MSPS,10-/12-Bit ADCs in 8-Lead TSOT AD7273/AD7274 FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput rate: 3 MSPS Specified for VDD of 2.35 V to 3.6 V Power consumption 11.4 mW at 3 MSPS with 3 V supplies Wide input bandwidth 70 dB SNR at 1 MHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Temperature range: −40°C to +125°C Power-down mode: 0.1 μA typ 8-lead TSOT package 8-lead MSOP package VDD VIN T/H AGND 10-/12-BIT SUCCESSIVE APPROXIMATION ADC VREF SCLK CONTROL LOGIC SDATA AD7273/AD7274 DGND 04973-001 CS Figure 1. GENERAL DESCRIPTION The AD7273/AD7274 are 10-/12-bit, high speed, low power, successive approximation ADCs, respectively. The parts operate from a single 2.35 V to 3.6 V power supply and feature throughput rates of up to 3 MSPS. Each part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 55 MHz. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS, and the conversion is also initiated at this point. The conversion rate is determined by the SCLK. There are no pipeline delays associated with these parts. The AD7273/AD7274 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the parts is applied externally and can be in the range of 1.4 V to VDD. This allows the widest dynamic input range to the ADC. Table 1. Part Number AD72731 AD72741 AD7276 AD7277 AD7278 1 Resolution 10 12 12 10 8 Package 8-lead MSOP 8-Lead TSOT 8-lead MSOP 8-Lead TSOT 8-lead MSOP 6-Lead TSOT 8-lead MSOP 6-Lead TSOT 8-lead MSOP 6-Lead TSOT Parts contain external reference pin. PRODUCT HIGHLIGHTS 1. 3 MSPS ADCs in an 8-lead TSOT package. 2. High throughput with low power consumption. 3. Flexible power/serial clock speed management. Allows maximum power efficiency at low throughput rates. 4. Reference can be driven up to the power supply. 5. No pipeline delay. 6. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD7273/AD7274 TABLE OF CONTENTS Features .............................................................................................. 1 ADC Transfer Function............................................................. 15 General Description ......................................................................... 1 Typical Connection Diagram ....................................................... 16 Functional Block Diagram .............................................................. 1 Analog Input ............................................................................... 16 Product Highlights ........................................................................... 1 Digital Inputs .............................................................................. 16 Revision History ............................................................................... 2 Modes of Operation ....................................................................... 17 Specifications..................................................................................... 3 Normal Mode.............................................................................. 17 AD7274 Specifications................................................................. 3 Partial Power-Down Mode ....................................................... 17 AD7273 Specifications................................................................. 5 Full Power-Down Mode ............................................................ 17 Timing Specifications .................................................................. 7 Power-Up Times......................................................................... 18 Timing Examples.......................................................................... 8 Power vs. Throughput Rate....................................................... 20 Absolute Maximum Ratings............................................................ 9 Serial Interface ................................................................................ 21 ESD Caution.................................................................................. 9 Microprocessor Interfacing....................................................... 23 Pin Configurations and Function Descriptions ......................... 10 Application Hints ........................................................................... 24 Typical Performance Characteristics ........................................... 11 Grounding and Layout .............................................................. 24 Terminology .................................................................................... 14 Evaluating the AD7273/AD7274 Performance......................... 24 Circuit Information ........................................................................ 15 Outline Dimensions ....................................................................... 25 Converter Operation.................................................................. 15 Ordering Guide .......................................................................... 25 REVISION HISTORY 9/05—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7273/AD7274 SPECIFICATIONS AD7274 SPECIFICATIONS VDD = 2.35 V to 3.6 V, VREF = 2.35 V to VDD, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 3 Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Power Supply Rejection Ratio (PSRR) DC ACCURACY Resolution Integral Nonlinearity3 Differential Nonlinearity3 Offset Error3 Gain Error3 Total Unadjusted Error (TUE)3 ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage Range DC leakage Current Input Capacitance Input Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding B Grade 1 Unit 2 68 69.5 −73 −78 −80 dB min dB min dB max dB typ dB typ −82 −82 5 18 55 8 82 dB typ dB typ ns typ ps typ MHz typ MHz typ dB typ 12 ±1 ±1 ±3 ±3.5 ±3.5 Bits LSB max LSB max LSB max LSB max LSB max 0 to VREF ±1 ±5.5 42 10 V μA max μA max pF typ pF typ 1.4 to VDD ±1 20 32 V min/V max μA max pF typ Ω typ 1.7 2 0.7 0.8 ±1 2 V min V min V max V max μA max pF max VDD − 0.2 V min 0.2 V max ±2.5 μA max 4.5 pF max Straight (natural) binary Rev. 0 | Page 3 of 28 Test Conditions/Comments fIN = 1 MHz sine wave fa = 1 MHz, fb = 0.97 MHz fa = 1 MHz, fb = 0.97 MHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 12 bits −40°C to +85°C 85°C to 125°C When in track When in hold 2.35 V ≤ VDD ≤ 2.7 V 2.7 V < VDD ≤ 3.6 V 2.35 V ≤ VDD < 2.7 V 2.7 V ≤ VDD ≤ 3.6 V Typically 10 nA, VIN = 0 V or VDD ISOURCE = 200 μA, VDD = 2.35 V to 3.6 V ISINK = 200 μA AD7273/AD7274 Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate POWER RQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) Power Dissipation 5 Normal Mode (Operational) Partial Power-Down Full Power-Down B Grade 1 Unit 2 Test Conditions/Comments 291 60 3 ns max ns max MSPS max 14 SCLK cycles with SCLK at 48 MHz 2.35/3.6 V min/V max 1 5 3.8 34 2 10 mA typ mA max mA typ μA typ μA max μA max −40°C to +85°C, typically 0.1 μA 85°C to 125°C 18 11.4 102 7.2 mW max mW typ μW max μW max VDD = 3.6 V , fSAMPLE = 3 MSPS VDD = 3 V VDD = 3 V VDD = 3.6 V, −40°C to +85°C 1 Temperature range from −40°C to +125°C. Typical specifications are tested with VDD = 3 V and VREF = 3 V at 25°C. 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. 2 Rev. 0 | Page 4 of 28 See the Serial Interface section Digital I/Ps = 0 V or VDD VDD = 3 V, SCLK on or off VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS VDD = 3 V AD7273/AD7274 AD7273 SPECIFICATIONS VDD = 2.35 V to 3.6 V, VREF = 2.35 V to VDD, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Signal-to-Noise + Distortion (SINAD) 3 Total Harmonic Distortion (THD)3 Peak Harmonic or Spurious Noise (SFDR)3 Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Power Supply Rejection Ratio (PSRR) DC ACCURACY Resolution Integral Nonlinearity3 Differential Nonlinearity3 Offset Error3 Gain Error3 Total Unadjusted Error (TUE)3 ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage Range DC leakage Current Input Capacitance Input Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VIN Input Current, IIN Input Capacitance, CIN 4 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance4 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time3 Throughput Rate B Grade 1 Unit 2 61 −72 −77 −80 dB min dB max dB typ dB typ −81 −81 5 18 74 10 82 dB typ dB typ ns typ ps typ MHz typ MHz typ dB typ 10 ±0.5 ±0.5 ±1 ±1.5 ±2.5 Bits LSB max LSB max LSB max LSB max LSB max 0 to VREF ±1 ±5.5 42 10 V μA max μA max pF typ pF typ 1.4 to VDD ±1 20 32 V min/V max μA max pF typ Ω typ 1.7 2 0.7 0.8 ±1 2 V min V min V max V max μA max pF max Test Conditions/Comments fIN = 1 MHz sine wave fa = 1 MHz, fb = 0.97 MHz fa = 1 MHz, fb = 0.97 MHz @ 3 dB @ 0.1 dB Guaranteed no missed codes to 10 bits −40°C to +85°C 85°C to 125°C When in track When in hold 2.35 V ≤ VDD ≤ 2.7 V 2.7 V < VDD ≤ 3.6 V 2.35 V ≤ VDD< 2.7 V 2.7 V ≤ VDD ≤ 3.6 V Typically 10 nA, VIN = 0 V or VDD VDD − 0.2 V min 0.2 V max ±2.5 μA max 4.5 pF max Straight (natural) binary ISOURCE = 200 μA; VDD = 2.35 V to 3.6 V ISINK = 200 μA 250 60 3.45 12 SCLK cycles with SCLK at 48 MHz ns max ns max MSPS max Rev. 0 | Page 5 of 28 See the Serial Interface section AD7273/AD7274 Parameter POWER RQUIREMENTS VDD IDD Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) Power Dissipation 5 Normal Mode (Operational) Partial Power-Down Full Power-Down B Grade 1 Unit 2 2.35/3.6 V min/V max 0.6 5 3.2 34 2 10 mA typ mA max mA typ μA typ μA max μA max −40°C to +85°C, typically 0.1 μA 85°C to 125°C 18 9.6 102 7.2 mW max mW typ μW max μW max VDD = 3.6 V , fSAMPLE = 3 MSPS VDD = 3 V VDD = 3 V VDD = 3.6 V, −40°C to +85°C 1 Temperature range from −40°C to +125°C. Typical specifications are tested with VDD = 3 V and VREF = 3 V at 25°C. 3 See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. 2 Rev. 0 | Page 6 of 28 Test Conditions/Comments Digital I/Ps = 0 V or VDD VDD = 3 V, SCLK on or off VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS VDD = 3 V AD7273/AD7274 TIMING SPECIFICATIONS VDD = 2.35 V to 3.6 V; VREF = 2.35 to VDD; TA = TMIN to TMAX, unless otherwise noted. 1 Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Table 4. Parameter fSCLK 2 tCONVERT tQUIET t1 t2 t3 4 t44 t5 t6 t74 t8 Limit at TMIN, TMAX AD7273/AD7274 500 48 14 × tSCLK 12 × tSCLK 4 3 6 4 15 0.4 tSCLK 0.4 tSCLK 5 14 5 4.2 1 t9 tPOWER-UP 5 Unit kHz min 3 MHz max Description AD7274 AD7273 Minimum quiet time required between bus relinquish and start of next conversion Minimum CS pulse width CS to SCLK setup time Delay from CS until SDATA three-state disabled Data access time after SCLK falling edge SCLK low pulse width SCLK high pulse width SCLK to data valid hold time SCLK falling edge to SDATA three-state SCLK falling edge to SDATA three-state CS rising edge to SDATA three-state Power-up time from full power-down ns min ns min ns min ns max ns max ns min ns min ns min ns max ns min ns max μs max 1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Minimum fSCLK at which specifications are guaranteed. 4 The time required for the output to cross the VIH or VIL voltage. 5 See the Power-Up Times section t4 t8 SCLK SCLK Figure 4. SCLK Falling Edge SDATA Three-State Figure 2. Access Time After SCLK Falling Edge t7 SCLK VIH 04973-003 SDATA VIL 1.4V SDATA Figure 3. Hold Time After SCLK Falling Edge Rev. 0 | Page 7 of 28 04973-004 VIL 04973-002 VIH SDATA AD7273/AD7274 Timing Example 2 TIMING EXAMPLES The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz, and the throughput is 2.97 MSPS. This produces a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns min and tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 14 ns max. This satisfies the minimum requirement of 4 ns for tQUIET. th For the AD7274, if CS is brought high during the 14 SCLK rising edge after the two leading zeros and 12 bits of the conversion are provided, the part can achieve the fastest throughput rate, 3 MSPS. If CS is brought high during the 16th SCLK rising edge after the two leading zeros, 12 bits of the conversion, and two trailing zeros are provided, a throughput rate of 2.97 MSPS is achievable. This is illustrated in the following two timing examples. Timing Example 1 In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz, and the throughput is 3 MSPS. This produces a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns min and tACQ = 67 ns. This satisfies the requirement of 60 ns for tACQ. Figure 6 also shows that tACQ comprises 0.5(1/fSCLK) + t9 + tQUIET, where t9 = 4.2 ns max. This allows a value of 52.8 ns for tQUIET, satisfying the minimum requirement of 4 ns. t1 CS tCONVERT SCLK t6 1 2 3 4 t3 Z SDATA B 5 13 DB11 DB10 DB9 15 t5 t7 t4 ZERO 14 16 t8 tQUIET DB1 DB0 ZERO THREESTATE TWO LEADING ZEROS ZERO TWO TRAILING ZEROS THREE-STATE 04973-005 t2 1/THROUGHPUT Figure 5. AD7274 Serial Interface Timing 16 SCLK Cycle t1 CS tCONVERT t2 SCLK t6 1 2 3 4 t3 Z SDATA B 5 13 t7 t4 ZERO DB11 DB10 DB9 14 t5 DB1 t9 tQUIET DB0 THREE-STATE 04973-006 THREESTATE TWO LEADING ZEROS 1/THROUGHPUT Figure 6.AD7274 Serial Interface Timing 14 SCLK Cycle t1 CS tCONVERT t2 B 1 2 3 4 5 12 13 14 15 16 t8 tQUIET tACQUISITION 12.5(1/fSCLK) 1/THROUGHPUT Figure 7. Serial Interface Timing 16 SCLK Cycle Rev. 0 | Page 8 of 28 04973-007 SCLK AD7273/AD7274 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameters VDD to AGND/DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Input Current to Any Pin Except Supplies 1 Operating Temperature Range Commercial (B Grade) Storage Temperature Range Junction Temperature 6-Lead TSOT Package θJA Thermal Impedance θJC Thermal Impedance 8-Lead MSOP Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature Soldering Reflow (10 to 30 sec) Lead Temperature Soldering Reflow (10 to 30 sec) ESD 1 Ratings −0.3 V to +6 V −0.3 V to VDD + 0.3 V −0.3 V to +6 V −0.3 V to VDD + 0.3 V ±10 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −40°C to +125°C −65°C to +150°C 150°C 230°C/W 92°C/W 205.9°C/W 43.74°C/W 255°C 260°C 1.5 kV Transient currents of up to 100 mA cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 9 of 28 AD7273/AD7274 SDATA 2 CS 3 AGND 4 8 AD7273/ AD7274 TOP VIEW (Not to Scale) 7 VDD 1 VIN SDATA 2 DGND 6 SCLK 5 VREF DGND 3 AD7273/ AD7274 8 AGND 7 CS SCLK TOP VIEW VIN 4 (Not to Scale) 5 VREF 04973-008 VDD 1 Figure 8. 8-Lead MSOP Pin Configuration 6 04973-009 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 9. 8-Lead TSOT Pin Configuration Table 6. Pin Function Descriptions Pin No. MSOP TSOT 1 1 2 2 Mnemonic VDD SDATA 3 7 CS 4 8 AGND 5 5 VREF 6 6 SCLK 7 3 DGND 8 4 VIN Description Power Supply Input. The VDD range for the AD7273/AD7274 is from 2.35 V to 3.6 V. Data Out. Logic output. The conversion result from the AD7273/AD7274 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7274 consists of two leading zeros followed by the 12 bits of conversion data and two trailing zeros, provided MSB first. The data stream from the AD7273 consists of two leading zeros followed by the 10 bits of conversion data and four trailing zeros, provided MSB first. Chip Select. Active low logic input. This input provides the dual function of initiating conversion on the AD7273/AD7274 and framing the serial data transfer. Analog Ground. Ground reference point for all circuitry on the AD7273/AD7274. All analog signals and any external reference signal should be referred to this AGND voltage. Voltage Reference Input. This pin becomes the reference voltage input. An external reference should be applied at this pin. The external reference input range is 1.4 V to VDD. A 10 μF capacitor should be tied between this pin and AGND. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of AD7273/AD7274. Digital Ground. Ground reference point for all digital circuitry on the AD7273/AD7274. The DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Analog Input. Single-ended analog input channel. The input range is 0 to VREF. Rev. 0 | Page 10 of 28 AD7273/AD7274 TYPICAL PERFORMANCE CHARACTERISTICS 72.2 SNR (dB) –40 VDD = 3V 16384 POINT FFT FSAMPLE = 3MSPS FIN = 1MHz SINAD = 71.05 THD = –80.9 SFDR = –82.2 FSAMPLE = 3MSPS 72.0 VDD = 2.5V 71.8 VDD = 3.6V 71.6 SNR (dB) –20 –60 –80 71.4 71.2 71.0 70.8 –100 70.6 1500 04973-010 1400 1300 1200 1100 900 1000 800 700 600 500 400 300 200 0 100 FREQUENCY (kHz) 70.2 100 1000 1500 INPUT FREQUENCY (kHz) 04973-013 70.4 –120 Figure 13. AD7274 SNR vs. Analog Input Frequency at 3 MSPS for Various Supply Voltages, SCLK Frequency = 48 MHz Figure 10. AD7274 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz –72 SNR (dB) –40 16384 POINT FFT FSAMPLE = 3MSPS FIN = 1MHz SINAD = 66.56 THD = –77.4 SFDR = –78.2 –74 –76 VDD = 3V –78 THD (dB) –20 –60 –80 VDD = 2.5V –82 –80 –84 VDD = 3.6V –86 –100 04973-011 1500 1400 1300 1200 1100 1000 900 800 700 600 500 –40 FSAMPLE = 3MSPS –50 71.4 71.2 71.0 VDD = 3.6V THD (dB) RIN = 100Ω 70.8 –60 –70 VDD = 2.5V RIN = 10Ω –80 VDD = 3V 69.4 69.2 69.0 100 1000 RIN = 0Ω 1500 INPUT FREQUENCY (kHz) Figure 12. AD7274 SINAD vs. Analog Input Frequency at 3 MSPS for Various Supply Voltages, SCLK Frequency = 48 MHz –90 100 04973-012 SINAD (dB) 71.6 70.6 70.4 70.2 70.0 69.8 69.6 1500 Figure 14. THD vs. Analog Input Frequency at 3 MSPS for Various Supply Voltages, SCLK Frequency = 48 MHz Figure 11. AD7273 Dynamic Performance at 3 MSP, Input Tone = 1 MHz 72.2 72.0 71.8 1000 INPUT FREQUENCY (kHz) 1000 INPUT FREQUENCY (kHz) 1500 04973-015 400 300 200 0 100 FREQUENCY (kHz) –90 100 04973-014 –88 –120 Figure 15. THD vs. Analog Input Frequency at 3 MSPS for Various Source Impedance, SCLK Frequency = 48 MHz, Supply Voltage = 3 V Rev. 0 | Page 11 of 28 AD7273/AD7274 –70 1.0 0.8 0.6 –80 INL ERROR (LSB) PSRR (dB) 0.4 –90 POSITIVE INL 0.2 0 –0.2 –0.4 NEGATIVE INL –100 –0.6 100mV p-p SINE WAVE ON AVDD NO DECOUPLING 500 1000 1500 2000 2500 3000 SUPPLY RIPPLE FREQUENCY (MHz) –1.0 1.4 04973-016 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 REFERENCE VOLTAGE (V) Figure 16. Power Supply Rejection Ratio (PSRR) vs. Supply Ripple Frequency Without Decoupling 04973-019 –0.8 –110 Figure 19. Change in INL vs. Reference Voltage, 3 V Supply 1.0 1.0 VDD = 3V 0.8 0.8 0.6 0.6 0.4 0.4 DNL ERROR (LSB) INL ERROR (LSB) POSITIVE DNL 0.2 0 –0.2 0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 0 500 1000 1500 2000 2500 3000 3500 4000 CODES –1.0 1.4 04973-017 –1.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 REFERENCE VOLTAGE (V) Figure 17. AD7274 INL Performance Figure 20. Change in DNL vs. Reference Voltage, 3 V Supply 1.0 3.60 VDD = 3V 0.8 3.40 3.20 0.6 3.00 VDD = 3V 2.80 MAX CURRENT (mA) 0.4 0.2 0 –0.2 –0.4 2.60 VDD = 3.6V 2.40 2.20 2.00 1.80 1.60 VDD = 2.5V 1.40 1.20 –0.6 –1.0 0 500 1000 1500 2000 2500 3000 CODES 3500 4000 0.80 0.60 0 10 20 30 40 SCLK FREQUENCY (MHz) Figure 21. Maximum Current vs. Supply Voltage for Different SCLK Frequencies Figure 18. AD7274 DNL Performance Rev. 0 | Page 12 of 28 50 04973-021 1.00 –0.8 04973-018 DNL ERROR (LSB) 1.6 04973-020 NEGATIVE DNL AD7273/AD7274 18000 12.0 30,000 CODES EFFECTIVE NUMBERS OF BITS 16000 12000 10000 8000 6000 4000 11.5 11.0 10.5 0 2045 2046 2047 2048 2049 CODE 2050 Figure 22. Histogram of Codes for 30,000 Samples 10.0 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 VREF (V) Figure 23. ENOB/SINAD vs. Reference Voltage Rev. 0 | Page 13 of 28 3.4 3.6 04973-023 2000 04973-022 NUMBER OF CODES 14000 AD7273/AD7274 TERMINOLOGY Integral Nonlinearity (INL) The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7273/ AD7274, the endpoints of the transfer function are zero scale at 0.5 LSB below the first code transition and full scale at 0.5 LSB above the last code transition. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 0.5 LSB. Gain Error The deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal, that is, VREF – 1.5 LSB, after adjusting for the offset error. Total Unadjusted Error (TUE) A comprehensive specification that includes gain, linearity, and offset errors. Track-and-Hold Acquisition Time The time required for the output of the track-and-hold amplifier to reach its final value, within ±0.5 LSB, after the end of the conversion. See the Serial Interface section for more details. Signal-to-Noise + Distortion Ratio (SINAD) The measured ratio of signal to noise plus distortion at the output of the ADC. The signal is the rms amplitude of the fundamental, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), including harmonics but excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. For an ideal N-bit converter, the SINAD is SINAD = 6.02 N + 1.76 dB According to this equation, the SINAD is 74 dB for a 12-bit converter and 62 dB for a 10-bit converter. However, various error sources in the ADC, including integral and differential nonlinearities and internal ac noise sources, cause the measured SINAD to be less than its theoretical value. Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. It is defined as: THD (dB ) = 20 log where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise (SFDR) The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum; however, for ADCs with harmonics buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, …. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the secondorder terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The AD7273/AD7274 are tested using the CCIF standard in which two input frequencies are used (see fa and fb in the Specifications section). In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. Power Supply Rejection Ratio (PSRR) The ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC VDD supply of frequency fS. PSRR (dB ) = 10 log (Pf Pf S ) where Pf is the power at frequency f in the ADC output; PfS is the power at frequency fS coupled onto the ADC VDD supply. Aperture Delay The measured interval between the leading edge of the sampling clock and the point at which the ADC actually takes the sample. Aperture Jitter The sample-to-sample variation in the effective point in time at which the sample is taken. V2 2 + V3 2 + V 4 2 + V5 2 + V6 2 V1 Rev. 0 | Page 14 of 28 AD7273/AD7274 CIRCUIT INFORMATION The AD7273/AD7274 provide the user with an on-chip trackand-hold ADC and a serial interface housed in an 8-lead TSOT or an 8-lead MSOP package, which offers the user considerable space-saving advantages over alternative solutions. The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC. The analog input range is 0 to VREF. An external reference in the range of 1.4 V to VDD is required by the ADC. When the ADC starts a conversion, SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced (see Figure 25). The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 26 shows the ADC transfer function. CHARGE REDISTRIBUTION DAC SAMPLING CAPACITOR A VIN SW1 ACQUISITION PHASE B The AD7273/AD7274 also feature a power-down option to save power between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. CONTROL LOGIC SW2 COMPARATOR VDD/2 04973-025 The AD7273/AD7274 are high speed, low power, 10-/12-bit, single supply ADCs, respectively. The parts can be operated from a 2.35 V to 3.6 V supply. When operated from any supply voltage within this range, the AD7273/AD7274 are capable of throughput rates of 3 MSPS when provided with a 48 MHz clock. AGND Figure 25. ADC Conversion Phase CONVERTER OPERATION ADC TRANSFER FUNCTION The AD7273/AD7274 are successive approximation ADCs based on a charge redistribution DAC. Figure 24 and Figure 25 show simplified schematics of the ADC. Figure 24 shows the ADC during its acquisition phase, where SW2 is closed, SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on VIN. The output coding of the AD7273/AD7274 is straight binary. The designed code transitions occur midway between successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The LSB size is VREF/4,096 for the AD7274 and VREF/1,024 for the AD7273. The ideal transfer characteristic for the AD7273/AD7274 is shown in Figure 26. CHARGE REDISTRIBUTION DAC SW1 B ACQUISITION PHASE VDD/2 SW2 COMPARATOR AGND CONTROL LOGIC 111...000 011...111 1LSB = VREF/4096 (AD7274) 1LSB = VREF/1024 (AD7273) 000...010 000...001 000...000 0V 0.5LSB Figure 24. ADC Acquisition Phase +VREF – 1.5LSB ANALOG INPUT Figure 26. AD7273/AD7274 Transfer Characteristic Rev. 0 | Page 15 of 28 04973-026 ADC CODE SAMPLING CAPACITOR A 04973-024 VIN 111...111 111...110 AD7273/AD7274 TYPICAL CONNECTION DIAGRAM The conversion result is output in a 16-bit word with two leading zeros followed by the 12-bit or 10-bit result. The 12-bit result from the AD7274 is followed by two trailing zeros, and the 10-bit result from the AD7273 is followed by four trailing zeros. Table 7 provides some typical performance data with various references under the same setup conditions for the AD7274. on resistance of a switch. This resistor is typically about 75 Ω. Capacitor C2 is the ADC sampling capacitor and has a capacitance of 32 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by using a band-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADCs. This may necessitate the use of an input buffer amplifier. The AD8021 op amp is compatible with this device; however, the choice of the op amp is a function of the particular application. VDD Table 7. AD7274 Performance (Various Voltage Reference IC) AD7274 SNR Performance 1 MHz Input 71.3 dB 70.1 dB 70.9 dB Voltage Reference AD780 @ 2.5 V AD780 @ 3 V REF195 D1 R1 VIN C1 4pF C2 D2 CONVERSION PHASE–SWITCH OPEN TRACK PHASE–SWITCH CLOSED 04973-028 Figure 27 shows a typical connection diagram for the AD7273/ AD7274. An external reference must be applied to the ADC. This reference can be in the range of 1.4 V to VDD. A precision reference, such as the REF19x family or the ADR421, can be used to supply the reference voltage to the AD7273/AD7274. Figure 28. Equivalent Analog Input Circuit 3.6V SUPPLY 4.6 mA 0V TO VREF INPUT REF195 2.5V 10pF When no amplifier is used to drive the analog input, the source impedance should be limited to a low value. The maximum source impedance depends on the amount of THD that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 14 shows a graph of the THD vs. the analog input frequency for different source impedances when using a supply voltage of 3 V and sampling at a rate of 3 MSPS. 10μF VDD VIN VREF 0.1μF AD7273/ AD7274 0.1μF SCLK SDATA CS DSP/ μC/μP SERIAL INTERFACE 04973-027 AGND/DGND Figure 27. AD7273/AD7274 Typical Connection Diagram ANALOG INPUT Figure 28 shows an equivalent circuit of the analog input structure of the AD7273/AD7274. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 300 mV. Signals exceeding this value cause these diodes to become forward biased and to start conducting current into the substrate. These diodes can conduct a maximum current of 10 mA without causing irreversible damage to the part. Capacitor C1 in Figure 28 is typically about 4 pF and can primarily be attributed to pin capacitance. Resistor R1 is a lumped component made up of the DIGITAL INPUTS The digital inputs applied to the AD7273/AD7274 are not limited by the maximum ratings that limit the analog inputs. Instead, the digital inputs can be applied at up to 6 V and are not restricted by the VDD + 0.3 V limit of the analog inputs. For example, if the AD7273/AD7274 were operated with a VDD of 3 V, then 5 V logic levels could be used on the digital inputs. However, it is important to note that the data output on SDATA still has 3 V logic levels when VDD = 3 V. Another advantage of SCLK and CS not being restricted by the VDD + 0.3 V limit is that power supply sequencing issues are avoided. For example, unlike with the analog inputs, with the digital inputs, if CS or SCLK are applied before VDD, there is no risk of latch-up. Rev. 0 | Page 16 of 28 AD7273/AD7274 MODES OF OPERATION The mode of operation of the AD7273/AD7274 is selected by controlling the logic state of the CS signal during a conversion. There are three possible modes of operation: normal mode, partial power-down mode, and full power-down mode. The point at which CS is pulled high after the conversion is initiated determines which power-down mode, if any, the device enters. Similarly, if the device is already in power-down mode, CS can control whether the device returns to normal operation or remains in power-down mode. These modes of operation are designed to provide flexible power management options, which can be chosen to optimize the power dissipation/throughput rate ratio for different application requirements. NORMAL MODE This mode is intended for fastest throughput rate performance because the AD7273/AD7274 remain fully powered at all times, eliminating worry about power-up times. Figure 29 shows the general diagram of the operation of the AD7273/AD7274 in this mode. The conversion is initiated on the falling edge of CS as described in the Serial Interface section. To ensure that the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges elapse after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling, but before the 16th SCLK falling edge, the part remains powered up, but the conversion is terminated, and SDATA goes back into three-state. For the AD7274, a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7273, a minimum of 12 serial clock cycles are required to complete the conversion and access the complete conversion result. CS can idle high until the next conversion or low until CS returns high before the next conversion (effectively idling CS low). Once a data transfer is complete (SDATA has returned to three-state), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again. PARTIAL POWER-DOWN MODE This mode is intended for use in applications where slower throughput rates are required. An example of this is when either the ADC is powered down between each conversion or a series of conversions is performed at a high throughput rate and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7273/AD7274 are in partial power-down mode, all analog circuitry is powered down except the bias generation circuit. To enter partial power-down mode, interrupt the conversion process by bringing CS high between the second and 10th falling edges of SCLK, as shown in Figure 30. Once CS is brought high in this window of SCLKs, the part enters partial power-down mode, the conversion that was initiated by the falling edge of CS is terminated, and SDATA goes back into three-state. If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This prevents accidental power-down due to glitches on the CS line. To exit this mode of operation and power up the AD7274/ AD7273, perform a dummy conversion. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up once 16 SCLKs elapse; valid data results from the next conversion, as shown in Figure 31. If CS is brought high before the 10th falling edge of SCLK, the AD7274/ AD7273 goes into full power-down mode. Therefore, although the device may begin to power up on the falling edge of CS, it powers down on the rising edge of CS as long as this occurs before the 10th SCLK falling edge. If the AD7273/AD7274 is already in partial power-down mode and CS is brought high before the 10th falling edges of SCLK, the device enters full power-down mode. For more information on the power-up times associated with partial power-down mode in various configurations, see the Power-Up Times section. FULL POWER-DOWN MODE This mode is intended for use in applications where throughput rates slower than those in the partial power-down mode are required, because power-up from a full power-down takes substantially longer than that from a partial power-down. This mode is suited to applications where a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and thus power-down. When the AD7273/AD7274 are in full power-down mode, all analog circuitry is powered down. To enter full power-down mode put the device into partial power-down mode by bringing CS high between the second and 10th falling edges of SCLK. In the next conversion cycle, interrupt the conversion process in the way shown in Figure 32 by bringing CS high before the 10th SCLK falling edge. Once CS is brought high in this window of SCLKs, the part powers down completely. Note that it is not necessary to complete 16 SCLKs once CS is brought high to enter either of the power-down modes. Glitch protection is not available when entering full power-down mode. To exit full power-down mode and power up the AD7273/ AD7274 again, perform a dummy conversion, similar to when powering up from partial power-down mode. On the falling Rev. 0 | Page 17 of 28 AD7273/AD7274 edge of CS, the device begins to power up and continues to power up until after the falling edge of the 10th SCLK as long as CS is held low. The power-up time required must elapse before a conversion can be initiated, as shown in Figure 33. See the Power-Up Times section for the power-up times associated with the AD7273/AD7274. POWER-UP TIMES The AD7273/AD7274 has two power-down modes, partial power-down and full power-down, which are described in detail in the Modes of Operation section. This section deals with the power-up time required when coming out of either of these modes. To power up from partial power-down mode, one cycle is required. Therefore, with a SCLK frequency of up to 48 MHz, one dummy cycle is sufficient to allow the device to power up from partial power-down mode. Once the dummy cycle is complete, the ADC is fully powered up and the input signal is acquired properly. The quiet time, tQUIET, must be allowed from the point where the bus goes back into three-state after the dummy conversion to the next falling edge of CS. mode, the track-and-hold, which is in hold mode while the part is powered down, returns to track mode after the first SCLK edge is received after the falling edge of CS. This is shown as Point A in Figure 31. When power supplies are first applied to the AD7273/AD7274, the ADC can power up in either of the power-down modes or in normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. Likewise, if the part is to be kept in partial power-down mode immediately after the supplies are applied, two dummy cycles must be initiated. The first dummy cycle must hold CS low until after the 10th SCLK falling edge (see Figure 29). In the second cycle, CS must be brought high between the second and 10th SCLK falling edges (see Figure 30). Alternatively, if the part is to be placed into full power-down mode after the supplies are applied, three dummy cycles must be initiated. The first dummy cycle must hold CS low until after the 10th SCLK falling edge (see Figure 29); the second and third dummy cycles place the part into full power-down mode (see Figure 32). See also the Modes of Operation section. To power up from full power-down, approximately 1 μs should be allowed from the falling edge of CS, shown in Figure 33 as tPOWER-UP. Note that during power-up from partial power-down AD7273/AD7674 CS 1 10 12 14 16 SDATA VALID DATA Figure 29. Normal Mode Operation Rev. 0 | Page 18 of 28 04973-029 SCLK AD7273/AD7274 CS 1 2 10 16 04973-030 SCLK THREE-STATE SDATA Figure 30. Entering Partial Power-Down Mode THE PART IS FULLY POWERED UP, SEE POWERUP TIMES SECTION THE PART BEGINS TO POWER UP CS 1 10 16 1 16 SCLK INVALID DATA 04973-031 A SDATA VALID DATA Figure 31. Exiting Partial Power-Down Mode THE PART ENTERS PARTIAL POWER DOWN THE PART BEGINS TO POWER UP THE PART ENTERS FULL POWER DOWN CS 1 2 10 16 1 10 16 THREE-STATE INVALID DATA SDATA 04973-032 SCLK THREE-STATE VALID DATA Figure 32. Entering Full Power-Down Mode THE PART BEGINS TO POWER UP THE PART IS FULLY POWERED UP tPOWER-UP CS 1 10 16 1 16 SDATA INVALID DATA VALID DATA Figure 33. Exiting Full Power-Down Mode Rev. 0 | Page 19 of 28 04973-033 SCLK AD7273/AD7274 7.00 POWER VS. THROUGHPUT RATE VDD = 3V 5.80 POWER (mW) 48MHz SCLK 5.40 5.00 4.60 VARIABLE SCLK 04973-034 4.20 3.80 3.40 200 400 600 800 1000 1200 1400 1600 1800 2000 THROUGHPUT (kSPS) Figure 34. Power vs. Throughput, Normal Mode 7.2 6.8 6.4 6.0 5.6 5.2 4.8 4.4 4.0 3.6 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 VDD = 3V 04973-035 Figure 35 shows that as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption over time drops accordingly. For example, if the AD7273/AD7274 are operated in continuous sampling mode with a throughput rate of 200 kSPS and a SCLK of 48 MHz (VDD = 3 V) and the devices are placed into power-down mode between conversions, the power consumption is calculated as follows. The power dissipation during normal operation is 11.6 mW (VDD = 3 V). If the power-up time is one dummy cycle, that is, 333 ns, and the remaining conversion time is 290 ns, the AD7273/AD7274 can be said to dissipate 11.6 mW for 623 ns during each conversion cycle. If the throughput rate is 200 kSPS, the cycle time is 5 μs and the average power dissipated during each cycle is 623/5,000 × 9.6 mW = 1.42 mW. Figure 35 shows the power vs. throughput rate when using the partial power-down mode between conversions at 3 V. The powerdown mode is intended for use with throughput rates of less than 600 kSPS, because at higher sampling rates there is no power saving achieved by using the power-down mode. 6.20 POWER (mW) Figure 34 shows the power consumption of the device in normal mode, in which the part is never powered down. By using the power-down mode of the AD7273/AD7274 when not performing a conversion, the average power consumption of the ADC decreases as the throughput rate decreases. 6.60 0 200 400 600 800 1000 THROUGHPUT (kSPS) Figure 35. Power vs. Throughput, Partial Power-Down Mode Rev. 0 | Page 20 of 28 AD7273/AD7274 SERIAL INTERFACE Figure 36 through Figure 38 show the detailed timing diagrams for serial interfacing to the AD7274 and AD7273, respectively. The serial clock provides the conversion clock and controls the transfer of information from the AD7273/AD7274 during conversion. If the user considers a 14-SCLK cycle serial interface for the AD7273/AD7274, CS must be brought high after the 14th SCLK falling edge. Then the last two trailing zeros are ignored, and SDATA goes back into three-state. In this case, the 3 MSPS throughput can be achieved by using a 48 MHz clock frequency. The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode and takes the bus out of three-state. The analog input is sampled and the conversion is initiated at this point. CS going low clocks out the first leading zero to be read by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges, beginning with the second leading zero. Therefore, the first falling clock edge on the serial clock provides the first leading zero and clocks out the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, because it is clocked out on the previous (15th) falling edge. For the AD7274, the conversion requires completing 14 SCLK cycles. Once 13 SCLK falling edges have elapsed, the track-andhold goes back into track mode on the next SCLK rising edge, as shown in Figure 36 at Point B. If the rising edge of CS occurs before 14 SCLKs have elapsed, the conversion is terminated and the SDATA line goes back into three-state. If 16 SCLKs are considered in the cycle, the last two bits are zeros and SDATA returns to three-state on the 16th SCLK falling edge, as shown in Figure 37. For the AD7273, the conversion requires completing 12 SCLK cycles. Once 11 SCLK falling edges elapse, the track-and-hold goes back into track mode on the next SCLK rising edge, as shown in Figure 38 at Point B. If the rising edge of CS occurs before 12 SCLKs elapse, the conversion is terminated and the SDATA line goes back into three-state. If 16 SCLKs are considered in the cycle, the AD7273 clocks out four trailing zeros for the last four bits and SDATA returns to three-state on the 16th SCLK falling edge, as shown in Figure 38. In applications with a slower SCLK, it is possible to read data on each SCLK rising edge. In such cases, the first falling edge of SCLK clocks out the second leading zero and can be read on the first rising edge. However, the first leading zero clocked out when CS goes low is missed if read within the first falling edge. The 15th falling edge of SCLK clocks out the last bit and can be read on the 15th rising SCLK edge. If CS goes low just after one SCLK falling edge elapses, CS clocks out the first leading zero and can be read on the SCLK rising edge. The next SCLK falling edge clocks out the second leading zero and can be read on the following rising edge. t1 CS tCONVERT t6 1 SCLK 2 3 4 t3 SDATA THREESTATE Z B 5 13 t7 t4 ZERO DB11 DB10 14 t5 t9 tQUIET DB9 DB1 DB0 TWO LEADING ZEROS 1/THROUGHPUT Figure 36. AD7274 Serial Interface Timing Diagram 14 SCLK Cycle Rev. 0 | Page 21 of 28 THREE-STATE 04973-036 t2 AD7273/AD7274 t1 CS tCONVERT t2 t6 1 SCLK 2 3 4 t3 THREESTATE Z 13 DB11 DB10 DB9 15 16 t5 t7 t4 ZERO 14 t8 tQUIET DB1 DB0 ZERO ZERO THREE-STATE TWO LEADING ZEROS TWO TRAILING ZEROS 04973-037 SDATA B 5 1/THROUGHPUT Figure 37. AD7274 Serial Interface Timing Diagram 16 SCLK Cycle t1 CS tCONVERT t2 2 t3 THREESTATE Z ZERO 3 4 11 12 13 t5 t4 DB9 10 DB8 14 15 16 t8 t7 DB1 DB0 ZERO ZERO tQUIET ZERO ZERO THREE-STATE TWO LEADING ZEROS FOUR TRAILING ZEROS 1/THROUGHPUT Figure 38. AD7273 Serial Interface Timing Diagram Rev. 0 | Page 22 of 28 04973-038 SDATA t6 B 1 SCLK AD7273/AD7274 Table 8. The SPORT0 Receive Configuration 1 Register (SPORT0_RCR1) MICROPROCESSOR INTERFACING AD7273/AD7274 to ADSP-BF53x The ADSP-BF53x family of DSPs interfaces directly to the AD7273/AD7274 without requiring glue logic. The SPORT0 Receive Configuration 1 register should be set up as outlined in Table 8. AD7273/ AD72741 ADSP-BF53x1 SPORT0 SCLK RCLK0 DOUT DR0PRI 1ADDITIONAL RFS0 TFSR = RFSR = 1 DT0 PINS OMITTED FOR CLARITY Figure 39. Interfacing to the ADSP-BF53x Description Sample data with falling edge of RSCLK Active low frame signal Frame every word Internal RFS used Receive MSB first Zero fill Internal receive clock Receive enabled 16-bit data-word (or can be set to 1101 for a 14-bit data-word) 04973-039 CS DIN Setting RCKFE = 1 LRFS = 1 RFSR = 1 IRFS = 1 RLSBIT = 0 RDTYPE = 00 IRCLK = 1 RSPEN = 1 SLEN = 1111 To implement the power-down modes, set SLEN to 1001 to issue an 8-bit SCLK burst. Rev. 0 | Page 23 of 28 AD7273/AD7274 APPLICATION HINTS GROUNDING AND LAYOUT The printed circuit board that houses the AD7273/AD7274 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This design facilitates using ground planes that can be easily separated. To provide optimum shielding for ground planes, a minimum etch technique is generally best. All AGND pins of the AD7273/ AD7274 should be sunk into the AGND plane. Digital and analog ground planes should be joined in only one place. If the AD7273/AD7274 are in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at only one point, a star ground point, established as close as possible to the ground pin on the AD7273/AD7274. Avoid running digital lines under the device, because this couples noise onto the die. However, the analog ground plane should be allowed to run under the AD7273/AD7274 to avoid noise coupling. The power supply lines to the AD7273/AD7274 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. To avoid radiating noise to other sections of the board, components with fast-switching signals, such as clocks, should be shielded with digital ground, and they should never be run near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces on opposite sides of the board should run at right angles to each other. A microstrip technique is by far the best method, but it is not always possible to use this approach with a doublesided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 μF ceramic capacitors in parallel with 0.1 μF capacitors to AGND/DGND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 μF capacitors should have low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic or surface-mount types of capacitors. Capacitors with low ESR and low ESI provide a low impedance path to ground at high frequencies, which allows them to handle transient currents due to internal logic switching. EVALUATING THE AD7273/AD7274 PERFORMANCE The recommended layout for the AD7273/AD7274 is outlined in the evaluation board documentation. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7273/AD7274 evaluation board, as well as many other Analog Devices evaluation boards ending in the CB designator, to demonstrate/evaluate the ac and dc performance of the AD7273/AD7274. The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the AD7273/AD7274. The software and documentation are on a CD shipped with the evaluation board. Rev. 0 | Page 24 of 28 AD7273/AD7274 OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1 2 3 4 1.60 BSC 3.00 BSC 2.80 BSC 8 3.00 BSC PIN 1 INDICATOR 1 5 4.90 BSC 4 0.65 BSC *0.90 0.87 0.84 1.95 BSC PIN 1 0.65 BSC *1.00 MAX 0.10 MAX 0.38 0.22 0.20 0.08 SEATING PLANE 0.60 0.45 0.30 8° 4° 0° *COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.23 0.08 0.80 0.60 0.40 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 40. 8-Lead Thin Small Outline Transistor Package [TSOT] (UJ-8) Dimensions shown in millimeters Figure 41. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model AD7274BRM AD7274BRMZ 2 AD7274BRMZ-REEL2 AD7274BUJ-500RL7 AD7274BUJZ-500RL72 AD7274BUJZ-REEL72 AD7273BRMZ2 AD7273BRMZ-REEL2 AD7273BUJ-REEL7 AD7273BUJZ-500RL72 EVAL-AD7274CB 3 EVAL-AD7273CB3 EVAL-CONTROL BRD2 4 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Linearity Error (LSB) 1 ±1 max ±1 max ±1 max ±1 max ±1 max ±1 max ±0.5 max ±0.5 max ±0.5 max ±0.5 max Package Description 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Thin Small Outline Transistor Package (TSOT) 8-Lead Thin Small Outline Transistor Package (TSOT) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Mini Small Outline Package (MSOP) 8-Lead Thin Small Outline Transistor Package (TSOT) 8-Lead Thin Small Outline Transistor Package (TSOT) Evaluation Board Evaluation Board Control Board 1 Package Option RM-8 RM-8 RM-8 UJ-8 UJ-8 UJ-8 RM-8 RM-8 UJ-8 UJ-8 Branding C1V C34 C34 C1V C34 C34 C33 C33 C1U C33 Linearity error refers to integral nonlinearity. Z = Pb-free part. This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes. 4 This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards that end in a CB designator. To order a complete evaluation kit, the particular ADC evaluation board (such as EVAL-AD7273CB/AD7274CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the relevant evaluation board technical note for more information. 2 3 Rev. 0 | Page 25 of 28 AD7273/AD7274 NOTES Rev. 0 | Page 26 of 28 AD7273/AD7274 NOTES Rev. 0 | Page 27 of 28 AD7273/AD7274 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04973–0–9/05(0) T T Rev. 0 | Page 28 of 28