AD7403TRIZ-EP-RL7

16-Bit, Isolated Sigma-Delta Modulator AD7403-EP Enhanced Product FEATURES FUNCTIONAL BLOCK DIAGRAM VDD1 BUF VDD2 CLK DECODER CLK ENCODER DATA ENCODER DATA DECODER MCLKIN (5MHz TO 16MHz) REF VIN+ Σ-Δ ADC VIN– MDAT AD7403-EP GND2 GND1 13395-001 5 MHz to 16 MHz external clock input rate 16 bits, no missing codes Signal-to-noise ratio (SNR): 88 dB typical Effective number of bits (ENOB): 14.2 bits typical Offset drift vs. temperature: 1.6 µV/°C typical On-board digital isolator On-board reference Full-scale analog input range: ±320 mV High common-mode transient immunity: >25 kV/µs Wide-body SOIC with increased creepage package Slew rate limited output for low EMI Safety and regulatory approvals UL recognition 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 1250 VPEAK Figure 1. ENHANCED PRODUCT FEATURES Defense and aerospace applications (AQEC standard) Military temperature range: −55°C to +125°C Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request APPLICATIONS Shunt current monitoring AC motor controls Power and solar inverters Wind turbine inverters Data acquisition systems Analog-to-digital and optoisolator replacements GENERAL DESCRIPTION The AD7403-EP1 is a high performance, second-order, Σ-Δ modulator that converts an analog input signal into a high speed, single-bit data stream, with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The device operates from a 5 V (VDD1) power supply and accepts a differential input signal of ±250 mV (±320 mV full-scale). The differential input is ideally suited to shunt voltage monitoring in high voltage applications where galvanic isolation is required. 1 The analog input is continuously sampled by a high performance analog modulator, and converted to a ones density digital output stream with a data rate of up to 16 MHz. The original information can be reconstructed with an appropriate digital filter to achieve 88 dB signal to noise ratio (SNR) at 78.1 kSPS. The serial interface is digitally isolated. High speed complementary metal oxide semiconductor (CMOS) technology, combined with monolithic transformer technology, means the on-chip isolation provides outstanding performance characteristics, superior to alternatives such as optocoupler devices. The AD7403-EP device is offered in a 16-lead, wide-body SOIC package and has an operating temperature range of −55°C to +125°C. Additional application and technical information can be found in the AD7403 data sheet. Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7403-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Enhanced Product Features ............................................................ 1 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics ...............................................................................6 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................7 General Description ......................................................................... 1 ESD Caution...................................................................................7 Functional Block Diagram .............................................................. 1 Pin Configurations and Function Descriptions ............................8 Revision History ............................................................................... 2 Typical Performance Characteristics ..............................................9 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 12 Timing Specifications .................................................................. 4 Ordering Guide .......................................................................... 12 Package Characteristics ............................................................... 5 Insulation and Safety Related Specifications ............................ 5 Regulatory Information ............................................................... 5 REVISION HISTORY 4/16—Revision 0: Initial Version Rev. 0 | Page 2 of 12 Enhanced Product AD7403-EP SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 4.5 V to 5.5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, TA = −55°C to +125°C, fMCLKIN = 5 MHz to 16 MHz, tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground. Table 1. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity (INL) 1 Differential Nonlinearity (DNL)1 Offset Error1 Offset Drift vs. Temperature 2 Min ISOLATION TRANSIENT IMMUNITY1 LOGIC INPUTS Input Voltage High (VIH) Low (VIL) Input Current (IIN) Input Capacitance (CIN) LOGIC OUTPUTS Output Voltage High (VOH) Low (VOL) POWER REQUIREMENTS VDD1 VDD2 IDD1 IDD2 Power Dissipation 1 2 ±2 ±12 ±0.99 ±0.9 3.8 3.1 ±0.2 1.6 1.3 50 ±0.2 65 40 ±0.6 −320 −250 Input Common-Mode Voltage Range Dynamic Input Current DC Leakage Current Input Capacitance DYNAMIC SPECIFICATIONS1 Signal-to-Noise-and-Distortion Ratio (SINAD) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Effective Number of Bits (ENOB) Noise Free Code Resolution Max 16 Offset Drift vs. VDD12 Gain Error1 Gain Error Drift vs. Temperature2 Gain Error Drift vs. VDD12 ANALOG INPUT Input Voltage Range Typ ±0.95 95 60 +320 +250 −200 to +300 ±45 0.05 ±0.01 14 ±50 ±0.6 Unit Test Conditions/Comments Bits LSB LSB mV µV/°C µV/°C µV/V % FSR ppm/°C µV/°C mV/V Filter output truncated to 16 bits mV mV mV µA µA µA pF Guaranteed no missed codes to 16 bits 0°C to 85°C Full-scale range For specified performance VIN+ = ±250 mV, VIN− = 0 V VIN+ = 0 V, VIN− = 0 V VIN+ = 1 kHz 82 86 13.1 14 25 87 88 −94 −95 14.2 dB dB dB dB Bits Bits kV/µs 30 CMOS with Schmitt trigger 0.8 × VDD2 0.2 × VDD2 ±0.6 10 V V µA pF 0.4 V V IO = −200 µA IO = 200 µA 5.5 5.5 36 18 297 V V mA mA mW VDD1 = 5.5 V VDD2 = 5.5 V VDD1 = VDD2 = 5.5 V VDD2 − 0.1 4.5 4.5 30 12 231 See the Terminology section of the AD7403 datasheet. Not production tested. Sample tested during initial release to ensure compliance. Rev. 0 | Page 3 of 12 AD7403-EP Enhanced Product TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 4.5 V to 5.5 V, TA = −55°C to +125°C, unless otherwise noted. Sample tested during initial release to ensure compliance. It is recommended to read MDAT on the MCLKIN rising edge. Table 2. Parameter fMCLKIN t11 t21 t3 t4 Limit at TMIN, TMAX Typ Max 16 45 12 0.45 × tMCLKIN 0.45 × tMCLKIN Unit MHz ns ns ns ns Description Master clock input frequency Data access time after MCLKIN rising edge Data hold time after MCLKIN rising edge Master clock low time Master clock high time Defined as the time required from an 80% MCLKIN input level to when the output crosses 0.8 V or 2.0 V for VDD2 = 3 V to 3.6 V or when the output crosses 0.8 V or 0.7 × VDD2 for VDD2 = 4.5 V to 5.5 V as outlined in Figure 2. Measured with a ±200 μA load and a 25 pF load capacitance. t4 80% MCLKIN t1 t2 t3 2.0V OR 0.7 × VDD2 1 MDAT 0.8V 1SEE NOTE 1 OF TABLE 3 FOR FURTHER DETAILS. Figure 2. Data Timing Rev. 0 | Page 4 of 12 13395-002 1 Min 5 Enhanced Product AD7403-EP PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 IC Junction to Ambient Thermal Resistance 1 Symbol RI-O CI-O θJA Min Typ 1012 2.2 45 Max Unit Ω pF °C/W Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces The device is considered a 2-terminal device. For AD7403-EP, Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 4. Parameter Input to Output Momentary Withstand Voltage Minimum External Air Gap (Clearance) Symbol VISO L(I01) Value 5000 min 8.3 min 1, 2 Unit V mm Minimum External Tracking (Creepage) L(I02) 8.3 min1 mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.034 min >400 II mm V Test Conditions/Comments 1 minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303 Part 1 3 Material Group (DIN VDE 0110, 1/89, Table I)3 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m. Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained. 3 CSA CTI rating for the AD7403-EP is >575 V and therefore Material Group II isolation group. 1 2 REGULATORY INFORMATION Table 5. UL 1 Recognized under 1577 Component Recognition Program1 5000 V rms Isolation Voltage Single Protection File E214100 CSA Approved under CSA Component Acceptance Notice 5A VDE 2 Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Basic insulation per CSA 60950-1-07 and IEC 60950-1, 830 V rms (1173 VPEAK), maximum working voltage 3 Reinforced insulation per CSA 60950-1-07 and IEC 60950-1. 415 V rms (586 VPEAK) maximum working voltage3 Reinforced insulation per IEC 60601-1, 250 V rms (353 VPEAK) maximum working voltage File 205078 Reinforced insulation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, 1250 VPEAK File 2471900-4880-0001 In accordance with UL 1577, each AD7403-EP is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA). In accordance with DIN V VDE V 0884-10, each AD7403-EP is proof tested by applying an insulation test voltage ≥ 2344 VPEAK for 1 second (partial discharge detection limit = 5 pC). 3 Rating is calculated for a pollution degree of 2 and a Material Group III. The AD7403-EP RI-16-2 package material is rated by CSA to a CTI of >575 V and therefore Material Group II. 1 2 Rev. 0 | Page 5 of 12 AD7403-EP Enhanced Product DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 6. Description INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage ≤300 V rms For Rated Mains Voltage ≤450 V rms For Rated Mains Voltage ≤600 V rms For Rated Mains Voltage ≤1000 V rms CLIMATIC CLASSIFICATION POLLUTION DEGREE (DIN VDE 0110, TABLE 1) MAXIMUM WORKING INSULATION VOLTAGE INPUT TO OUTPUT TEST VOLTAGE, METHOD B1 VIORM × 1.875 = VPR, 100% Production Test, tm = 1 Second, Partial Discharge < 5 pC INPUT TO OUTPUT TEST VOLTAGE, METHOD A After Environmental Test Subgroup 1 VIORM × 1.6 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC After Input and/or Safety Test Subgroup 2/ Safety Test Subgroup 3 VIORM × 1.2 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 Seconds) SURGE ISOLATION VOLTAGE 1.2 µs Rise Time, 50 μs, 50% Fall Time SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, SEE Figure 3) Case Temperature Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation INSULATION RESISTANCE AT TS, VIO = 500 V Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. 0 | Page 6 of 12 13395-003 SAFE OPERATING POWER (W) 1 200 VIORM I to IV I to IV I to IV I to IV 40/105/21 2 1250 VPEAK 2344 VPEAK 2000 VPEAK 1500 8000 7500 VPEAK VPEAK VPEAK VPEAK 150 2.78 >109 °C W Ω TS PSO RIO 2 50 100 150 AMBIENT TEMPERATURE (°C) Unit VIOTM VIOSM 3 0 Characteristic VPD(M) VPR(M) 4 0 Symbol Enhanced Product AD7403-EP ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground. Table 7. Parameter VDD1 to GND1 VDD2 to GND2 Analog Input Voltage to GND1 Digital Input Voltage to GND2 Output Voltage to GND2 Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature Pb-Free Temperature, Soldering Reflow ESD FICDM2 HBM3 Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −1 V to VDD1 + 0.3 V −0.3 V to VDD2 + 0.5 V −0.3 V to VDD2 + 0.3 V ±10 mA −55°C to +125°C −65°C to +150°C 150°C Table 8. Maximum Continuous Working Voltage1 Parameter AC Voltage Bipolar Waveform Max Unit Constraint 1250 VPEAK Unipolar Waveform 1250 VPEAK 1250 VPEAK 20-year minimum lifetime (VDE approved working voltage) 20-year minimum lifetime 20-year minimum lifetime DC Voltage 1 Maximum continuous working voltage refers to continuous voltage magnitude imposed across the isolation barrier. ESD CAUTION 260°C 2 kV ±1250 V ±4000 V Transient currents of up to 100 mA do not cause SCR to latch up. JESD22-C101; RC network: 1 Ω, Cpkg; Class: IV. 3 ESDA/JEDEC JS-001-2011; RC network: 1.5 kΩ, 100 pF; Class: 3A. 1 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 7 of 12 AD7403-EP Enhanced Product PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 GND2 VIN+ 2 15 NIC2 NIC1 5 AD7403-EP TOP VIEW (Not to Scale) 14 VDD2 13 MCLKIN 12 NIC2 NIC1 6 11 MDAT VDD1 7 10 NIC2 GND1 8 9 GND2 1NIC = NOT INTERNALLY CONNECTED. CONNECT TO V DD1 , GND1, OR LEAVE FLOATING. 2NIC = NOT INTERNALLY CONNECTED. CONNECT TO V DD2 , GND2, OR LEAVE FLOATING. 13395-004 VIN– 3 GND1 4 Figure 4. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1, 7 Mnemonic VDD1 2 3 4, 8 5, 6 9, 16 10, 12, 15 11 VIN+ VIN− GND1 NIC GND2 NIC MDAT 13 MCLKIN 14 VDD2 Description Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7403-EP and is relative to GND1. For device operation, connect the supply voltage to both Pin 1 and Pin 7. Decouple each supply pin to GND1 with a 10 μF capacitor in parallel with a 1 nF capacitor. Positive Analog Input. Negative Analog Input. Normally connected to GND1. Ground 1. This pin is the ground reference point for all circuitry on the isolated side. Not Internally Connected. These pins are not internally connected. Connect to VDD1, GND1, or leave floating. Ground 2. This pin is the ground reference point for all circuitry on the nonisolated side. Not Internally Connected. These pins are not internally connected. Connect to VDD2, GND2, or leave floating. Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are clocked out on the rising edge of the MCLKIN input and are valid on the following MCLKIN rising edge. Master Clock Logic Input. 5 MHz to 20 MHz frequency range. The bit stream from the modulator is propagated on the rising edge of the MCLKIN. Supply Voltage, 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2. Decouple this supply to GND2 with a 100 nF capacitor. Rev. 0 | Page 8 of 12 Enhanced Product AD7403-EP TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD1 = 5 V, VDD2 = 5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, fMCLKIN = 16 MHz, using a sinc3 filter with a 256 oversampling ratio (OSR), unless otherwise noted. 0 200mV p-p SINE WAVE ON VDD1 1nF DECOUPLING 0 MCLKIN = 16MHz MCLKIN = 10MHz fIN = 1kHz –40 MAGNITUDE (dB) –40 PSRR (dB) SNR = 88.6dB SINAD = 88.3dB THD = –100.5dB –20 –20 –60 –80 –60 –80 –100 –100 –120 –120 0 200 400 600 800 SUPPLY RIPPLE FREQUENCY (kHz) 1000 –160 0 CMRR (dB) –40 15 20 25 30 Figure 8. Typical Fast Fourier Transform (FFT) 1.0 MCLKIN = 16MHz, SINC3 DECIMATION RATE = 256 MCLKIN = 10MHz, SINC3 DECIMATION RATE = 256 MCLKIN = 16MHz, UNFILTERED MCLKIN = 10MHz, UNFILTERED SHORTED INPUTS 200mV p-p SINE WAVE ON INPUTS MCLK = 16MHz 0.8 0.6 DNL ERROR (LSB) –20 10 FREQUENCY (kHz) Figure 5. PSRR vs. Supply Ripple Frequency 0 5 13395-008 –140 13395-005 –140 –60 –80 0.4 0.2 0 –0.2 –0.4 –100 –0.6 –120 1 10 100 –1.0 13395-006 –140 0.1 1000 RIPPLE FREQUENCY (kHz) 0 10 20 30 40 50 60 50 60 CODE (k) Figure 6. CMRR vs. Common-Mode Ripple Frequency 13395-009 –0.8 Figure 9. Typical DNL Error 1.5 90 89 1.0 88 INL ERROR (LSB) 86 85 84 0.5 0 83 16MHz MCLKIN, 4.5V VDD1 16MHz MCLKIN, 5V VDD1 16MHz MCLKIN, 5.5V VDD1 81 80 100 1k ANALOG INPUT FREQUENCY (Hz) 10k –1.0 0 10 20 30 40 CODE (k) Figure 10. Typical INL Error Figure 7. SINAD vs. Analog Input Frequency Rev. 0 | Page 9 of 12 13395-010 –0.5 82 13395-007 SINAD (dB) 87 AD7403-EP Enhanced Product 800 692381 600 150 500 100 400 300 200 0 –50 1147 32764 32765 32766 32767 32768 1061 0 32769 32770 CODE –150 –60 13395-011 0 –35 SNR SINAD 15 40 65 90 115 140 TEMPERATURE (°C) Figure 11. Histogram of Codes at Code Center 100 –10 13395-014 –100 100 0 50 160941 144470 10MHz 16MHz VDD1 = 5V 200 OFFSET (µV) HITS PER CODE (k) 700 250 MCLKIN = 10MHz VIN+ = VIN– = 0V 1M SAMPLES Figure 14. Offset vs. Temperature 5 fIN = 1kHz MCLKIN = 10MHz MCLKIN = 16MHz 4 3 2 GAIN (mV) SNR AND SINAD (dB) 90 80 1 0 –1 –2 70 –3 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) –5 –60 13395-012 60 –50 15 40 65 90 115 140 Figure 15. Gain Error vs. Temperature 35 THD, MCLK = 16MHz SFDR, MCLK = 16MHz fIN = 1kHz 30 –70 25 –90 –100 15 MCLKIN = 16MHz, MCLKIN = 16MHz, MCLKIN = 16MHz, MCLKIN = 16MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, 10 –110 –120 –50 20 5 –25 0 25 50 75 100 TEMPERATURE (°C) 125 150 Figure 13. THD and SFDR vs. Temperature 0 4.50 4.75 5.00 5.25 –55°C 0°C +25°C +125°C –55°C 0°C +25°C +125°C 5.50 VDD1 (V) Figure 16. IDD1 vs. VDD1 at Various Temperatures and Clock Rates Rev. 0 | Page 10 of 12 13395-016 IDD1 (mA) –80 13395-013 SNR AND SINAD (dB) –10 TEMPERATURE (°C) Figure 12. SNR and SINAD vs. Temperature –60 –35 13395-015 –4 Enhanced Product AD7403-EP 12 30 TA = –55°C TA = –40°C TA = 0°C TA = +25°C TA = +85°C TA = +125°C 29 28 TA = –55°C TA = –40°C TA = 0°C TA = +25°C TA = +85°C TA = +125°C DC INPUT DC INPUT 11 IDD2 (mA) IDD1 (mA) 27 26 25 10 24 0 –125 250 125 VIN+ DC INPUT (mV) 10 –250 13395-017 22 –250 0 –125 250 125 VIN+ DC INPUT (mV) 13395-019 23 Figure 19. IDD2 vs. VIN+ DC Input at Various Temperatures Figure 17. IDD1 vs. VIN+ DC Input at Various Temperatures 50 14 DC INPUT 40 12 30 IIN+ (µA) 20 8 6 MCLKIN = 16MHz, MCLKIN = 16MHz, MCLKIN = 16MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, 3.5 –55°C 0°C +85°C –55°C 0°C +85°C MCLKIN = 16MHz, MCLKIN = 16MHz, MCLKIN = 16MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, MCLKIN = 10MHz, 4.5 4.0 5.0 –40°C +25°C +125°C –40°C +25°C +125°C –30 MCLKIN = 5MHz MCLKIN = 10MHz MCLKIN = 16MHz –40 5.5 VDD2 (V) –50 –320 –240 –160 –80 0 80 160 240 VIN+ DC INPUT (mV) Figure 20. IIN+ vs. VIN+ DC Input at Various Clock Rates Figure 18. IDD2 vs. VDD2 at Various Temperatures and Clock Rates Rev. 0 | Page 11 of 12 320 13395-020 0 3.0 0 –20 4 2 10 –10 13395-018 IDD2 (mA) 10 AD7403-EP Enhanced Product OUTLINE DIMENSIONS 12.85 12.75 12.65 1.93 REF 16 9 7.60 7.50 7.40 10.51 10.31 10.11 8 PIN 1 MARK 2.64 2.54 2.44 2.44 2.24 0.30 0.20 0.10 COPLANARITY 0.1 0.71 0.50 0.31 0.25 BSC GAGE PLANE 45° SEATING PLANE 1.27 BSC 1.01 0.76 0.51 0.46 0.36 COMPLIANT TO JEDEC STANDARDS MS-013-AC 0.32 0.23 8° 0° 11-15-2011-A 1 Figure 21. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-16-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7403TRIZ-EP AD7403TRIZ-EP-RL7 EVAL-AD7403FMCZ EVAL-SDP-CH1Z 1 Temperature Range −55°C to +125°C −55°C to +125°C Package Description 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] AD7403 Evaluation Board System Demonstration Platform Z = RoHS Compliant Part. ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13395-0-4/16(0) Rev. 0 | Page 12 of 12 Package Option RI-16-2 RI-16-2