AD743

Ultralow Noise BiFET Op Amp AD743 FEATURES Ultralow Noise Performance 2.9 nV/√Hz at 10 kHz 0.38 V p-p, 0.1 Hz to 10 Hz 6.9 fA/√Hz Current Noise at 1 kHz Excellent DC Performance 0.5 mV Max Offset Voltage 250 pA Max Input Bias Current 1000 V/mV Min Open-Loop Gain AC Performance 2.8 V/ s Slew Rate 4.5 MHz Unity-Gain Bandwidth THD = 0.0003% @ 1 kHz Available in Tape and Reel in Accordance with EIA-481A Standard APPLICATIONS Sonar Preamplifiers High Dynamic Range Filters (>140 dB) Photodiode and IR Detector Amplifiers Accelerometers GENERAL DESCRIPTION CONNECTION DIAGRAMS 8-Lead PDIP (N) NULL –IN +IN –VS 1 2 3 4 TOP VIEW 16-Lead SOIC (R) NC OFFSET NULL –IN NC +IN –VS NC NC 1 2 3 4 5 6 7 8 TOP VIEW AD743 8 NC 7 6 5 +VS OUT NULL 8 16 NC AD743 15 NC 14 NC 13 +VS 12 OUTPUT 11 OFFSET NULL NC = NO CONNECT 10 NC 9 NC NC = NO CONNECT The AD743 is an ultralow noise, precision, FET input, monolithic operational amplifier. It offers a combination of the ultralow voltage noise generally associated with bipolar input op amps and the very low input current of a FET input device. Furthermore, the AD743 does not exhibit an output phase reversal when the negative common-mode voltage limit is exceeded. The AD743’s guaranteed, maximum input voltage noise of 4.0 nV/√Hz at 10 kHz is unsurpassed for a FET input monolithic op amp, as is the maximum 1.0 µV p-p, 0.1 Hz to 10 Hz noise. The AD743 also has excellent dc performance with 250 pA maximum input bias current and 0.5 mV maximum offset voltage. The AD743 is specifically designed for use as a preamp in capacitive sensors, such as ceramic hydrophones. The AD743J is rated over the commercial temperature range of 0°C to 70°C. The AD743 is available in a 16-lead SOIC and 8-lead PDIP. PRODUCT HIGHLIGHTS 2. The combination of low voltage and low current noise make the AD743 ideal for charge sensitive applications such as accelerometers and hydrophones. 3. The low input offset voltage and low noise level of the AD743 provide >140 dB dynamic range. 4. The typical 10 kHz noise level of 2.9 nV/√Hz permits a three op amp instrumentation amplifier, using three AD743s, to be built which exhibits less than 4.2 nV/√Hz noise at 10 kHz and which has low input bias currents. 1000 R SOURCE EO R SOURCE OP27 AND RESISTOR (—) INPUT VOLTAGE NOISE (nV/ Hz) 100 AD743 AND RESISTOR OR OP27 AND RESISTOR 10 AD743 AND RESISTOR ( ) 1. The low offset voltage and low input offset voltage drift of the AD743 coupled with its ultralow noise performance mean that the AD743 can be used for upgrading many applications now using bipolar amplifiers. RESISTOR NOISE ONLY (– – –) 1 100 1k 10k 100k 1M 10M SOURCE RESISTANCE ( ) Figure 1. Input Voltage Noise vs. Source Resistance R EV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD743–SPECIFICATIONS Parameter INPUT OFFSET VOLTAGE Initial Offset Initial Offset vs. Temperature vs. Supply (PSRR) vs. Supply (PSRR) INPUT BIAS CURRENT 3 Either Input Either Input @ TMAX Either Input Either Input, VS = ± 5 V INPUT OFFSET CURRENT Offset Current @ TMAX FREQUENCY RESPONSE Gain BW, Small Signal Full Power Response Slew Rate, Unity Gain Settling Time to 0.01% Total Harmonic Distortion4 (TPC 16) INPUT IMPEDANCE Differential Common Mode INPUT VOLTAGE RANGE Differential5 Common-Mode Voltage Over Maximum Operating Range 6 Common-Mode Rejection Ratio INPUT VOLTAGE NOISE 1 (@ 25 C and 15 V dc, unless otherwise noted.) Typ 0.25 Max 1.0 1.5 Unit mV mV µV/°C dB dB pA nA pA pA pA nA MHz kHz V/µs µs % Ω pF Ω pF V V V dB dB µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA/√Hz V/mV V/mV V/mV V V V V mA V V mA Conditions Min TMIN to TMAX TMIN to TMAX 12 V to 18 V2 TMIN to TMAX VCM = 0 V VCM = 0 V VCM = 10 V VCM = 0 V VCM = 0 V VCM = 0 V G = –1 VO = 20 V p-p G = –1 f = 1 kHz G = –1 90 88 2 96 150 250 30 40 400 8.8 600 200 150 2.2 4.5 25 2.8 6 0.0003 1 3 1 0 10 2 0 1 0 11 1 8 ± 20 +13.3, –10.7 VCM = ± 10 V TMIN to TMAX 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 1 kHz VO = ± 10 V, RLOAD ≥ 2 kΩ TMIN to TMAX RLOAD = 600 Ω RLOAD ≥ 600 Ω RLOAD ≥ 600 Ω TMIN to TMAX RLOAD ≥ 2 kΩ Short Circuit 1000 800 1200 +13, –12 +13.6, –12.6 +12, –10 ± 12 20 +13.8, –13.1 40 ± 15 8.1 No. of Transistors 50 –10 80 78 +12 95 0.38 5.5 3.6 3.2 2.9 6.9 4000 5.0 4.0 INPUT CURRENT NOISE OPEN-LOOP GAIN OUTPUT CHARACTERISTICS Voltage Current POWER SUPPLY Rated Performance Operating Range Quiescent Current TRANSISTOR COUNT ± 4.8 ± 18 10.0 NOTES 1 Input offset voltage specifications are guaranteed after five minutes of operation at T A = 25°C. 2 Test conditions: +V S = 15 V, –VS = 12 V to 18 V; and +V S = 12 V to 18 V, –V S = 15 V. 3 Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = 25°C. For higher temperature, the current doubles every 10 °C. 4 Gain = –1, R L = 2 kΩ, CL = 10 pF. 5 Defined as voltage between inputs, such that neither exceeds ± 10 V from common. 6 The AD743 does not exhibit an output phase reversal when the negative common-mode limit is exceeded. All min and max specifications are guaranteed. Specifications subject to change without notice. –2– R EV. E AD743 ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Internal Power Dissipation2 Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS Storage Temperature Range (N, R) . . . . . . . –65°C to +125°C Operating Temperature Range AD743J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-lead PDIP: JA = 100°C/W, JC = 30°C/W. 16-lead SOIC: JA = 100°C/W, JC = 30°C/W. Model AD743JN AD743JR-16 AD743JR-16-REEL AD743JR-16-REEL7 *N = PDIP; R = SOIC. Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C Package Option* N-8 R-16 Tape and Reel Tape and Reel ESD SUSCEPTIBILITY An ESD classification per method 3015.6 of MIL-STD-883C has been performed on the AD743. The AD743 is a Class 1 device, passing at 1000 V and failing at 1500 V on null Pins 1 and 5, when tested, using an IMCS 5000 automated ESD tester. Pins other than null pins fail at greater than 2500 V. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD743 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. R EV. E –3– AD743–Typical Performance Characteristics (@ 25 C, VS = 15 V) 20 RLOAD = 10k OUTPUT VOLTAGE SWING (V) 20 OUTPUT VOLTAGE SWING (V p-p) 20 RLOAD = 10k 15 POSITIVE SUPPLY 35 30 25 20 15 10 5 0 10 INPUT VOLTAGE SWING (V) 15 +VIN 10 10 –VIN 5 50 NEGATIVE SUPPLY 0 0 5 10 15 SUPPLY VOLTAGE ( V) 20 0 0 5 10 15 SUPPLY VOLTAGE ( V) 100 1k LOAD RESISTANCE ( ) 10k TPC 1. Input Voltage Swing vs. Supply Voltage TPC 2. Output Voltage Swing vs. Supply Voltage TPC 3. Output Voltage Swing vs. Load Resistance 12 10–6 10–7 200 100 QUIESCENT CURRENT (mA) 9 INPUT BIAS CURRENT (A) OUTPUT IMPEDANCE ( ) 10–8 10–9 10–10 10–11 10 6 1 3 0.1 0 0 5 10 15 SUPPLY VOLTAGE ( V) 20 10–12 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE ( C) 0.01 10k 100k 1M 10M FREQUENCY (Hz) 100M TPC 4. Quiescent Current vs. Supply Voltage 300 TPC 5. Input Bias Current vs. Temperature 80 70 TPC 6. Output Impedance vs. Frequency (Closed-Loop Gain = –1) 7.0 GAIN BANDWIDTH PRODUCT (MHz) INPUT BIAS CURRENT (pA) 6.0 200 CURRENT LIMIT (mA) 60 50 40 30 20 10 + OUTPUT CURRENT 5.0 100 – OUTPUT CURRENT 4.0 3.0 0 –12 0 –9 –6 –3 3 6 9 COMMON-MODE VOLTAGE (V) 12 0 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE ( C) 2.0 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE ( C) TPC 7. Input Bias Current vs. Common-Mode Voltage TPC 8. Short Circuit Current Limit vs. Temperature TPC 9. Gain Bandwidth Product vs. Temperature –4– R EV. E AD743 100 100 3.5 150 80 80 OPEN-LOOP GAIN (dB) OPEN-LOOP GAIN (dB) PHASE 60 60 PHASE MARGIN (Degrees) 140 SLEW RATE (V/ s) 3.0 130 40 GAIN 20 40 120 20 2.5 0 –20 100 0 –20 100M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 2.0 –60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE ( C) 80 0 15 5 10 SUPPLY VOLTAGE ( V) 20 TPC 10. Open-Loop Gain and Phase vs. Frequency TPC 11. Slew Rate vs. Temperature (Gain = –1) TPC 12. Open-Loop Gain vs. Supply Voltage, RLOAD = 2 kΩ 120 COMMON-MODE REJECTION (dB) 120 35 30 POWER SUPPLY REJECTION (dB) 100 VCM = 10V 100 OUTPUT VOLTAGE (V p-p) 80 80 + SUPPLY 60 25 RL = 2k 20 15 10 5 0 10 60 40 40 – SUPPLY 20 20 0 100 1k 10k 100k 1M 0 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) 100 1k FREQUENCY (Hz) 10k TPC 13. Common-Mode Rejection vs. Frequency TPC 14. Power Supply Rejection vs. Frequency TPC 15. Large Signal Frequency Response VOLTAGE NOISE (PREFERRED TO INPUT) (nV/ Hz) CURRENT NOISE SPECTRAL DENSITY (fA/ Hz) –70 –80 –90 THD (dB) 100 1k CLOSED-LOOP GAIN = 10 1 100 –100 GAIN = +10 –110 –120 GAIN = –1 –130 –140 10 1 CLOSED-LOOP GAIN = 10 10 100 1k 10k FREQUENCY (Hz) 100k 0.1 1 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 1 10 100 1k FREQUENCY (Hz) 10k 100k TPC 16. Total Harmonic Distortion vs. Frequency TPC 17. Input Voltage Noise Spectral Density TPC 18. Input Current Noise Spectral Density R EV. E –5– AD743 69 63 57 NUMBER OF UNITS 51 45 39 33 27 21 15 9 3 2.5 2.7 2.9 3.1 3.3 3.5 3.8 INPUT VOLTAGE NOISE (nV/ Hz) TPC 19. Typical Noise Distribution @ 10 kHz (602 Units) TPC 23. Unity-Gain Follower Small Signal Pulse Response 100pF +VS 1F 2 7 AD743 4 –VS 0.1 F 6 15 VOS ADJUST 2M 1M 2k +VS 2k VIN 2 7 AD743 3 4 –VS SQUARE WAVE INPUT 1F 0.1 F 1F 6 CL 100pF 0.1 F VOUT 3 0.1 F 1F TPC 20. Offset Null Configuration TPC 24. Unity-Gain Inverter +VS 2 VIN 300 *3 7 AD743 4 –VS SQUARE WAVE INPUT 1F 0.1 F 1F 6 RL 2k CL 10pF 0.1 F VOUT *OPTIONAL, NOT REQUIRED TPC 21. Unity-Gain Follower TPC 25. Unity-Gain Inverter Large Signal Pulse Response TPC 22. Unity-Gain Follower Large Signal Pulse Response TPC 26. Unity-Gain Inverter Small Signal Pulse Response –6– R EV. E AD743 OP AMP PERFORMANCE: JFET VS. BIPOLAR The AD743 is the first monolithic JFET op amp to offer the low input voltage noise of an industry-standard bipolar op amp without its inherent input current errors. This is demonstrated in Figure 2, which compares input voltage noise versus input source resistance of the OP27 and AD743 op amps. From this figure, it is clear that at high source impedance the low current noise of the AD743 also provides lower total noise. It is also important to note that with the AD743 this noise reduction extends all the way down to low source impedances. The lower dc current errors of the AD743 also reduce errors due to offset and drift at high source impedances (Figure 3). 1000 low frequency noise performance. Random air currents can generate varying thermocouple voltages that appear as low frequency noise; therefore, sensitive circuitry should be well shielded from air flow. Keeping absolute chip temperature low also reduces low frequency noise in two ways. First, the low frequency noise is strongly dependent on the ambient temperature and increases above +25°C. Second, since the gradient of temperature from the IC package to ambient is greater, the noise generated by random air currents, as previously mentioned, will be larger in magnitude. Chip temperature can be reduced both by operation at reduced supply voltages and by the use of a suitable clip-on heat sink, if possible. Low frequency current noise can be computed from the magnitude of the dc bias current R SOURCE EO R SOURCE OP27 AND RESISTOR (—) INPUT VOLTAGE NOISE (nV/ Hz) ˜ = 2qI ∆f In B and increases below approximately 100 Hz with a 1/f power spectral density. For the AD743, the typical value of current noise is 6.9 fA/√Hz at 1 kHz. Using the formula 100 AD743 AND RESISTOR OR OP27 AND RESISTOR 10 AD743 AND RESISTOR ( ) ˜ In = 4kT / R∆f to compute the Johnson noise of a resistor, expressed as a current, one can see that the current noise of the AD743 is equivalent to that of a 3.45 108 Ω source resistance. RESISTOR NOISE ONLY (– – –) 1 100 1k 10k 100k 1M 10M SOURCE RESISTANCE ( ) Figure 2. Total Input Noise Spectral Density @ 1 kHz vs. Source Resistance 100 At high frequencies, the current noise of a FET increases proportionately to frequency. This noise is due to the “real” part of the gate input impedance, which decreases with frequency. This noise component usually is not important, since the voltage noise of the amplifier impressed upon its input capacitance is an apparent current noise of approximately the same magnitude. In any FET input amplifier, the current noise of the internal bias circuitry can be coupled externally via the gate-to-source capacitances and appears as input current noise. This noise is totally correlated at the inputs, so source impedance matching will tend to cancel out its effect. Both input resistance and input capacitance should be balanced whenever dealing with source capacitances of less than 300 pF in value. LOW NOISE CHARGE AMPLIFIERS OP27 INPUT OFFSET VOLTAGE (mV) 10 1 AD743 0.1 100 1k 10k 100k 1M 10M SOURCE RESISTANCE ( ) As stated, the AD743 provides both low voltage and low current noise. This combination makes this device particularly suitable in applications requiring very high charge sensitivity, such as capacitive accelerometers and hydrophones. When dealing with a high source capacitance, it is useful to consider the total input charge uncertainty as a measure of system noise. Charge (Q) is related to voltage and current by the simply stated fundamental relationships Q = CV and I = dQ dt Figure 3. Input Offset Voltage vs. Source Resistance DESIGNING CIRCUITS FOR LOW NOISE An op amp’s input voltage noise performance is typically divided into two regions: flatband and low frequency noise. The AD743 offers excellent performance with respect to both. The figure of 2.9 nV/√Hz @ 10 kHz is excellent for a JFET input amplifier. The 0.1 Hz to 10 Hz noise is typically 0.38 µV p-p. The user should pay careful attention to several design details in order to optimize As shown, voltage, current, and charge noise can all be directly related. The change in open circuit voltage (∆V) on a capacitor will equal the combination of the change in charge (∆Q/C) and the change in capacitance with a built in charge (Q/∆C). R EV. E –7– AD743 DECIBELS REFERENCED TO 1V/ Hz Figures 4 and 5 show two ways to buffer and amplify the output of a charge output transducer. Both require using an amplifier that has a very high input impedance, such as the AD743. Figure 4 shows a model of a charge amplifier circuit. Here, amplification depends on the principle of conservation of charge at the input of amplifier A1, which requires that the charge on capacitor CS be transferred to capacitor CF, thus yielding an output voltage of ∆Q/CF. The amplifier’s input voltage noise will appear at the output amplified by the noise gain (1 + (CS/CF)) of the circuit. CF RB* R1 R2 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –200 –210 –220 0.01 0.1 1 10 100 FREQUENCY (Hz) 1k 10k 100k NOISE DUE TO IB ALONE NOISE DUE TO RB ALONE TOTAL OUTPUT NOISE CS CB* RB* A1 R1 = CS R2 CF Figure 6. Noise at the Outputs of the Circuits of Figures 4 and 5. Gain = +10, CS = 3000 pF, RB = 22 MΩ *OPTIONAL, SEE TEXT Figure 4. Charge Amplifier Circuit R1 CB* However, this does not change the noise contribution of RB which, in this example, dominates at low frequencies. The graph of Figure 7 shows how to select an RB large enough to minimize this resistor’s contribution to overall circuit noise. When the equivalent current noise of RB ((√4kT)/R equals the noise of IB (√2qIB), there is diminishing return in making RB larger. 5.2 1010 R2 RB* CS RB A2 5.2 109 *OPTIONAL, SEE TEXT Figure 5. Model for a High Z Follower with Gain RESISTANCE ( ) 5.2 108 The circuit in Figure 5 is simply a high impedance follower with gain. Here the noise gain (1 + (R1/R2)) is the same as the gain from the transducer to the output. In both circuits, resistor RB is required as a dc bias current return. There are three important sources of noise in these circuits. Amplifiers A1 and A2 contribute both voltage and current noise, while resistor RB contributes a current noise of T ˜ ∆f N = 4k RB where k = Boltzman’s Constant = 1.381 × 10–23 joules/kelvin T = Absolute Temperature, kelvin (0°C = 273.2 kelvin) f = Bandwidth—in Hz (assuming an ideal “brick wall” filter) This must be root-sum-squared with the amplifier’s own current noise. Figure 6 shows that these circuits in Figures 4 and 5 have an identical frequency response and noise performance (provided that CS/CF = R1/ R2). One feature of the first circuit is that a “T” network is used to increase the effective resistance of RB and to improve the low frequency cutoff point by the same factor. 5.2 107 5.2 106 1pA 10pA 100pA INPUT BIAS CURRENT 1nA 10nA Figure 7. Graph of Resistance vs. Input Bias Current Where the Equivalent Noise √4kT/R, Equals the Noise of the Bias Current √2qIB To maximize dc performance over temperature, the source resistances should be balanced on each input of the amplifier. This is represented by the optional resistor RB in Figures 4 and 5. As previously mentioned, for best noise performance, care should be taken to also balance the source capacitance designated by CB. The value for CB in Figure 4 would be equal to CS in Figure 5. At values of CB over 300 pF, there is a diminishing impact on noise; capacitor CB can then be simply a large bypass of 0.01 µF or greater. –8– R EV. E AD743 HOW CHIP PACKAGE TYPE AND POWER DISSIPATION AFFECT INPUT BIAS CURRENT INPUT BIAS CURRENT (pA) 300 As with all JFET input amplifiers, the input bias current of the AD743 is a direct function of device junction temperature, IB approximately doubling every 10°C. Figure 8 shows the relationship between the bias current and the junction temperature for the AD743. This graph shows that lowering the junction temperature will dramatically improve IB. 10–6 TA = +25 C 200 JA = 165 C/W JA = 115 C/W JA = 0 C/W 100 10–7 INPUT BIAS CURRENT (A) 0 10–8 TA = 25 C VS = ±15V 5 10 SUPPLY VOLTAGE ( V) 15 10–9 Figure 10. Input Bias Current vs. Supply Voltage for Various Values of JA TJ 10–10 10–11 A (J TO DIE MOUNT) 10–12 –60 –40 –20 0 20 40 60 80 100 120 140 B JUNCTION TEMPERATURE ( C) (DIE MOUNT TO CASE) TA CASE A+ B= Figure 8. Input Bias Current vs. Junction Temperature The dc thermal properties of an IC can be closely approximated by using the simple model of Figure 9, where current represents power dissipation, voltage represents temperature, and resistors represent thermal resistance ( in °C/W). TJ JC CA JC Figure 11. Breakdown of Various Package Thermal Resistances REDUCED POWER SUPPLY OPERATION FOR LOWER I B PIN JA TA PIN = DEVICE DISSIPATION TA = AMBIENT TEMPERATURE TJ = JUNCTION TEMPERATURE JC = THERMAL RESISTANCE—JUNCTION TO CASE CA = THERMAL RESISTANCE—CASE TO AMBIENT Reduced power supply operation lowers IB in two ways: first, by lowering both the total power dissipation and second, by reducing the basic gate-to-junction leakage (Figure 10). Figure 12 shows a 40 dB gain piezoelectric transducer amplifier, which operates without an ac-coupling capacitor over the –40°C to +85°C temperature range. If the optional coupling capacitor is used, this circuit will operate over the entire –55°C to +125°C military temperature range. 100 C1* 108 ** CT** +5V 10k Figure 9. Device Thermal Model From this model, TJ = TA + JA PIN. Therefore, IB can be determined in a particular application by using Figure 8 together with the published data for JA and power dissipation. The user can modify JA by using of an appropriate clip-on heat sink, such as the Aavid No. 5801. JA is also a variable when using the AD743 in chip form. Figure 10 shows the bias current versus the supply voltage with JA as the third variable. This graph can be used to predict bias current after JA has been computed. Again, bias current will double for every 10°C. The designer using the AD743 in chip form (Figure 11) must also be concerned with both JC and CA, since JC can be affected by the type of die mount technology used. Typically, JC will be in the 3°C/W to 5°C/W range; therefore, for normal packages, this small power dissipation level may be ignored. But, with a large hybrid substrate, JC will dominate proportionately more of the total JA. TRANSDUCER CT 108 AD743 –5V *OPTIONAL DC BLOCKING CAPACITOR **OPTIONAL, SEE TEXT Figure 12. Piezoelectric Transducer R EV. E –9– AD743 AN INPUT IMPEDANCE COMPENSATED, SALLEN-KEY FILTER C1 1250pF R1 110M 22M ) R3 1k The simple high-pass filter of Figure 13 has an important source of error which is often overlooked. Even 5 pF of input capacitance in amplifier A will contribute an additional 1% of pass-band amplitude error, as well as distortion, proportional to the C/V characteristics of the input junction capacitance. The addition of the network designated Z will balance the source impedance—as seen by A—and thus eliminate these errors. +VS (5 R2 9k C2 2.2 F R4 18M AD711 500k Z R5 18M C3 2.2 F A 1000pF 1000pF 500k –VS 1000pF Z 1000pF 500k 500k AD743 B AND K MODEL 4370 OR EQUIVALENT OUTPUT 0.8mV/pC Figure 13. Input Impedance Compensated Sallen-Key Filter TWO HIGH PERFORMANCE ACCELEROMETER AMPLIFIERS Figure 14b. Accelerometer Circuit Using a DC Servo Amplifier Two of the most popular charge-out transducers are hydrophones and accelerometers. Precision accelerometers are typically calibrated for a charge output (pC/g).* Figures 14a and 14b show two ways in which to configure the AD743 as a low noise charge amplifier for use with a wide variety of piezoelectric accelerometers. The input sensitivity of these circuits will be determined by the value of capacitor C1 and is equal to A dc servo loop (Figure 14b) can be used to assure a dc output which is > R1 OR R2 A OUTPUT R1 B OUTPUT CB RB RS CS INVERTING CONNECTION B CB = C F CS RB = R1 RS Figure 17. Optional External Components for Balancing Source Impedances R EV. E –11– AD743 OUTLINE DIMENSIONS 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0.375 (9.53) 0.365 (9.27) 0.355 (9.02) 8 5 16-Lead Standard Small Outline Package [SOIC] Wide Body (R-16) Dimensions shown in millimeters and (inches) 1 4 0.295 (7.49) 0.285 (7.24) 0.275 (6.98) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) MIN SEATING PLANE 0.060 (1.52) 0.050 (1.27) 0.045 (1.14) 16 9 7.60 (0.2992) 7.40 (0.2913) 0.100 (2.54) BSC 0.180 (4.57) MAX 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.135 (3.43) 0.120 (3.05) 1 8 10.65 (0.4193) 10.00 (0.3937) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20) 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.33 (0.0130) 2.65 (0.1043) 2.35 (0.0925) 0.75 (0.0295) 0.25 (0.0098) 45 COPLANARITY 0.10 SEATING PLANE 0.32 (0.0126) 0.23 (0.0091) 8 0 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MO-095AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Revision History Location 7/03—Data Sheet changed from REV. D to REV. E. Page Deleted K Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/02—Data Sheet changed from REV. C to REV. D. Edits to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Deleted AD7435 column from SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Deleted METALLIZATION PHOTOGRAPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to REDUCE POWER SUPPLY OPERATION FOR LOWER IB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Deleted 8-Pin CERDIP (Q) package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 –12– R EV. E C00830–0–7/03(E) 10.50 (0.4134) 10.10 (0.3976)