AD7440BRM

Differential Input, 1 MSPS 10-Bit and 12-Bit ADCs in an 8-Lead SOT-23 AD7440/AD7450A FEATURES FUNCTIONAL BLOCK DIAGRAM Fast throughput rate: 1 MSPS Specified for VDD of 3 V and 5 V Low power at max throughput rate 4 mW max at 1 MSPS with 3 V supplies 9.25 mW max at 1 MSPS with 5 V supplies Fully differential analog input Wide input bandwidth 70 dB SINAD at 100 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible Power-down mode: 1 μA max 8-lead SOT-23 and MSOP packages VDD VIN+ T/H VIN– 12-BIT SUCCESSIVE APPROXIMATION ADC VREF SCLK AD7440/AD7450A SDATA CONTROL LOGIC 03051-A-001 CS GND APPLICATIONS Figure 1. Transducer interface Battery-powered systems Data acquisition systems Portable instrumentation Motor control GENERAL DESCRIPTION 1 The AD7440/AD7450A are 10-bit and 12-bit high speed, low power, successive approximation (SAR) analog-to-digital converters with a fully differential analog input. These parts operate from a single 3 V or 5 V power supply and use advanced design techniques to achieve very low power dissipation at throughput rates up to 1 MSPS. The SAR architecture of these parts ensures that there are no pipeline delays. The parts contain a low noise, wide bandwidth, differential track-and-hold amplifier (T/H) that can handle input frequencies up to 3.5 MHz. The reference voltage is applied externally to the VREF pin and can be varied from 100 mV to 3.5 V depending on the power supply and what suits the application. The value of the reference voltage determines the common-mode voltage range of the part. With this truly differential input structure and variable reference input, the user can select a variety of input ranges and bias points. The conversion process and data acquisition are controlled using CS and the serial clock, allowing the device to interface with microprocessors or DSPs. The input signals are sampled on the falling edge of CS; the conversion is also initiated at this point. The SAR architecture of these parts ensures that there are no pipeline delays. The AD7440 and the AD7450A use advanced design techniques to achieve very low power dissipation at high throughput rates. PRODUCT HIGHLIGHTS 1. Operation with either 3 V or 5 V power supplies. 2. High throughput with low power consumption. With a 3 V supply, the AD7440/AD7450A offer 4 mW max power consumption for 1 MSPS throughput. 3. Fully differential analog input. 4. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. These parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. 5. Variable voltage reference input. 6. No pipeline delay. 7. Accurate control of the sampling instant via a CS input and once-off conversion control. 8. ENOB > eight bits typically with 100 mV reference. 1 Protected by U.S. Patent Number 6,681,332. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD7440/AD7450A TABLE OF CONTENTS AD7440–Specifications.................................................................... 3 Digital Inputs .............................................................................. 19 AD7450A–Specifications................................................................. 5 Reference ..................................................................................... 19 Timing Specifications....................................................................... 7 Single-Ended Operation............................................................ 20 Absolute Maximum Ratings............................................................ 8 Serial Interface ............................................................................ 21 ESD Caution.................................................................................. 8 Modes of Operation ....................................................................... 23 Pin Configurations and Function Descriptions ........................... 9 Normal Mode.............................................................................. 23 Terminology .................................................................................... 10 Power-Down Mode .................................................................... 23 AD7440/AD7450A–Typical Performance Characteristics ....... 12 Power-Up Time .......................................................................... 24 Circuit Information ........................................................................ 15 Power vs. Throughput Rate....................................................... 24 Converter Operation.................................................................. 15 Microprocessor and DSP Interfacing ...................................... 25 ADC Transfer Function............................................................. 15 Grounding and Layout Hints.................................................... 26 Typical Connection Diagram ................................................... 16 Evaluating the AD7440/AD7450A Performance................... 26 Analog Input ............................................................................... 16 Outline Dimensions ....................................................................... 27 Driving Differential Inputs ....................................................... 18 Ordering Guide............................................................................... 28 REVISION HISTORY 9/05—Rev. B to Rev. C Changes to Ordering Guide ............................................................ 28 2/04—Data Sheet changed from Rev. A to Rev. B Added Patent Note .............................................................................. 1 1/04—Data Sheet changed from Rev. 0 to Rev. A Updated Format.................................................................... Universal Changes to General Description ....................................................... 1 Changes to Table 1 footnotes ............................................................. 3 Changes to Table 2 footnotes ............................................................. 5 Changes to Table 3 footnotes ............................................................. 7 Rev. C | Page 2 of 28 AD7440/AD7450A AD7440–SPECIFICATIONS Table 1. VDD = 2.7 V to 3.6 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.5 V; VCM 1 = VREF; TA = TMIN to TMAX, unless otherwise noted. Temperature range for B Version: –40°C to +85°C. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay2 Aperture Jitter2 Full Power Bandwidth2, 3 DC ACCURACY Resolution Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 Zero-Code Error2 Positive Gain Error2 Negative Gain Error2 ANALOG INPUT Full-Scale Input Span Absolute Input Voltage VIN+ VIN– DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage DC Leakage Current VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 7 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding Test Conditions/Comments fIN = 100 kHz B Version Unit 61 –74 –76 dB min dB max dB max –83 –83 5 50 20 2.5 dB typ dB typ ns typ ps typ MHz typ MHz typ 10 ±0.5 ±0.5 ±2.5 ±1 ±1 Bits LSB max LSB max LSB max LSB max LSB max 2 × VREF 4 VIN+ – VIN– V VCM = VREF VCM = VREF VCM ± VREF/2 VCM ± VREF/2 ±1 30/10 V V μA max pF typ 2.5 5 V 2.0 6 V ±1 10/30 μA max pF typ 2.4 0.8 ±1 10 V min V max μA max pF max 2.8 2.4 0.4 ±1 10 Twos complement V min V min V max μA max pF max –82 dB typ –82 dB typ fa = 90 kHz, fb = 110 kHz @ –3 dB @ –0.1 dB Guaranteed no missed codes to 10 bits When in track-and-hold VDD = 4.75 V to 5.25 V (±1% tolerance for specified performance) VDD = 2.7 V to 3.6 V (±1% tolerance for specified performance) When in track-and-hold Typically 10 nA, VIN = 0 V or VDD VDD = 4.75 V to 5.25 V; ISOURCE = 200 μA VDD = 2.7 V to 3.6 V; ISOURCE = 200 μA ISINK = 200 μA Rev. C | Page 3 of 28 AD7440/AD7450A Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VDD IDD 8 Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down Mode Test Conditions/Comments B Version Unit 888 ns with an 18 MHz SCLK Sine wave input Step input 16 200 290 1 SCLK cycles ns max ns max MSPS max Range: 3 V + 20%/–10%; 5 V ± 5% 2.7/5.25 V min/V max SCLK on or off VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V SCLK on or off 0.5 1.95 1.45 1 mA typ mA max mA max μA max VDD = 5 V, 1.55 mW typ for 100 kSPS 9 VDD = 3 V, 0.6 mW typ for 100 kSPS9 VDD = 5 V, SCLK on or off VDD = 3 V, SCLK on or off 9.25 4 5 3 mW max mW max μW max μW max 1 Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 28 and Figure 29. See the Terminology section. Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result. 4 Because the input spans of VIN+ and VIN– are both VREF and are 180° out of phase, the differential voltage is 2 × VREF. 5 The AD7440 is functional with a reference input from 100 mV and for VDD = 5 V; the reference can range up to 3.5 V. 6 The AD7440 is functional with a reference input from 100 mV and for VDD = 3 V; the reference can range up to 2.2 V. 7 Guaranteed by characterization. 8 Measured with a midscale dc input. 9 See the Power vs. Throughput section. 2 3 Rev. C | Page 4 of 28 AD7440/AD7450A AD7450A–SPECIFICATIONS Table 2. VDD = 2.7 V to 3.6 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.5 V; VCM 1 = VREF; TA = TMIN to TMAX, unless otherwise noted. Temperature range for B Version: –40°C to +85°C. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Aperture Delay2 Aperture Jitter2 Full Power Bandwidth2, 3 DC ACCURACY Resolution Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 Zero-Code Error2 Positive Gain Error2 Negative Gain Error2 ANALOG INPUT Full-Scale Input Span Absolute Input Voltage VIN+ VIN– DC Leakage Current Input Capacitance REFERENCE INPUT VREF Input Voltage DC Leakage Current VREF Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 7 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding Test Conditions/Comments fIN = 100 kHz B Version Unit 70 –76 –74 –76 –74 dB min dB max dB max dB max dB max –89 –89 5 50 20 2.5 dB typ dB typ ns typ ps typ MHz typ MHz typ 12 ±1 ±0.95 ±6 ±2 ±2 Bits LSB max LSB max LSB max LSB max LSB max 2 × VREF 4 VIN+ – VIN– V VCM = VREF VCM = VREF VCM ± VREF/2 VCM ± VREF/2 ±1 30/10 V V μA max pF typ 2.5 5 V 2.0 6 V ±1 10/30 μA max pF typ 2.4 0.8 ±1 10 V min V max μA max pF max 2.8 2.4 0.4 ±1 10 Twos complement V min V min V max μA max pF max VDD = 4.75 V to 5.25 V, –86 dB typ VDD = 2.7 V to 3.6 V, –84 dB typ VDD = 4.75 V to 5.25 V, –86 dB typ VDD = 2.7 V to 3.6 V, –84 dB typ fa = 90 kHz, fb = 110 kHz @ –3 dB @ –0.1 dB Guaranteed no missed codes to 12 bits When in track-and-hold VDD = 4.75 V to 5.25 V (±1% tolerance for specified performance) VDD = 2.7 V to 3.6 V (±1% tolerance for specified performance) When in track-and-hold Typically 10 nA, VIN = 0 V or VDD VDD = 4.75 V to 5.25 V; ISOURCE = 200 μA VDD = 2.7 V to 3.6 V; ISOURCE = 200 μA ISINK = 200 μA Rev. C | Page 5 of 28 AD7440/AD7450A Parameter CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2 Throughput Rate POWER REQUIREMENTS VDD IDD 8 Normal Mode (Static) Normal Mode (Operational) Full Power-Down Mode Power Dissipation Normal Mode (Operational) Full Power-Down Test Conditions/Comments B Version Unit 888 ns with an 18 MHz SCLK Sine wave input Step input 16 200 290 1 SCLK cycles ns max ns max MSPS max Range: 3 V + 20%/–10%; 5 V ± 5% 2.7/5.25 V min/V max SCLK on or off VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V SCLK on or off 0.5 1.95 1.45 1 mA typ mA max mA max μA max VDD = 5 V, 1.55 mW typ for 100 kSPS 9 VDD = 3 V, 0.6 mW typ for 100 kSPS9 VDD = 5 V, SCLK on or off VDD = 3 V, SCLK on or off 9.25 4 5 3 mW max mW max μW max μW max 1 Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 28 and Figure 29. See the Terminology section. Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result. 4 Because the input spans of VIN+ and VIN– are both VREF and are 180° out of phase, the differential voltage is 2 × VREF. 5 The AD7450A is functional with a reference input from 100 mV and for VDD = 5 V; the reference can range up to 3.5 V. 6 The AD7450A is functional with a reference input from 100 mV and for VDD = 3 V; the reference can range up to 2.2 V. 7 Guaranteed by characterization. 8 Measured with a midscale dc input. 9 See the Power vs. Throughput section. 2 3 Rev. C | Page 6 of 28 AD7440/AD7450A TIMING SPECIFICATIONS Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 2, Figure 3, and the Serial Interface section. Table 3. VDD = 2.7 V to 3.6 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.5 V; VCM 1 = VREF; TA = TMIN to TMAX, unless otherwise noted. Parameter fSCLK 2 tCONVERT tQUIET t1 t2 t3 3 t43 t5 t6 t7 t8 4 tPOWER-UP 5 Limit at TMIN, TMAX 10 18 16 × tSCLK 888 60 10 10 20 40 0.4 tSCLK 0.4 tSCLK 10 10 35 1 Unit kHz min MHz max Description tSCLK = 1/fSCLK ns max ns min ns min ns min ns max ns max ns min ns min ns min ns min ns max μs max Minimum quiet time between the end of a serial read and the next falling edge of CS Minimum CS pulse width CS falling edge to SCLK falling edge setup time Delay from CS falling edge until SDATA three-state disabled Data access time after SCLK falling edge SCLK high pulse width SCLK low pulse width SCLK edge to data valid hold time SCLK falling edge to SDATA three-state enabled SCLK falling edge to SDATA three-state enabled Power-up time from full power-down 1 Common-mode voltage. Mark/space ratio for the SCLK input is 40/60 to 60/40. Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V or 0.4 V or 2.0 V for VDD = 3 V. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish time of the part and is independent of the bus loading. 5 See Power-Up Time section. 2 3 t1 CS 1 SCLK 2 3 t3 4 5 0 0 4 LEADING ZEROS B 13 14 0 DB11 15 t6 t7 t4 0 SDATA tCONVERT t5 DB10 DB2 16 t8 DB1 03051-A-002 t2 tQUIET DB0 THREE-STATE Figure 2. AD7450A Serial Interface Timing Diagram t1 CS 1 SCLK 2 3 t3 SDATA tCONVERT t5 4 5 0 0 0 14 DB9 DB8 15 t6 t7 t4 0 B 13 DB0 16 t8 0 0 tQUIET 2 TRAILING ZEROS THREE-STATE 4 LEADING ZEROS Figure 3. AD7440 Serial Interface Timing Diagram Rev. C | Page 7 of 28 03051-A-003 t2 AD7440/AD7450A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. 1.6mA IOL Table 4. Rating –0.3 V to +7 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V –0.3 V to +7 V –0.3 V to VDD + 0.3 V –0.3 V to VDD + 0.3 V ±10 mA TO OUTPUT PIN 1.6V CL 25pF 200μA Figure 4. Load Circuit for Digital Output Timing Specifications –40°C to +85°C –65°C to +150°C 150°C 205.9°C/W 211.5°C/W 43.74°C/W 91.99°C/W 215°C 220°C 1 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Transient currents of up to 100 mA do not cause SCR latch up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 8 of 28 IOH 03051-A-004 Parameter VDD to GND VIN+ to GND VIN– to GND Digital Input Voltage to GND Digital Output Voltage to GND VREF to GND Input Current to Any Pin Except Supplies 1 Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature θJA Thermal Impedance MSOP SOT-23 θJC Thermal Impedance MSOP SOT-23 Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD AD7440/AD7450A AD7440/ AD7450A SDATA 3 8 VREF VREF 1 7 VIN+ VIN+ 2 6 VIN– TOP VIEW CS 4 (Not to Scale) 5 GND 03051-A-005 VDD 1 SCLK 2 AD7440/ AD7450A 8 VDD 7 SCLK SDATA TOP VIEW GND 4 (Not to Scale) 5 CS VIN– 3 6 03051-A-006 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. Pin Configuration for 8-Lead MSOP Figure 5. Pin Configuration for 8-Lead SOT-23 Table 5. Pin Function Descriptions Mnemonic VREF VIN+ VIN– GND CS SDATA SCLK VDD Function Reference Input for the AD7440/AD7450A. An external reference must be applied to this input. For a 5 V power supply, the reference is 2.5 V (±1%) for specified performance. For a 3 V power supply, the reference is 2 V (±1%) for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1 μF. See the Reference section for more details. Positive Terminal for Differential Analog Input. Negative Terminal for Differential Analog Input. Analog Ground. Ground reference point for all circuitry on the AD7440/AD7450A. All analog input signals and any external reference signal should be referred to this GND voltage. Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7440/AD7450A and framing the serial data transfer. Serial Data. Logic output. The conversion result from the AD7440/AD7450A is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7450A consists of four leading zeros followed by the 12 bits of conversion data, which are provided MSB first; the data stream of the AD7440 consists of four leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros. In both cases, the output coding is twos complement. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process. Power Supply Input. VDD is 3 V (+20%/–10%) or 5 V (±5%). This supply should be decoupled to GND with a 0.1 μF capacitor and a 10 μF tantalum capacitor in parallel. Rev. C | Page 9 of 28 AD7440/AD7450A TERMINOLOGY Signal-to-(Noise + Distortion) Ratio Aperture Delay This is the measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by the following: This is the amount of time from the leading edge of the sampling clock until the ADC actually takes the sample. Signal-to-(Noise + Distortion) = (6.02N + 1.76)dB. Thus for a 12-bit converter, this is 74 dB; and for a 10-bit converter, this is 62 dB. This is the sample-to-sample variation in the effective point in time at which the actual sample is taken. Full Power Bandwidth The full power bandwidth of an ADC is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a full-scale input. Common-Mode Rejection Ratio (CMRR) The common-mode rejection ratio is the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the common-mode voltage of VIN+ and VIN– of frequency fS as follows: Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7440/AD7450A, it is defined as THD (dB) = 20 log Aperture Jitter V 2 2 + V 3 2 + V 4 2 + V5 2 + V6 2 V1 CMRR (dB) = 10 log (Pf/Pfs) where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic (spurious noise) is the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at the sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the second-order terms include (fa + fb) and (fa – fb), while the thirdorder terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). The AD7440/AD7450A is tested using the CCIF standard of two input frequencies near the top end of the input bandwidth. In this case, the second-order terms are distanced in frequency from the original sine waves, while the third-order terms are at a frequency close to the input frequencies. As a result, the second- and thirdorder terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals, expressed in dB. Pf is the power at the frequency f in the ADC output; Pfs is the power at frequency fS in the ADC output. Integral Nonlinearity (INL) This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity (DNL) This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Zero-Code Error This is the deviation of the midscale code transition (111...111 to 000...000) from the ideal VIN+ − VIN– (i.e., 0 LSB). Positive Gain Error This is the deviation of the last code transition (011...110 to 011...111) from the ideal VIN+ – VIN– (i.e., +VREF − 1 LSB), after the zero code error has been adjusted out. Negative Gain Error This is the deviation of the first code transition (100...000 to 100...001) from the ideal VIN+ − VIN– (i.e., –VREF + 1 LSB), after the zero code error has been adjusted out. Track-and-Hold Acquisition Time The track-and-hold acquisition time is the minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within 0.5 LSB of the applied input signal. Rev. C | Page 10 of 28 AD7440/AD7450A PSRR (dB) = 10log(Pf/PfS) Power Supply Rejection Ratio (PSRR) The power supply rejection ratio is the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV p-p sine wave applied to the ADC VDD supply of frequency fS. The frequency of this input varies from 1 kHz to 1 MHz. Pf is the power at frequency f in the ADC output; Pfs is the power at frequency fS in the ADC output. Rev. C | Page 11 of 28 AD7440/AD7450A AD7440/AD7450A–TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, fS = 1 MSPS, fSCLK = 18 MHz, unless otherwise noted. 75 0 VDD = 5.25V 8192 POINT FFT fSAMPLE = 1MSPS fIN = 100kSPS SINAD = +71.7dB THD = –82dB SFDR = –83dB VDD = 4.75V –20 –40 VDD = 3.6V SNR (dB) 65 VDD = 2.7V –60 –80 –100 60 03051-A-007 –120 55 10 100 03051-A-010 SINAD (dB) 70 –140 1000 0 100 FREQUENCY (kHz) 0 1.0 –10 0.8 –20 0.6 –30 0.4 –40 –50 –60 VDD = 3V 400 500 0.2 0 –0.2 –0.4 03051-A-008 –90 VDD = 5V –100 10 100 1000 03051-A-011 –0.6 –80 –0.8 –1.0 0 10000 1024 2048 3072 4096 CODE FREQUENCY (kHz) Figure 11. Typical DNL for the AD7450A for VDD = 5 V Figure 8. CMRR vs. Frequency for VDD = 5 V and 3 V 1.0 0 100mV p-p SINEWAVE ON VDD NO DECOUPLING ON VDD 0.8 –20 0.6 0.4 –60 INL ERROR (LSB) –40 VDD = 3V VDD = 5V –80 0.2 0 –0.2 –0.4 –0.6 03051-A-009 –100 –120 0 100 200 300 400 500 600 700 800 900 03051-A-012 PSRR (dB) 300 Figure 10. AD7450A Dynamic Performance with VDD = 5 V DNL ERROR (LSB) CMRR (dB) Figure 7. AD7450A SINAD vs. Analog Input Frequency for Various Supply Voltages –70 200 FREQUENCY (kHz) –0.8 –1.0 0 1000 1024 2048 3072 CODE SUPPLY RIPPLE FREQUENCY (kHz) Figure 9. PSRR vs. Supply Ripple Frequency without Supply Decoupling Rev. C | Page 12 of 28 Figure 12. Typical INL for the AD7450A for VDD = 5 V 4096 AD7440/AD7450A 3.0 2.5 2.5 2.0 1.5 CHANGE IN INL (LSB) 1.5 1.0 POSITIVE DNL 0.5 0 POSITIVE INL 0.5 0 –0.5 NEGATIVE INL NEGATIVE DNL –1.0 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 –1.5 –2.0 3.5 0 2.0 7 ZERO-CODE ERROR (LSB) 8 1.5 1.0 POSITIVE DNL 0.5 03051-A-014 0 NEGATIVE DNL –1.0 0.5 1.0 1.0 2.0 2.2 2.5 1.5 2.0 2.2 6 VDD = 5V 5 4 3 VDD = 3V 2 1 0 2.5 0 0.5 1.0 VREF (V) Figure 14. Change in DNL vs. VREF for the AD7450A for VDD = 3 V 1.5 2.0 VREF (V) 2.5 3.0 3.5 Figure 17. Change in Zero-Code Error vs. Reference Voltage for VDD = 5 V and 3 V for the AD7450A 12.0 5 11.5 3 2 1 POSITIVE INL 0 –1 NEGATIVE INL –2 03051-A-015 –3 –4 –5 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 VDD = 5V 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 0 3.5 Figure 15. Change in INL vs. VREF for the AD7450A for VDD = 5 V VDD = 3V 11.0 03051-A-018 EFFECTIVE NUMBER OF BITS 4 CHANGE IN INL (LSB) 1.5 Figure 16. Change in INL vs. VREF for the AD7450A for VDD = 3 V 2.5 0 0.5 VREF (V) Figure 13. Change in DNL vs. VREF for the AD7450A for VDD = 5 V –0.5 03051-A-016 03051-A-013 –1.0 –0.5 CHANGE IN DNL (LSB) 1.0 03051-A-017 CHANGE IN DNL (LSB) 2.0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 Figure 18. Change in ENOB vs. Reference Voltage for VDD = 5 V and 3 V for the AD7450A Rev. C | Page 13 of 28 AD7440/AD7450A 10,000 VIN+ = VIN– 9,000 10,000 CONVERSIONS fS = 1MSPS 8,000 0.5 10,000 CODES 0.4 0.3 DNL ERROR (LSB) 7,000 6,000 5,000 4,000 3,000 0.1 0 –0.1 –0.2 1,000 0 2044 2045 2046 2047 2048 03051-A-021 –0.3 03051-A-019 2,000 0.2 –0.4 –0.5 2049 0 256 CODE Figure 19. Histogram of 10,000 Conversions of a DC Input for the AD7450A with VDD = 5 V 768 1024 Figure 21. Typical DNL for the AD7440 for VDD = 5 V 0.5 0 8192 POINT FFT fSAMPLE = 1MSPS fIN = 100kHz SINAD = +61.6dB THD = –81.7dB SFDR = –83.1dB –20 0.4 0.3 0.2 INL ERROR (LSB) –40 –60 –80 0.1 0 –0.1 –0.2 –100 –140 0 100 200 300 400 03051-A-022 –0.3 –120 03051-A-020 SNR (dB) 512 CODE –0.4 –0.5 0 500 256 512 768 CODE FREQUENCY (kHz) Figure 22. Typical INL for the AD7440 for VDD = 5 V Figure 20. AD7440 Dynamic Performance with VDD = 5 V Rev. C | Page 14 of 28 1024 AD7440/AD7450A CIRCUIT INFORMATION When they are operated with a 5 V supply, the maximum reference that can be applied is 3.5 V. When they are operated with a 3 V supply, the maximum reference that can be applied is 2.2 V (see the Reference section). The AD7440/AD7450A have an on-chip differential track-andhold amplifier, a successive approximation (SAR) ADC, and a serial interface housed in either an 8-lead SOT-23 or an MSOP package. The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC. The AD7440/AD7450A feature a power-down option for reduced power consumption between conversions. The powerdown feature is implemented across the standard serial interface as described in the Modes of Operation section. When the ADC starts a conversion (Figure 24), SW3 opens and SW1 and SW2 move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC’s output code. The output impedances of the sources driving the VIN+ and the VIN– pins must be matched; otherwise, the two inputs have different settling times, resulting in errors. CAPACITIVE DAC VIN– COMPARATOR 1LSB = 2×VREF/4096 AD7450A 1LSB = 2×VREF/1024 AD7440 011...111 011...110 COMPARATOR CAPACITIVE DAC Figure 23. ADC Acquisition Phase 000...001 000...000 111...111 100...010 100...001 100...000 1 LSB –VREF 0 LSB +VREF – 1 LSB ANALOG INPUT (VIN+ – VIN–) 03051-A-025 CS 03051-A-023 VREF CS Figure 24. ADC Conversion Phase CONTROL LOGIC SW3 VIN– CONTROL LOGIC CAPACITIVE DAC ADC CODE A B SW2 SW2 VREF CS SW1 A B SW3 CAPACITIVE DAC A SW1 The output coding for the AD7440/AD7450A is twos complement. The designed code transitions occur at successive LSB values (1 LSB, 2 LSBs, and so on). The LSB size of the AD7450A is 2 × VREF/4096, and the LSB size of the AD7440 is 2 × VREF/1024. The ideal transfer characteristic of the AD7440/AD7450A is shown in Figure 25. The AD7440/AD7450A are successive approximation ADCs based around two capacitive DACs. Figure 23 and Figure 24 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC is comprised of control logic, an SAR, and two capacitive DACs. In Figure 23 (acquisition phase), SW3 is closed, SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. B A ADC TRANSFER FUNCTION CONVERTER OPERATION VIN+ CS B VIN+ 03051-A-024 The AD7440/AD7450A are 10-bit and 12-bit fast, low power, single-supply, successive approximation analog-to-digital converters (ADCs). They can operate with a 5 V or 3 V power supply and are capable of throughput rates up to 1 MSPS when supplied with an 18 MHz SCLK. They require an external reference to be applied to the VREF pin, with the value of the reference chosen depending on the power supply and what suits the application. Figure 25. AD7440/AD7450A Ideal Transfer Characteristic Rev. C | Page 15 of 28 AD7440/AD7450A TYPICAL CONNECTION DIAGRAM Figure 26 shows a typical connection diagram for the AD7440/AD7450A for both 5 V and 3 V supplies. In this setup, the GND pin is connected to the analog ground plane of the system. The VREF pin is connected to either a 2.5 V or a 2 V decoupled reference source, depending on the power supply, to set up the analog input range. The common-mode voltage has to be set up externally and is the value on which the two inputs are centered. The conversion result is output in a 16-bit word with four leading zeros followed by the MSB of the 12-bit or 10-bit result. The 10-bit result of the AD7440 is followed by two trailing zeros. For more details on driving the differential inputs and setting up the common mode, refer to the Driving Differential Inputs section. 3V/5V SUPPLY When a conversion takes place, the common mode is rejected, resulting in a virtually noise-free signal of amplitude –VREF to +VREF, corresponding to the digital codes of 0 to 4096 in the case of the AD7450A and 0 to 1024 in the AD7440. SERIAL INTERFACE VDD VREF p-p CM* VIN+ SCLK AD7440/ AD7450A CM* 4.5 CS VIN– 4.0 GND VREF 0.1μF μC/μP SDATA 2V/2.5V VREF 03051-A-026 VREF p-p For ease of use, the common mode can be set up to equal VREF, resulting in the differential signal being ±VREF centered on VREF. *CM IS THE COMMON-MODE VOLTAGE. Figure 26. Typical Connection Diagram ANALOG INPUT The analog input of the AD7440/AD7450A is fully differential. Differential signals have a number of benefits over singleended signals, including noise immunity based on the device’s common-mode rejection, improvements in distortion performance, doubling of the device’s available dynamic range, and flexibility in input ranges and bias points. Figure 27 defines the fully differential analog input of the AD7440/AD7450A. 3.5 3.25V 3.0 2.5 COMMON-MODE RANGE 2.0 1.75V 1.5 1.0 03051-A-028 10μF Figure 28 and Figure 29 show how the common-mode range typically varies with VREF for both a 5 V and a 3 V power supply. The common mode must be in this range to guarantee the functionality of the AD7440/AD7450A. COMMON-MODE VOLTAGE (V) 0.1μF The common mode is the average of the two signals, that is, (VIN+ + VIN–)/2 and is therefore the voltage that the two inputs are centered on. This results in the span of each input being CM ± VREF/2. This voltage has to be set up externally, and its range varies with VREF. As the value of VREF increases, the common-mode range decreases. When driving the inputs with an amplifier, the actual common-mode range is determined by the amplifier’s output voltage swing. 0.5 0 0 0.5 1.0 1.5 2.0 VREF (V) 2.5 3.0 3.5 Figure 28. Input Common-Mode Range vs. VREF (VDD = 5 V and VREF (Max) = 3.5 V) 2.5 VIN+ COMMON-MODE VOLTAGE VREF p-p VIN– 03051-A-027 AD7440/ AD7450A Figure 27. Differential Input Definitions The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN– pins (i.e., VIN+ – VIN–). VIN+ and VIN– are simultaneously driven by two signals each of amplitude VREF that are 180° out of phase. The amplitude of the differential signal is therefore –VREF to +VREF peak-to-peak (2 × VREF). This is true regardless of the common mode (CM). Rev. C | Page 16 of 28 1.5 COMMON-MODE RANGE 1.0 1V 0.5 03051-A-029 VREF p-p COMMON-MODE VOLTAGE (V) 2V 2.0 0 0 0.25 0.50 0.75 1.00 1.25 VREF (V) 1.50 1.75 Figure 29. Input Common-Mode Range vs. VREF (VDD = 3 V and VREF (Max) =2V) 2.00 AD7440/AD7450A Figure 30 shows examples of the inputs to VIN+ and VIN– for different values of VREF for VDD = 5 V. It also gives the maximum and minimum common-mode voltages for each reference value according to Figure 28. REFERENCE = 2V VIN– COMMON-MODE (CM) CMMIN = 1V CMMAX = 4V 2V p-p VIN+ When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases, and performance degrades. Figure 32 shows a graph of THD vs. the analog input signal frequency for different source impedances for VDD = 5 V. REFERENCE = 2.5V 2.5V p-p VIN+ 03051-A-030 VIN– COMMON-MODE (CM) CMMIN = 1.25V CMMAX = 3.75V For ac applications, removing high frequency components from the analog input signal through the use of an RC low-pass filter on the relevant analog input pins is recommended. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of op amp is a function of the particular application. Figure 30. Examples of the Analog Inputs to VIN+ and VIN– for Different Values of VREF for VDD = 5 V Analog Input Structure 0 TA = 25°C VDD = 5V Figure 31 shows the equivalent circuit of the analog input structure of the AD7440/AD7450A. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The capacitors, C1 in Figure 31, are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 Ω. The capacitors, C2, are the ADC’s sampling capacitors and have a capacitance of 16 pF typically. THD (dB) –20 –40 RIN = 1kΩ RIN = 510Ω –60 RIN = 300Ω RIN = 10Ω –100 10 03051-A-032 –80 100 1000 INPUT FREQUENCY (kHz) Figure 32. THD vs. Analog Input Frequency for Various Source Impedances for VDD = 5 V VDD D R1 VIN+ C1 Figure 33 shows a graph of the THD vs. the analog input frequency for VDD of 5 V ± 5% and 3 V + 20%/–10%, while sampling at 1 MSPS with an SCLK of 18 MHz. In this case, the source impedance is 10 Ω. C2 D –50 TA = 25°C –55 VDD VDD = 2.7V –60 R1 VIN– C2 VDD = 3.6V THD (dB) –65 D 03051-A-031 C1 –70 –75 –80 Figure 31. Equivalent Analog Input Circuit Conversion Phase–Switches Open; Track Phase–Switches Closed –85 VDD = 5.25V VDD = 4.75V –90 10 100 03051-A-033 D 1000 INPUT FREQUENCY (kHz) Figure 33. THD vs. Analog Input Frequency for 3 V and 5 V Supply Voltages Rev. C | Page 17 of 28 AD7440/AD7450A of switched capacitance on the front end of the ADCs. The RC low-pass filter on each analog input is recommended in ac applications to remove high frequency components of the analog input. The architecture of the AD8138 results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. DRIVING DIFFERENTIAL INPUTS Differential operation requires VIN+ and VIN– to be driven simultaneously with two equal signals that are 180° out of phase. The common mode must be set up externally and has a range determined by VREF, the power supply, and the particular amplifier used to drive the analog inputs (see Figure 28 and Figure 29). Differential modes of operation with either an ac or dc input provide the best THD performance over a wide frequency range. Because not all applications have a signal preconditioned for differential operation, there is often a need to perform single-ended-to-differential conversion. If the analog input source being used has zero impedance, all four resistors (RG1, RG2, RF1, and RF2) should be the same. If the source has a 50 Ω impedance and a 50 Ω termination, for example, the value of RG2 should be increased by 25 Ω to balance this parallel impedance on the input and thus ensure that both the positive and negative analog inputs have the same gain (see Figure 34). The outputs of the amplifier are perfectly matched, balanced differential outputs of identical amplitude and are exactly 180° out of phase. Differential Amplifier An ideal method of applying differential drive to the AD7440/AD7450A is to use a differential amplifier such as the AD8138. This part can be used as a single-ended-to-differential amplifier or as a differential-to-differential amplifier. In both cases, the analog input needs to be bipolar. It also provides common-mode level shifting and buffering of the bipolar input signal. Figure 34 shows how the AD8138 can be used as a single-ended-to-differential amplifier. The positive and negative outputs of the AD8138 are connected to the respective inputs on the ADC via a pair of series resistors to minimize the effects The AD8138 is specified with +3 V, +5 V, and ±5 V power supplies, but the best results are obtained with a ±5 V supply. The AD8132 is a lower cost device that could also be used in this configuration with slight differences in characteristics to the AD8138 but with similar performance and operation. 3.75V 2.5V 1.25V RF1 RS* RG1 +2.5V GND –2.5V VOCM 51Ω RG2 VIN+ C* AD8138 RS* AD7440/ AD7450A VIN– VREF C* *MOUNT AS CLOSE TO THE AD7440/AD7450A AS POSSIBLE AND ENSURE HIGH PRECISION RS AND CS ARE USED. RS–50Ω; C–1nF RG1 = RF1 = RF2 = 499Ω; RG2 = 523Ω 3.75V 2.5V 1.25V EXTERNAL VREF (2.5V) Figure 34. Using the AD8138 as a Single-Ended-to-Differential Amplifier Rev. C | Page 18 of 28 03051-A-034 RF2 AD7440/AD7450A Op Amp Pair RF Transformer An op amp pair can be used to directly couple a differential signal to the AD7440/AD7450A. The circuit configurations shown in Figure 35 and Figure 36 show how a dual op amp can be used to convert a single-ended signal into a differential signal for both a bipolar and unipolar input signal, respectively. An RF transformer with a center tap offers a good solution for generating differential inputs in systems that do not need to be dc-coupled. Figure 37 shows how a transformer is used for single-ended-to-differential conversion. It provides the benefits of operating the ADC in the differential mode without contributing additional noise and distortion. An RF transformer also has the benefit of providing electrical isolation between the signal source and the ADC. A transformer can be used for most ac applications. The center tap is used to shift the differential signal to the common-mode level required; in this case, it is connected to the reference so the common-mode level is the value of the reference. 3.75V 2.5V 1.25V Take care when choosing the op amp; the selection depends on the required power supply and system performance objectives. The driver circuits in Figure 35 and Figure 36 are optimized for dc coupling applications requiring best distortion performance. R R VIN+ C R The circuit configuration shown in Figure 35 converts a unipolar, single-ended signal into a differential signal. AD7440/ AD7450A VIN– VREF 3.75V 2.5V 1.25V The differential op amp driver circuit in Figure 36 is configured to convert and level shift a single-ended, ground-referenced (bipolar) signal to a differential signal centered at the VREF level of the ADC. EXTERNAL VREF 03051-A-037 The voltage applied to Point A sets up the common-mode voltage. In both diagrams, it is connected in some way to the reference, but any value in the common-mode range can be input here to set up the common mode. The AD8022 is a suitable dual op amp that could be used in this configuration to provide differential drive to the AD7440/AD7450A. Figure 37. Using an RF Transformer to Generate Differential Inputs 220Ω 2 × VREF p-p DIGITAL INPUTS 390Ω VREF V+ VDD 27Ω The digital inputs applied to the device are not limited by the maximum ratings, which limit the analog limits. Instead the digital inputs applied, CS and SCLK, can go to 7 V and are not restricted by the VDD + 0.3 V limits as on the analog input. GND V– VIN+ 220Ω 220Ω VIN– AD7440/ AD7450A VREF V+ 27Ω 0.1μF V– 03051-A-036 A 10kΩ EXTERNAL VREF Figure 35. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal into a Differential Signal 390Ω V+ VDD 27Ω V– 220Ω VIN+ 220Ω 220Ω AD7440/ AD7450A VIN– VREF V+ A 27Ω 0.1μF 10kΩ EXTERNAL VREF 03051-A-035 V– 20kΩ REFERENCE An external reference source is required to supply the reference to the device. This reference input can range from 100 mV to 3.5 V. With a 5 V power supply, the specified reference is 2.5 V and the maximum reference is 3.5 V. With a 3 V power supply, the specified reference is 2 V and the maximum reference is 2.2 V. In both cases, the reference is functional from 100 mV. 220Ω 2 × VREF p-p GND The main advantage of the inputs not being restricted to the VDD + 0.3 V limit is that power supply sequencing issues are avoided. If CS and SCLK are applied before VDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V was applied prior to VDD. Ensure that, when choosing the reference value for a particular application, the maximum analog input range (VIN max) is never greater than VDD + 0.3 V to comply with the maximum ratings of the device. The following two examples calculate the maximum VREF input that can be used when operating the AD7440/AD7450A at a VDD of 5 V and 3 V, respectively. Figure 36. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal into a Differential Signal Rev. C | Page 19 of 28 AD7440/AD7450A Example 1 Table 6. Examples of Suitable Voltage References VIN max = VDD + 0.3 VIN max = VREF + VREF/2 Reference AD780 ADR421 ADR420 If VDD = 5 V, then VIN max = 5.3 V. Therefore 3 × VREF/2 = 5.3 V VREF max = 3.5 V Output Voltage (V) 2.5/3 2.5 2.048 Initial Accuracy (%) 0.04 0.04 0.05 Operating Current (μA) 1000 500 500 SINGLE-ENDED OPERATION Example 2 VIN max = VDD + 0.3 VIN max = VREF + VREF/2 If VDD = 3 V, then VIN max = 3.3 V. Therefore, 3 × VREF/2 = 3.3 V VREF max = 2.2 V Thus, when operating at VDD = 3 V, the value of VREF can range from 100 mV to a maximum value of 2.2 V. When VDD = 2.7 V, VREF max = 2 V. These examples show that the maximum reference applied to the AD7440/AD7450A is directly dependent on the value applied to VDD. To operate the AD7440/AD7450A in single-ended mode, the VIN+ input is coupled to the signal source, while the VIN– input is biased to the appropriate voltage corresponding to the midscale code transition. This voltage is the common mode, which is a fixed dc voltage (usually the reference). The VIN+ input swings around this value and should have a voltage span of 2 × VREF to make use of the full dynamic range of the part. The input signal therefore has peak-to-peak values of common mode ±VREF. If the analog input is unipolar, an op amp in a noninverting unity gain configuration can be used to drive the VIN+ pin. The ADC operates from a single supply, so it is necessary to level shift ground-based bipolar signals to comply with the input requirements. An op amp can be configured to rescale and level shift the ground-based bipolar signal, so it is compatible with the selected input range of the AD7440/AD7450A (Figure 39). The value of the reference sets the analog input span and the common-mode voltage range. Errors in the reference source result in gain errors in the AD7440/AD7450A transfer function and add to specified full-scale errors on the part. A 0.1 μF capacitor should be used to decouple the VREF pin to GND. 5V 2.5V 0V R +2.5V 0V –2.5V VIN R VIN+ R AD7440/ AD7450A R VIN– Figure 38 shows a typical connection diagram for the VREF pin. Table 6 lists examples of suitable voltage references. 0.1μF EXTERNAL VREF (2.5V) VDD AD7440/ AD7450A* NC VDD 0.1μF 10nF 0.1μF OPSEL 8 NC 2 VIN 7 3 TEMP VOUT 6 NC 2.5V 1 4 GND TRIM 5 NC Figure 39. Applying a Bipolar Single-Ended Input to the AD7440/AD7450A VREF 0.1μF NC = NO CONNECT *ADDITIONAL PINS OMITTED FOR CLARITY 03051-A-038 AD780 VREF 03051-A-039 Thus, when operating at VDD = 5 V, the value of VREF can range from 100 mV to a maximum value of 3.5 V. When VDD = 4.75 V, VREF max = 3.17 V. When supplied with a 5 V power supply, the AD7440/AD7450A can handle a single-ended input. The design of these devices is optimized for differential operation, so with a single-ended input, performance degrades. Linearity degrades by typically 0.2 LSB, the full-scale errors degrade typically by 1 LSB, and ac performance is not guaranteed. Figure 38. Typical VREF Connection Diagram for VDD = 5 V Rev. C | Page 20 of 28 AD7440/AD7450A Sixteen serial clock cycles are required to perform a conversion and access data from the AD7440/AD7450A. CS going low provides the first leading zero to be read in by the DSP or microcontroller. The remaining data is then clocked out on the subsequent SCLK falling edges beginning with the second leading zero. Thus, the first falling clock edge on the serial clock provides the second leading zero. The final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. Once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that before the next conversion is initiated, enough time is left to meet the acquisition and quiet time specifications (see Timing Examples 1 and 2). To achieve 1 MSPS with an 18 MHz clock for VDD = 3 V and 5 V, an 18-clock burst performs the conversion and leaves enough time before the next conversion for the acquisition and quiet time. SERIAL INTERFACE Figure 2 and Figure 3 show detailed timing diagrams for the serial interface of the AD7450A and the AD7440, respectively. The serial clock provides the conversion clock and also controls the transfer of data from the devices during conversion. CS initiates the conversion process and frames the data transfer. The falling edge of CS puts the track-and-hold into hold mode and takes the bus out of three-state. The analog input is sampled and the conversion is initiated at this point. The conversion requires 16 SCLK cycles to complete. Once 13 SCLK falling edges have occurred, the track-and-hold goes back into track on the next SCLK rising edge, as shown at Point B in Figure 2 and Figure 3. On the 16th SCLK falling edge, the SDATA line goes back into three-state. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion terminates and the SDATA line goes back into three-state. In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge; that is, the first rising edge of SCLK after the CS falling edge would have the leading zero provided and the 15th SCLK edge would have DB0 provided. The conversion result from the AD7440/AD7450A is provided on the SDATA output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7450A consists of four leading zeros followed by 12 bits of conversion data provided MSB first; the data stream of the AD7440 consists of four leading zeros, followed by the 10 bits of conversion data followed by two trailing zeros, which is also provided MSB first. In both cases, the output coding is twos complement. CS SCLK tCONVERT t5 1 2 3 4 5 B 13 C 14 t6 15 16 t8 tQUIET tACQUISITION 12.5(1/FSCLK) 1/THROUGHPUT Figure 40. Serial Interface Timing Example Rev. C | Page 21 of 28 03051-A-040 10ns t2 AD7440/AD7450A Timing Example 1 Timing Example 2 Having FSCLK = 18 MHz and a throughput rate of 1 MSPS gives a cycle time of Having FSCLK = 5 MHz and a throughput rate of 315 kSPS gives a cycle time of 1/Throughput = 1/1,000,000 = 1 μs A cycle consists of 1/Throughput = 1/315,000 = 3.174 μs A cycle consists of t2 + 12.5(1/FSCLK) + tACQ = 1 μs Therefore, if t2 = 10 ns t2 + 12.5(1/FSCLK) + tACQ = 3.174 μs Therefore, if t2 is 10 ns 10 ns + 12.5(1/18 MHz) + tACQ = 1 μs tACQ = 296 ns 10 ns + 12.5(1/5 MHz) + tACQ = 3.174 μs tACQ = 664 ns This 296 ns satisfies the requirement of 290 ns for tACQ. This 664 ns satisfies the requirement of 290 ns for tACQ. From Figure 40, tACQ comprises From Figure 40, tACQ comprises 2.5(1/FSCLK) + t8 + tQUIET where t8 = 35 ns. This allows a value of 122 ns for tQUIET, satisfying the minimum requirement of 60 ns. 2.5(1/FSCLK) + t8 + tQUIET where t8 = 35 ns. This allows a value of 129 ns for tQUIET, satisfying the minimum requirement of 60 ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 60 ns minimum tQUIET between conversions. In Timing Example 2, the signal should be fully acquired at approximately Point C in Figure 40. Rev. C | Page 22 of 28 AD7440/AD7450A MODES OF OPERATION POWER-DOWN MODE The operational mode of the AD7440/AD7450A is selected by controlling the logic state of the CS signal during a conversion. There are two possible modes of operation, normal and powerdown. The point at which CS is pulled high after the conversion has been initiated determines whether or not the device enters power-down mode. Similarly, if already in power-down, CS controls whether the devices return to normal operation or remain in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the ADC is then powered down for a relatively long duration between these bursts of conversions. When the AD7440/AD7450A are in the power-down mode, all analog circuitry is powered down. To enter power-down mode, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 42. NORMAL MODE This mode is intended for fastest throughput rate performance. The user does not have to worry about any power-up times with the AD7440/AD7450A remaining fully powered up all the time. Figure 41 shows the general diagram of the operation of the AD7440/AD7450A in this mode. The conversion is initiated on the falling edge of CS, as described in the Serial Interface section. To ensure the part remains fully powered up, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. CS 10 Once CS has been brought high in this window of SCLKs, the part enters power-down, the conversion that was initiated by the falling edge of CS is terminated, and SDATA goes back into three-state. The time from the rising edge of CS to SDATA three-state enabled is never greater than t8 (refer to the Timing Specifications). If CS is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental power-down due to glitches on the CS line. 16 03051-A-041 4 LEADING ZEROS + CONVERSION RESULT THREE-STATE Figure 42. Entering Power-Down Mode SCLK SDATA 10 SDATA CS 1 1 2 03051-A-042 SCLK Figure 41. Normal Mode Operation In order to exit this mode of operation and power up the AD7440/AD7450A again, a dummy conversion is performed. On the falling edge of CS, the device begins to power up and continues to power up as long as CS is held low until after the falling edge of the 10th SCLK. The device is fully powered up after 1 μs has elapsed and, as shown in Figure 43, valid data results from the next conversion. If CS is brought high any time after the 10th SCLK falling edge, but before the 16th SCLK falling edge, the part remains powered up but the conversion terminates and SDATA goes back into three-state. Sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. CS may idle high until the next conversion or may idle low until sometime prior to the next conversion. Once a data transfer is complete, when SDATA has returned to three-state, another conversion can be initiated after the quiet time, tQUIET, has elapsed by again bringing CS low. tPOWER-UP PART BEGINS TO POWER UP CS A THIS PART IS FULLY POWERED UP WITH VIN FULLY ACQUIRED 1 10 16 1 10 16 SDATA INVALID DATA VALID DATA Figure 43. Exiting Power-Down Mode Rev. C | Page 23 of 28 03153-A-031 SCLK AD7440/AD7450A If CS is brought high before the 10th falling edge of SCLK, the AD7440/AD7450A again goes back into power-down. This avoids accidental power-up due to glitches on the CS line or an inadvertent burst of eight SCLK cycles while CS is low. So although the device may begin to power up on the falling edge of CS, it again powers down on the rising edge of CS as long as it occurs before the 10th SCLK falling edge. POWER-UP TIME The power-up time of the AD7440/AD7450A is typically 1 μs, which means that with any frequency of SCLK up to 18 MHz, one dummy cycle is always sufficient to allow the device to power up. Once the dummy cycle is complete, the ADC is fully powered up and the input signal is acquired properly. The quiet time, tQUIET, must still be allowed from the point at which the bus goes back into three-state after the dummy conversion to the next falling edge of CS. When running at the maximum throughput rate of 1 MSPS, the AD7440/AD7450A power up and acquire a signal within ±0.5 LSB in one dummy cycle, 1 μs. When powering up from the power-down mode with a dummy cycle, as in Figure 43, the track-and-hold, which was in hold mode while the part was powered down, returns to track mode after the first SCLK edge the part receives after the falling edge of CS. This is shown as Point A in Figure 43. Although at any SCLK frequency one dummy cycle is sufficient to power up the device and acquire VIN, it does not mean that a full dummy cycle of 16 SCLKs must always elapse to power up the device and acquire VIN fully; 1 μs is sufficient to power up the device and acquire the input signal. For example, if a 5 MHz SCLK frequency was applied to the ADC, the cycle time would be 3.2 μs (1/(5 MHz) × 16). In one dummy cycle, 3.2 μs, the part would be powered up and VIN acquired fully. However, after 1 μs with a 5 MHz SCLK, only five SCLK cycles would have elapsed. At this stage, the ADC would be fully powered up and the signal acquired. So in this case, the CS can be brought high after the 10th SCLK falling edge and brought low again after a time, tQUIET, to initiate the conversion. When power supplies are first applied to the device, the ADC may power up in either power-down mode or normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if the user wants the part to power up in power-down mode, the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as the one shown in Figure 42. Once supplies are applied to the AD7440/AD7450A, the powerup time is the same as that when powering up from powerdown mode. It takes about 1 μs to power up fully if the part powers up in normal mode. It is not necessary to wait 1 μs before executing a dummy cycle to ensure the desired mode of operation. Instead, the dummy cycle can occur directly after power is supplied to the ADC. If the first valid conversion is then performed directly after the dummy conversion, ensure that adequate acquisition time has been allowed. As mentioned earlier, when powering up from the power-down mode, the part returns to track mode upon the first SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are applied, the track-and-hold is already in track mode. Assuming the user has the facility to monitor the ADC supply current, this means the ADC powers up in the desired mode of operation, and thus a dummy cycle is not required to change mode. A dummy cycle is therefore not required to place the track-and-hold into track mode. POWER VS. THROUGHPUT RATE By using the power-down mode on the AD7440/AD7450A when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 44 shows how, as the throughput rate is reduced, the device remains in its power-down state longer and the average power consumption is reduced accordingly for both 5 V and 3 V power supplies. For example, if the AD7440/AD7450A are operated in continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 18 MHz, and the device is placed in powerdown mode between conversions, the power consumption is calculated as follows: Power Dissipation during Normal Operation = 9.25 mW max (for VDD = 5 V) If the power-up time is one dummy cycle (1 μs), and the remaining conversion time is another cycle (1 μs), the AD7440/AD7450A can be said to dissipate 9.25 mW for 2 μs 1 during each conversion cycle. If the throughput rate = 100 kSPS, the cycle time = 10 μs and the average power dissipated during each cycle is (2/10) × 9.25 mW = 1.85 mW. For the same scenario, if VDD = 3 V, the power dissipation during normal operation is 4 mW max. The AD7440/AD7450A can now be said to dissipate 4 mW for 2 μs1 during each conversion cycle. 1 This figure assumes a very short time to enter power-down mode. This increases as the burst of clocks used to enter this mode is increased. Rev. C | Page 24 of 28 AD7440/AD7450A Thus, the average power dissipated during each cycle with a throughput rate of 100 kSPS is (2/10) × 4 mW = 0.8 mW. This is how the power numbers in Figure 44 are calculated. For throughput rates above 320 kSPS, it is recommended to reduce the serial clock frequency for best power performance. 100 VDD = 5V The timer registers, for example, are loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and therefore the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given (AX0 = TX0), the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high again before starting transmission. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, then the data may be transmitted or it may wait until the next clock edge. 1 VDD = 3V 0.01 03051-A-044 0.1 0 50 100 150 200 250 THROUGHPUT (kSPS) 300 350 Figure 44. Power vs. Throughput Rate for Power-Down Mode MICROPROCESSOR AND DSP INTERFACING The serial interface on the AD7440/AD7450A allows the parts to be directly connected to many different microprocessors. This section explains how to interface the AD7440/AD7450A with some of the more common microcontroller and DSP serial interface protocols. ADSP-21xx* AD7440/ AD7450A* SCLK SCLK DR SDATA RFS CS TFS AD7440/AD7450A to ADSP-21xx The ADSP-21xx family of DSPs is interfaced directly to the AD7440/AD7450A without any glue logic required. *ADDITIONAL PINS REMOVED FOR CLARITY Figure 45. Interfacing to the ADSP-21xx The SPORT control register should be set up as follows: For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, an SCLK of 2 MHz is obtained and eight master clock periods elapse for every SCLK period. If the timer registers are loaded with the value 803, then 100.5 SCLKs occur between interrupts and subsequently between transmit instructions. This situation results in nonequidistant sampling as the transmit instruction is occurring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, equidistant sampling is implemented by the DSP. Table 7. Parameter TFSW = RFSW = 1 INVRFS = INVTFS = 1 DTYPE = 00 SLEN = 1111 ISCLK = 1 TFSR = RFSR = 1 IRFS = 0 ITFS = 1 03051-A-045 POWER (mW) 10 The connection diagram is shown in Figure 45. The ADSP-21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described. The frame synchronization signal generated on the TFS is tied to CS and, as with all signal processing applications, equidistant sampling is necessary. However in this example, the timer interrupt is used to control the sampling rate of the ADC; under certain conditions, equidistant sampling may not be achieved. Description Alternate framing Active low frame signal Right-justify data 16-bit data-words Internal serial clock Frame every word To implement power-down mode, SLEN should be set to 1001 to issue an 8-bit SCLK burst. Rev. C | Page 25 of 28 AD7440/AD7450A AD7440/AD7450A to TMS320C5x/C54x GROUNDING AND LAYOUT HINTS The serial interface on the TMS320C5x/C54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7440/AD7450A. The CS input allows easy interfacing between the TMS320C5x/C54x and the AD7440/AD7450A without any glue logic required. The serial port of the TMS320C5x/C54x is set up to operate in burst mode with internal CLKx (Tx serial clock) and FSx (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1, and TxM = 1. The format bit, FO, may be set to 1 to set the word length to eight bits to implement the power-down mode on the AD7440/AD7450A. The connection diagram is shown in Figure 46. For signal processing applications, it is imperative that the frame synchronization signal from the TMS320C5x/C54x provide equidistant sampling. The printed circuit board that houses the AD7440/AD7450A should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should be joined in only one place, a star ground point established as close to the GND pin on the AD7440/AD7450A as possible. Avoid running digital lines under the devices because this couples noise onto the die. The analog ground plane should be allowed to run under the AD7440/AD7450A to avoid noise coupling. The power supply lines to the AD7440/AD7450A should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. TMS320C5x/ C54x* AD7440/ AD7450A* SCLK CLKx CLKR DR SDATA CS FSR 03051-A-046 FSx *ADDITIONAL PINS REMOVED FOR CLARITY Figure 46. Interfacing to the TMS320C5x/C54 AD7440/AD7450A to DSP56xxx The connection diagram in Figure 47 shows how the device can be connected to the synchronous serial interface (SSI) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in synchronous mode (SYN bit in CRB = 1) with internally generated 1-word frame sync for both Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word length to 16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To implement power-down mode on the AD7440/AD7450A, the word length can be changed to 8 bits by setting Bits WL1 = 0 and WL0 = 0 in CRA. For signal processing applications, it is imperative that the frame synchronization signal from the DSP56xxx provide equidistant sampling. AD7440/ AD7450A* DSP56xxx* SCLK SCLK CS SR2 03051-A-047 SDATA SRD Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 μF tantalum capacitors in parallel with 0.1 μF capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device. EVALUATING THE AD7440/AD7450A PERFORMANCE The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the evaluation board controller. The evaluation board controller can be used in conjunction with the AD7440/AD7450A evaluation board, as well as many other Analog Devices evaluation boards ending with the CB designator, to demonstrate and evaluate the ac and dc performance of the AD7440/AD7450A. The software allows the user to perform ac (fast Fourier transform) and dc (histogram of codes) tests on the device. See the AD7440/AD7450A application note that accompanies the evaluation kit for more information. *ADDITIONAL PINS REMOVED FOR CLARITY Figure 47. Interfacing to the DSP56xxx Rev. C | Page 26 of 28 AD7440/AD7450A OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1 2 3 4 1.60 BSC 2.80 BSC PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.30 1.15 0.90 1.45 MAX 0.38 0.22 0.15 MAX 0.22 0.08 0.60 0.45 0.30 8° 4° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 48. 8-Lead Small Outline Transistor Package [SOT-23] (RT-8) Dimensions shown in millimeters 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5 5.15 4.90 4.65 4 PIN 1 0.65 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 49. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. C | Page 27 of 28 0.80 0.60 0.40 AD7440/AD7450A ORDERING GUIDE Model AD7440BRT-REEL7 AD7440BRT-R2 AD7440BRTZ-REEL7 2 AD7440BRTZ-R22 AD7440BRM AD7440BRM-REEL7 AD7440BRMZ2 AD7450ABRT-REEL7 AD7450ABRT-R2 AD7450ABRTZ-REEL72 AD7450ABRM AD7450ABRM-REEL7 AD7450ABRMZ2 EVAL-AD7440CB 3 EVAL-AD7450ACB3 EVAL-CONTROL BRD2 4 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Linearity Error (LSB) 1 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±1 ±1 ±1 ±1 ±1 ±1 1 Package Description 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead MSOP 8-lead MSOP 8-lead MSOP 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead MSOP 8-lead MSOP 8-lead MSOP Package Option RT-8 RT-8 RT-8 RT-8 RM-8 RM-8 RM-8 RT-8 RT-8 RT-8 RM-8 RM-8 RM-8 Evaluation Board Evaluation Board Controller Board Branding CTB CTB C3J C3J CTB CTB C3J CSB CSB C4N CSB CSB C4N Linearity error here refers to integral nonlinearity error. Z = Pb-free part. 3 This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes. 4 Evaluation board controller. This board is a complete unit allowing a PC to control and communicate with all Analog Devices’ evaluation boards ending in the CB designator. For a complete evaluation kit, order the ADC evaluation board (that is, the EVAL-AD7450ACB or EVAL-AD7440CB), the EVAL-CONTROL BRD2, and a 12 V ac transformer. See the AD7440/AD7450A application note that accompanies the evaluation kit for more information. 2 © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03051–0–9/05(C) Rev. C | Page 28 of 28