AD7524LP

a FEATURES Microprocessor Compatible (6800, 8085, Z80, Etc.) TTL/CMOS Compatible Inputs On-Chip Data Latches Endpoint Linearity Low Power Consumption Monotonicity Guaranteed (Full Temperature Range) Latch Free (No Protection Schottky Required) APPLICATIONS Microprocessor Controlled Gain Circuits Microprocessor Controlled Attenuator Circuits Microprocessor Controlled Function Generation Precision AGC Circuits Bus Structured Instruments CMOS 8-Bit Buffered Multiplying DAC AD7524 FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The AD7524 is a low cost, 8-bit monolithic CMOS DAC designed for direct interface to most microprocessors. Basically an 8-bit DAC with input latches, the AD7524’s load cycle is similar to the “write” cycle of a random access memory. Using an advanced thin-film on CMOS fabrication process, the AD7524 provides accuracy to 1/8 LSB with a typical power dissipation of less than 10 milliwatts. A newly improved design eliminates the protection Schottky previously required and guarantees TTL compatibility when using a +5 V supply. Loading speed has been increased for compatibility with most microprocessors. Featuring operation from +5 V to +15 V, the AD7524 interfaces directly to most microprocessor buses or output ports. Excellent multiplying characteristics (2- or 4-quadrant) make the AD7524 an ideal choice for many microprocessor controlled gain setting and signal control applications. Model1 AD7524JN AD7524KN AD7524LN AD7524JP AD7524KP AD7524LP AD7524JR AD7524AQ AD7524BQ AD7524CQ AD7524SQ AD7524TQ AD7524UQ AD7524SE AD7524TE AD7524UE ORDERING GUIDE Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C Nonlinearity (VDD = +15 V) ± 1/2 LSB ± 1/4 LSB ± 1/8 LSB ± 1/2 LSB ± 1/4 LSB ± 1/8 LSB ± 1/2 LSB ± 1/2 LSB ± 1/4 LSB ± 1/8 LSB ± 1/2 LSB ± 1/4 LSB ± 1/8 LSB ± 1/2 LSB ± 1/4 LSB ± 1/8 LSB Package Option2 N-16 N-16 N-16 P-20A P-20A P-20A R-16A Q-16 Q-16 Q-16 Q-16 Q-16 Q-16 E-20A E-20A E-20A NOTES 1 To order MIL-STD-883, Class B processed parts, add/883B to part number. Contact your local sales office for military data sheet. For U.S. Standard Military Drawing (SMD) see DESC drawing #5962-87700. 2 E = Leadless Ceramic Chip Carrier: N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD7524–SPECIFICATIONS (V Parameter STATIC PERFORMANCE Resolution Relative Accuracy J, A, S Versions K, B, T Versions L, C, U Versions Monotonicity Gain Error2 Average Gain TC 3 DC Supply Rejection,3 ∆Gain/∆VDD Output Leakage Current IOUT1 (Pin 1) IOUT2 (Pin 2) DYNAMIC PERFORMANCE Output Current Settling Time3 (to 1/2 LSB) AC Feedthrough3 at OUT1 at OUT2 REFERENCE INPUT RIN (Pin 15 to GND)4 ANALOG OUTPUTS Output Capacitance3 COUT1 (Pin 1) COUT2 (Pin 2) COUT1 (Pin 1) COUT2 (Pin 2) DIGITAL INPUTS Input HIGH Voltage Requirement VIH Input LOW Voltage Requirement VIL Input Current IIN Input Capacitance3 DB0–DB7 WR, CS SWITCHING CHARACTERISTICS Chip Select to Write Setup Time5 tCS AD7524J, K, L, A, B, C AD7524S, T, U Chip Select to Write Hold Time tCH All Grades Write Pulse Width tWR AD7524J, K, L, A, B, C AD7524S, T, U Data Setup Time tDS AD7524J, K, L, A, B, C AD7524S, T, U Data Hold Time tDH All Grades POWER SUPPLY IDD 8 ± 1/2 ± 1/2 ± 1/2 Guaranteed ± 2 1/2 ± 40 0.08 0.002 ± 50 ± 50 8 ± 1/2 ± 1/4 ± 1/8 Guaranteed ± 1 1/4 ± 10 0.02 0.001 ± 50 ± 50 REF = +10 V, VOUT1 = VOUT2 = 0 V, unless otherwise noted) Test Conditions/Comments Limit, TA = +25 C Limit, TMIN, TMAX1 VDD = +5 V VDD = +15 V VDD = 5 V VDD = +15 V Units 8 ± 1/2 ± 1/2 ± 1/2 Guaranteed ± 3 1/2 ± 40 0.16 0.01 ± 400 ± 400 8 ± 1/2 ± 1/4 ± 1/8 Guaranteed ± 1 1/2 ± 10 0.04 0.005 ± 200 ± 200 Bits LSB max LSB max LSB max Gain TC Measured from +25 °C to TMIN or from +25°C to TMAX % FSR/% max ∆VDD = ± 10% % FSR/% typ nA max nA max DB0–DB7 = 0 V; WR, CS = 0 V; VREF = ± 10 V DB0–DB7 = VDD; WR, CS = 0 V; VREF = ± 10 V LSB max ppm/°C 400 250 500 350 ns max OUT1 Load = 100 Ω, CEXT = 13 pF; WR, CS = 0 V; DB0–DB7 = 0 V to VDD to 0 V. VREF = ± 10 V, 100 kHz Sine Wave; DB0–DB7 = 0 V; WR, CS = 0 V 0.25 0.25 5 20 0.25 0.25 5 20 0.5 0.5 5 20 0.5 0.5 5 20 % FSR max % FSR max kΩ min kΩ max 120 30 30 120 120 30 30 120 120 30 30 120 120 30 30 120 pF max pF max pF max pF max DB0–DB7 = VDD; WR, CS = 0 V DB0–DB7 = 0 V; WR, CS = 0 V +2.4 +0.8 ±1 5 20 +13.5 +1.5 ±1 5 20 +2.4 +0.5 ± 10 5 20 +13.5 +1.5 ± 10 5 20 V min V max µA max pF max pF max VIN = 0 V or VDD VIN = 0 V VIN = 0 V See Timing Diagram tWR = tCS 170 170 100 100 220 240 130 150 ns min ns min 0 0 0 0 ns min tCS ≥ tWR, tCH ≥ 0 170 170 100 100 220 240 130 150 ns min ns min 135 135 60 60 170 170 80 100 ns min ns min 10 1 100 10 2 100 10 2 500 10 2 500 ns min mA max µA max All Digital Inputs VIL or VIH All Digital Inputs 0 V or VDD NOTES 1 Temperature ranges as follows: J, K, L versions: –40°C to +85°C A, B, C versions: –40°C to +85°C S, T, U versions: –55°C to +125°C 2 Gain error is measured using internal feedback resistor. Full-Scale Range (FSR) = V REF. 3 Guaranteed not tested. 4 DAC thin-film resistor temperature coefficient is approximately –300 ppm/ °C. 5 AC parameter, sample tested @ +25 °C to ensure conformance to specification. Specifications subject to change without notice. –2– REV. B AD7524 ABSOLUTE MAXIMUM RATINGS* (TA = +25°C, unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Digital Input Voltage to GND . . . . . . . . –0.3 V to VDD +0.3 V OUT1, OUT2 to GND . . . . . . . . . . . . . –0.3 V to VDD +0.3 V *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Power Dissipation (Any Package) To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Derates above 75°C by . . . . . . . . . . . . . . . . . . . . 6 mW/°C Operating Temperature Commercial (J, K, L) . . . . . . . . . . . . . . . . . –40°C to +85°C Industrial (A, B, C) . . . . . . . . . . . . . . . . . . –40°C to +85°C Extended (S, T, U) . . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7524 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE TERMINOLOGY RELATIVE ACCURACY: A measure of the deviation from a straight line through the end points of the DAC transfer function. Normally expressed as a percentage of full scale range. For the AD7524 DAC, this holds true over the entire VREF range. with all 1s in the DAC after offset error has been adjusted out and is expressed in LSBs. Gain Error is adjustable to zero with an external potentiometer. FEEDTHROUGH ERROR: Error caused by capacitive coupling from VREF to output with all switches OFF. RESOLUTION: Value of the LSB. For example, a unipolar con- OUTPUT CAPACITANCE: Capacity from OUT1 and verter with n bits has a resolution of (2–n) (VREF). A bipolar conOUT2 terminals to ground. verter of n bits has a resolution of [2–(n–1)] [VREF]. Resolution in no OUTPUT LEAKAGE CURRENT: Current which appears way implies linearity. on OUT1 terminal with all digital inputs LOW or on OUT2 GAIN ERROR: Gain Error is a measure of the output error beterminal when all inputs are HIGH. This is an error current tween an ideal DAC and the actual device output. It is measured which contributes an offset voltage at the amplifier output. PIN CONFIGURATIONS DIP, SOIC PLCC LCCC REV. B –3– AD7524 CIRCUIT DESCRIPTION CIRCUIT INFORMATION WRITE MODE The AD7524, an 8-bit multiplying D/A converter, consists of a highly stable thin film R-2R ladder and eight N-channel current switches on a monolithic chip. Most applications require the addition of only an output operational amplifier and a voltage or current reference. The simplified D/A circuit is shown in Figure 1. An inverted R-2R ladder structure is used—that is, the binarily weighted currents are switched between the OUT1 and OUT2 bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. When CS and WR are both LOW, the AD7524 is in the WRITE mode, and the AD7524 analog output responds to data activity at the DB0–DB7 data bus inputs. In this mode, the AD7524 acts like a nonlatched input D/A converter. HOLD MODE When either CS or WR is HIGH, the AD7524 is in the HOLD mode. The AD7524 analog output holds the value corresponding to the last digital input present at DB0–DB7 prior to WR or CS assuming the HIGH state. MODE SELECTION TABLE CS L H X WR L X H Mode Write Hold Hold DAC Response DAC responds to data bus (DB0–DB7) inputs. Data bus (DB0–DB7) is Locked Out: DAC holds last data present when WR or CS assumed HIGH state. L = Low State, H = High State, X = Don't Care. WRITE CYCLE TIMING DIAGRAM Figure 1. Functional Diagram EQUIVALENT CIRCUIT ANALYSIS The equivalent circuit for all digital inputs LOW is shown in Figures 2. In Figure 2 with all digital inputs LOW, the reference current is switched to OUT2. The current source ILEAKAGE is composed of surface and junction leakages to the substrate while the 1 current source represents a constant 1-bit cur256 rent drain through the termination resistor on the R-2R ladder. The “ON” capacitance of the output N-channel switches is 120 pF, as shown on the OUT2 terminal. The “OFF” switch capacitance is 30 pF, as shown on the OUT1 terminal. Analysis of the circuit for all digital inputs high is similar to Figure 2 however, the “ON” switches are now on terminal OUT1, hence the 120 pF appears at that terminal. Figure 2. AD7524 DAC Equivalent Circuit—All Digital Inputs Low INTERFACE LOGIC INFORMATION MODE SELECTION AD7524 mode selection is controlled by the CS and WR inputs. Figure 3. Supply Current vs. Logic Level Typical plots of supply current, IDD, versus logic input voltage, VIN, for VDD = +5 V and VDD = +15 V are shown above. –4– REV. B AD7524 ANALOG CIRCUIT CONNECTIONS AD7524 AD7524 Figure 4. Unipolar Binary Operation (2-Quadrant Multiplication) Table I. Unipolar Binary Code Table Figure 5. Bipolar (4-Quadrant) Operation Table II. Bipolar (Offset Binary) Code Table Digital Input MSB LSB 1111 1111 1000 0001 1000 0000 0111 1111 0000 0001 0000 0000 Analog Output –VREF (255/256) –VREF (129/256) –VREF (128/256) = –VREF/2 –VREF (127/256) –VREF (1/256) –VREF (0/256) = 0 Digital Input MSB LSB 1111 1111 1000 0001 1000 0000 0111 1111 0000 0001 0000 0000 Note: 1 LSB = (2–7)(VREF) = 1/128 (VREF) Analog Output +VREF (127/128) +VREF (1/128 ) 0 –VREF (1/128) –VREF (127/128) –VREF (128/128) Note: 1 LSB = (2 –8)(VREF) = 1/256 (VREF) MICROPROCESSOR INTERFACE Figure 6. AD7524/8085A Interface Figure 7. AD7524/MC6800 Interface REV. B –5– AD7524 POWER GENERATION Figure 8. –6– REV. B AD7524 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Terminal Ceramic Leadless Chip Carrier (E-20A) 0.200 (5.08) BSC 0.100 (2.54) BSC 3 4 1 20-Lead Plastic Leadless Chip Carrier (PLCC) (P-20A) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) 0.100 (2.54) 0.064 (1.63) 0.095 (2.41) 0.075 (1.90) 0.358 (9.09) 0.358 (9.09) 0.342 (8.69) MAX SQ SQ 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.075 (1.91) REF 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 19 18 20 0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC 3 4 BOTTOM VIEW 14 13 8 9 19 18 PIN 1 IDENTIFIER TOP VIEW (PINS DOWN) 8 9 14 13 0.050 (1.27) BSC 45° TYP 0.150 (3.81) BSC 0.088 (2.24) 0.054 (1.37) 0.055 (1.40) 0.045 (1.14) 0.020 (0.50) R 0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.02) SQ 0.385 (9.78) 16-Lead Plastic DIP (Narrow) (N-16) 0.840 (21.33) 0.745 (18.93) 16 1 9 8 16-Lead Cerdip (Q-16) 0.005 (0.13) MIN 16 0.080 (2.03) MAX 9 0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 1 8 0.310 (7.87) 0.220 (5.59) PIN 1 0.840 (21.34) MAX 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.070 (1.77) SEATING 0.045 (1.15) PLANE 0.015 (0.381) 0.008 (0.204) 0.100 (2.54) BSC 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15° 0° 0.015 (0.38) 0.008 (0.20) 16-Lead Narrow-Body (SOIC) (R-16A) 0.3937 (10.00) 0.3859 (9.80) 16 1 9 8 0.1574 (4.00) 0.1497 (5.80) 0.2550 (6.20) 0.2284 (5.80) PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45° 0.0099 (0.25) SEATING PLANE 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) REV. B –7– –8– C542e–5–11/86 PRINTED IN U.S.A.