AD7622BSTZRL

16-Bit, 1.5 LSB INL, 2 MSPS PulSAR® ADC AD7622 FEATURES APPLICATIONS Medical instruments High speed data acquisition/high dynamic data acquisition Digital signal processing Spectrum analysis Instrumentation Communications ATE FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND AGND OVDD AD7622 AVDD OGND REF REF AMP IN+ SERIAL PORT SWITCHED CAP DAC IN– 16 PARALLEL INTERFACE PDREF D[15:0] SER/PAR BUSY RD CLOCK PDBUF CS CONTROL LOGIC AND CALIBRATION CIRCUITRY PD OB/2C RESET 06023-001 BYTESWAP WARP NORMAL CNVST Figure 1. Table 1. PulSAR 48-Lead ADC Selection Type/kSPS Pseudo Differential True Bipolar True Differential 18-Bit Multichannel/ Simultaneous GENERAL DESCRIPTION 100 to 250 AD7651, AD7660, AD7661 AD7610, AD7663 AD7675 AD7631, AD7678 500 to 570 AD7650, AD7652, AD7664, AD7666 AD7665 AD7676 AD7679 AD7654 650 to 1000 AD7653, AD7667 AD7612, AD7671 AD7677 AD7634, AD7674 AD7655 >1000 AD7621, AD7622, AD7623 AD7641, AD7643 1.50 POSITIVE INL = +0.43 LSB NEGATIVE INL = –0.49 LSB 1.00 0.50 INL (LSB) The AD7622 is a 16-bit, 2 MSPS, charge redistribution SAR, fully differential, analog-to-digital converter (ADC) that operates from a single 2.5 V power supply. The part contains a high speed, 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports. It features two very high sampling rate modes (wideband warp and warp) and a fast mode (normal) for asynchronous rate applications. The AD7622 is hardware factory calibrated and tested to ensure ac parameters, such as signal-to-noise ratio (SNR), in addition to the more traditional dc parameters of gain, offset, and linearity. The AD7622 is available in Pb-free only packages with operation specified from −40°C to +85°C. DVDD DGND 0 –0.50 –1.00 –1.50 06023-005 Throughput 2 MSPS (wideband warp and warp mode) 1.5 MSPS (normal mode) INL: ±0.5 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR) 16-bit resolution with no missing codes Dynamic range: 92.5 dB typical SINAD: 91 dB minimum @ 20 kHz (VREF = 2.5 V) THD: −115 dB typical @ 20 kHz (VREF = 2.5 V) 2.048 V internal reference: typical drift 8 ppm/°C; TEMP output Differential input range: ±VREF (VREF up to 2.5 V) No pipeline delay (SAR architecture) Parallel (16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface SPI®/QSPI™/MICROWIRE™/DSP compatible Single 2.5 V supply operation Power dissipation 70 mW typical @ 2 MSPS with internal REF 2 μW in power-down mode Pb-free, 48-lead LQFP and 48-lead LFCSP Pin compatible with other PulSAR 48-lead ADCs 0 16384 32768 49152 65536 CODE Figure 2. Integral Nonlinearity vs. Code Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2020 Analog Devices, Inc. All rights reserved. AD7622 TABLE OF CONTENTS Features .............................................................................................. 1  Multiplexed Inputs..................................................................... 17  Applications ...................................................................................... 1  Driver Amplifier Choice ........................................................... 18  General Description ......................................................................... 1  Voltage Reference Input............................................................ 19  Functional Block Diagram .............................................................. 1  Power Supply .............................................................................. 20  Revision History ............................................................................... 2  Conversion Control ................................................................... 20  Specifications .................................................................................... 3  Interfaces ......................................................................................... 21  Timing Specifications ...................................................................... 5  Digital Interface .......................................................................... 21  Absolute Maximum Ratings ........................................................... 7  Parallel Interface......................................................................... 21  ESD Caution.................................................................................. 7  Serial interface ............................................................................ 22  Pin Configuration and Function Descriptions ............................ 8  Master Serial Interface ............................................................... 22  Terminology .................................................................................... 11  Slave Serial Interface .................................................................. 24  Typical Performance Characteristics ........................................... 12  Microprocessor Interfacing ...................................................... 26  Applications Information.............................................................. 15  Application Hints ........................................................................... 27  Circuit Information ................................................................... 15  Layout .......................................................................................... 27  Converter Operation.................................................................. 15  Evaluating the AD7622 Performance...................................... 27  Modes of Operation ................................................................... 15  Outline Dimensions ....................................................................... 28  Transfer Functions ..................................................................... 16  Ordering Guide .......................................................................... 28  Typical Connection Diagram ....................................................... 17  Analog Inputs ............................................................................. 17  REVISION HISTORY 8/2020—Rev. 0 to Rev. A Changed CP-48-1 to CP-48-4 ...................................... Throughout Added Figure 5; Renumbered Sequentially .................................. 8 Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 28 6/2006—Revision 0: Initial Version Rev. A | Page 2 of 28 AD7622 SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance2 THROUGHPUT SPEED Complete Cycle Throughput Rate Time Between Conversions Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error3 No Missing Codes Differential Linearity Error Transition Noise Transition Noise Zero Error, TMIN to TMAX5 Zero Error Temperature Drift Gain Error, TMIN to TMAX5 Gain Error Temperature Drift Power Supply Sensitivity AC ACCURACY Dynamic Range Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) −3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Conditions Min 16 VIN+ − VIN− VIN+, VIN− to AGND fIN = 100 kHz 2 MSPS throughput −VREF −0.1 Wideband warp, warp modes Wideband warp, warp modes Wideband warp, warp modes Normal mode Normal mode TMIN to TMAX = −40°C to +85°C Typ Max Unit Bits +VREF AVDD1 V V dB μA 500 2 1 667 1.5 ns MSPS ms ns MSPS +1.5 ±0.5 ±4 LSB4 Bits LSB LSB LSB LSB ppm/°C LSB ppm/°C LSB 92.5 92 90.5 91 117 110 101 −115 −109 −100 92 90.5 91 50 dB6 dB dB dB dB dB dB dB dB dB dB dB dB MHz 1 5 ns ps rms ns 58 3.5 0.001 0 −1.5 16 −1 VREF = 2.5 V VREF = 2.048 V ±0.5 +1.25 0.5 0.6 −10 +10 ±0.5 −8 AVDD = 2.5 V ± 5% VREF = 2.5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.048 V fIN = 100 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.048 V fIN = 100 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.048 V fIN = 100 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz, VREF = 2.048 V fIN = 100 kHz, VREF = 2.5 V Full-scale step PDREF = PDBUF = low REF @ 25°C −40°C to +85°C AVDD = 2.5 V ± 5% Rev. A | Page 3 of 28 91.5 91 89.5 91 89.5 +8 140 2.038 2.048 ±8 ±15 2.058 V ppm/°C ppm/V AD7622 Parameter Turn-On Settling Time REFBUFIN Output Voltage REFBUFIN Output Resistance EXTERNAL REFERENCE Voltage Range Current Drain REFERENCE BUFFER REFBUFIN Input Voltage Range REFBUFIN Input Current TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format7 Pipeline Delay8 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current10 AVDD11 AVDD DVDD OVDD12 Power Dissipation11 With Internal Reference10 Without Internal Reference10 In Power-Down Mode12 TEMPERATURE RANGE13 Specified Performance Conditions CREF = 10 μF REFBUFIN @ 25°C PDREF = PDBUF = high REF 2 MSPS throughput PDREF = high, PDBUF = low REF = 2.048 V typ REFBUFIN = 1.2 V Min Typ 5 1.19 6.33 Max Unit ms V kΩ 1.8 2.5 150 AVDD + 0.1 V μA 1.05 1.2 1 1.30 V nA @ 25°C 278 1 4.7 −0.3 1.7 −1 −1 ISINK = 500 μA ISOURCE = −500 μA mV mV/°C kΩ +0.6 5.25 +1 +1 V V μA μA 0.4 V V 2.63 2.63 3.6 V V V OVDD − 0.3 2.37 2.37 2.309 2 MSPS throughput With internal reference Without internal reference 24 23 2.5 1 2 MSPS throughput 2 MSPS throughput PD = high TMIN to TMAX 70 65 2 −40 1 2.5 2.5 mA mA mA mA 85 80 mW mW μW +85 °C When using an external reference. With the internal reference, the input range is −0.1 V to VREF. See Analog Inputs section. 3 Linearity is tested using endpoints, not best fit. 4 LSB means least significant bit. With the ±2.048 V input range, 1 LSB is 62.5 μV. 5 See Voltage Reference Input section. These specifications do not include the error contribution from the external reference. 6 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 7 Parallel or serial 16-bit. 8 Conversion results are available immediately after completed conversion. 9 See the Absolute Maximum Ratings section. 10 In wideband and warp modes. Tested in parallel reading mode. 11 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high. 12 With all digital inputs forced to OVDD. 13 Consult sales for extended temperature range. 2 Rev. A | Page 4 of 28 AD7622 TIMING SPECIFICATIONS AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter CONVERSION AND RESET (Refer to Figure 32 and Figure 33) Convert Pulse Width Time Between Conversions (Warp Mode2/Normal Mode3) CNVST Low to BUSY High Delay BUSY High All Modes (Except Master Serial Read After Convert) Warp Mode/Normal Mode Aperture Delay End of Conversion to BUSY Low Delay Conversion Time (Warp Mode/Normal Mode) Acquisition Time (Warp Mode/Normal Mode) RESET Pulse Width RESET Low to BUSY High Delay4 BUSY High Time from RESET Low4 PARALLEL INTERFACE MODES (Refer to Figure 34 to Figure 37 ) CNVST Low to Data Valid Delay (Warp Mode/Normal Mode) Data Valid to BUSY Low Delay Bus Access Request to Data Valid Bus Relinquish Time MASTER SERIAL INTERFACE MODES5 (Refer to Figure 38 and Figure 39) CS Low to SYNC Valid Delay CS Low to Internal SCLK Valid Delay5 CS Low to SDOUT Delay CNVST Low to SYNC Delay (Warp Mode/Normal Mode) SYNC Asserted to SCLK First Edge Delay Internal SCLK Period6 Internal SCLK High6 Internal SCLK Low6 SDOUT Valid Setup Time6 SDOUT Valid Hold Time6 SCLK Last Edge to SYNC Delay6 CS High to SYNC HI-Z CS High to Internal SCLK HI-Z CS High to SDOUT HI-Z BUSY High in Master Serial Read After Convert6 CNVST Low to SYNC Asserted Delay (Warp Mode/Normal Mode) SYNC Deasserted to BUSY Low Delay SLAVE SERIAL INTERFACE MODES (Refer to Figure 41 and Figure 42) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK High External SCLK Low See Notes on next page. Rev. A | Page 5 of 28 Symbol Min t1 t2 t3 15 500/667 t4 t5 t6 t7 t8 t9 t38 t39 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 Typ Max Unit 701 ns ns ns 23 360/485 1 10 360/485 140/182 15 10 500 360/485 2 20 15 2 10 10 10 15/135 2 8 2 3 1 0 0 20 10 10 10 See Table 4 375/500 13 5 1 5 5 12.5 5 5 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns AD7622 1 See the Conversion Control section. All timings for wideband warp mode are the same as warp mode. 3 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 4 See the Digital Interface section and the RESET section. 5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications. 2 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK High Minimum Internal SCLK Low Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum BUSY High Width Maximum Warp Mode Normal Mode 500µA 0 0 3 8 20 2 2 1 0 0 0 1 3 16 40 8 8 5 0.5 0.5 1 0 3 32 60 16 16 15 10 9 1 1 3 64 140 32 32 5 28 26 Unit ns ns ns ns ns ns ns ns t28 t28 0.64 0.76 0.92 1.04 1.47 1.59 2.57 2.69 μs μs IOL 1.4V CL 50pF 2V IOH NOTE IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. tDELAY tDELAY 2V 0.8V 2V 0.8V Figure 4. Voltage Reference Levels for Timing Figure 3. Load Circuit for Digital Interface Timing, SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. A | Page 6 of 28 06023-003 500µA 0.8V 06023-002 TO OUTPUT PIN Symbol t18 t19 t19 t20 t21 t22 t23 t24 AD7622 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs/Outputs IN+1, IN−, REF, REFBUFIN, TEMP, INGND, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD OVDD AVDD to DVDD AVDD, DVDD to OVDD Digital Inputs PDREF, PDBUF2 Internal Power Dissipation3 Internal Power Dissipation4 Junction Temperature Storage Temperature Range Rating AVDD + 0.3 V to AGND − 0.3 V ±0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −0.3 V to +2.7 V −0.3 V to +3.8 V ±2.8 V −3.8 V to +2.8 V −0.3 V to +5.5 V ±20 mA 700 mW 2.5 W 125°C –65°C to +125°C 1 See Analog Inputs section. See Voltage Reference Input section. Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W. 4 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. 2 3 ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 7 of 28 AD7622 30 DGND 29 BUSY D0 9 28 D15 27 D14 D1 10 D2/DIVSCLK[0] 11 26 D13 25 D12 SER/PAR 8 REFGND REF AGND NC IN– 30 DGND 29 BUSY D0 9 D1 10 28 D15 D2/DIVSCLK[0] 11 D3/DIVSCLK[1] 12 26 D13 NC = NO CONNECT 27 D14 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 06023-050 D11/RDERROR 24 D10/SYNC 23 D9/SCLK 22 D8/SDOUT 21 DGND 20 DVDD 19 OVDD 18 OGND 17 D7/RDC/SDIN 16 D6/INVSCLK 15 D4/EXT/INT 13 NC = NO CONNECT D5/INVSYNC 14 D3/DIVSCLK[1] 12 31 RD TOP VIEW (Not to Scale) 06023-004 NORMAL 7 SER/PAR 8 32 CS AD7622 WARP 6 NORMAL 7 D11/RDERROR 31 RD TOP VIEW (Not to Scale) 33 RESET OB/2C 5 D9/SCLK D10/SYNC AD7622 34 PD DVDD DGND D8/SDOUT 33 RESET 32 CS 35 CNVST DGND 3 BYTESWAP 4 OVDD 34 PD 36 AGND PIN 1 IDENTIFIER D7/RDC/SDIN OGND DGND 3 AGND 1 AVDD 2 D4/EXT/INT D5/INVSYNC D6/INVSCLK 36 AGND 35 CNVST OB/2C 5 WARP 6 IN+ AGND 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 AVDD 2 BYTESWAP 4 AVDD PDBUF PDREF REFBUFIN TEMP 37 REF 38 REFGND 39 IN– 40 NC 41 AGND 42 AGND 43 IN+ 44 AVDD 45 TEMP 46 REFBUFIN 47 PDREF 48 PDBUF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. 48-Lead LFCSP Pin Configuration Figure 6. 48-Lead LQFP Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 36, 41, 42 2, 44 3 4 Mnemonic AGND Type1 P Description Analog Power Ground. AVDD DGND BYTESWAP P P DI 5 OB/2C DI 6 WARP DI 7 NORMAL DI 8 SER/PAR DI/O 9, 10 D[0:1] DO 11, 12 D[2:3] or DIVSCLK[0:1] DI/O Input Analog Power Pins. Nominally 2.5 V. Digital Power Ground. Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. Conversion Mode Selection. When WARP = high and NORMAL = high, this selects wideband warp mode with slightly improved linearity and THD. When WARP = high and NORMAL = low, this selects warp mode. In either mode, these are the fastest modes; maximum throughput is achievable, and a minimum conversion rate must be applied to guarantee full specified accuracy. Conversion Mode Selection. When NORMAL = low and WARP = low, this input selects normal mode where full accuracy is maintained independent of the minimum conversion rate. Serial/Parallel Selection Input. When SER/PAR = high, the serial interface is selected and some bits of the data bus are used as a serial port; the remaining data bits are high impedance outputs. When SER/PAR = low, the parallel port is selected. Bit 0 and Bit 1 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of the interface mode. When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. When SER/PAR = high, serial clock division selection. When using serial master read after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. Rev. A | Page 8 of 28 AD7622 Pin No. 13 Mnemonic D4 or EXT/INT Type1 DI/O 14 D5 or INVSYNC DI/O 15 D6 or INVSCLK DI/O 16 D7 or RDC DI/O or SDIN 17 18 OGND OVDD P P 19 20 21 DVDD DGND D8 or SDOUT P P DO 22 D9 or SCLK DI/O 23 D10 or SYNC DO Description When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus. When SER/PAR = high, serial clock source select. This input is used to select the internally generated (master) or external (slave) serial data clock. When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output. When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated by CS, connected to the SCLK input. When SER/PAR = low, this output is used as Bit 5 of the parallel port data output bus. When SER/PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. When SER/PAR = low, this output is used as Bit 6 of the parallel port data output bus. When SER/PAR] = high, invert SCLK select. In all serial modes, this input is used to invert the SCLK signal. When SER/PAR = low, this output is used as bit 7 of the parallel port data output bus. When SER/PAR = high, read during convert. When using serial master mode (EXT/INT = low), RDC is used to select the read mode. When RDC = high, the previous conversion result is output on SDOUT during conversion and the period of SCLK changes (see the Master Serial Interface section). When RDC = low (read after convert), the current result can be output on SDOUT only when the conversion is complete. When SER/PAR = low, serial data in. When using serial slave mode, (EXT/INT = high), SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read sequence. If not used, connect to OVDD or OGND. Input/Output Interface Digital Power Ground. Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (2.5 V or 3 V). Digital Power. Nominally at 2.5 V. Digital Power Ground. When SER/PAR = low, this output is used as Bit 8 of the parallel port data output bus. When SER/PAR = high, serial data output. In serial mode, this pin is used as the serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7622 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In master mode, EXT/INT = low, SDOUT is valid on both edges of SCLK. In slave mode, EXT/INT = high: When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. 2 When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.2 When SER/PAR = low, this output is used as Bit 9 of the parallel port data output bus. When SER/PAR = high, serial clock. In all serial modes, this pin is used as the serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated, depends on the logic state of the INVSCLK pin. When SER/PAR = low, this output is used as Bit 10 of the parallel port data output bus. When SER/PAR = high, frame synchronization. In serial master mode (EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid. Rev. A | Page 9 of 28 AD7622 Pin No. 24 Mnemonic D11 or RDERROR Type1 DO 25 to 28 29 D[12:15] DO BUSY DO 30 31 DGND RD P DI 32 CS DI 33 RESET DI 34 PD DI 35 CNVST DI 37 REF AI/O 38 39 40 43 45 REFGND IN− NC IN+ TEMP AI AI 46 REFBUFIN AI/O 47 PDREF DI 48 PDBUF DI 1 2 AI AO Description When SER/PAR = low, this output is used as Bit 11 of the parallel port data output bus. When SER/PAR = high, read error. In serial slave mode (EXT/INT = high), this output is used as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 12 to Bit 15 of the parallel port data output bus. These pins are always outputs, regardless of the interface mode. Busy Output. Transitions high when a conversion is started and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data-ready clock signal. Digital Power Ground. Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode. Reset Input. When high, resets the AD7622. Current conversion, if any, is aborted. Falling edge of RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the RESET section. If not used, this pin can be tied to DGND. Power-Down Input. When high, power downs the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. Reference Output/Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal reference and buffer. Refer to the Voltage Reference Input section. Reference Input Analog Ground. Differential Negative Analog Input. No Connect. Differential Positive Analog Input. Temperature Sensor Analog Output. Normally, 278 mV @ 25°C with a temperature coefficient of 1 mV/°C. This pin can be used to measure the temperature of the AD7622. See the Temperature Sensor section. Internal Reference Output/Reference Buffer Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical) band gap output on this pin, which needs external decoupling. The internal fixed gain reference buffer uses this to produce 2.048 V on the REF pin. When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high), applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section. Internal Reference Power-Down Input. When low, the internal reference is enabled. When high, the internal reference is powered down and an external reference must been used. Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (must be low when using internal reference). When high, the buffer is powered-down. AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. With an SCLK period ≥ (2 × t32). With an SCLK period < (2 × t32), SDOUT is valid on the next rising edge with INVSCLK = low and next falling edge with INVSCLK = high. Rev. A | Page 10 of 28 AD7622 TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Gain Error The first transition (from 000…00 to 000…01) should occur for an analog voltage ½ LSB above the nominal negative full scale (−2.0479688 V for the ±2.048 V range). The last transition (from 111…10 to 111…11) should occur for an analog voltage 1½ LSB below the nominal full scale (+2.0479531 V for the ±2.048 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Signal to (Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by ENOB = [(SINADdB − 1.76)/6.02] Aperture Delay Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Zero Error The zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Transient Response The time required for the AD7622 to achieve its rated accuracy after a full-scale step function is applied to its input. Dynamic Range It is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. It is derived from the typical shift of output voltage at 25°C on a sample of parts maximum and minimum reference output voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C using Reference Voltage Temperature Coefficient Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. TCVREF ppm/C   VREF  Max   VREF  Min  106 VREF 25C   TMAX  TMIN  where: VREF (Max) = Maximum VREF at TMIN, T(25°C), or TMAX VREF (Min) = Minimum VREF at TMIN, T(25°C), or TMAX VREF (25°C) = VREF at 25°C TMAX = +85°C TMIN = –40°C Rev. A | Page 11 of 28 AD7622 TYPICAL PERFORMANCE CHARACTERISTICS 1.50 1.25 POSITIVE INL = +0.43 LSB NEGATIVE INL = –0.49 LSB 1.00 1.00 0.75 0.50 DNL (LSB) INL (LSB) 0.50 0 –0.50 0.25 0 –0.25 –0.50 0 16384 32768 49152 –0.75 –1.00 65536 06023-008 –1.50 06023-005 –1.00 0 16384 32768 CODE Figure 7. Integral Nonlinearity vs. Code 65536 Figure 10. Differential Nonlinearity vs. Code 250000 200000 σ = 0.5 VREF = 2.5V σ = 0.5 VREF = 2.048V 171449 196433 200000 160000 150000 120000 COUNTS COUNTS 49152 CODE 100000 80000 50640 44 0 76 0 0 7FF8 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF CODES IN HEX 0 8000 2.0484 3 ZERO ERROR, GAIN ERROR (LSB) 4 2.0482 VREF (V) 2.0480 2.0478 2.0476 2.0474 06023-007 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 784 0 457 1 0 8000 Figure 11. Histogram of 261,120 Conversions of a DC Input at the Code Center (Internal Reference) 2.0486 2.0472 0 7FF8 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF CODES IN HEX Figure 8. Histogram of 261,120 Conversions of a DC Input at the Code Center (External Reference) 2.0470 –55 37789 40000 06023-009 0 36872 125 Figure 9. Typical Reference Voltage Output vs. Temperature (2 Units) Rev. A | Page 12 of 28 GAIN ERROR 2 1 ZERO ERROR 0 –1 –2 –3 –4 –55 06023-010 0 27695 06023-006 50000 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 Figure 12. Zero Error, Gain Error vs. Temperature 105 125 AD7622 0 0 fS = 2MSPS fIN = 20.1kHz –80 –100 –120 –140 100 200 300 400 500 600 700 800 900 –120 –140 06023-014 –180 1000 0 100 200 FREQUENCY (kHz) 15.2 89 14.8 SINAD 14.4 ENOB 14.0 SNR 13.6 81 13.2 79 12.8 77 12.4 1 10 12.0 1000 100 –70 –80 15.5 91 SINAD 15.0 90 ENOB 89 14.5 88 87 86 –55 –35 –15 60 50 THD, HARMONICS (dB) 70 –120 40 1 SECOND HARMONIC 10 100 14.0 125 120 –90 SFDR (dB) 80 –110 105 110 90 THD 85 –80 30 20 1000 FREQUENCY (kHz) 110 SFDR –100 100 THD –110 90 –120 80 –130 06023-013 THD, HARMONICS (dB) –90 5 25 45 65 TEMPERATURE (°C) Figure 17. SNR, SINAD, and ENOB vs. Temperature 100 –140 1000 SNR 120 SFDR THIRD HARMONIC 900 92 FREQUENCY (kHz) –130 800 16.0 Figure 14. SNR, SINAD, and ENOB vs. Frequency –100 700 93 SNR, SINAD (dB) 15.6 91 ENOB (Bits) 93 75 600 94 06023-012 SNR, SINAD (dB) 16.0 83 500 Figure 16. FFT 100 kHz 95 85 400 FREQUENCY (kHz) Figure 13. FFT 20 kHz 87 300 ENOB (Bits) 0 –100 06023-015 –180 –80 –160 06023-011 –160 –60 SECOND HARMONIC –140 –55 –35 –15 70 THIRD HARMONIC 5 25 45 65 TEMPERATURE (°C) 85 105 Figure 18. THD, Harmonics, and SFDR vs. Temperature Figure 15. THD, Harmonics, and SFDR vs. Frequency Rev. A | Page 13 of 28 SFDR (dB) –60 –40 60 125 06023-016 –40 fS = 2MSPS fIN =100.7kHz SNR = 91dB THD = –100dB SFDR = 101dB SINAD = 90.5dB –20 SNR = 92dB THD = –117dB SFDR = 103dB SINAD = 92dB AMPLITUDE (dB of Full Scale) AMPLITUDE (dB of Full Scale) –20 AD7622 100k AVDD 10k OPERATING CURRENTS (µA) SINAD 92.0 91.5 91.0 –60 –50 –40 –30 –20 –10 0 1k DVDD 100 OVDD = 3.3V, ALL MODES 10 1 OVDD = 2.5V, ALL MODES 0.1 0.01 10 PDREF = PDBUF = HIGH 100 1k INPUT LEVEL (dB) 100k 10M 1M SAMPLING RATE (SPS) Figure 19. SNR and SINAD vs. Input Level (Referred to Full Scale) Figure 21. Operating Currents vs. Sample Rate 16 20 14 18 12 16 OVDD = 2.5V @ 85°C t12 DELAY (ns) OVDD = 2.5V @ 25°C 10 DVDD 8 OVDD, 3.3V 6 14 12 10 OVDD = 3.3V @ 25°C OVDD, 2.5V 8 2 6 AVDD 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 20. Power-Down Operating Currents vs. Temperature 4 OVDD = 3.3V @ 85°C 4 50 100 150 200 CL (pF) Figure 22. Typical Delay vs. Load Capacitance CL Rev. A | Page 14 of 28 06023-020 4 06023-018 OPERATING CURRENTS (µA) 10k 06023-019 SNR 92.5 06023-017 SNR, SINAD REFERRED TO FULL SCALE (dB) 93.0 AD7622 APPLICATIONS INFORMATION IN+ AGND LSB MSB 32,768C 16,384C 4C 2C C SW+ SWITCHES CONTROL C BUSY REF COMP REFGND 32,768C 16,384C 4C 2C MSB C CONTROL LOGIC OUTPUT CODE C SW– LSB CNVST 06023-021 AGND IN– Figure 23. ADC Simplified Schematic CIRCUIT INFORMATION The AD7622 is a very fast, low power, single-supply, precise 16-bit ADC using successive approximation architecture. The AD7622 features different modes to optimize performances according to the applications. In warp mode, the AD7622 is capable of converting 2,000,000 samples per second (2 MSPS). The AD7622 provides the user with an on-chip track-and-hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7622 can operate from a single 2.5 V supply and interface to either 5 V, 3.3 V, or 2.5 V digital logic. It is housed in a 48-lead LQFP package or a tiny 48-lead LFCSP package, which combines space savings with flexibility and allows the AD7622 to be configured as either a serial or a parallel interface. The AD7622 is pin-to-pin compatible with other PulSAR ADC’s and is a speed upgrade of the AD7677. CONVERTER OPERATION The AD7622 is a successive approximation ADC based on a charge redistribution DAC. Figure 23 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors that are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to AGND via SW+ and SW−. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. A conversion phase is initiated once the acquisition phase is complete and the CNVST input goes low. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the inputs (IN+ and IN−) captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 throughVREF/65536). The control logic toggles these switches, starting with the MSB first, to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings BUSY output low. MODES OF OPERATION The AD7622 features three modes of operations: wideband warp, warp, and normal. Each of these modes is more suitable for specific applications. The wideband warp (WARP = high, NORMAL = high) and warp (WARP = high, NORMAL = low) modes allow the fastest conversion rate of up to 2 MSPS. However, in these modes, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms (for instance after power-up), the first conversion result should be ignored. These modes make the AD7622 ideal for applications where both high accuracy and fast sample rates are required. Wideband warp mode offers slightly improved linearity and THD over warp mode. Normal mode (NORMAL = low, WARP = low) is the fastest mode (1.5 MSPS) without any limitation on time between conversions. This mode makes the AD7622 ideal for asynchronous applications, such as data acquisition systems, where both high accuracy and fast sample rates are required. Rev. A | Page 15 of 28 AD7622 TRANSFER FUNCTIONS Table 7. Output Codes and Ideal Input Voltages Description FSR −1 LSB FSR − 2 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR 111...111 111...110 111...101 1 000...010 000...001 000...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB 2 Digital Output Code (Hex) Straight Twos Binary Complement 1 0xFFFF 0x7FFF1 0xFFFE 0x7FFE 0x8001 0x0001 0x8000 0x0000 0x7FFF 0xFFFF 0x0001 0x8001 0x00002 0x80002 Analog Input VREF = 2.048 V +2.047938 V +2.047875 V +62.5 μV 0V −62.5 μV −2.047938 V −2.048 V This is also the code for overrange analog input (VIN+ − VIN− above +VREF − VREFGND). This is also the code for underrange analog input (VIN+ − VIN− below −VREF + VREFGND). +FSR – 1 LSB 06023-022 ADC CODE (Straight Binary) Using the OB/2C digital input, the AD7622 offers two output codings: straight binary and twos complement. The LSB size with VREF = 2.048 V is 2 × VREF/ 65536 which is 62.5 μV. Refer to Figure 24 and Table 7 for the ideal transfer characteristic. +FSR – 1.5 LSB ANALOG INPUT Figure 24. ADC Ideal Transfer Function DIGITAL SUPPLY (2.5V) NOTE 5 DIGITAL INTERFACE SUPPLY (2.5V OR 3.3V) 10Ω ANALOG SUPPLY (2.5V) 100nF 10µF 10µF AVDD REF CREF 10µF 100nF AGND 100nF 10µF 100nF DGND DVDD OVDD NOTE 3 OGND SERIAL PORT SCLK REFBUFIN SDOUT REFGND NOTE 4 BUSY NOTE 2 ANALOG INPUT + U1 15Ω CNVST IN+ 2.7nF MICROCONVERTER/ MICROPROCESSOR/ DSP NOTE 7 D 50pF AD7622 CC 50Ω OB/2C NOTE 1 SER/PAR OVDD WARP NORMAL NOTE 2 ANALOG INPUT – U2 CC 15Ω 2.7nF NOTE 1 CS IN– CLOCK RD NOTE 3 PD PDREF PDBUF RESET 50pF 10kΩ 1. SEE ANALOG INPUTS SECTION. 2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION. 4. A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (FOR EXAMPLE, PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTION, SEE POWER-UP SECTION. 7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. Figure 25. Typical Connection Diagram Rev. A | Page 16 of 28 06023-023 NOTE 6 AD7622 TYPICAL CONNECTION DIAGRAM Figure 25 shows a typical connection diagram for the AD7622. Different circuitry shown in this diagram is optional and is discussed in the following sections. ANALOG INPUTS Figure 26 shows an equivalent circuit of the input structure of the AD7622. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V, because this causes the diodes to become forwardbiased and to start conducting current. These diodes can handle a forward-biased current of 100 mA maximum. For instance, these conditions could eventually occur when the input buffer’s U1 or U2 supplies are different from AVDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. AVDD D1 RIN IN+ OR IN– Because the input impedance of the AD7622 is very high, the AD7622 can be directly driven by a low impedance source without gain error. To further improve the noise filtering achieved by the AD7622’s analog input circuit, an external 1-pole RC filter between the amplifier’s outputs and the ADC analog inputs can be used, as shown in Figure 25. However, large source impedances significantly affect the ac performance, especially the total harmonic distortion (THD). The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency, as shown in Figure 28. CIN –60 –65 D2 RS = 500Ω 06023-024 CPIN comprised of some serial resistors and the on resistance of the switches. CIN is typically 12 pF and is mainly the ADC sampling capacitor. During the conversion phase, when the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that has a typical −3 dB cutoff frequency of 50 MHz, thereby reducing an undesirable aliasing effect and limiting the noise coming from the inputs. AGND –70 –75 The analog input of the AD7622 is a true differential structure. By using this differential input, small signals common to both inputs are rejected, as shown in Figure 27, representing the typical CMRR over frequency with internal and external references. THD (dB) Figure 26. AD7622 Simplified Analog Input –80 RS = 100Ω –85 RS = 50Ω –90 –95 RS = 15Ω –100 –105 70 1 10 100 1000 INPUT FREQUENCY (kHz) EXT REF 06023-026 75 Figure 28. THD vs. Analog Input Frequency and Source Resistance CMRR (dB) 65 MULTIPLEXED INPUTS INT REF 60 55 45 1 10 100 1000 FREQUENCY (kHz) 10000 06023-025 50 Figure 27. Analog Input CMRR vs. Frequency During the acquisition phase for ac signals, the impedance of the analog inputs, IN+ and IN−, can be modeled as a parallel combination of capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 175 Ω and is a lumped component When using the full 2 MSPS throughput in multiplexed applications for a full-scale step, the RC filter, as shown in Figure 25, does not settle in the required acquisition time, t8. These values are chosen to optimize the best SNR performance of the AD7622. To use the full 2 MSPS throughput in multiplexed applications, the RC should be adjusted to satisfy t8 (which is ~ 7 × RC time constant). However, lowering R and C increases the RC filter bandwidth and allows more noise into the AD7622, which degrades SNR. To preserve the SNR performance in these applications using the RC filter shown in Figure 25, the AD7622 should be run with t8 > 280 ns; or approximately 1/(t7 + t8) ~ 1.55 MSPS in wideband and warp modes. Rev. A | Page 17 of 28 AD7622 Although the AD7622 is easy to drive, the driver amplifier needs to meet the following requirements:   For multichannel, multiplexed applications, the driver amplifier and the AD7622 analog input circuit must be able to settle for a full-scale step of the capacitor array at an 16-bit level (0.0015%). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. The AD8021 op amp, which combines ultralow noise and high gain bandwidth, meets this settling time requirement even when used with gains up to 13. The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7622. The noise coming from the driver is filtered by the AD7622 analog input circuit 1-pole, low-pass filter made by RIN and CIN or by the external filter, if one is used. The SNR degradation due to the amplifier is SNRLOSS   45   20log  πf πf  452  3dB Ne N  2  3dB Ne N  2 2 2        where: f–3dB is the input bandwidth of the AD7622 (50 MHz) or the cutoff frequency of the input RC filter shown in Figure 25 (3.9 MHz), if one is used. N is the noise factor of the amplifier (1 in buffer configuration). eN+ and eN− are the equivalent input voltage noise densities of the op amps connected to IN+ and IN−, in nV/√Hz. This approximation can be used when the resistances used around the amplifier are small. If larger resistances are used, their noise contributions should also be root-sum squared. The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an NPO ceramic or mica type. Moreover, the use of a noninverting 1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. The AD8022 can also be used when a dual version is needed and a gain of 1 is present. The AD829 is an alternative in applications where high frequency (above 100 kHz) performance is not required. In applications with a gain of 1, an 82 pF compensation capacitor is required. The AD8610 is an option when low bias current is needed in low frequency applications. Refer to Table 8 for some recommended op amps. Table 8. Recommended Driver Amplifiers Amplifier ADA4841-x AD829 AD8021 AD8022 AD8610/AD8620 Single-to-Differential Driver For applications using unipolar analog signals, a single-endedto-differential driver, as shown in Figure 29, allows for a differential input into the part. This configuration, when provided an input signal of 0 to VREF, produces a differential ±VREF with midscale at VREF/2. The 1-pole filter using R = 15 Ω and C = 2.7nF provides a corner frequency of 3.9 MHz. If the application can tolerate more noise, the AD8139 differential driver can be used. U1 ANALOG INPUT (UNIPOLAR 0V TO 2.048V) For instance, when using op amps with an equivalent input noise density of 2.1 nV/√Hz, such as the AD8021, with a noise gain of 1 when configured as a buffer, degrades the SNR by only 0.1 dB when using the RC filter in Figure 25, and by 1.3 dB without it.  Typical Application Very low noise, low distortion, low power, low frequency Very low noise, low frequency Very low noise, high frequency Very low noise, high frequency, dual Low bias current, low frequency, single/dual The driver needs to have a THD performance suitable to that of the AD7622. Figure 15 gives the THD vs. frequency that the driver should exceed. Rev. A | Page 18 of 28 590Ω 15Ω 590Ω 2.7nF 15Ω U2 5kΩ 5kΩ AD8021 10pF AD8021 100nF IN+ AD7622 IN– REF 2.7nF 10pF 10µF Figure 29. Single-Ended-to-Differential Driver Circuit (Internal Reference Buffer Used) 06023-041 DRIVER AMPLIFIER CHOICE AD7622 VOLTAGE REFERENCE INPUT The advantages of directly using the external voltage reference are: The AD7622 allows the choice of either a very low temperature drift internal voltage reference, an external 1.2 V reference that can be buffered using the internal reference buffer, or an external reference.  Unlike many ADCs with internal references, the internal reference of the AD7622 provides excellent performance and can be used in almost all applications. 2.048  SNR  20 log    2.50   Internal Reference (PDBUF = Low, PDREF = Low) To use the internal reference, the PDREF and PDBUF inputs must both be low. This produces a 1.2 V band gap output on REFBUFIN, which is amplified by the internal buffer and results in a 2.048 V reference on the REF pin. The internal reference is temperature compensated to 2.048 V ± 10 mV. The reference is trimmed to provide a typical drift of 8 ppm/°C. This typical drift characteristic is shown in Figure 9. The output resistance of REFBUFIN is 6.33 kΩ (minimum) when the internal reference is enabled. It is necessary to decouple this with a ceramic capacitor greater than 100 nF. Therefore, the capacitor provides an RC filter for noise reduction. Because the output impedance of REFBUFIN is typically 6.33 kΩ, relative humidity (among other industrial contaminates) can directly affect the drift characteristics of the reference. Typically, a guard ring is used to reduce the effects of drift under such circumstances. However, because the AD7622 has a fine lead pitch, guarding this node is not practical. Therefore, in these industrial and other types of applications, it is recommended to use a conformal coating, such as Dow Corning® 1-2577 or HumiSeal® 1B73. External 1.2 V Reference and Internal Buffer (PDBUF = Low, PDREF = High) To use an external reference along with the internal buffer, PDREF should be high and PDBUF should be low. This powers down the internal reference and allows an external 1.2 V reference to be applied to REFBUFIN, producing 2.048 V (typically) on the REF pin. External 2.5 V Reference (PDBUF = High, PDREF = High) To use an external 2.5 V reference directly on the REF pin, PDREF and PDBUF should both be high. For improved drift performance, an external reference, such as the AD780, ADR421, ADR431, or ADR441, can be used. The SNR and dynamic range improvement (about 1.7 dB) resulting from the use of a reference voltage very close to the supply (2.5 V) instead of a typical 2.048 V reference when the internal reference is used. This is calculated by The power savings when the internal reference is powered down (PDREF high). PDREF and PDBUF power down the internal reference and the internal reference buffer, respectively. The input current of PDREF and PDBUF should never exceed 20 mA. This can occur when the driving voltage is above AVDD (for instance, at power-up). In this case, a 125 Ω series resistor is recommended. Reference Decoupling Whether using an internal or external reference, the AD7622 voltage reference input (REF) has a dynamic input impedance; therefore, it should be driven by a low impedance source with efficient decoupling between the REF and REFGND inputs. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and REFGND with minimum parasitic inductance. A 10 μF (X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum capacitor) is appropriate when using either the internal reference or one of the recommended reference voltages. The placement of the reference decoupling is also important to the performance of the AD7622. The decoupling capacitor should be mounted on the same side as the ADC right at the REF pin with a thick PCB trace. The REFGND should also connect to the reference decoupling capacitor with the shortest distance. For applications that use multiple AD7622 devices, it is more effective to use an external reference with the internal reference buffer to buffer the reference voltage. However, because the reference buffers are not unity gain, ratiometric, simultaneously sampled designs should use an external reference and external buffer, such as the AD8031/AD8032; therefore, preserving the same reference level for all converters. The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a ±15 ppm/°C TC of the reference changes full scale by ±1 LSB/°C. Note that VREF can be increased to AVDD + 0.1 V. Because the input range is defined in terms of VREF, this would essentially increase the range to 0 V to 2.8 V with an AVDD = 2.7 V. Rev. A | Page 19 of 28 AD7622 Temperature Sensor The TEMP pin measures the temperature of the AD7622. To improve the calibration accuracy over the temperature range, the output of the TEMP pin is applied to one of the inputs of the analog switch (such as, ADG779), and the ADC itself is used to measure its own temperature. This configuration is shown in Figure 30. TEMP TEMPERATURE SENSOR IN+ ANALOG INPUT (UNIPOLAR) AD8021 06023-027 ADG779 AD7622 CC Figure 30. Use of the Temperature Sensor POWER SUPPLY The AD7622 uses three sets of power supply pins: an analog 2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.3 V and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 25. A simple power-on reset circuit, as shown in Figure 25, can be used to minimize the digital interface. As OVDD powers up, the capacitor is shorted and brings RESET high; it is then charged returning RESET to low. However, this circuit only works when powering up the AD7622 because the power-down mode (PD = high) does not power down any of the supplies and as a result, RESET is low. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, drive the digital inputs close to the power rails (that is, OVDD and OGND). CONVERSION CONTROL The AD7622 is controlled by the CNVST input. A falling edge on CNVST is all that is necessary to initiate a conversion. Detailed timing diagrams of the conversion process are shown in Figure 32. Once initiated, it cannot be restarted or aborted, even by the power-down input, PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. t2 t1 CNVST The AD7622 is independent of power supply sequencing and thus free from supply induced voltage latch-up. In addition, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 31. 65.0 BUSY t6 t5 MODE ACQUIRE CONVERT t7 62.5 ACQUIRE CONVERT t8 Figure 32. Basic Conversion Timing 60.0 PSRR (dB) t4 t3 06023-030 Power Sequencing EXT REF For optimal performance, the rising edge of CNVST should not occur after the maximum CNVST low time, t1, or until the end of conversion. 57.5 55.0 INT REF 52.5 Although CNVST is a digital signal, it should be designed with special care with fast, clean edges and levels with minimum overshoot and undershoot or ringing. 50.0 45.0 1 10 100 1000 FREQUENCY (kHz) 10000 06023-029 47.5 Figure 31. PSRR vs. Frequency Power-Up At power-up, or when returning to operational mode from the power-down mode (PD = high), the AD7622 engages an initialization process. During this time, the first 128 conversions should be ignored or the RESET input could be pulsed to engage a faster initialization process. Refer to the Digital Interface section for RESET and timing details. The CNVST trace should be shielded with ground and a low value serial resistor (for example, 50 Ω) termination should be added close to the output of the component that drives this line. In addition, a 50 pF capacitor is recommended to further reduce the effects of overshoot and undershoot as shown in Figure 25. For applications where SNR is critical, the CNVST signal should have very low jitter. This can be achieved by using a dedicated oscillator for CNVST generation, or by clocking CNVST with a high frequency, low jitter clock, as shown in Figure 25. Rev. A | Page 20 of 28 AD7622 INTERFACES DIGITAL INTERFACE CS = RD = 0 The AD7622 has a versatile digital interface that can be set up as either a serial or a parallel interface with the host system. The serial interface is multiplexed on the parallel data bus. The AD7622 digital interface also accommodates 2.5 V, 3.3 V, or 5 V logic with either OVDD at 2.5 V or 3.3 V. OVDD defines the logic high output voltage. In most applications, the OVDD supply pin of the AD7622 is connected to the host system interface 2.5 V or 3.3 V digital supply. By using the OB/2C input pin, either twos complement or straight binary coding can be used. CNVST The two signals CS and RD control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7622 in multicircuit applications and is held low in a single AD7622 design. RD is generally used to enable the conversion result on the data bus. RESET The RESET input is used to reset the AD7622 and generate a fast initialization. A rising edge on RESET aborts the current conversion (if any) and tristates the data bus. The falling edge of RESET clears the data bus and engages the initialization process indicated by pulsing BUSY high. Conversions can take place after the falling edge of BUSY. Refer to Figure 33 for the RESET timing details. t1 t10 BUSY t4 t3 DATA BUS PREVIOUS CONVERSION DATA 04761-032 t11 NEW DATA Figure 34. Master Parallel Data Timing for Reading (Continuous Read) Slave Parallel Interface In slave parallel reading mode, the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 35 and Figure 36, respectively. When the data is read during the conversion, it is recommended that it is read-only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. CS RD t9 BUSY CNVST DATA BUS DATA CURRENT CONVERSION t12 04761-033 RESET t13 Figure 35. Slave Parallel Data Timing for Reading (Read After Convert) t38 t39 06023-031 BUSY t8 CS = 0 Figure 33. RESET Timing t1 CNVST, RD PARALLEL INTERFACE The AD7622 is configured to use the parallel interface when SER/PAR is held low. BUSY Data can be continuously read by tying CS and RD low, thus requiring minimal microprocessor connections. However, in this mode, the data bus is always driven and cannot be used in shared bus applications, unless the device is held in RESET. Figure 34 details the timing for this mode. t4 t3 DATA BUS PREVIOUS CONVERSION t12 t13 Figure 36. Slave Parallel Data Timing for Reading (Read During Convert) Rev. A | Page 21 of 28 06023-042 Master Parallel Interface AD7622 8-Bit Interface (Master or Slave) MASTER SERIAL INTERFACE The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 37, when BYTESWAP is low, the LSB byte is output on D[7:0] and the MSB is output on D[15:8]. When BYTESWAP is high, the LSB and MSB bytes are swapped, and the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16-bit data can be read in two bytes on either D[15:8] or D[7:0]. This interface can be used in both master and slave parallel reading modes. Internal Clock Usually, because the AD7622 is used with a fast throughput, the master read during conversion mode, RDC/SDIN = high, is the most recommended serial mode. In this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions. In this mode, the SCLK period changes because the LSBs require more time to settle and the SCLK is derived from the SAR conversion cycle. CS RD BYTESWAP HI-Z HIGH BYTE t12 PINS D[7:0] HI-Z LOW BYTE LOW BYTE t12 HI-Z t13 HIGH BYTE 06023-034 PINS D[15:8] The AD7622 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin = low. The AD7622 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted. Depending on the state of the read during convert input, RDC/SDIN, the data can be read after each conversion or during the following conversion. Figure 38 and Figure 39 show detailed timing diagrams of these two modes. HI-Z Figure 37. 8-Bit and 16-Bit Parallel Interface SERIAL INTERFACE The AD7622 is configured to use the serial interface when SER/PAR = high. The AD7622 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock. In read after conversion mode, RDC/SDIN = low, it should be noted that unlike other modes, the BUSY signal returns low after the 16 data bits are pulsed out and not at the end of the conversion phase, resulting in a longer BUSY width. As a result, the maximum throughput cannot be achieved in this mode. In addition, in read after convert mode, the SCLK frequency can be slowed down to accommodate different hosts using the DIVSCLK[1:0] inputs. Refer to Table 4 for the SCLK timing details when using these inputs. Rev. A | Page 22 of 28 AD7622 RDC/SDIN = 0 EXT/INT = 0 INVSCLK = INVSYNC = 0 CS, RD t3 CNVST t28 BUSY t30 t29 t25 SYNC t18 t19 t14 t20 1 2 D15 D14 SCLK t24 t21 3 14 15 D2 D1 t26 16 t15 t27 X t16 D0 06023-035 SDOUT t23 t22 Figure 38. Master Serial Data Timing for Reading (Read After Convert) RDC/SDIN = 1 EXT/INT = 0 INVSCLK = INVSYNC = 0 CS, RD t1 CNVST t3 BUSY t17 t25 SYNC t19 t20 t21 t14 SCLK t15 1 t24 2 3 14 15 t18 t16 X t22 t27 D15 D14 D2 D1 D0 06023-036 SDOUT t26 16 t23 Figure 39. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. A | Page 23 of 28 AD7622 SLAVE SERIAL INTERFACE The AD7622 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or a discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 41 and Figure 42 show the detailed timing diagrams of these methods. While the AD7622 is performing a bit decision, it is important that voltage transients be avoided on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7622 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, a discontinuous clock is toggled only when BUSY is low or, more importantly, that it does not transition during the latter half of BUSY high. External Discontinuous Clock Data Read After Conversion Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 41 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the conversion result can be read while both CS and RD are low. Data is shifted out MSB first with 16 clock pulses and is valid on the rising and falling edges of the clock. Among the advantages of this method is the fact that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is the ability to read the data at any speed up to 80 MHz, which accommodates both the slow digital host interface and the fast serial reading. It is also possible to begin to read data after conversion and continue to read the last bits after a new conversion is initiated. In this reading mode, it is recommended to pause digital activity just prior to initiating a conversion (SCLK should be held high or low). Once the conversion has begun, the reading can continue. In addition, in this mode, the use of a slower clock speed can be used to read the data because the total reading time is the acquisition time, t8 + half of the conversion time, t7 (t8 + ½ × t7, see the External Clock Data Read During Previous Conversion section). Finally, in this mode only, the AD7622 provides a daisy-chain feature using the RDC/SDIN pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when desired, as, for instance, in isolated multiconverter applications. An example of the concatenation of two devices is shown in Figure 40. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the edge of SCLK opposite to the one used to shift out the data on SDOUT. Therefore, the MSB of the upstream converter just follows the LSB of the downstream converter on the next SCLK cycle. BUSY OUT BUSY BUSY AD7622 AD7622 #2 (UPSTREAM) #1 (DOWNSTREAM) RDC/SDIN SDOUT CNVST RDC/SDIN SDOUT DATA OUT CNVST CS CS SCLK SCLK SCLK IN CS IN CNVST IN 06023-037 External Clock Figure 40. Two AD7622 Devices in a Daisy-Chain Configuration External Clock Data Read During Previous Conversion Figure 42 shows the detailed timing diagrams of this method. During a conversion, while CS and RD are both low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses and is valid on both the rising and falling edge of the clock. The 16 bits have to be read before the current conversion is complete; otherwise, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no daisy-chain feature in this mode, and the RDC/SDIN input should always be tied either high or low. To reduce performance degradation due to digital activity, a fast discontinuous clock (at least 60 MHz when normal mode is used, or 80 MHz when warp mode is used) is recommended to ensure that all the bits are read during the first half of the SAR conversion phase. If the maximum throughput is not used, thus allowing more acquisition time, then the use of a slower clock speed can be used to read the data. Rev. A | Page 24 of 28 AD7622 RD = 0 INVSCLK = 0 EXT/INT = 1 CS BUSY t36 SCLK t35 t37 1 2 t31 3 14 15 16 17 18 t32 X SDOUT D15 t16 D14 D13 D1 D0 X15 X14 X14 X13 X1 X0 Y15 Y14 SDIN X15 t33 06023-038 t34 Figure 41. Slave Serial Data Timing for Reading (Read After Convert) EXT/INT = 1 CS RD = 0 INVSCLK = 0 CNVST BUSY t3 t36 SCLK t35 t37 1 2 t31 14 15 16 D15 D14 D13 D1 D0 t16 Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) Rev. A | Page 25 of 28 06023-039 t32 X SDOUT 3 AD7622 MICROPROCESSOR INTERFACING SPI Interface (ADSP-219x) The AD7622 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD7622 is designed to interface with a parallel 8-bit or 16-bit wide interface or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7622 to prevent digital noise from coupling into the ADC. The SPI Interface (ADSP-219x) section illustrates the use of the AD7622 with the ADSP-219x SPI-equipped DSP. Figure 43 shows an interface diagram between the AD7622 and an SPI-equipped DSP, the ADSP-219x. To accommodate the slower speed of the DSP, the AD7622 acts as a slave device and data must be read after conversion. This mode also allows the daisy-chain feature. The convert command can be initiated in response to an internal timer interrupt. The 16-bit output data are read with three SPI byte access. The reading process can be initiated in response to the end-of-conversion signal (BUSY going low) using an interrupt line of the DSP. The serial peripheral interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock phase bit (CPHA) = 1, and the SPI interrupt enable (TIMOD) = 00 by writing to the SPI control register (SPICLTx). It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbps, allowing it to read an ADC result in less than 1 μs. When a higher sampling rate is desired, it is recommended to use one of the parallel interface modes. DVDD BUSY MODE1 CS EXT/INT SDOUT SCLK RD CNVST ADSP-219x1 PFx SPIxSEL (PFx) MISOx SCKx PFx OR TFSx INVSCLK 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 43. Interfacing the AD7622 to ADSP-219x Rev. A | Page 26 of 28 06023-040 AD7622 MODE0 AD7622 APPLICATION HINTS LAYOUT While the AD7622 has very good immunity to noise on the power supplies, exercise care with the grounding layout. To facilitate the use of ground planes that can be easily separated, design the printed circuit board that houses the AD7622 so that the analog and digital sections are separated and confined to certain areas of the board. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7622, or as close as possible to the AD7622. If the AD7622 is in a system where multiple devices require analog-to-digital ground connections, the connections should still be made at one point only, a star ground point, established as close as possible to the AD7622. To prevent coupling noise onto the die, avoid radiating noise, and reduce feedthrough:  Do not run digital lines under the device.  Run the analog ground plane under the AD7622.  Shield fast switching signals, like CNVST or clocks, with digital ground to avoid radiating noise to other sections of the board, and never run them near analog signal paths.  Avoid crossover of digital and analog signals.  Run traces on different but close layers of the board, at right angles to each other, to reduce the effect of feedthrough through the board. The power supply lines to the AD7622 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the impedance of the supplies presented to the AD7622, and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each of the power supplies pins, AVDD, DVDD, and OVDD. The capacitors should be placed close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 μF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The DVDD supply of the AD7622 can be either a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, and no separate supply is available, it is recommended to connect the DVDD digital supply to the analog supply AVDD through an RC filter, and to connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. Refer to Figure 25 for an example of this configuration. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7622 has four different ground pins: REFGND, AGND, DGND, and OGND. REFGND senses the reference voltage and, because it carries pulsed currents, should have a low impedance return to the reference. AGND is the ground to which most internal ADC analog signals are referenced; it must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. The layout of the decoupling of the reference voltage is important. To minimize parasitic inductances, place the decoupling capacitor close to the ADC and connect it with short, thick traces. EVALUATING THE AD7622 PERFORMANCE A recommended layout for the AD7622 is outlined in the documentation of the EVAL-AD7622-CB evaluation board for the AD7622. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVALCONTROL BRD3. Rev. A | Page 27 of 28 AD7622 OUTLINE DIMENSIONS 7.10 7.00 SQ 6.90 PIN 1 INDICATOR AREA DETAIL A (JEDEC 95) 0.30 0.23 0.18 37 36 P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 48 1 0.50 BSC 5.20 5.10 SQ 5.00 EXPOSED PAD 12 0.45 0.40 0.35 0.80 0.75 0.70 END VIEW 13 0.20 MIN BOTTOM VIEW 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE PKG-004509 24 10-10-2018-C TOP VIEW COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4 Figure 44. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-4) Dimensions shown in millimeters 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 PIN 1 0.15 0.05 7.00 BSC SQ TOP VIEW 1.45 1.40 1.35 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY VIEW A (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH 24 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 45. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model AD7622BCPZ1 AD7622BCPZRL1 AD7622BSTZ1 AD7622BSTZRL1 EVAL-AD7622CB2 EVAL-CONTROL BRD33 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package (LFCSP) 48-Lead Lead Frame Chip Scale Package (LFCSP) 48-Lead Low Profile Quad Flat Package (LQFP) 48-Lead Low Profile Quad Flat Package (LQFP) Evaluation Board Controller Board 1 Package Option CP-48-4 CP-48-4 ST-48 ST-48 Z = Pb-free part. This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. 2 ©2006–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06023–8/20(A) Rev. A | Page 28 of 28