AD7666ASTZRL

16-Bit 500 kSPS PulSAR® Unipolar ADC with Reference AD7666 FUNCTIONAL BLOCK DIAGRAM 2.5 V internal reference: typical drift 3 ppm/°C Guaranteed max drift 15 ppm/°C Throughput: 500 kSPS INL: ±2.0 LSB max (±0.0038% of full scale) 16-bit resolution with no missing codes S/(N+D): 88 dB min @ 20 kHz THD: –96 dB max @ 20 kHz Analog input voltage range: 0 V to 2.5 V Both AC and DC specifications No pipeline delay Parallel and serial 5 V/3 V interface SPI®/QSPITM/MICROWIRETM/DSP compatible Single 5 V supply operation Power dissipation 66 mW typ, 132 µW @ 1 kSPS without REF 81 mW typ with REF 48-lead LQFP and 48-lead LFCSP packages Pin-to-pin compatible with PulSAR ADCs APPLICATIONS Data acquisition Medical instruments Digital signal processing Spectrum analysis Instrumentation Battery-powered systems Process control REFBUFIN REF REFGND AGND AVDD The AD7666 is available in a 48-lead LQFP and a tiny 48-lead LFCSP, with operation specified from –40°C to +85°C. DGND OVDD AD7666 IN OGND SERIAL PORT REF 16 SWITCHED CAP DAC INGND DATA[15:0] BUSY PARALLEL INTERFACE PDREF PDBUF CLOCK RESET RD CS PD CONTROL LOGIC AND CALIBRATION CIRCUITRY SER/PAR OB/2C BYTESWAP CNVST Figure 1. Functional Block Diagram Table 1. PulSAR Selection Type/kSPS PseudoDifferential True Bipolar True Differential 18-Bit Multichannel/ Simultaneous 100–250 AD7651 AD7660/AD7661 AD7663 AD7675 500–570 AD7650/AD7652 AD7664/AD7666 AD7665 AD7676 AD7678 AD7679 AD7654 AD7655 800– 1000 AD7653 AD7667 AD7671 AD7677 AD7674 PRODUCT HIGHLIGHTS 1. Fast Throughput. The AD7666 is a 500 kSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. 2. Superior INL. The AD7666 has a maximum integral nonlinearity of 2.0 LSB with no missing 16-bit codes. 3. Internal Reference. The AD7666 has an internal reference with a typical temperature drift of 3 ppm/°C. 4. Single-Supply Operation. The AD7666 operates from a single 5 V supply. Its power dissipation decreases with throughput. 5. Serial or Parallel Interface. Versatile parallel or 2-wire serial interface arrangement is compatible with both 3 V and 5 V logic. GENERAL DESCRIPTION The AD7666 is a 16-bit, 500 kSPS, charge redistribution SAR analog-to-digital converter that operates from a single 5 V power supply. The part contains a high speed, 16-bit sampling ADC, an internal conversion clock, internal reference, error correction circuits, and both serial and parallel system interface ports. The AD7666 is hardware factory-calibrated and comprehensively tested to ensure ac parameters such as signalto-noise ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offset, and linearity. DVDD Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 03034-0-001 FEATURES One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD7666 TABLE OF CONTENTS Specifications..................................................................................... 3 Digital Interface.......................................................................... 22 Timing Specifications....................................................................... 5 Parallel Interface......................................................................... 22 Absolute Maximum Ratings............................................................ 7 Serial Interface ............................................................................ 22 ESD Caution.................................................................................. 7 Master Serial Interface............................................................... 23 Pin Configuration and Function Descriptions............................. 8 Slave Serial Interface .................................................................. 24 Definitions of Specifications ......................................................... 11 Microprocessor Interfacing....................................................... 26 Typical Performance Characteristics ........................................... 12 Application Hints ........................................................................... 27 Circuit Information ........................................................................ 16 Bipolar and Wider Input Ranges .............................................. 27 Converter Operation.................................................................. 16 Layout .......................................................................................... 27 Typical Connection Diagram ................................................... 18 Evaluating the AD7666’s Performance .................................... 27 Power Dissipation versus Throughput .................................... 20 Outline Dimensions ....................................................................... 28 Conversion Control.................................................................... 21 Ordering Guide .......................................................................... 28 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7666 SPECIFICATIONS Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance1 THROUGHPUT SPEED Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Differential Linearity Error Transition Noise Unipolar Zero Error, TMIN to TMAX3 Unipolar Zero Error Temperature Drift Full-Scale Error, TMIN to TMAX 3 Full-Scale Error Temperature Drift Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Conditions Min 16 VIN – VINGND VIN VINGND fIN = 10 kHz 500 kSPS Throughput 0 –0.1 –0.1 Max Unit Bits VREF +3 +0.5 V V V dB µA 2 500 µs kSPS +2.0 ±1.4 ±2 LSB2 Bits LSB LSB LSB ppm/°C % of FSR ppm/°C LSB 89.2 107 –106 89.1 30 12 dB4 dB dB dB dB MHz 65 7.7 0 –2.0 16 –1.0 +1.5 0.7 ±5 ±0.5 REF = 2.5 V ±0.08 AVDD = 5 V ± 5% fIN = 20 kHz fIN = 20 kHz fIN = 20 kHz fIN = 20 kHz –60 dB Input, fIN = 20 kHz 88 96 88 –3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response REFERENCE Internal Reference Voltage Internal Reference Temperature Drift Output Voltage Hysteresis Long Term Drift Line Regulation Turn-On Settling Time Temperature Pin Voltage Output @ 25°C Temperature Sensitivity Output Resistance External Reference Voltage Range External Reference Current Drain Typ –96 2 5 Full-Scale Step VREF @ 25°C –40°C to +85°C –40°C to +85°C 2.493 AVDD = 5 V ± 5% CREF = 10 µF 2.5 ±3 50 100 ±15 5 500 kSPS Throughput 300 1 4 2.5 120 2.3 Rev. 0 | Page 3 of 28 ns ps rms 750 ns 2.507 ±15 V ppm/°C ppm ppm/1000 Hours ppm/V ms AVDD – 1.85 mV mV/°C kΩ V µA AD7666 Parameter DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format5 Pipeline Delay6 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current AVDD8 AVDD9 DVDD10 OVDD10 Power Dissipation without REF8, 10 Power Dissipation with REF8, 10 TEMPERATURE RANGE11 Specified Performance Conditions Min Typ –0.3 2.0 –1 –1 ISINK = 1.6 mA ISOURCE = –500 µA 500 kSPS Throughput With Reference and Buffer Reference and Buffer Alone 5 5 12.2 3 4.1 102 66 132 81 500 kSPS Throughput 1 kSPS Throughput 500 kSPS Throughput –40 1 Unit +0.8 DVDD + 0.3 +1 +1 V V µA µA 0.4 V V 5.25 5.25 5.257 V V V OVDD – 0.6 4.75 4.75 2.7 TMIN to TMAX Max 90 mA mA mA µA mW µW mW +85 °C 75 See Analog Input section. LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV. See the Definitions of Specifications section. These specifications do not include the error contribution from the external reference. 4 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Parallel or Serial 16-Bit. 6 Conversion results are available immediately after completed conversion. 7 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 8 With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH. 9 With PDREF, PDBUF LOW and PD HIGH. 10 Tested in parallel reading mode. 11 Consult factory for extended temperature range. 2 3 Rev. 0 | Page 4 of 28 AD7666 TIMING SPECIFICATIONS Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter Refer to Figure 33 and Figure 34 Convert Pulse Width Time between Conversions CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except Master Serial Read after Convert Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time Acquisition Time RESET Pulse Width Refer to Figure 35, Figure 36, and Figure 37 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish Time Refer to Figure 39 and Figure 40 (Master Serial Interface Modes)1 CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay1 CS LOW to SDOUT Delay CNVST LOW to SYNC Delay SYNC Asserted to SCLK First Edge Delay Internal SCLK Period2 Internal SCLK HIGH2 Internal SCLK LOW2 SDOUT Valid Setup Time2 SDOUT Valid Hold Time2 SCLK Last Edge to SYNC Delay2 CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert2 CNVST LOW to SYNC Asserted Delay SYNC Deasserted to BUSY LOW Delay Refer to Figure 41 and Figure 42 (Slave Serial Interface Modes)1 External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW 1 Symbol Min t1 t2 t3 t4 t5 t6 t7 t8 t9 10 2 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 Typ Max 35 1.25 2 10 1.25 750 10 1.25 12 45 15 5 10 10 10 525 3 25 12 7 4 2 3 40 10 10 10 See Table 4 1.25 25 5 3 5 5 25 10 10 Rev. 0 | Page 5 of 28 ns µs ns µs ns ns µs ns ns µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns 18 In serial interface mode, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. In serial master read during convert mode. See Table 4 for serial master read after convert mode. 2 Unit ns ns ns ns ns ns ns AD7666 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum BUSY HIGH Width Maximum Symbol t18 t19 t19 t20 t21 t22 t23 t24 t24 Rev. 0 | Page 6 of 28 0 0 3 25 40 12 7 4 2 3 2 0 1 17 50 70 22 21 18 4 55 2.5 1 0 17 100 140 50 49 18 30 130 3.5 1 1 17 200 280 100 99 18 80 290 5.75 Unit ns ns ns ns ns ns ns ns µs AD7666 ABSOLUTE MAXIMUM RATINGS Table 5. AD7666 Stress Ratings1 1.6mA TO OUTPUT PIN 1.4V CL 60pF* ±0.3 V 500µA –0.3 V to +7 V ±7 V –0.3 V to +7 V –0.3 V to DVDD + 0.3 V ±20 mA 700 mW 2.5 W 150°C –65°C to +150°C 300°C IOL IOH * IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. 03033-0-002 Rating AVDD + 0.3 V to AGND – 0.3 V Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs CL = 10 pF 2V 0.8V tDELAY tDELAY 2V 0.8V 2V 0.8V Figure 3. Voltage Reference Levels for Timing 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 See the Voltage Reference Input section. 4 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W 5 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 28 03033-0-003 Parameter IN2, TEMP2, REF, REFBUFIN, INGND, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD, OVDD AVDD to DVDD, AVDD to OVDD DVDD to OVDD Digital Inputs PDREF, PDBUF3 Internal Power Dissipation4 Internal Power Dissipation5 Junction Temperature Storage Temperature Range Lead Temperature Range (Soldering 10 sec) AD7666 REFGND REF INGND AGND NC AGND AVDD IN TEMP REFBUFIN PDREF PDBUF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 AVDD 2 36 AGND PIN 1 IDENTIFIER 35 CNVST NC 3 BYTESWAP 4 34 PD 33 RESET OB/2C 5 NC 6 32 CS AD7666 31 RD TOP VIEW (Not to Scale) NC 7 SER/PAR 8 30 DGND 29 BUSY D0 9 28 D15 D1 10 D2/DIVSCLK0 11 27 D14 26 D13 D3/DIVSCLK1 12 03034-0-004 D11/RDERROR D9/SCLK D10/SYNC D8/SDOUT DVDD DGND OVDD OGND D7/RDC/SDIN D4/EXT/INT D5/INVSYNC D6/INVSCLK NC = NO CONNECT 25 D12 13 14 15 16 17 18 19 20 21 22 23 24 Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48) Table 6. Pin Function Descriptions Mnemonic AGND Type1 P Description Analog Power Ground Pin. AVDD NC P Input Analog Power Pin. Nominally 5 V. No Connect. BYTESWAP DI 5 OB/2C DI 8 SER/PAR DI 9, 10 D[0:1] DO 11, 12 D[2:3]or DIVSCLK[0:1] DI/O 13 D4 or EXT/INT DI/O 14 D5 or INVSYNC DI/O 15 D6 or INVSCLK DI/O Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus. When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus. When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave modes. Pin No. 1, 36, 41, 42 2, 44 3, 6, 7, 40 4 Rev. 0 | Page 8 of 28 AD7666 Pin No. 16 Mnemonic D7 or RDC/SDIN Type1 DI/O 17 18 19 20 21 OGND OVDD DVDD DGND D8 or SDOUT P P P P DO 22 D9 or SCLK DI/O 23 D10 or SYNC DO 24 D11 or RDERROR DO 25–28 D[12:15] DO 29 BUSY DO 30 31 32 DGND RD CS P DI DI 33 RESET DI 34 PD DI 35 CNVST DI 37 38 39 REF REFGND INGND AI/O AI AI Description When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. Input/Output Interface Digital Power Ground. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Digital Power. Nominally at 5 V. Digital Power Ground. When SER/PAR is LOW, this output is used as Bit 8 of the parallel port data output bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7666 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode when EXT/INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. When SER/PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus. When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while the SDOUT output is valid. When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When SER/PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the state of SER/PAR. Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. Must Be Tied to Digital Ground. Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. Reset Input. When set to a logic HIGH, this pin resets the AD7666 and the current conversion, if any, is aborted. If not used, this pin could be tied to DGND. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. Start Conversion. If CNVST is HIGH when the acquisition phase (t8) is complete, the next falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. The mode is most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. Reference Input Voltage. On-chip reference output voltage. Reference Input Analog Ground. Analog Input Ground. Rev. 0 | Page 9 of 28 AD7666 Pin No. 43 45 46 47 Mnemonic IN TEMP REFBUFIN PDREF Type1 AI AO AI/O DI 48 PDBUF DI Description Primary Analog Input with a Range of 0 V to 2.5 V. Temperature Sensor Voltage Output. Reference Input Voltage. The reference output and the reference buffer input. This pin allows the choice of internal or external voltage references. When LOW, the on-chip reference is turned on. When HIGH, the internal reference is switched off and an external reference must be used. This pin allows the choice of buffering an internal or external reference with the internal buffer. When LOW, the buffer is selected. When HIGH, the buffer is switched off. 1 AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power. Rev. 0 | Page 10 of 28 AD7666 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity Error (INL) Aperture Delay Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Full-Scale Error The last transition (from 011…10 to 011…11 in twos complement coding) should occur for an analog voltage 1½ LSB below the nominal full scale (2.49994278 V for the 0 V to 2.5 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level. Transient Response Transient response is the time required for the AD7666 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the maximum and minimum reference output voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C using the following equation: TCV REF ( ppm / °C ) = VREF ( Max) – VREF ( Min) × 10 6 VREF (25°C ) × (TMAX – TMIN ) The first transition should occur at a level ½ LSB above analog ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero error is the deviation of the actual transition from that point. where: VREF(Max) = Maximum VREF at TMIN, T(25°C), or TMAX VREF(Min) = Minimum VREF at TMIN, T(25°C), or TMAX VREF(25°C) = VREF at +25°C TMAX = +85°C TMIN = –40°C Spurious-Free Dynamic Range (SFDR) Thermal Hysteresis SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Thermal hysteresis is defined as the absolute maximum change of reference output voltage after the device is cycled through temperature from either Unipolar Zero Error Effective Number Of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) and is expressed in bits by the following formula: T_HYS+ = +25°C to TMAX to +25°C T_HYS– = +25°C to TMIN to +25°C It is expressed in ppm using the following equation: ENOB = (S/[N+D]dB – 1.76)/6.02 VHYS ( ppm) = Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal, and is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. VREF (25°C ) − VREF (T _ HYS) × 10 6 VREF (25°C ) where: VREF(25°C) = VREF at 25°C VREF(T_HYS) = Maximum change of VREF at T_HYS+ or T_HYS–. Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels. Rev. 0 | Page 11 of 28 AD7666 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 1.5 1.5 1.0 1.0 0.5 DNL (LSB) INL (LSB) 0.5 0 0 –0.5 –1.0 –0.5 0 16384 32768 49152 65536 CODE –1.0 03034-0-005 –2.0 0 16384 65536 Figure 8. Differential Nonlinearity vs. Code 20 20 15 15 NUMBER OF UNITS 10 10 5 5 0.5 1.0 1.5 2.0 POSITIVE INL (LSB) 0 –2.0 03034-0-006 0 –1.5 –1.0 –0.5 0 NEGATIVE INL (LSB) 03034-0-009 NUMBER OF UNITS 49152 CODE Figure 5. Integral Nonlinearity vs. Code 0 32768 03034-0-008 –1.5 Figure 9. Typical Negative INL Distribution (99 Units) Figure 6. Typical Positive INL Distribution (99 Units) 40 30 NUMBER OF UNITS 20 10 20 0 0 0.25 0.50 0.75 1.00 1.25 POSITIVE DNL (LSB) 1.50 0 –1.00 –0.75 –0.50 –0.25 NEGATIVE DNL (LSB) Figure 10. Typical Negative DNL Distribution (99 Units) Figure 7. Typical Positive DNL Distribution (99 Units) Rev. 0 | Page 12 of 28 0 03034-0-010 10 03034-0-007 NUMBER OF UNITS 30 AD7666 120000 180000 111791 112335 160000 148481 100000 140000 120000 COUNTS COUNTS 80000 60000 100000 80000 15968 53814 52691 60000 40000 40000 20187 20000 20000 0 0 8000 8001 8002 8003 8004 CODE IN HEX 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF –20 fS = 500kSPS fIN = 101.361kHz –75 –40 SNR = 88.6dB THD = –98.1dB SFDR = 99.2dB S/[N+D] = 88.1dB THD, HARMONICS (dB) –80 –100 –120 110 100 90 –90 80 –95 70 –100 –105 –115 –180 250 FREQUENCY (kHz) 30 –120 1 10 20 1000 100 FREQUENCY (kHz) 15.5 15.0 89 SNR 14.5 87 86 S/[N+D] 14.0 85 ENOB (Bits) 88 84 ENOB 83 13.5 81 100 FREQUENCY (kHz) 13.0 1000 03034-0-013 82 SNR, S/[N+D] REFERRED TO FULL-SCALE (dB) 91 90 SNR, S/[N+D] (dB) 40 Figure 15. THD, Harmonics, and SFDR vs. Frequency 91 10 50 THIRD HARMONIC Figure 12. FFT Plot 1 60 SECOND HARMONIC THD –160 200 120 –85 –110 150 8002 –80 –140 100 0 8001 SFDR 03034-0-012 AMPLITUDE (dB of Full Scale) –70 50 34 8000 Figure 14. Histogram of 261,120 Conversions of a DC Input at the Code Center 0 0 3300 CODE IN HEX Figure 11. Histogram of 261,120 Conversions of a DC Input at the Code Transition –60 2789 03034-0-014 7FFC 7FFD 7FFE 7FFF 11 0 03034-0-011 0 SFDR (dB) 4 03034-0-015 623 211 1 90 SNR S/[N+D] 89 88 –60 –50 –40 –30 –20 –10 0 INPUT LEVEL (dB) Figure 16. SNR and S/(N+D) vs. Input Level (Referred to Full Scale) Figure 13. SNR, S/(N+D), and ENOB vs. Frequency Rev. 0 | Page 13 of 28 03034-0-016 0 AD7666 ENOB 90 14.5 89 SNR 14.0 ENOB (Bits) 15.0 S/[N+D] 88 87 –55 –35 –15 5 25 45 65 85 105 13.0 125 TEMPERATURE (°C) 4 FULL-SCALE ERROR 3 2 1 0 –1 ZERO ERROR –2 –3 –4 –5 –6 –55 03034-0-017 13.5 5 ZERO ERROR, FULL-SCALE ERROR (LSB) 91 SNR, S/[N+D] (dB) 6 15.5 –35 –15 5 25 45 65 85 105 03034-0-020 92 125 TEMPERATURE (°C) Figure 20. Zero Error, Full-Scale Error without Reference vs. Temperature Figure 17. SNR, S/(N+D), and ENOB vs. Temperature 2.5016 –100 2.5014 2.5010 –105 2.5008 VREF (V) THD 2.5006 2.5004 2.5002 –110 2.5000 2.4998 –115 –55 –35 –15 THIRD HARMONIC 5 25 45 65 85 105 2.4996 125 TEMPERATURE (°C) 2.4994 –40 –20 0 20 40 60 80 100 03034-0-021 SECOND HARMONIC 03034-0-018 THD, HARMONICS (dB) 2.5012 120 TEMPERATURE (°C) Figure 21.Typical Reference Voltage Output vs. Temperature (2 Units) Figure 18. THD and Harmonics vs. Temperature 25 100000 20 NUMBER OF UNITS 1000 100 AVDD 10 DVDD OVDD 1 0.1 15 10 5 PDREF = PDBUF = HIGH 0.001 10 100 1k 10k 100k SAMPLING RATE (SPS) Figure 19. Operating Current vs. Sample Rate 1M 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 REFERENCE DRIFT (ppm/°C) 03034-0-039 0.01 03034-0-019 OPERATING CURRENTS (µA) 10000 Figure 22. Reference Voltage Temperature Coefficient Distribution (93 Units) Rev. 0 | Page 14 of 28 AD7666 50 OVDD = 2.7V @ 85°C 45 OVDD = 2.7V @ 25°C 40 30 25 OVDD = 5V @ 85°C 20 OVDD = 5V @ 25°C 15 10 5 0 0 50 100 150 CL (pF) 200 03035-0-023 t12 DELAY (ns) 35 Figure 23. Typical Delay vs. Load Capacitance, CL Rev. 0 | Page 15 of 28 AD7666 CIRCUIT INFORMATION IN REF REFGND MSB 32,768C 16,384C LSB 4C 2C C SWA SWITCHES CONTROL C BUSY CONTROL LOGIC INGND OUTPUT CODE 65,536C SWB CNVST 03033-0-020 COMP Figure 24. ADC Simplified Schematic The AD7666 is a very fast, low power, single supply, precise 16-bit analog-to-digital converter (ADC). The AD7666 is capable of converting 100,000 samples per second (500 kSPS) and allows power savings between conversions. The AD7666 provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7666 can be operated from a single 5 V supply and can be interfaced to either 5 V or 3 V digital logic. It is housed in either a 48-lead LQFP or a 48-lead LFCSP that saves space and allows flexible configurations as either a serial or parallel interface. The AD7666 is pin-to-pin compatible with PulSAR ADCs and is an upgrade of the AD7661 and AD7664. CONVERTER OPERATION The AD7666 is a successive-approximation ADC based on a charge redistribution DAC. Figure 24 shows a simplified schematic of the ADC. The capacitive DAC consists of an array of 16 binary weighted capacitors and an additional LSB capacitor. The comparator’s negative input is connected to a dummy capacitor of the same value as the capacitive DAC array. During the acquisition phase, the common terminal of the array tied to the comparator's positive input is connected to AGND via SWA. All independent switches are connected to the analog input IN. Thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on IN. Similarly, the dummy capacitor acquires the analog signal on INGND. When CNVST goes LOW, a conversion phase is initiated. When the conversion phase begins, SWA and SWB are opened. The capacitor array and dummy capacitor are then disconnected from the inputs and connected to REFGND. Therefore, the differential voltage between IN and INGND captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4, …VREF/65536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After this process is completed, the control logic generates the ADC output code and brings the BUSY output LOW. Rev. 0 | Page 16 of 28 AD7666 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Using the OB/2C digital input, the AD7666 offers two output codings: straight binary and twos complement. The LSB size is VREF/65536, which is about 38.15 µV. The AD7666’s ideal transfer characteristic is shown in Figure 25 and Table 7. Description FSR –1 LSB FSR – 2 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 1 LSB = V REF /65536 111...111 111...110 111...101 Digital Output Code (Hex) Straight Twos Binary Complement FFFF1 7FFF1 FFFE 7FFE 8001 0001 8000 0000 7FFF FFFF 0001 8001 00002 80002 1 This is also the code for overrange analog input (VIN – VINGND above VREF – VREFGND). 2 This is also the code for underrange analog input (VIN below VINGND). 000...010 000...001 000...000 0V 1 LSB 0.5 LSB VREF – 1 LSB 03033-0-021 VREF – 1.5 LSB ANALOG INPUT Figure 25. ADC Ideal Transfer Function 20Ω ANALOG SUPPLY (5V) + 10µF + 100nF AVDD 10µF DGND AGND 100nF 100nF DVDD OVDD + DIGITAL SUPPLY (3.3V OR 5V) 10µF OGND SERIAL PORT SCLK REF CR4 SDOUT REFBUFIN1 100nF REFGND AD7666 CNVST D3 15Ω U12 ANALOG INPUT (0V TO 2.5V) µC/µP/DSP BUSY IN CC OB/2C SER/PAR 2.7nF DVDD INGND PDREF PD PDBUF RESET CS RD BYTESWAP CLOCK NOTES 1THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER. 2THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3OPTIONAL LOW JITTER. 4A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. Figure 26. Typical Connection Diagram Rev. 0 | Page 17 of 28 03034-0-022 ADC CODE (Straight Binary) Analog Input 2.499962 V 2.499923 V 1.250038 V 1.25 V 1.249962 V 38 µV 0V AD7666 TYPICAL CONNECTION DIAGRAM Figure 26 shows a typical connection diagram for the AD7666. Analog Input Figure 27 shows an equivalent circuit of the input structure of the AD7666. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN and INGND. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V. This will cause these diodes to become forward-biased and start conducting current. These diodes can handle a forward-biased current of 100 mA maximum. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from AVDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. AVDD D1 C2 –50 D2 AGND RS = 500Ω –60 RS = 100Ω Figure 27. Equivalent Analog Input Circuit This analog input structure allows the sampling of the differential signal between IN and INGND. Unlike other converters, INGND is sampled at the same time as IN. By using this differential input, small signals common to both inputs are rejected, as shown in Figure 28, which represents the typical CMRR over frequency with on-chip and external references. For instance, by using INGND to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated. THD (dB) –70 RS = 50Ω RS = 20Ω –80 –90 –100 –110 1 10 100 1000 INPUT FREQUENCY (kHz) 03034-0-029 C1 R1 When the source impedance of the driving circuit is low, the AD7666 can be driven directly. Large source impedances will significantly affect the ac performance, especially total harmonic distortion (THD). The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency, as shown in Figure 29. 03033-0-023 IN OR INGND During the acquisition phase, the impedance of the analog input IN can be modeled as a parallel combination of capacitor C1 and the network formed by the series connection of R1 and C2. C1 is primarily the pin capacitance. R1 is typically 168 Ω and is a lumped component made up of some serial resistors and the on resistance of the switches. C2 is typically 60 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to C1. R1 and C2 make a 1-pole low-pass filter that reduces undesirable aliasing effect and limits the noise. Figure 29. THD vs. Analog Input Frequency and Source Resistance 90 Driver Amplifier Choice EXT REF 80 Although the AD7666 is easy to drive, the driver amplifier needs to meet the following requirements: REF • 60 50 40 30 1 10 100 1000 FREQUENCY (kHz) 10000 03034-0-028 CMRR (dB) 70 Figure 28. Analog Input CMRR vs. Frequency Rev. 0 | Page 18 of 28 The driver amplifier and the AD7666 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. The tiny op amp AD8021, which combines ultra low noise and high gain-bandwidth, meets this settling time requirement even when used with gains up to 13. AD7666 • The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7666. The noise coming from the driver is filtered by the AD7666 analog input circuit, 1-pole, low-pass filter made by R1 and C2 or by the external filter, if one is used. The SNR degradation due to the amplifier is SNR LOSS ⎛ ⎜ 28 = 20 log ⎜ ⎜ π ⎜ 784 + f −3dB (Ne N )2 2 ⎝ eN is the noise factor of the amplifier (+1 in buffer configuration). is the equivalent input noise voltage of the op amp, in nV/√Hz. For instance, a driver with an equivalent input noise of 2 nV/√Hz, like the AD8021 with a noise gain of +1 when configured as a buffer, degrades the SNR by only 0.13 dB when using the filter shown in Figure 26, and by 0.43 dB without the filter shown in Figure 26. • The AD7666 allows the choice of either a very low temperature drift internal voltage reference or an external 2.5 V reference. Unlike many ADCs with internal references, the internal reference of the AD7666 provides excellent performance and can be used in almost all applications. To use the internal reference along with the internal buffer, PDREF and PDBUF should both be LOW. This will produce 1.2 V on REFBUFIN which, amplified by the buffer, will result in a 2.5 V reference on the REF pin. ⎞ ⎟ ⎟ ⎟ ⎟ ⎠ where: f–3dB is the input bandwidth of the AD7666 (13 MHz) or the cutoff frequency of the input filter (3.9 MHz), if one is used. N Voltage Reference Input The driver needs to have a THD performance suitable to that of the AD7666. Figure 15 gives the THD versus frequency that the driver should exceed. The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an NPO ceramic or mica type. Moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. The AD8022 could also be used if a dual version is needed and gain of 1 is present. The AD829 is an alternative in applications where high frequency (above 100 kHz) performance is not required. In gain of 1 applications, it requires an 82 pF compensation capacitor. The AD8610 is an option when low bias current is needed in low frequency applications. The output impedance of REFBUFIN is 11 kΩ (minimum) when the internal reference is enabled. It is necessary to decouple REFBUFIN with a ceramic capacitor greater than 10 nF. Thus the capacitor provides an RC filter for noise reduction. To use an external reference along with the internal buffer, PDREF should be HIGH and PDBUF should be LOW. This powers down the internal reference and allows the 2.5 V reference to be applied to REFBUFIN. To use an external reference directly on REF pin, PDREF and PDBUF should both be HIGH. PDREF and PDBUF power down the internal reference and the internal reference buffer, respectively. Note that the PDREF and PDBUF input current should never exceed 20 mA. This could eventually occur when input voltage is above AVDD (for instance at power up). In this case, a 100 Ω series resistor is recommended. The internal reference is temperature compensated to 2.5 V ± 7 mV. The reference is trimmed to provide a typical drift of 3 ppm/°C . This typical drift characteristic is shown in Figure 22. For improved drift performance, an external reference, such as the AD780, can be used. The AD7666 voltage reference input REF has a dynamic input impedance; it should therefore be driven by a low impedance source with efficient decoupling between the REF and REFGND inputs. This decoupling depends on the choice of the voltage reference, but usually consists of a low ESR tantalum capacitor connected to REF and REFGND, with minimum parasitic inductance. A 10 µF (X5R, 1206 size) ceramic chip capacitor (or 47 µF tantalum capacitor) is appropriate when using either the internal reference or one of these recommended reference voltages: • The low noise, low temperature drift ADR421 and AD780 • The low power ADR291 • The low cost AD1582 Rev. 0 | Page 19 of 28 AD7666 For applications that use multiple AD7666s, it is more effective to use the internal buffer to buffer the reference voltage. 90 80 Care should be taken with the voltage reference’s temperature coefficient, which directly affects the full-scale accuracy if this parameter matters. For instance, a ±15 ppm/°C temperature coefficient of the reference changes full scale by ±1 LSB/°C. EXT REF PSRR (dB) 70 Note that VREF can be increased to AVDD – 1.85 V. Since the input range is defined in terms of VREF, this would essentially increase the range to 0 V to 3 V with an AVDD above 4.85 V. The AD780 can be selected with a 3 V reference voltage. AD7666 Figure 30. Temperature Sensor Connection Diagram Power Supply The AD7666 uses three power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/ output interface supply OVDD. OVDD allows direct interface with any logic between 2.7 V and DVDD + 0.3 V. To reduce the supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 26. The AD7666 is independent of power supply sequencing once OVDD does not exceed DVDD by more than 0.3 V, and is thus free of supply voltage induced latch-up. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 31, which represents PSRR over frequency with on-chip and external references. 10 100 1000 10000 FREQUENCY (kHz) Figure 31. PSRR vs. Frequency POWER DISSIPATION VERSUS THROUGHPUT Operating currents are very low during the acquisition phase, allowing significant power savings when the conversion rate is reduced (see Figure 32). The AD7666 automatically reduces its power consumption at the end of each conversion phase. This makes the part ideal for very low power battery applications. The digital interface and the reference remain active even during the acquisition phase. To reduce operating digital supply currents even further, digital inputs need to be driven close to the power supply rails (i.e., DVDD or DGND), and OVDD should not exceed DVDD by more than 0.3 V. 1M 100k 10k 1k 100 PDREF = PDBUF = HIGH 10 10 100 1k 10k 100k SAMPLING RATE (SPS) Figure 32. Power Dissipation vs. Sampling Rate Rev. 0 | Page 20 of 28 1M 03034-0-032 CC 1 POWER DISSIPATION (µW) AD8021 TEMPERATURE SENSOR 03034-0-024 IN 30 03034-0-031 40 TEMP ANALOG INPUT (UNIPOLAR) INT REF 50 The TEMP pin, which measures the temperature of the AD7666, can be used as shown in Figure 30. The output of TEMP pin is applied to one of the inputs of the analog switch (e.g., ADG779), and the ADC itself is used to measure its own temperature. This configuration is very useful for improving the calibration accuracy over the temperature range. ADG779 60 AD7666 CONVERSION CONTROL t2 CNVST BUSY t4 t3 Conversions can be automatically initiated with the AD7666. If CNVST is held LOW when BUSY is LOW, the AD7666 controls the acquisition phase and automatically initiates a new conversion. By keeping CNVST LOW, the AD7666 keeps the conversion process running by itself. It should be noted that the analog input must be settled when BUSY goes LOW. Also, at power-up, CNVST should be brought LOW once to initiate the conversion process. In this mode, the AD7666 can run slightly faster than the guaranteed 500 kSPS. Although CNVST is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. t6 t5 MODE ACQUIRE CONVERT ACQUIRE t7 CONVERT t8 03033-0-026 Figure 33 shows the detailed timing diagrams of the conversion process. The AD7666 is controlled by the CNVST signal, which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the conversion is complete. CNVST operates independently of CS and RD. t1 Figure 33. Basic Conversion Timing t9 RESET BUSY DATA 03033-0-027 t8 The CNVST trace should be shielded with ground and a low value serial resistor (i.e., 50 Ω) termination should be added close to the output of the component that drives this line. CNVST Figure 34. RESET Timing For applications where SNR is critical, the CNVST signal should have very low jitter. This may be achieved by using a dedicated oscillator for CNVST generation, or to clock CNVST with a high frequency, low jitter clock, as shown in Figure 26. CS = RD = 0 t1 CNVST t10 BUSY t4 t3 PREVIOUS CONVERSION DATA NEW DATA Figure 35. Master Parallel Data Timing for Reading (Continuous Read) Rev. 0 | Page 21 of 28 03033-0-028 DATA BUS t11 AD7666 DIGITAL INTERFACE CS The two signals, CS and RD, control the interface. CS and RD have a similar effect because they are OR’d together internally. When at least one of these signals is HIGH, the interface outputs are in high impedance. Usually CS allows the selection of each AD7666 in multicircuit applications and is held low in a single AD7666 design. RD is generally used to enable the conversion result on the data bus. RD BUSY DATA BUS CURRENT CONVERSION t12 03033-0-029 The AD7666 has a versatile digital interface; it can be interfaced with the host system by using either a serial or a parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7666 digital interface also accommodates both 3 V and 5 V logic by simply connecting the OVDD supply pin of the AD7666 to the host system interface digital supply. Finally, by using the OB/2C input pin, both twos complement or straight binary coding can be used. t13 Figure 36. Slave Parallel Data Timing for Reading (Read after Convert) CS = 0 t1 CNVST, RD PARALLEL INTERFACE The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 38, the LSB byte is output on D[7:0] and the MSB is output on D[15:8] when BYTESWAP is LOW. When BYTESWAP is HIGH, the LSB and MSB bytes are swapped and the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16-bit data can be read in two bytes on either D[15:8] or D[7:0]. BUSY t4 t3 DATA BUS t12 The AD7666 is configured to use the serial interface when SER/PAR is held HIGH. The AD7666 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edges of the data clock. t13 Figure 37. Slave Parallel Data Timing for Reading (Read during Convert) CS RD BYTESWAP PINS D[15:8] SERIAL INTERFACE 03033-0-030 PREVIOUS CONVERSION HI-Z HIGH BYTE t12 PINS D[7:0] Rev. 0 | Page 22 of 28 HI-Z LOW BYTE LOW BYTE t12 HIGH BYTE Figure 38. 8-Bit Parallel Interface HI-Z t13 HI-Z 03033-0-031 The AD7666 is configured to use the parallel interface when SER/PAR is held LOW. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 36 and Figure 37, respectively. When the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. AD7666 MASTER SERIAL INTERFACE Usually, because the AD7666 is used with a fast throughput, the Master Read During Conversion mode is the most recommended serial mode. In this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions. Internal Clock The AD7666 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held LOW. The AD7666 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. Depending on the RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 39 and Figure 40 show detailed timing diagrams of these two modes. In Read After Conversion mode, it should be noted that unlike in other modes, the BUSY signal returns LOW after the 16 data bits are pulsed out and not at the end of the conversion phase, which results in a longer BUSY width. RDC/SDIN = 0 EXT/INT = 0 INVSCLK = INVSYNC = 0 CS, RD t3 CNVST t28 BUSY t30 t29 t25 SYNC t 14 t18 t19 t 20 1 SCLK t 24 t21 2 3 14 15 t26 16 t 15 t27 D15 X t 16 D14 D2 D1 D0 03033-0-032 SDOUT t23 t 22 Figure 39. Master Serial Data Timing for Reading (Read after Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t1 CNVST t3 BUSY t17 t25 SYNC t14 t 19 t 20 t 21 SCLK 1 t24 2 3 14 15 t18 SDOUT X t16 t22 t26 16 t27 D15 D14 D2 D1 D0 t23 Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. 0 | Page 23 of 28 03033-0-033 t15 AD7666 SLAVE SERIAL INTERFACE External Clock The AD7666 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held HIGH. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both LOW, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or a discontinuous clock. A discontinuous clock can be either normally HIGH or normally LOW when inactive. Figure 41 and Figure 42 show the detailed timing diagrams of these methods. Usually, because the AD7666 has a longer acquisition phase than conversion phase, the data are read immediately after conversion. EXT/INT = 1 RD While the AD7666 is performing a bit decision, it is important that voltage transients be avoided on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7666 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when BUSY is LOW, or, more importantly, that it does not transition during the latter half of BUSY HIGH. RD = 0 INVSCLK = 0 BUSY t 36 SCLK t 35 t37 1 2 t31 3 14 15 16 17 18 t32 X SDOUT D15 t16 D14 D13 D1 D0 X15 X14 X14 X13 X1 X0 Y15 Y14 SDIN X15 t33 03033-0-034 t 34 Figure 41. Slave Serial Data Timing for Reading (Read after Convert) EXT/INT = 1 CS RD = 0 INVSCLK = 0 CNVST BUSY t3 t35 t36 t37 SCLK 1 2 t31 14 15 16 D15 D14 D13 D1 D0 t 16 Figure 42. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. 0 | Page 24 of 28 03033-0-035 t32 X SDOUT 3 AD7666 External Discontinuous Clock Data Read After Conversion External Clock Data Read During Conversion Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 41 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning LOW, the conversion’s result can be read while both CS and RD are LOW. Data is shifted out MSB first with 16 clock pulses and is valid on the rising and falling edges of the clock. Among the advantages of this method is the fact that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is the ability to read the data at any speed up to 40 MHz, which accommodates both the slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7666 provides a daisy-chain feature using the RDC/SDIN pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when desired, as, for instance, in isolated multiconverter applications. Figure 42 shows the detailed timing diagrams of this method. During a conversion, while both CS and RD are LOW, the result of the previous conversion can be read. The data is shifted out MSB first with 16 clock pulses, and is valid on both the rising and falling edges of the clock. The 16 bits must be read before the current conversion is complete; otherwise, RDERROR is pulsed HIGH and can be used to interrupt the host interface to prevent incomplete data reading. There is no daisy-chain feature in this mode and the RDC/SDIN input should always be tied either HIGH or LOW. To reduce performance degradation due to digital activity, a fast discontinuous clock of at least 18 MHz is recommended to ensure that all the bits are read during the first half of the conversion phase. It is also possible to begin to read data after conversion and continue to read the last bits after a new conversion has been initiated. This allows the use of a slower clock speed like 14 MHz. An example of the concatenation of two devices is shown in Figure 43. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the opposite edge of SCLK of the one used to shift out the data on SDOUT. Therefore, the MSB of the “upstream” converter just follows the LSB of the “downstream” converter on the next SCLK cycle. BUSY OUT BUSY BUSY AD7666 AD7666 #2 (UPSTREAM) #1 (DOWNSTREAM) SDOUT RDC/SDIN SDOUT CNVST CNVST CS CS SCLK SCLK DATA OUT 03034-0-036 RDC/SDIN SCLK IN CS IN CNVST IN Figure 43. Two AD7666s in a Daisy-Chain Configuration Rev. 0 | Page 25 of 28 AD7666 MICROPROCESSOR INTERFACING The AD7666 is ideally suited for traditional dc measurement applications supporting a microprocessor, and for ac signal processing applications interfacing to a digital signal processor. The AD7666 is designed to interface either with a parallel 8-bit or 16-bit wide interface, or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7666 to prevent digital noise from coupling into the ADC. The following section discusses the use of an AD7666 with an ADSP-219x SPI equipped DSP. going LOW) using an interrupt line of the DSP. The serial interface (SPI) on the ADSP-219x is configured for master mode— (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit (CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by writing to the SPI control register (SPICLTx). To meet all timing requirements, the SPI clock should be limited to 17 Mbps, which allows it to read an ADC result in less than 1 µs. When a higher sampling rate is desired, use of one of the parallel interface modes is recommended. DVDD Figure 44 shows an interface diagram between the AD7666 and the SPI equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7666 acts as a slave device and data must be read after conversion. This mode also allows the daisychain feature. The convert command can be initiated in response to an internal timer interrupt. The reading process can be initiated in response to the end-of-conversion signal (BUSY ADSP-219x* AD7666* SER/PAR EXT/INT BUSY CS RD INVSCLK SDOUT SCLK CNVST PFx SPIxSEL (PFx) MISOx SCKx PFx or TFSx * ADDITIONAL PINS OMITTED FOR CLARITY Figure 44. Interfacing the AD7666 to an SPI Interface Rev. 0 | Page 26 of 28 03034-0-037 SPI Interface (ADSP-219x) AD7666 APPLICATION HINTS BIPOLAR AND WIDER INPUT RANGES In some applications, it is desirable to use a bipolar or wider analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although the AD7666 has only one unipolar range, simple modifications of input driver circuitry allow bipolar and wider input ranges to be used without any performance degradation. Figure 45 shows a connection diagram that allows this. Component values required and resulting full-scale ranges are shown in Table 8. When desired, accurate gain and offset can be calibrated by acquiring a ground and voltage reference using an analog multiplexer (U2), as shown in Figure 45. The power supply lines to the AD7666 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply’s impedance presented to the AD7666 and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each power supply pin—AVDD, DVDD, and OVDD—close to, and ideally right up against these pins and their corresponding ground pins. Additionally, low ESR 10 µF capacitors should be located near the ADC to further reduce low frequency ripple. CF R1 R2 ANALOG INPUT 15Ω IN U1 2.7nF AD7666 U2 R3 R4 Running digital lines under the device should be avoided since these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7666 to avoid noise coupling. Fast switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of crosstalk through the board. 100nF INGND REF 03034-0-038 CREF REFGND Figure 45. Using the AD7666 in 16-Bit Bipolar and/or Wider Input Ranges Table 8. Component Values and Input Ranges Input Range ±10 V ±5 V 0 V to –5 V R1 (Ω) 500 500 500 R2 (kΩ) 4 2 1 R3 (kΩ) 2.5 2.5 None R4 (kΩ) 2 1.67 0 LAYOUT The AD7666 has very good immunity to noise on the power supplies. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD7666 should be designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7666, or as close as possible to the AD7666. If the AD7666 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7666. The DVDD supply of the AD7666 can be a separate supply, or can come from the analog supply AVDD or the digital interface supply OVDD. When the system digital supply is noisy or when fast switching digital signals are present, if no separate supply is available, the user should connect DVDD to AVDD through an RC filter (see Figure 26) and the system supply to OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7666 has five different ground pins: INGND, REFGND, AGND, DGND, and OGND. INGND is used to sense the analog input signal. REFGND senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. AGND is the ground to which most internal ADC analog signals are referenced; it must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. EVALUATING THE AD7666’S PERFORMANCE A recommended layout for the AD7666 is outlined in the EVAL-AD7666 evaluation board for the AD7666. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD2. Rev. 0 | Page 27 of 28 AD7666 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 10° 6° 2° 1.45 1.40 1.35 0.15 0.05 SEATING PLANE PIN 1 SEATING PLANE 7.00 BSC SQ TOP VIEW 0.20 0.09 (PINS DOWN ) VIEW A 7° 3.5° 0° 0.10 MAX COPLANARITY 25 12 24 13 0.27 0.22 0.17 0.50 BSC VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 46. 48-Lead Quad Flatpack (LQFP) [ST-48] Dimensions shown in millimeters 7.00 BSC SQ 0.60 MAX 0.60 MAX 0.30 0.23 0.18 37 36 PIN 1 INDICATOR 6.75 BSC SQ TOP VIEW PIN 1 INDICATOR 48 1 5.25 5.10 SQ 4.95 BOTTOM VIEW 0.50 0.40 0.30 25 24 12 13 0.25 MIN 1.00 0.85 0.80
MAX 12° 5.50 REF 0.80 MAX 0.65 TYP PADDLE CONNECTED TO AGND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 47. 48-Lead Frame Chip Scale Package (LFCSP) [CP-48] Dimensions shown in millimeters ORDERING GUIDE Model AD7666AST AD7666ASTRL AD7666ACP AD7666ACPRL EVAL-AD7666CB1 EVAL-CONTROL BRD22 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description Quad Flatpack (LQFP) Quad Flatpack (LQFP) Lead Frame Chip Scale (LFCSP) Lead Frame Chip Scale (LFCSP) Evaluation Board Controller Board 1 Package Option ST-48 ST-48 CP-48 CP-48 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. 2 © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03034–0–1/04(0) Rev. 0 | Page 28 of 28