AD7683ARM

16-Bit, 100 kSPS, Single-Ended PulSAR ADC in MSOP/QFN AD7683 FEATURES APPLICATION DIAGRAM 0.5V TO VDD 2.7V TO 5.5V VDD DCLOCK AD7683 DOUT 3-WIRE SPI INTERFACE CS GND Figure 1. Table 1. MSOP, QFN (LFCSP)/SOT-23, 14-/16-/18-Bit PulSAR ADC APPLICATIONS Battery-powered equipment Data acquisition Instrumentation Medical instruments Process control 16-Bit True Differential 16-Bit Pseudo Differential 14-Bit Pseudo Differential The AD7683 is a 16-bit, charge redistribution, successive approximation, PulSAR® analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.7 V and 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes (B grade), an internal conversion clock, and a serial, SPI-compatible interface port. The part also contains a low noise, wide bandwidth, short aperture delay, +IN –IN Type 18-Bit True Differential GENERAL DESCRIPTION REF 0V TO VREF 04301-001 16-bit resolution with no missing codes Throughput: 100 kSPS INL: ±1 LSB typical, ±3 LSB maximum Pseudo differential analog input range 0 V to VREF with VREF up to VDD Single-supply operation: 2.7 V to 5.5 V Serial interface SPI/QSPI/MICROWIRE/DSP compatible Power dissipation: 4 mW @ 5 V, 1.5 mW @ 2.7 V, 150 μW @ 2.7 V/10 kSPS Standby current: 1 nA 8-lead packages: MSOP 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) Improved second source to ADS8320 and ADS8325 100 kSPS 250 kSPS AD7691 AD7684 AD7687 AD7680 AD7683 AD7940 AD7685 AD7694 AD7942 400 kSPS to 500 kSPS AD7690 AD7688 AD7693 AD7686 AD7946 ≥1000 kSPS AD7982 AD7984 ADC Driver ADA4941 ADA4841 AD7980 ADA4941 ADA4841 ADA4841 ADA4841 track-and-hold circuit. On the CS falling edge, it samples an analog input, +IN, between 0 V to REF with respect to a ground sense, –IN. The reference voltage, REF, is applied externally and can be set up to the supply voltage. Its power scales linearly with throughput. The AD7683 is housed in an 8-lead MSOP or an 8-lead QFN (LFCSP) package, with an operating temperature specified from −40°C to +85°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004–2008 Analog Devices, Inc. All rights reserved. AD7683 TABLE OF CONTENTS Features .............................................................................................. 1  Circuit Information.................................................................... 12  Applications ....................................................................................... 1  Converter Operation.................................................................. 12  Application Diagram ........................................................................ 1  Transfer Functions ..................................................................... 12  General Description ......................................................................... 1  Typical Connection Diagram ................................................... 13  Revision History ............................................................................... 2  Analog Input ............................................................................... 13  Specifications..................................................................................... 3  Driver Amplifier Choice ........................................................... 13  Timing Specifications .................................................................. 5  Voltage Reference Input ............................................................ 14  Absolute Maximum Ratings............................................................ 6  Power Supply............................................................................... 14  Thermal Resistance ...................................................................... 6  Digital Interface .......................................................................... 14  ESD Caution .................................................................................. 6  Layout .......................................................................................... 14  Pin Configuration and Function Descriptions ............................. 7  Evaluating the AD7683 Performance ...................................... 14  Terminology ...................................................................................... 8  Outline Dimensions ....................................................................... 15  Typical Performance Characteristics ............................................. 9  Ordering Guide .......................................................................... 16  Applications Information ............................................................... 12  REVISION HISTORY 2/08—Rev. 0 to Rev. A Change to Title .................................................................................. 1 Moved Figure 3, Figure 4, and Figure 5 ......................................... 5 Changes to Figure 4 .......................................................................... 5 Moved Figure 17 and Figure 18 .................................................... 11 Changes to Figure 22 ...................................................................... 13 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 16 9/04—Initial Version: Revision 0 Rev. A | Page 2 of 16 AD7683 SPECIFICATIONS VDD = 2.7 V to 5.5 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25°C Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate DCLOCK Frequency REFERENCE Voltage Range Load Current DIGITAL INPUTS Logic Levels VIL VIH IIL IIH Input Capacitance DIGITAL OUTPUTS Data Format VOH VOL POWER SUPPLIES VDD VDD Range1 Operating Current VDD Standby Current2, 3 Power Dissipation TEMPERATURE RANGE Specified Performance Conditions Min 16 +IN − (–IN) +IN −IN fIN = 100 kHz Acquisition phase 0 −0.1 −0.1 AD7683 All Grades Typ Max VREF VDD + 0.1 0.1 65 1 See the Analog Input section 0 0 0.5 100 kSPS, V+IN − V−IN = VREF/2 = 2.5 V μs kSPS MHz VDD + 0.3 V μA 0.3 × VDD VDD + 0.3 +1 +1 V V μA μA pF 5 ISOURCE = −500 μA ISINK = +500 μA Specified performance Serial, 16 bits straight binary VDD − 0.3 0.4 V V 2.7 2.0 5.5 5.5 V V 50 6 μA μA nA mW mW μW +85 °C 100 kSPS throughput VDD = 5 V VDD = 2.7 V VDD = 5 V, 25°C VDD = 5 V VDD = 2.7 V VDD = 2.7 V, 10 kSPS throughput2 TMIN to TMAX 800 560 1 4 1.5 150 −40 1 See the Typical Performance Characteristics section for more information. With all digital inputs forced to VDD or GND, as required. 3 During acquisition phase. 2 Rev. A | Page 3 of 16 V V V dB nA 10 100 2.9 50 −0.3 0.7 × VDD −1 −1 Unit Bits AD7683 VDD = 5 V; VREF = VDD; TA = –40°C to +85°C, unless otherwise noted. Table 3. VDD = 5 V ± 5% ±3 0.5 ±2 ±0.3 ±0.7 ±0.3 ±0.05 AC ACCURACY Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Effective Number of Bits fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz 90 −100 −100 90 14.7 1 2 Conditions Min A Grade Typ Max Parameter ACCURACY No Missing Codes Integral Linearity Error Transition Noise Gain Error 1 , TMIN to TMAX Gain Error Temperature Drift Offset Error1, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity 15 −6 +6 Min 16 −3 ±24 ±1.6 88 88 B Grade Typ Max Unit ±1 0.5 ±2 ±0.3 ±0.4 ±0.3 ±0.05 Bits LSB LSB LSB ppm/°C mV ppm/°C LSB +3 ±15 ±1.6 dB 2 dB dB dB Bits 91 −108 −106 91 14.8 See the Terminology section. These specifications include full temperature range variation but do not include the error contribution from the external reference. All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. VDD = 2.7 V; VREF = 2.5V; TA = –40°C to +85°C, unless otherwise noted. Table 4. Parameter ACCURACY No Missing Codes Integral Linearity Error Transition Noise Gain Error 1 , TMIN to TMAX Gain Error Temperature Drift Offset Error1, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Effective Number of Bits 1 2 Conditions Min 15 −6 A Grade Typ Max VDD = 2.7 V ±5% ±3 0.85 ±2 ±0.3 ±0.7 ±0.3 ±0.05 fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz 85 −96 −94 85 13.8 +6 ±30 ±3.5 Min 16 −3 B Grade Typ Max Unit ±1 0.85 ±2 ±0.3 ±0.7 ±0.3 ±0.05 Bits LSB LSB LSB ppm/°C mV ppm/°C LSB 86 −100 −98 86 14 +3 ±15 ±3.5 dB 2 dB dB dB Bits See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. Rev. A | Page 4 of 16 AD7683 TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; TA = −40°C to +85°C, unless otherwise noted. Table 5. Parameter Throughput Rate CS Falling to DCLOCK Low CS Falling to DCLOCK Rising DCLOCK Falling to Data Remains Valid CS Rising Edge to DOUT High Impedance DCLOCK Falling to Data Valid Acquisition Time DOUT Fall Time DOUT Rise Time Symbol tCYC tCSD tSUCS tHDO tDIS tEN tACQ tF tR Min Typ 20 5 Max 100 0 16 14 16 100 50 11 11 25 25 Unit kHz μs ns ns ns ns ns ns ns 400 Timing and Circuit Diagrams tCYC COMPLETE CYCLE CS tSUCS tACQ POWER DOWN 1 4 5 tCSD DOUT tEN HIGH-Z tDIS tHDO D15 D14 D13 D12 D11 D10 D9 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 (MSB) (LSB) NOTES 1. A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES. DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING. Figure 2. Serial Interface Timing 500µA 1.4V CL 100pF 500µA 04301-003 TO DOUT IOL IOH Figure 3. Load Circuit for Digital Interface Timing 2V 0.8V tEN 2V 0.8V 04301-004 tEN 2V 0.8V Figure 4. Voltage Reference Levels for Timing 10% tR tF Figure 5. DOUT Rise and Fall Timing Rev. A | Page 5 of 16 04301-006 90% DOUT HIGH-Z 04301-002 DCLOCK AD7683 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Analog Inputs +IN1, –IN1 REF Supply Voltages VDD to GND Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Lead Temperature Range Vapor Phase (60 sec) Infrared (15 sec) 1 Rating GND − 0.3 V to VDD + 0.3 V or ±130 mA GND − 0.3 V to VDD + 0.3 V −0.3 V to +6 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −65°C to +150°C 150°C JEDEC J-STD-20 215°C 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Table 7. Thermal Resistance Package Type 8-Lead MSOP ESD CAUTION See the Analog Input section. Rev. A | Page 6 of 16 θJA 200 θJC 44 Unit °C/W AD7683 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF 1 8 AD7683 VDD DCLOCK TOP VIEW 6 DOUT (Not to Scale) GND 4 5 CS 7 –IN 3 04301-005 +IN 2 Figure 6. 8-Lead MSOP and QFN (LFCSP) Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 Mnemonic REF Type 1 AI 2 +IN AI 3 –IN AI 4 5 GND CS P DI 6 7 8 DOUT DCLOCK VDD DO DI P 1 Function Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. Decouple the REF pin closely to the GND pin with a ceramic capacitor of a few μF. Analog Input. It is referred to Pin –IN. The voltage range, that is, the difference between +IN and –IN, is 0 V to VREF. Analog Input Ground Sense. Connect this pin to either the analog ground plane or a remote sense ground. Power Supply Ground. Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as soon as the conversion is completed. It also enables DOUT. When high, DOUT is high impedance. Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK. Serial Data Clock Input. Power Supply. AI = analog input; DI = digital input; DO = digital output; and P = power. Rev. A | Page 7 of 16 AD7683 TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 21). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition should occur at a level ½ LSB above analog ground (38.1 μV for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111...10 to 111...11) should occur for an analog voltage 1½ LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD (as represented by S/(N+D)) by the following formula and is expressed in bits: ENOB = (S /[N + D ]dB − 1.76 ) / 6.02 Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Aperture Delay Aperture delay is a measure of the acquisition performance and is the time between the falling edge of the CS input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. Rev. A | Page 8 of 16 AD7683 TYPICAL PERFORMANCE CHARACTERISTICS 3 3 POSITIVE DNL = +0.43LSB NEGATIVE DNL = –0.41LSB 2 1 1 0 0 –1 –1 –2 –2 –3 0 16384 32768 49152 –3 65536 04301-011 DNL (LSB) 2 04301-012 INL (LSB) POSITIVE INL = +0.43LSB NEGATIVE INL = –0.97LSB 0 16384 32768 CODE 49152 65536 CODE Figure 7. Integral Nonlinearity vs. Code Figure 10. Differential Nonlinearity vs. Code 7000 120000 62564 VDD = REF = 2.5V VDD = REF = 5V 102287 6000 100000 5000 4000 COUNTS COUNTS 80000 35528 3000 60000 25440 40000 2000 0 1 50 04301-009 0 0 4604 2755 130 0 0 8 0 79FD 79FE 79FF 7A00 7A01 7A02 7A03 7A04 7A05 7A06 7A07 7A08 0 0 0 AMPLITUDE (dB OF FULL SCALE) –80 –100 –120 –140 0 10 20 30 40 –40 –60 –80 –100 –120 –140 –160 –180 50 FREQUENCY (kHz) 04301-007 –160 –180 0 7A16 16384 POINT FFT VDD = REF = 2.5V fS = 100kSPS fIN = 20.43kHz SNR = 88.7dB THD = –102.6dB SFDR = –104.6dB –20 04301-008 AMPLITUDE (dB OF FULL SCALE) –60 0 7A15 Figure 11. Histogram of a DC Input at the Code Center 16384 POINT FFT VDD = REF = 5V fS = 100kSPS fIN = 20.43kHz SNR = 92.7dB THD = –105.7dB SFDR = –106.4dB –40 7A11 7A12 7A13 7A14 CODE IN HEX Figure 8. Histogram of a DC Input at the Code Center –20 6 7A0E 7A0F 7A10 CODE IN HEX 0 13619 04301-010 15152 20000 1000 0 10 20 30 FREQUENCY (kHz) Figure 9. FFT Plot Figure 12. FFT Plot Rev. A | Page 9 of 16 40 50 AD7683 100 17 95 16 –80 SNR VREF 2.5V = –1dB ENOB THD (dB) 15 SINAD ENOB (Bits) –90 90 –95 VREF 5V = –1dB –100 85 14 2.5 3.0 3.5 4.0 4.5 5.0 13 5.5 –110 04301-015 80 2.0 04301-013 –105 0 40 80 REFERENCE VOLTAGE (V) 120 160 200 FREQUENCY (kHz) Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage Figure 15. THD vs. Frequency 100 1200 95 1000 fS = 100kSPS OPERATING CURRENT (µA) VREF = 5V, –10dB 90 VREF = 5V, –1dB 85 VREF = 2.5V, –1dB 80 75 600 400 0 50 100 150 0 2.0 200 FREQUENCY (kHz) 04301-017 70 800 200 04301-014 SINAD (dB) SNR, SINAD (dB) –85 2.5 3.0 3.5 4.0 4.5 SUPPLY (V) Figure 14. SINAD vs. Frequency Figure 16. Operating Current vs. Supply Rev. A | Page 10 of 16 5.0 5.5 AD7683 900 6 VDD = 5V, fS = 100kSPS 5 800 OFFSET, GAIN ERROR (LSB) OPERATING CURRENT (µA) 4 700 600 VDD = 2.7V, fS = 100kSPS 500 400 300 200 3 2 OFFSET ERROR 1 0 –1 –2 GAIN ERROR –3 04301-018 0 –55 –34 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 500 250 04301-019 POWER-DOWN CURRENT (nA) 750 –15 5 25 45 65 –6 –55 –35 –15 5 25 45 65 85 105 Figure 19. Offset and Gain Error vs. Temperature 1000 –35 –5 TEMPERATURE (°C) Figure 17. Operating Current vs. Temperature 0 –55 04301-016 –4 100 85 105 125 TEMPERATURE (°C) Figure 18. Power-Down Current vs. Temperature Rev. A | Page 11 of 16 125 AD7683 APPLICATIONS INFORMATION +IN SWITCHES CONTROL MSB REF 32,768C 16,384C LSB 4C 2C C SW+ C BUSY COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC OUTPUT CODE C MSB LSB SW– 04301-020 CNV –IN Figure 20. ADC Simplified Schematic CIRCUIT INFORMATION The AD7683 is a low power, single-supply, 16-bit ADC using a successive approximation architecture. The AD7683 is capable of converting 100,000 samples per second (100 kSPS) and powers down between conversions. When operating at 10 kSPS, for example, it consumes typically 150 μW with a 2.7 V supply, ideal for battery-powered applications. array between GND and REF, the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4...VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code. TRANSFER FUNCTIONS ADC CODE (STRAIGHT BINARY) The AD7683 is specified from 2.7 V to 5.5 V. It is housed in an 8-lead MSOP or a tiny, 8-lead QFN (LFCSP) package. The AD7683 is an improved second source to the ADS8320 and ADS8325. For even better performance, consider the AD7685. CONVERTER OPERATION The AD7683 is a successive approximation ADC based on a charge redistribution DAC. Figure 20 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary-weighted capacitors that connect to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the +IN and −IN inputs. When the acquisition phase is complete and the CS input goes low, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs, +IN and −IN, captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor 111...111 111...110 111...101 000...010 000...001 000...000 –FS –FS + 1 LSB +FS – 1 LSB +FS – 1.5 LSB –FS + 0.5 LSB ANALOG INPUT 04301-021 The AD7683 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple, multiplexed channel applications. The ideal transfer function for the AD7683 is shown in Figure 21 and Table 9. Figure 21. ADC Ideal Transfer Function Table 9. Output Codes and Ideal Input Voltages Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 1 Analog Input VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 μV 0V Digital Output Code Hexadecimal FFFF 1 8001 8000 7FFF 0001 0000 2 This is also the code for an overranged analog input (V+IN – V–IN above VREF – VGND). 2 This is also the code for an underranged analog input (V+IN – V–IN below VGND). Rev. A | Page 12 of 16 AD7683 (NOTE 1) REF 100nF REF 33Ω VDD +IN 0V TO VREF AD7683 2.7nF (NOTE 3) 2.7V TO 5.25V CREF 2.2µF TO 10µF (NOTE 2) –IN (NOTE 4) DCLOCK DOUT 3-WIRE INTERFACE CS GND 04301-022 NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). 3. SEE DRIVER AMPLIFIER CHOICE SECTION. 4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION. Figure 22. Typical Application Diagram TYPICAL CONNECTION DIAGRAM Figure 22 shows an example of the recommended application diagram for the AD7683. ANALOG INPUT Figure 23 shows an equivalent circuit of the input structure of the AD7683. The two diodes, D1 and D2, provide ESD protection for the analog inputs, +IN and −IN. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this causes these diodes to become forward-biased and start conducting current. However, these diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions can eventually occur when the input buffer (U1) supplies are different from VDD. In such a case, use an input buffer with a short-circuit current limitation to protect the part. pass filter that reduces undesirable aliasing effects and limits the noise. When the source impedance of the driving circuit is low, the AD7683 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. DRIVER AMPLIFIER CHOICE Although the AD7683 is easy to drive, the driver amplifier needs to meet the following requirements: • The noise generated by the driver amplifier needs to be kept as low as possible to preserve the SNR and transition noise performance of the AD7683. Note that the AD7683 has a noise figure much lower than most other 16-bit ADCs and, therefore, can be driven by a noisier op amp while preserving the same or better system performance. The noise coming from the driver is filtered by the AD7683 analog input circuit, 1-pole, low-pass filter made by RIN and CIN or by the external filter, if one is used. • For ac applications, the driver needs to have a THD performance suitable to that of the AD7683. Figure 15 shows the THD vs. frequency that the driver should exceed. • For multichannel multiplexed applications, the driver amplifier and the AD7683 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. VDD D1 +IN OR –IN CIN D2 04301-023 CPIN RIN GND Figure 23. Equivalent Analog Input Circuit This analog input structure allows the sampling of the differential signal between +IN and −IN. By using this differential input, small signals common to both inputs are rejected. For instance, by using −IN to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated. During the acquisition phase, the impedance of the analog input, +IN, can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 600 Ω and is a lumped component consisting of some serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, when the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low- Table 10. Recommended Driver Amplifiers Amplifier ADA4841 OP184 AD8605, AD8615 AD8519 AD8031 Rev. A | Page 13 of 16 Typical Application Very low noise and low power Low power, low noise, and low frequency 5 V single-supply, low power Low power and low frequency High frequency and low power AD7683 The AD7683 voltage reference input, REF, has a dynamic input impedance. Therefore, it should be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. DCLOCK falling edges. The data is valid on both DCLOCK edges. Although the rising edge can be used to capture the data, a digital host also using the DCLOCK falling edge allows a faster reading rate, provided it has an acceptable hold time. CONVERT When REF is driven by a very low impedance source (such as an unbuffered reference voltage like the low temperature drift ADR43x reference or a reference buffer using the AD8031 or the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If desired, smaller reference decoupling capacitors with values as low as 2.2 μF can be used with a minimal impact on performance, especially DNL. POWER SUPPLY The AD7683 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure 24. This makes the part ideal for low sampling rates (even of a few Hz) and low batterypowered applications. 1000 VDD = 5V 10 1 0.1 0.01 10 100 1k 10k DCLOCK DOUT DATA IN CLK Figure 25. Connection Diagram LAYOUT Design the PCB that houses the AD7683 so that the analog and digital sections are separated and confined to certain areas of the board. The pin configuration of the AD7683, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7683 is used as a shield. Fast switching signals, such as CS or clocks, should never run near analog signal paths. Avoid crossover of digital and analog signals. Use at least one ground plane. It can be common or split between the digital and analog sections. In such a case, it should be joined underneath the AD7683. VDD = 2.7V 04301-024 OPERATING CURRENT (µA) 100 DIGITAL HOST CS AD7683 04301-025 VOLTAGE REFERENCE INPUT 100k SAMPLING RATE (SPS) Figure 24. Operating Current vs. Sampling Rate DIGITAL INTERFACE The AD7683 is compatible with SPI®, QSPI™, digital hosts, MICROWIRE™, and DSPs (for example, Blackfin® ADSP-BF53x or ADSP-219x). The connection diagram is shown in Figure 25 and the corresponding timing is given in Figure 2. A falling edge on CS initiates a conversion and the data transfer. After the fifth DCLOCK falling edge, DOUT is enabled and forced low. The data bits are then clocked, MSB first, by subsequent The AD7683 voltage reference input (REF) has a dynamic input impedance and should be decoupled with minimal parasitic inductances. Accomplish this by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and by connecting these pins with wide, low impedance traces. Finally, decouple the power supply, VDD, of the AD7683 with a ceramic capacitor, typically 100 nF, placed close to the AD7683. Connect it using short and large traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. EVALUATING THE AD7683 PERFORMANCE Other recommended layouts for the AD7683 are outlined in the evaluation board for the AD7683 (EVAL-AD7683CBZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3Z. Rev. A | Page 14 of 16 AD7683 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5 5.15 4.90 4.65 4 PIN 1 0.65 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.38 0.22 COPLANARITY 0.10 0.80 0.60 0.40 8° 0° 0.23 0.08 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 26. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions Shown in millimeters 0.35 0.30 0.25 0.65 BSC 8 5 PIN 1 INDEX AREA *EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 4 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.80 MAX 0.55 NOM 1 2.48 2.38 2.23 0.05 MAX 0.02 NOM 1.74 1.64 1.49 PIN 1 INDICATOR (R 0.19) *PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. 0.20 REF Figure 27. 8-Terminal Quad Flat No Lead Package (QFN) [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-3) Dimensions Shown in millimeters Rev. A | Page 15 of 16 022808-B 3.00 BSC SQ AD7683 ORDERING GUIDE Model AD7683ACPZRL 1 AD7683ACPZRL71 AD7683ARM AD7683ARMRL7 AD7683ARMZ1 AD7683ARMZRL71 AD7683BCPZRL1 AD7683BCPZRL71 AD7683BRM AD7683BRMRL7 AD7683BRMZ1 AD7683BRMZRL71 EVAL-AD7683CBZ1 EVAL-CONTROL BRD3Z1, 2 1 2 Integral Nonlinearity ±6 LSB max ±6 LSB max ±6 LSB max ±6 LSB max ±6 LSB max ±6 LSB max ±3 LSB max ±3 LSB max ±3 LSB max ±3 LSB max ±3 LSB max ±3 LSB max Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description QFN [LFCSP_WD] QFN [LFCSP_WD] MSOP MSOP MSOP MSOP QFN [LFCSP_WD] QFN [LFCSP_WD] MSOP MSOP MSOP MSOP Evaluation Board Controller Board Package Option CP-8-3 CP-8-3 RM-8 RM-8 RM-8 RM-8 CP-8-3 CP-8-3 RM-8 RM-8 RM-8 RM-8 Z= RoHS Compliant Part. This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. ©2004–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04301-0-2/08(A) Rev. A | Page 16 of 16 Branding C4G C4G C1L C1L C4G C4G C38 C38 C1C C1C C38 C38 Ordering Quantity Reel, 5,000 Reel, 1,500 Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000 Reel, 5,000 Reel, 1,500 Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000