AD7845KN

a FEATURES 12-Bit CMOS MDAC with Output Amplifier 4-Quadrant Multiplication Guaranteed Monotonic (TMIN to T MAX) Space-Saving 0.3" DIPs and 24- or 28-Terminal Surface Mount Packages Application Resistors On Chip for Gain Ranging, etc. Low Power LC 2MOS LC2MOS Complete 12-Bit Multiplying DAC AD7845 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Automatic Test Equipment Digital Attenuators Programmable Power Supplies Programmable Gain Amplifiers Digital-to-4–20 mA Converters GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7845 is the industry’s first 4-quadrant multiplying D/A converter with an on-chip amplifier. It is fabricated on the LC2MOS process, which allows precision linear components and digital circuitry to be implemented on the same chip. 1. Voltage Output Multiplying DAC The AD7845 is the first DAC which has a full 4-quadrant multiplying capability and an output amplifier on chip. All specifications include amplifier performance. The 12 data inputs drive latches which are controlled by standard CS and WR signals, making microprocessor interfacing simple. For stand-alone operation, the CS and WR inputs can be tied to ground, making all latches transparent. All digital inputs are TTL and 5 V CMOS compatible. 2. Matched Application Resistors Three application resistors provide an easy facility for gain ranging, voltage offsetting, etc. The output amplifier can supply ± 10 V into a 2 kΩ load. It is internally compensated, and its input offset voltage is low due to laser trimming at wafer level. For normal operation, RFB is tied to VOUT, but the user may alternatively choose RA, RB or RC to scale the output voltage range. 3. Space Saving The AD7845 saves space in two ways. The integration of the output amplifier on chip means that chip count is reduced. The part is housed in skinny 24-lead 0.3" DIP, 28-terminal LCC and PLCC and 24-terminal SOIC packages. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD7845* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DISCUSSIONS View a parametric search of comparable parts. View all AD7845 EngineerZone Discussions. DOCUMENTATION SAMPLE AND BUY Data Sheet Visit the product page to see pricing options. 2 • AD7845: LC MOS Complete 12-Bit Multiplying DAC Data Sheet TECHNICAL SUPPORT REFERENCE MATERIALS Submit a technical question or find your regional support number. Solutions Bulletins & Brochures • Digital to Analog Converters ICs Solutions Bulletin DOCUMENT FEEDBACK Submit feedback for this data sheet. DESIGN RESOURCES • AD7845 Material Declaration • PCN-PDN Information • Quality And Reliability • Symbols and Footprints This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified. 1 (V = +15 V, ⴞ 5%, V = –15 V, ⴞ 5%, V AD7845–SPECIFICATIONS V connected to R . V load = 2 k⍀, 100 pF. All specifications T to T unless otherwise noted.) DD OUT FB OUT Parameter REF = +10 V, AGND = DGND = O V, SS MIN MAX J Version K Version A Version B Version S Version T Version Units Test Conditions/Comments 12 12 12 12 12 12 Bits 1 LSB = ±1 ±1 ±1 ±1/2 ±3/4 ±1 ±1 ±1 ±1 ±1/2 ±3/4 ±1 ±1 ±1 ±1 ±1/2 ±3/4 ±1 LSB max LSB max LSB max ±2 ±3 ±1 ±2 ±2 ±3 ±1 ±2 ±2 ±4 ±1 ±3 All Grades Are Guaranteed Monotonic over Temperature DAC Register Loaded with All 0s. mV max mV max ±5 ±3 ±6 ±6 ±7 ±5 ±2 ±6 ±6 ±7 ±5 ±3 ±6 ±6 ±7 ±5 ±2 ±6 ±6 ±7 ±5 ±3 ±6 ±6 ±7 ±5 ±2 ±6 ±6 ±7 µV/°C typ LSB max LSB max LSB max LSB max Gain Temperature Coefficient; ±2 (∆Gain/∆Temperature) 2 ±2 ±2 ±2 ±2 ±2 ppm of FSR/°C RFB, VOUT Connected typ 8 16 8 16 8 16 8 16 8 16 8 16 kΩ min kΩ max Typical Input Resistance = 12 kΩ APPLICATION RESISTOR RATIO MATCHING 0.5 0.5 0.5 0.5 0.5 05 % max Matching Between RA, RB, RC DIGITAL INPUTS VIH (Input High Voltage) VIL (Input Low Voltage) IIN (Input Current) CIN (Input Capacitance) 2 2.4 0.8 ±1 7 2.4 0.8 ±1 7 2.4 0.8 ±1 7 2.4 0.8 ±1 7 2.4 0.8 ±1 7 2.4 0.8 ±1 7 V min V max µA max pF max ACCURACY Resolution Relative Accuracy at +25°C TMIN to T MAX Differential Nonlinearity Zero Code Offset Error at +25°C TMIN to T MAX Offset Temperature Coefficient; (∆Offset/∆Temperature) 2 Gain Error REFERENCE INPUT Input Resistance, Pin 17 POWER SUPPLY4 VDD Range VSS Range Power Supply Rejection ∆Gain/∆VDD ∆Gain/∆VSS IDD ISS VREF 212 = 2.4 mV RFB, VOUT Connected RC, VOUT Connected, VREF = +5 V RB, VOUT Connected, VREF = +5 V RA, VOUT Connected, VREF = +2.5 V Digital Inputs at 0 V and V DD 14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75 –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 –14.25/–15.75 14.25/15.75 14.25/15.75 –14.25/–15.75 –14.25/–15.75 V min/V max V min/V max ±0.01 ±0.01 6 4 ±0.01 ±0.01 6 4 ±0.01 ±0.01 6 4 % per % max % per % max mA max mA max VDD = +15 V ± 5%, VREF = –10 V VSS = –15 V ± 5%. VOUT Unloaded VOUT Unloaded To 0.01% of Full-Scale Range VOUT Load = 2 kΩ, 100 pF. DAC Register Alternately Loaded with All 0s and All 1s. Typically 2.5 µs at 25°C. VOUT Load = 2 kΩ, 100 pF. Measured with V REF = 0 V. DAC Register Alternately Loaded with All 0s and All 1s. VREF = ±10 V, 10 kHz Sine Wave DAC Register Loaded with All 0s. ±0.01 ±0.01 6 4 ±0.01 ±0.01 6 4 ±0.01 ±0.01 6 4 AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance and are not subject to test. DYNAMIC PERFORMANCE Output Voltage Settling Time 5 5 5 5 5 5 µs max Slew Rate Digital-to-Analog Glitch Impulse 11 55 11 55 11 55 11 55 11 55 11 55 V/µs typ nV–s typ Multiplying Feedthrough Error3 Unity Gain Small Signal Bandwidth 5 5 5 5 5 5 mV p-p typ 600 600 600 600 600 600 kHz typ Full Power Bandwidth 175 175 175 175 175 175 kHz typ Total Harmonic Distortion –90 –90 –90 –90 –90 –90 dB typ 85 85 85 85 85 dB min ±10 0.2 11 ±10 0.2 11 ±10 0.2 11 ±10 0.2 11 ±10 0.2 11 ±10 0.2 11 V min Ω typ mA typ 2 250 100 50 50 50 2 250 100 50 50 50 2 250 100 50 50 50 2 250 100 50 50 50 2 250 100 50 50 50 2 250 100 50 50 50 µV rms typ nV/√Hz typ nV/√Hz typ nV/√Hz typ nV/√Hz typ nV/√Hz typ OUTPUT CHARACTERISTICS5 Open Loop Gain 85 Output Voltage Swing Output Resistance Short Circuit Current @ +25°C Output Noise Voltage (0.1 Hz to 10 Hz) @ +25°C f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 100 kHz VOUT, RFB Connected. DAC Loaded with All 1s VREF = 100 mV p-p Sine Wave. VOUT, RFB Connected. DAC Loaded with All 1s. VREF = 20 V p-p Sine Wave. R L = 2 kΩ. VREF = 6 V rms, 1 kHz Sine Wave. VOUT, RFB Not Connected VOUT = ±10 V, RL = 2 kΩ RL = 2 kΩ, CL = 100 pF RFB, VOUT Connected, VOUT Shorted to AGND Includes Noise Due to Output Amplifier and Johnson Noise of RFB NOTES 1Temperature ranges are as follows: J, K Versions: 0°C to +70°C; A, B Versions: –40°C to +85°C; S, T Versions: –55°C to +125°C. 2Guaranteed by design and characterization, not production tested. 3The metal lid on the ceramic D-24A package is connected to Pin 12 (DGND). 4The device is functional with a power supply of ± 12 V. 5Minimum specified load resistance is 2 kΩ. Specifications subject to change without notice. –2– REV. B AD7845 TIMING CHARACTERISTICS1 (V DD = +15 V, ⴞ 5%. VSS = –15 V, ⴞ 5%. VREF = +10 V. AGND = DGND = O V.) Parameter Limit at TMIN to TMAX (All Versions) Units Test Conditions/Comments tCS tCH tWR tDS tDH 30 0 30 80 0 ns min ns min ns min ns min ns min Chip Select to Write Setup Time Chip Select to Write Hold Time Write Pulsewidth Data Setup Time Data Hold Time NOTES 1 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 (TA = +25°C unless otherwise stated) VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +17 V VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V VREF to AGND . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS – 0.3 V VRFB to AGND . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS – 0.3 V VRA to AGND . . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS – 0.3 V VRB to AGND . . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS – 0.3 V VRC to AGND . . . . . . . . . . . . . . . . . VDD + 0.3 V, VSS – 0.3 V VOUT to AGND2 . . . . . . . . . . . . . . . VDD + 0.3 V, VSS – 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V Power Dissipation (Any Package) To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW Derates above +75°C . . . . . . . . . . . . . . . . . . . . . 10 mW/°C Operating Temperature Range Commercial (J, K Versions) . . . . . . . . . . . . . 0°C to +70°C Industrial (A, B Versions) . . . . . . . . . . . . –40°C to +85°C Extended (S, T Versions) . . . . . . . . . . . . –55°C to +125°C Storage Temperature Range . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Only one Absolute Maximum Rating may be applied at any one time. 2 VOUT may be shorted to AGND provided that the power dissipation of the package is not exceeded. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7845 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE1 tCS Model2 Temperature Range Relative Accuracy @ +25ⴗC Package Option3 AD7845JN AD7845KN AD7845JP AD7845KP AD7845JR AD7845KR AD7845AQ AD7845BQ AD7845AR AD7845BR AD7845SQ/883B AD7845TQ/883B AD7845SE/883B 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –55°C to +125°C –55°C to +125°C –55°C to +125°C ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB N-24 N-24 P-28A P-28A R-24 R-24 Q-24 Q-24 R-24 R-24 Q-24 Q-24 E-28A 5V CS 0V tWR 5V WR 0V tDS tDH 5V DATA 0V NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. tR = tF = 20ns. V +V 2. TIMING MEASUREMENT REFERENCE LEVEL IS IH 2 IL Figure 1. AD7845 Timing Diagram NOTES 1Analog Devices reserves the right to ship either ceramic (D-24A) or cerdip (Q-24) hermetic packages. 2To order MIL-STD-883, Class B processed parts, add /883B to part number. 3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC. REV. B tCH –3– AD7845 PIN CONFIGURATIONS DIP, SOIC LCC PLCC TERMINOLOGY LEAST SIGNIFICANT BIT DIGITAL-TO-ANALOG GLITCH IMPULSE This is the analog weighting of 1 bit of the digital word in a V REF DAC. For the AD7845, 1 LSB = 12 . 2 This is the amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage. The measurement takes place with VREF = AGND. RELATIVE ACCURACY Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for both endpoints (i.e., offset and gain error are adjusted out) and is normally expressed in least significant bits or as a percentage of full-scale range. DIGITAL FEEDTHROUGH When the DAC is not selected (i.e., CS is high) high frequency logic activity on the device digital inputs is capacitively coupled through the device to show up as noise on the VOUT pin. This noise is digital feedthrough. DIFFERENTIAL NONLINEARITY MULTIPLYING FEEDTHROUGH ERROR Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of +1 LSB max over the operating temperature range ensures monotonicity. This is ac error due to capacitive feedthrough from the VREF terminal to VOUT when the DAC is loaded with all 0s. OPEN-LOOP GAIN Open-loop gain is defined as the ratio of a change of output voltage to the voltage applied at the VREF pin with all 1s loaded in the DAC. It is specified at dc. GAIN ERROR Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. Gain error is adjustable to zero with an external potentiometer. See Figure 13. UNITY GAIN SMALL SIGNAL BANDWIDTH This is the frequency at which the magnitude of the small signal voltage gain of the output amplifier is 3 dB below unity. The device is operated as a closed-loop unity gain inverter (i.e., DAC is loaded with all 1s). ZERO CODE OFFSET ERROR This is the error present at the device output with all 0s loaded in the DAC. It is due to the op amp input offset voltage and bias current and the DAC leakage current. OUTPUT RESISTANCE This is the effective output source resistance. TOTAL HARMONIC DISTORTION This is the ratio of the root-mean-square (rms) sum of the harmonics to the fundamental, expressed in dBs. FULL POWER BANDWIDTH Full power bandwidth is specified as the maximum frequency, at unity closed-loop gain, for which a sinusoidal input signal will produce full output at rated load without exceeding a distortion level of 3%. OUTPUT NOISE This is the noise due to the white noise of the DAC and the input noise of the amplifier. –4– REV. B Typical Performance Characteristics–AD7845 Figure 2. Frequency Response, G = –1 Figure 3. Output Voltage Swing vs. Resistive Load Figure 5. THD vs. Frequency Figure 6. Typical AD7845 Linearity vs. Power Supply Figure 4. Noise Spectral Density Figure 7. Multiplying Feedthrough Error vs. Frequency 80 70 60 OUTPUT – mV 50 40 30 20 10 0 –10 –20 Figure 8. Unity Gain Inverter Pulse Response (Large Signal) REV. B Figure 9. Unity Gain Inverter Pulse Response (Small Signal) –5– 0 2 4 6 8 10 12 14 16 TIME – s 18 20 Figure 10. Digital-to-Analog Glitch Impulse (All 1s to All 0s Transition) AD7845 PIN FUNCTION DESCRIPTION (DIP) Pin Mnemonic Description 1 2-11 12 13-14 15 16 17 18 19 20 21 22 23 24 VOUT DB11–DB2 DGND DB1–DB0 WR CS VREF AGND VSS VDD RA RB RC RFB Voltage Output Terminal Data Bit 11 (MSB) to Data Bit 2 Digital Ground. The metal lid on the ceramic package is connected to this pin Data Bit 1 to Data Bit 0 (LSB) Write Input. Active low Chip Select Input. Active low Reference Input Voltage which can be an ac or dc signal Analog Ground. This is the reference point for external analog circuitry Negative power supply for the output amplifier (nominal –12 V to +15 V) Positive power supply (nominal +12 V to +15 V) Application resistor. RA = 4 RFB Application resistor. RB = 2 RFB Application resistor. RC = 2 RFB Feedback resistor in the DAC. For normal operation this is connected to VOUT CIRCUIT INFORMATION Digital Section Each of the switches A–C steers 1/4 of the total reference current with the remaining 1/4 passing through the R-2R section. Figure 11 is a simplified circuit diagram of the AD7845 input control logic. When CS and WR are both low, the DAC latch is loaded with the data on the data inputs. All the digital inputs are TTL, HCMOS and +5 V CMOS compatible, facilitating easy microprocessor interfacing. All digital inputs incorporate standard protection circuitry. An output amplifier and feedback resistor perform the currentto-voltage conversion giving VOUT = – D × VREF where D is the fractional representation of the digital word. (D can be set from 0 to 4095/4096.) The amplifier can maintain ± 10 V across a 2 kΩ load. It is internally compensated and settles to 0.01% FSR (1/2 LSB) in less than 5 µs. The input offset voltage is laser trimmed at wafer level. The amplifier slew rate is typically 11 V/µs, and the unity gain small signal bandwidth is 600 kHz. There are three extra on-chip resistors (RA, R B, RC ) connected to the amplifier inverting terminal. These are useful in a number of applications including offset adjustment and gain ranging. VREF R R R Figure 11. AD7845 Input Control Logic D/A Section 2R 2R C B 2R 2R 2R 2R A S9 S8 S0 Figure 12 shows a simplified circuit diagram for the AD7845 D/A section and output amplifier. 2R IOUT A segmented scheme is used whereby the 2 MSBs of the 12-bit data word are decoded to drive the three switches A-C. The remaining 10 bits drive the switches (S0–S9) in a standard R-2R ladder configuration. –6– SHOWN FOR ALL 1s ON DAC AGND Figure 12. Simplified Circuit Diagram for the AD7845 D/A Section REV. B AD7845 UNIPOLAR BINARY OPERATION Figure 13 shows the AD7845 connected for unipolar binary operation. When VIN is an ac signal, the circuit performs 2-quadrant multiplication. The code table for Figure 13 is given in Table I. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) The recommended circuit for bipolar operation is shown in Figure 14. Offset binary coding is used. The offset specification of this circuit is determined by the matching of internal resistors RB and RC and by the zero code offset error of the device. Gain error may be adjusted by varying the ratio of R1 and R2. To use this circuit without trimming and keep within the gain error specifications, resistors R1 and R2 should be ratio matched to 0.01%. The code table for Figure 14 is given in Table II. Figure 13. Unipolar Binary Operation Table I. Unipolar Binary Code Table for AD7845 Binary Number In DAC Register Analog Output, VOUT MSB 1111 1111 LSB 1111  4095  –VIN    4096  1000 0000 0000  2048  –VIN   = –1/2 VIN  4096  0000 0000 0001  1  –VIN    4096  0000 0000 0000 0V OFFSET AND GAIN ADJUSTMENT FOR FIGURE 13 Zero Offset Adjustment Figure 14. Bipolar Offset Binary Operation Table II. Bipolar Code Table for Offset Binary Circuit of Figure 14 Binary Number In DAC Register Analog Output, VOUT MSB 1111 1111 LSB 1111  2047  +V IN    2048  1000 0000 0001  1  +V IN    2048  1000 0000 0000 0V 0111 1111 1111  1  –VIN    2048  0000 0000 0000  2048  –VIN  2048  = –VIN   1. Load DAC with all 0s. 2. Trim R3 until VOUT = 0 V. Gain Adjustment 1. Load DAC with all 1s. 2. Trim R1 so that VOUT = –VIN 4095 . 4096 In fixed reference applications, full scale can also be adjusted by omitting R1 and R2 and trimming the reference voltage magnitude. For high temperature applications, resistors and potentiometers should have a low temperature coefficient. REV. B –7– AD7845 APPLICATION S CIRCUITS PROGRAMMABLE GAIN AMPLIFIER (PGA) PROGRAMMABLE CURRENT SOURCES The AD7845 is ideal for designing programmable current sources using a minimum of external components. Figures 16 and 17 are examples. The circuit of Figure 16 drives a programmable current IL into a load referenced to a negative supply. Figure 17 shows the circuit for sinking a programmable current, IL. The same set of circuit equations apply for both diagrams. The AD7845 performs a PGA function when connected as in Figure 15. In this configuration, the R-2R ladder is connected in the amplifier feedback loop. RFB is the amplifier input resistor. As the code decreases, the R-2R ladder resistance increases and so the gain increases. VOUT = –VIN ×  1 4095  RDAC × ,  D = 0 to  RFB  4096  D IL = I3 = I2 + I1 1 R –VIN = –VIN × DAC × = , since RFB = RDAC R DAC D D  4095   D = 0 to  4096   I1 = D ×|V IN | , RDAC I2 = 1  D ×|V IN | D ×|V IN | R = , since RFB = RDAC R1  RDAC  FB R1 IL = D ×|V IN | D ×|V IN | + RDAC R1 = D ×|V IN | × R1  R1  1 +  RDAC   Note that by making R1 much smaller than RDAC, the circuit becomes insensitive to both the absolute value of RDAC and its temperature variations. Now, the only resistor determining load current IL is the sense resistor R1. If R1 = 100 Ω, then the programming range is 0 mA to 100 mA, and the resolution is 0.024 mA. Figure 15. AD7845 Connected as PGA As the programmed gain increases, the error and noise also increase. For this reason, the maximum gain should be limited to 256. Table III shows gain versus code. Note that instead of using RFB as the input resistor, it is also possible to use combinations of the other application resistors, RA, R B and RC. For instance, if RB is used instead of RFB , the gain range for the same codes of Table II now goes from l/2 to 128. Table III. Gain and Error vs. Input Code for Figure 15 Digital Inputs 1111 1000 0100 0010 0001 0000 0000 0000 0000 1111 0000 0000 0000 0000 1000 0100 0010 0001 1111 0000 0000 0000 0000 0000 0000 0000 0000 Gain Error (%) 4096/4095 ≈ 1 2 4 8 16 32 64 128 256 0.04 0.07 0.13 0.26 0.51 1.02 2.0 4.0 8.0 Figure 16. Programmable Current Source –8– REV. B AD7845 Figure 18. 4–20 mA Current Loop Figure 17. Programmable Current Sink 4–20 mA CURRENT LOOP APPLICATION HINTS The AD7845 provides an excellent way of making a 4-20 mA current loop circuit. This is basically a variation of the circuits in Figures 16 and 17 and is shown in Figure 18. The application resistor RA (Value 4R) produces the effective 4 mA offset. General Ground Management: AC or transient voltages between AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7845. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7845 AGND and DGND pins (IN914 or equivalent). IL = I3 = I2 + I1 Since I2 > I1, IL = –  2.5  2.5 VX × D × RFB  × 1 =  4R × RFB + R   DAC 156 156 and since RDAC=RFB=R  2.5  1000 IL =  4 + D × 2.5 × 156 mA   = [4 + (16 × D)]mA, where D goes from 0 to 1 with Digital Code When D = 0 (Code of all 0s): IL = 4 mA When D = 1 (Code of all 1s): IL = 20 mA The above circuit succeeds in significantly reducing the circuit component count. Both the on-chip output amplifier and the application resistor RA contribute to this. Digital Glitches: When a new digital word is written into the DAC, it results in a change of voltage applied to some of the DAC switch gates. This voltage change is coupled across the switch stray capacitance and appears as an impulse on the current output bus of the DAC. In the AD7845, impulses on this bus are converted to a voltage by RFB and the output amplifier. The output voltage glitch energy is specified as the area of the resulting spike in nV-seconds. It is measured with VREF connected to analog ground and for a zero to full-scale input code transition. Since microprocessor based systems generally have noisy grounds which couple into the power supplies, the AD7845 VDD and VSS terminals should be decoupled to signal ground. Temperature Coefficients: The gain temperature coefficient of the AD7845 has a maximum value of 5 ppm/°C. This corresponds to worst case gain shift of 2 LSBs over a 100°C temperature range. When trim resistors R1 and R2 in Figure 13 are used to adjust full-scale range, the temperature coefficient of R1 and R2 must be taken into account. The offset temperature coefficient is 5 ppm of FSR/°C maximum. This corresponds to a worst case offset shift of 2 LSBs over a 100°C temperature range. The reader is referred to Analog Devices Application Note “Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs,” Publication Number E630C-5-3/86. REV. B –9– AD7845 MICROPROCESSOR INTERFACING 16-BIT MICROPROCESSOR SYSTEMS Figures 19, 20 and 21 show how the AD7845 interfaces to three popular 16-bit microprocessor systems. These are the MC68000, 8086 and the TM32010. The AD7845 is treated as a memory-mapped peripheral to the processors. In each case, a write instruction loads the AD7845 with the appropriate data. The particular instructions used are as follows: MC68000: MOVE 8086: MOV 8-BIT MICROPROCESSOR SYSTEMS Figure 22 shows an interface circuit for the AD7845 to the 8085A 8-bit microprocessor. The software routine to load data to the device is given in Table IV. Note that the transfer of the 12 bits of data requires two write operations. The first of these loads the 4 MSBs into the 7475 latch. The second write operation loads the 8 LSBs plus the 4 MSBs (which are held by the latch) into the DAC. TMS32010: OUT Figure 22. 8085A Interface Table IV. Subroutine Listing for Figure 22 Figure 19. AD7845 to MC68000 Interface 2000 LOAD DAC: LXI MVI MOV INR MVI MOV Figure 20. AD7845 to 8086 Interface RET H,#3000 The H,L register pair are loaded with latch address 3000. A,#“MS” Load the 4 MSBs of data into accumulator. M,A Transfer data from accumulator to latch. L Increment H,L pair to AD7845 address. A,#“LS” Load the 8 LSBs of data into accumulator. M,A Transfer data from accumulator to DAC. End of routine. Figure 21. TMS32010 –10– REV. B AD7845 Figure 23 and 24 are the interface circuits for the Z80 and MC6809 microprocessors. Again, these use the same basic format as the 8085A interface. DIGITAL FEEDTHROUGH In the preceding interface configurations, most digital inputs to the AD7845 are directly connected to the microprocessor bus. Even when the device is not selected, these inputs will be constantly changing. The high frequency logic activity on the bus can feed through the DAC package capacitance to show up as noise on the analog output. To minimize this digital feedthrough isolate the DAC from the noise source. Figure 25 shows an interface circuit which uses this technique. All data inputs are latched from the busy by the CS signal. One may also use other means, such as peripheral interface devices, to reduce the digital feedthrough. Figure 23. AD7845 to Z80 Interface Figure 25. AD7845 Interface Circuit Using Latches to Minimize Digital Feedthrough Figure 24. MC6809 Interface REV. B –11– AD7845 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Terminal Leadless Ceramic Chip Carrier (E-28A) 24-Lead Cerdip (Q-24) 28-Terminal Plastic Leaded Chip Carrier (P-28A) 24-Lead Ceramic DIP (D-24A) 24-Lead SOIC (R-24) C1189b–1–9/99 24-Lead Plastic DIP (N-24) 0.6141 (15.60) 0.5985 (15.20) 24 13 1 PIN 1 0.0118 (0.30) 0.0500 0.0040 (0.10) (1.27) BSC –12– 12 0.4193 (10.65) 0.3937 (10.00) 0.1043 (2.65) 0.0926 (2.35) 88 08 0.0192 (0.49) SEATING 0.0125 (0.32) PLANE 0.0138 (0.35) 0.0091 (0.23) 0.0291 (0.74) 3 458 0.0098 (0.25) 0.0500 (1.27) 0.0157 (0.40) REV. B PRINTED IN U.S.A. 0.2992 (7.60) 0.2914 (7.40)