LC2MOS
Complete 14-Bit, Sampling ADCs
AD7871/AD7872
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Complete monolithic 14-bit ADC
Twos complement coding
Parallel, byte, and serial digital interface
80 dB SNR at 10 kHz input frequency
57 ns data access time
Low power: 50 mW typ
83 kSPS throughput rate
AGND
CREF
22
23
VDD
REF OUT VIN
25
26
21
TRACKAND-HOLD
R
R
COMP
3V
REFERENCE
CLK
APPLICATIONS
14-BIT
DAC
CLOCK
5
SAR +
COUNTER
14/8/CLK 28
CONTROL
LOGIC
CONVST 1
PARALLEL
AND SERIAL
INTERFACE
2
GENERAL DESCRIPTION
CS
4
6
20
14
27
DB13
DB0
DGND
VSS
Figure 1.
The AD7871/AD7872 are fast, complete, 14-bit analog-todigital converters (ADC). They consist of a track-and-hold
amplifier, successive approximation ADC, 3 V buried Zener
reference, and versatile interface logic. The ADC features a selfcontained, laser trimmed internal clock, so no external clock
timing components are required. The on-chip clock may be
overridden to synchronize ADC operation to the digital system
for minimum noise.
AGND
CREF
12
11
REF OUT VIN
13
3V
REFERENCE
3
VDD
9
16
TRACKAND-HOLD
R
CLK
VDD
14
R
The AD7871 offers a choice of three data output formats: a
single, parallel, 14-bit word; two 8-bit bytes or a 14-bit serial
data stream. The AD7872 is a serial output device only. The two
parts are capable of interfacing to all modern microprocessors
and digital signal processors.
COMP
14-BIT
DAC
CLOCK
SAR +
COUNTER
CONVST 2
CONTROL
LOGIC
SERIAL
INTERFACE
4
5
AD7872
6
SSTRB SCLK SDATA
8
15
DGND
VSS
12889-002
CONTROL 1
The AD7871/AD7872 operate from ±5 V power supplies,
accept bipolar input signals of ±3 V and can convert full power
signals up to 41.5 kHz.
In addition to the traditional dc accuracy specifications, the
AD7871/AD7872 are also fully specified for dynamic
performance parameters including distortion and signal-tonoise ratio.
3
RD BUSY/INT
AD7871
12889-001
Digital signal processing
High speed modems
Speech recognition and synthesis
Spectrum analysis
DSP servo control
Figure 2.
Both devices are fabricated in Analog Devices, Inc., LC2MOS
mixed technology process. The AD7871 is available in 28-pin
PDIP, PLCC, and CERDIP packages. The AD7872 is available in
a 16-pin PDIP, CERDIP, and SOIC packages.
PRODUCT HIGHLIGHTS
1.
2.
3.
Rev. F
Complete 14-Bit ADC on a Chip.
Dynamic Specifications for DSP Users.
Low Power.
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
©2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD7871/AD7872
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Unipolar Offset And Full-Scale Adjustment .......................... 11
Applications ....................................................................................... 1
Timing and Control ................................................................... 12
General Description ......................................................................... 1
Data Output Formats ................................................................. 12
Functional Block Diagrams ............................................................. 1
Mode 1 Interface......................................................................... 13
Product Highlights ........................................................................... 1
Mode 2 Interface......................................................................... 14
Revision History ............................................................................... 2
Dynamic Specifications ............................................................. 15
Specifications..................................................................................... 3
Microprocessor Interface .......................................................... 16
Timing Characteristics ................................................................ 5
StandAlone Operation ............................................................... 17
Absolute Maximum Ratings............................................................ 6
Applications Information .............................................................. 18
ESD Caution .................................................................................. 6
Layout Hints ................................................................................ 18
Pin Configuration and Function Descriptions ............................. 7
Noise ............................................................................................ 18
Theory of Operation ...................................................................... 10
Data Acquisition Board ............................................................. 18
Converter Details........................................................................ 10
Interface Connections ............................................................... 19
Internal Reference ...................................................................... 10
Power Supply Connections ....................................................... 19
Track-And-Hold Amplifier ....................................................... 10
Shorting Plug Options ............................................................... 19
Analog Input ............................................................................... 10
Outline Dimensions ....................................................................... 22
Bipolar Offset Scale Adjustment .............................................. 11
Ordering Guide .......................................................................... 25
Unipolar Operation .................................................................... 11
REVISION HISTORY
11/2018—Rev. E to Rev. F
Change to Integral Nonlinearity, T Version Parameter, Table 1 ...... 3
Added Figure 6; Renumbered Sequentially .................................. 7
Added Figure 9 .................................................................................. 9
Changes to Ordering Guide ............................................................ 24
1/2015—Rev. D to Rev. E
Updated Format .................................................................. Universal
Changed T Version Minimum SNR from 79 dB to 77 dB and
Changed T Version Maximum INL from ±1 LSB to ±1.3 LSB... 3
Deleted ADSP-2100 and TMS32020/C25 (Throughout).......... 15
Deleted DSP56000 and ADSP-2101/ADSP-2102 (Throughout)... 16
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 24
1/1997—Rev. C to Rev. D
Rev. F | Page 2 of 25
Data Sheet
AD7871/AD7872
SPECIFICATIONS
VDD = +5 V ± 5%, VSS = −5 V ± 5%, AGND = DGND = 0 V, fCLK = 2 MHz external, fSAMPLE = 83 kHz, all specifications TMIN to TMAX; unless
otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE2
Signal-to-Noise Ratio3 (SNR) at
+25°C
TMIN to TMAX
Total Harmonic Distortion
(THD)
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
Second-Order Terms
J, A
Versions1
K
Version1
B
Version1
T
Version1
Unit
Test Conditions/Comments
80
80
79
77
dB min
VIN = 10 kHz sine wave
80
−86
80
−88
79
77
dB min
dB max
VIN = 10 kHz sine wave
−86
−88
−85
−85
−85
−85
−86
−88
dB max
−86
−88
2
2
−85
2
−85
2
dB typ
μs max
14
14
14
14
14
14
14
14
Bits
Bits
±12
±12
±12
±½
±1
±12
±12
±12
±½
±1
±12
±12
±12
±½
±2
±12
±12
±12
LSB typ
LSB max
LSB max
LSB max
LSB max
±3
±500
±3
±500
±3
±500
±3
±500
V
μA max
2.99/3.01
2.99/3.01
2.99/3.01
2.99/3.01
2.98/3.02
2.98/3.02
2.98/3.02
2.98/3.02
±1.2
±40
±1.2
±40
±1.2
±40
±1.2
V min/V
max
V min/V
max
ppm/°C max
mV max
2.4
0.8
±10
±10
2.4
0.8
±10
±10
2.4
0.8
±10
±10
2.4
0.8
±10
±10
V min
V max
μA max
μA max
10
10
10
10
pF max
−85
Third-Order Terms
Track/Hold Acquisition Time
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes Are
Guaranteed
Integral Nonlinearity at +25°C
Integral Nonlinearity
Bipolar Zero Error
Positive Gain Error4
Negative Gain Error4
ANALOG INPUT
Input Voltage Range
Input Current
REFERENCE OUTPUT
REF OUT at +25°C
TMIN to TMAX
REF OUT Tempco
Reference Load Sensitivity
(ΔREF OUT/ΔI)
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Current (14/8/CLK Input
Only)
Input Capacitance, CIN5
dB typ
dB max
dB typ
−85
Rev. F | Page 3 of 25
dB typ
dB max
VIN = 10 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE =
50 kHz
fa = 9 kHz, fb = 9.5 kHz, fSAMPLE =
50 kHz
Typically 35 ppm
Reference load current change
(0 μA to 300 μA); reference load
should not be changed during
conversion
VDD = 5 V ±5%
VDD = 5 V ±5%
VIN = 0 V to VDD
VIN = VSS to VDD
AD7871/AD7872
Parameter
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
DB13 to DB0
Floating-State Leakage
Current
Floating-State Output
Capacitance5
CONVERSION TIME
External Clock
Internal Clock
POWER REQUIREMENTS
VDD
VSS
IDD
ISS
Power Dissipation
Data Sheet
J, A
Versions1
K
Version1
B
Version1
T
Version1
Unit
Test Conditions/Comments
4.0
0.4
4.0
0.4
4.0
0.4
4.0
0.4
V min
V max
ISOURCE = 40 μA
ISINK = 1.6 mA
10
10
10
10
μA max
15
15
15
15
pF max
10
10.5
10
10.5
10
11
10
11
μs max
μs max
+5
−5
13
6
95
+5
−5
13
6
95
+5
−5
13
6
95
+5
−5
13
6
95
V nom
V nom
mA max
mA max
mW max
1
Temperature ranges are as follows: J, K versions, 0°C to +70°C; A, B versions, −40°C to +85°C; T version; −55°C to +125°C.
VIN = ±3 V.
SNR calculation includes distortion and noise components.
4
Measured with respect to internal reference.
5
Sample tested at +25°C to ensure compliance.
2
3
Rev. F | Page 4 of 25
The internal clock has a nominal
value of 2 MHz
±5% for specified performance
±5% for specified performance
Typically 6 mA
Typically 4 mA
Typically 50 mW
Data Sheet
AD7871/AD7872
TIMING CHARACTERISTICS
VDD = +5 V ± 5%, VSS = −5 V ± 5%, AGND = DGND = 0 V. See Figure 16, Figure 17, Figure 18, and Figure 19.
Table 2.
Parameter1
t1
t2
t32
t4
t5
t62, 3
t72, 4
t8
t9
t10
t115
t126
t13
t14
t15
t16
t173
t18
t19
t20
Limit at TMIN, TMAX
(J, K, A, B Versions)
50
0
60
0
70
57
5
50
0
0
100
440
155
140
20
4
100
60
120
200
0
0
0
Limit at TMIN, TMAX
(T Version)
50
0
75
0
70
70
5
50
0
0
100
440
155
150
20
4
100
60
120
200
0
0
0
Unit
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
Test Conditions/Comments
CONVST pulse width
CS to RD setup time (Mode 1)
RD pulse width
CS to RD hold time (Mode 1)
RD to INT delay
Data access time after RD
Bus relinquish time after RD
HBEN to RD setup time
HBEN to RD hold time
SSTRB to SCLK falling edge setup time
SCLK cycle time
SCLK to VALID DATA DELAY; CL = 35 pF
SCLK rising edge to SSTRB
Bus relinquish time after SCLK
CS to RD setup time (Mode 2)
CS to BUSY propagation delay
Data set up time prior to BUSY
CS to RD hold time (Mode 2)
HBEN to CS setup time
HBEN to CS hold time
Serial timing is measured with a 4.7 kΩ pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up resistor on SCLK. The capacitance on all three outputs is 35 pF.
These timing specifications are 100% production tested. All other times are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf =
5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3
t6 and t17 are measured with the load circuits of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the Timing Characteristics is the true bus relinquish
time of the part and is independent of bus loading.
5
SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
6
SDATA will drive higher capacitive loads, but this will add to t12 because it increases the external RC time constant (4.7 kΩ||CL) and therefore the time to reach 2.4 V.
1
2
Rev. F | Page 5 of 25
AD7871/AD7872
Data Sheet
ABSOLUTE MAXIMUM RATINGS
IOL
1.6mA
Table 3.
TO OUTPUT
PIN
2.1V
CL
50pF
12889-003
Rating
−0.3 V to +7 V
+0.3 V to −7 V
−0.3 V to VDD + 0.3 V
VSS −0.3 V to VDD + 0.3 V
0 V to VDD
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
IOH
200µA
Figure 3. Load Circuit for Access Time
IOL
1.6mA
0°C to +70°C
−40°C to +85°C
−55°C to +125°C
−65°C to +150°C
+300°C
450 mW
6 mW/°C
TO OUTPUT
PIN
2.1V
CL
50pF
IOH
200µA
Figure 4. Load Circuit for Output Float Delay
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. F | Page 6 of 25
12889-004
Parameter
VDD to AGND
VSS to AGND
AGND to DGND
VIN to AGND
REF OUT, CREF to AGND
Digital Inputs to DGND
Digital Outputs to DGND
Operating Temperature Range
Commercial (J, K Versions)
Industrial (A, B Versions)
Extended (T Version)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Power Dissipation (Any Package) to +75°C
Derates above +75°C by
Data Sheet
AD7871/AD7872
BUSY/INT
4
25 REFOUT
CLK
5
DB13/HBEN
6
AD7871
TOP VIEW
(Not to Scale)
4
3
2
1
28
27
26
25 REFOUT
CLK 5
24 NC
DB13/HBEN 6
24 NC
DB12/SSTRB 7
23 CREF
22 AGND
23 CREF
AD7871
DB11/SCLK 8
22 AGND
TOP VIEW
(Not to Scale)
DB12/SSTRB
7
DB11/SCLK
8
21 VDD
DB10/SDATA
9
20 DB0/DB8
DB9 10
20 DB0/DB8
DB9 10
19 DB1/DB9
DB8 11
19 DB1/DB9
DB8 11
18 DB2/DB10
DB7 12
17 DB3/DB11
DB6 13
16 DB4/DB12
DGND 14
15 DB5/DB13
28
CS 2
27
VSS
RD 3
26
VIN
BUSY/INT 4
25
REFOUT
CLK 5
24
NC
DB12/SSTRB 7
AD7871
13
14
15
16
17
18
DB6
DGND
DB5/DB13
DB4/DB12
DB3/DB11
DB2/DB10
Figure 7. AD7871 PLCC
14/8/CLK
23 CREF
TOP VIEW
(Not to Scale) 22 AGND
DB11/SCLK 8
21
VDD
DB10/SDATA 9
20
DB0/DB8
DB9 10
19
DB1/DB9
DB8 11
18
DB2/DB10
DB7 12
17
DB3/DB11
DB6 13
16
DB4/DB12
DGND 14
15
DB5/DB13
NOTES
1. NC = NO CONNECT.
12889-100
DB13/HBEN 6
12
NOTES
1. NC = NO CONNECT.
Figure 5. AD7871 PDIP
CONVST 1
21 VDD
DB7
12889-005
NOTES
1. NC = NO CONNECT.
DB10/SDATA 9
12889-006
26 VIN
VIN
3
VSS
RD
14/8/CLK
27 VSS
CONVST
28 14/8/CLK
2
CS
1
CS
RD
CONVST
BUSY/INT
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. AD7871 CERDIP
Table 4. AD7871 Pin Function Descriptions
Pin No.
1
Mnemonic
CONVST
2
CS
3
4
5
RD
BUSY/INT
CLK
6
DB13/HBEN
7
DB12/SSTRB
8
DB11/SCLK
Description
Convert Start. A low to high transition on this input puts the track/hold into the hold mode. This input is
asynchronous to the CLK. CS and RD must be held high for the duration of this pulse.
Chip Select. Active low logic input. The device is selected when this input is active. With CONVST tied low, a new
conversion is initiated when CS goes low.
Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs.
Busy/Interrupt. Logic low output indicating converter status. See Figure 16, Figure 17, Figure 18, and Figure 19.
Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying this pin to VSS
enables the internal laser-trimmed oscillator.
Data Bit 13 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the 14/8/CLK input (see
Pin 28). When 14-bit data is selected, this pin provides the DB13 output. When either byte or serial data is
selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN is low, DB7 to
DB0 is the lower byte of data. With HBEN high, DB7 to DB0 is the upper byte of data (see Table 5).
Data Bit 12/Serial Strobe. When 14-bit data is selected, this pin provides the DB12 data output. Otherwise, it is an
active low three-state output that provides a framing pulse for serial data.
Data Bit 11/Serial Clock. When 14-bit data is selected, this pin provides the DB11 data output. Otherwise, SCLK is
the gated serial clock output that is derived from the internal or external ADC clock. If the 14/8/CLK input is held
at −5 V, then the SCLK runs continuously. With 14/8/CLK at 0 V, it is gated off (three-state) after serial transmission
Rev. F | Page 7 of 25
AD7871/AD7872
Pin No.
Mnemonic
9
DB10/SDATA
10 to 13
DB9 to DB6
14
15 to 20
DGND
DB5/DB13
to DB0/DB8
21
22
23
24
25
26
27
28
VDD
AGND
CREF
NC
REFOUT
VIN
VSS
14/8/CLK
Data Sheet
Description
is complete.
Data Bit 10/Serial Data. When 14-bit parallel data is selected, this pin provides the DB10 data output. Otherwise, it
is the three-state serial data output used in conjunction with SCLK and SSTRB in serial data transmission. Serial
data is valid on the falling edge of SCLK, when SSTRB is low.
Three-State Data Outputs controlled by CS and RD. Their function depends on the state of the 14/8/CLK and the
HBEN inputs. With 14/8/CLK high, they are always DB9 to DB6; with 14/8/CLK low, their function depends on
HBEN (see Table 5).
Digital Ground. Ground return for digital circuitry.
Three-State Data Outputs controlled by CS and RD. Their function depends on the 14/8/CLK DB0/DB8 and HBEN
inputs. With 14/8/CLK high, they are always DB5 to DB0; with 14/8/C LK low or −5 V, their function is controlled by
HBEN (see Table 5).
Positive Supply, +5 V ± 5%.
Analog Ground. Ground reference for analog circuitry.
Decoupling Point for On-Chip Reference. Connect a 10 nF capacitor between this pin and AGND.
No Connect.
Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability is 500 μA.
Analog Input. The input range is ±3 V.
Negative Supply, –5 V ± 5%.
Three-Function Input. Defines both the parallel and serial data formats. With this pin at +5 V, the output data is
14-bit parallel only. With this pin at 0 V, both byte and serial data are available, and the SCLK is noncontinuous.
With this pin at –5 V, both byte and serial data are available and the SCLK is continuous.
Table 5. Byte Output Format
HBEN
HIGH
LOW
DB7
LOW
DB7
DB6
LOW
DB6
DB5
DB13
DB5
DB4
DB12
DB4
Rev. F | Page 8 of 25
DB3
DB11
DB3
DB2
DB10
DB2
DB1
DB9
DB1
DB0
DB8
DB0
Data Sheet
AD7871/AD7872
CONTROL 1
16
VDD
CONTROL 1
16
VDD
CONVST 2
15
VSS
CONVST 2
15
VSS
AD7872
14
VIN
14
VIN
TOP VIEW
(Not to Scale)
13
REFOUT
12
AGND
11
CREF
NC 7
10
NC
DGND 8
9
VDD
NOTES
1. NC = NO CONNECT.
SCLK 5
AD7872
TOP VIEW 13 REFOUT
(Not to Scale) 12 AGND
C REF
SDATA 6
11
NC 7
10
NC
DGND 8
9
VDD
NOTES
1. NC = NO CONNECT.
Figure 8. AD7872 PDIP, SOIC
12889-101
SCLK 5
SDATA 6
CLK 3
SSTRB 4
12889-007
CLK 3
SSTRB 4
Figure 9. AD7872 CERDIP
Table 6. AD7872 Pin Function Descriptions
Pin No.
1
2
Mnemonic
CONTROL
CONVST
3
CLK
4
SSTRB
5
SCLK
6
SDATA
7
8
9
10
11
12
13
NC
DGND
VDD
NC
CREF
AGND
REFOUT
14
15
16
VIN
VSS
VDD
Description
Control Input. With this pin at 0 V, the SCLK is noncontinuous; with this pin at −5 V, the SCLK is continuous.
Convert Start. A low to high transition on this input puts the track/hold into the hold mode. This input is
asynchronous to the CLK.
Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying this pin to VSS
enables the internal laser-trimmed oscillator.
Serial Strobe. This is an active low three-state output that provides a framing pulse for serial data. An external
4.7 kΩ pull-up resistor is required on SSTRB.
Serial Clock. SCLK is the gated serial clock output derived from the internal or external ADC clock. If the 14/8/
CLK input is at −5 V, then the SCLK runs continuously. With CONTROL at 0 V, it is gated off (three-state) after the
serial transmission is complete. SCLK is an open-drain output and requires an external 2 kΩ pull-up resistor.
Serial Data. This is the three-state serial data output used in conjunction with SCLK and SSTRB in a serial data
transmission. Serial data is valid on the falling edge of SCLK, when SSTRB is low. An external 4.7 kΩ pull-up
resistor is required on SDATA.
No Connect.
Digital Ground. Ground return for digital circuitry.
Positive Supply for Analog Circuitry, +5 V ± 5%.
No Connect.
Decoupling Point for On-Chip Reference. Connect a 10 nF capacitor between this pin and AGND.
Analog Ground. Ground reference for analog circuitry.
Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability is
500 μA.
Analog Input. The input range is ±3 V.
Negative Supply, −5 V ± 5%.
Positive Supply for Analog Circuitry, +5 V ± 5%. Connect Pin 16 and Pin 9 together.
Rev. F | Page 9 of 25
AD7871/AD7872
Data Sheet
THEORY OF OPERATION
The AD7871/AD7872 is a complete 14-bit ADC, requiring no
external components apart from power supply decoupling
capacitors. It is comprised of a 14-bit successive approximation
ADC based on a fast settling voltage-output DAC, a high speed
comparator and CMOS SAR, a track-and-hold amplifier, a 3 V
buried Zener reference, a clock oscillator, and control logic.
The operation of the track-and-hold amplifier is essentially
transparent to the user. The track-and-hold amplifier goes from
its tracking mode to its hold mode at the start of conversion. If
the CONVST input is used to start conversion, then the track to
hold transition occurs on the rising edge of CONVST. If CS on
the AD7871 starts conversion, this transition occurs on the
falling edge of CS.
INTERNAL REFERENCE
ANALOG INPUT
The AD7871/AD7872 have an on-chip temperature
compensated buried Zener reference that is factory trimmed to
3 V ± 0 mV. Internally it provides both the DAC reference and
the dc bias required for bipolar operation. Reference noise is
minimized by connecting a capacitor between CREF and AGND.
For specified operation this capacitor should be 10 nF. The
reference output is available (REF OUT) and capable of
providing up to 500 μA to an external load.
Figure 11 shows the AD7871/AD7872 analog input. The analog
input range is ±3 V into an input resistance of typically 15 kΩ.
The designed code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . .
FS −3/2 LSBs). The output code is twos-complement binary
with 1 LSB = FS/16384 = 6 V/16384 = 366 μV. The ideal
input/output transfer function is shown in Figure 12.
The maximum recommended capacitance on REF OUT for
normal operation is 50 pF. If the reference is required for use
external to the AD7871/AD7872, decouple it with a 200 Ω
resistor in series with a parallel combination of a 10 μF
tantalum capacitor and a 0.1 μF ceramic capacitor. These
decoupling components are required to remove voltage spikes
caused by the internal operation of the AD7871/AD7872.
AD7871/AD7872
TRACK-AND-HOLD
AMPLIFIER
7.5kΩ
TO INTERNAL
COMPARATOR
7.5kΩ
TO INTERNAL
3V REFERENCE
Figure 11. Analog Input
CREF
VDD
AD7871/AD7872
12889-009
CONVERTER DETAILS
OUTPUT
CODE
TEMPERATURE
COMPENSATION
011…111
011…110
000…001
000…000
Figure 10. Reference Circuit
–FS
2
+FS – 1LSB
2
111…111
111…110
TRACK-AND-HOLD AMPLIFIER
The track-and-hold amplifier on the analog input of the
AD7871/AD7872 allows the ADC to accurately convert an
input sine wave of 6 V peak-peak amplitude to 14-bit accuracy.
The input bandwidth of the track-and-hold amplifier is much
greater than the Nyquist rate of the ADC even when the ADC is
operated at its maximum throughput rate. The 0.1 dB cutoff
frequency occurs typically at 500 kHz. The track-and-hold
amplifier acquires an input signal to 14-bit accuracy in less than
2 μs. The overall throughput rate is determined by the
conversion time plus the track-and-hold amplifier acquisition
time. For a 2 MHz input clock, the throughput time is 12 μs
maximum.
Rev. F | Page 10 of 25
FS = 6V
1LSB =
100…001
FS
16384
100…000
0V
INPUT VOLTAGE
Figure 12. Bipolar Input/Output Transfer Function
12889-010
REF OUT
000…110
12889-008
VSS
Data Sheet
AD7871/AD7872
BIPOLAR OFFSET SCALE ADJUSTMENT
V1
When the offset and full-scale errors of the AD7871/AD7872
need to be adjusted, offset error must be adjusted first. This is
achieved by trimming the offset of the op amp driving the
analog input of the AD7871/AD7872 while the input voltage is
½ LSB below AGND. The trim procedure is as follows: apply a
voltage of −0.183 mV (−½ LSB) at V1 in Figure 13 and adjust
the op amp offset voltage until the ADC output code flickers
between 11 1111 1111 1111 and 00 0000 0000 0000.
INPUT RANGE = 0V TO 5V
(0V TO 10V
AD711
R5
200Ω
VIN
R6
100Ω
R4
15kΩ (3.9kΩ)
R2
10kΩ
R1
10kΩ
AD7871/
AD7872*
REF OUT
AGND
R1
10kΩ
*ADDITIONAL PINS OMITTED FOR CLARITY.
INPUT RANGE = ±3V
AD711
R2
500Ω
Figure 14. Unipolar Circuit
VIN
R4
10kΩ
R3
10kΩ
12889-012
V1
R3
10kΩ (9.1kΩ)
The ideal input/output transfer function is shown in Figure 15.
The output can be converted to straight binary by inverting the
MSB.
AD7871/
AD7872*
OUTPUT
CODE
R5
10kΩ
AGND
12889-011
011…110
011…101
Figure 13. Bipolar Adjust Circuit
011…100
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC
positive full scale). The trim procedures for both cases are in the
following sections (see Figure 13).
FS = 5V (10V)
100…011
1LSB =
100…010
Positive Full-Scale Adjust
FS
10384
100…001
Apply a voltage of 2.9995 V (FS/2 −3/2 LSBs) at V1 and adjust
R2 until the ADC output code flickers between 01 1111 1111
1110 and 01 1111 1111 1111.
100…000
0V
V1, INPUT VOLTAGE
+FS – 1LSB
12889-013
*ADDITIONAL PINS OMITTED FOR CLARITY.
011…111
Figure 15. Unipolar Transfer Function
Negative Full-Scale Adjust
Apply a voltage of −2.9998 V (−FS/2 + 1/2 LSB) at V1 and adjust
R2 until the ADC output code flickers between 10 0000 0000
0000 and 10 0000 0000 0001.
UNIPOLAR OPERATION
A typical unipolar circuit is shown in Figure 14. The
AD7871/AD7872 REF OUT is used to offset the analog input
by 3 V. The analog input range is determined by the ratio of R3
to R4. The minimum range with which the circuit will work is
0 V to 3 V. The resistor values are given in Figure 14 for input
ranges of 0 to 5 V and 0 to 10 V. R5 and R6 are included for
offset and full scale adjust only and should be omitted if
adjustment is not required.
UNIPOLAR OFFSET AND FULL-SCALE
ADJUSTMENT
When absolute accuracy is required, offset and full-scale error
can be adjusted to zero. Offset must be adjusted before
full scale. This is achieved by applying an input voltage of ½
LSB to V1 and adjusting R6 until the ADC output code flickers
between 10 0000 0000 0000 and 10 0000 0000 0001. For fullscale adjustment, apply an input voltage of (FS −3/2 LSBs) to V1
and adjust R5 until the output code flickers between 01 1111
1111 1110 and 01 1111 1111 1111.
Rev. F | Page 11 of 25
AD7871/AD7872
Data Sheet
TIMING AND CONTROL
Parallel Output Format
The conversion time for both external and internal clocks can
vary from 19 to 20 rising clock edges depending on the
conversion start to ADC clock synchronization. If a conversion
is initiated within 30 ns prior to a rising edge of the ADC clock,
the conversion time will consist of 20 rising clock edges.
The two parallel formats available on the AD7871 are a 14-bit
wide data word and a 2-byte data word. In the first, all 14 bits of
data are available at the same time on DB13 (MSB) through
DB0 (LSB). In the second, two reads are required to access the
data. When this data format is selected, the DB13/HBEN pin
assumes the HBEN function. HBEN selects which byte of data
is to be read from the AD7871. When HBEN is low, the lower
eight bits of data are placed on the data bus during a read
operation; with HBEN high, the upper six bits of the 14-bit
word are placed on the data bus. These six bits are right justified
and thereby occupy the lower six bits of the byte while the
upper two bits are zeros.
There are two basic operating modes for the AD7871. In the
first mode (Mode 1), the CONVST line is used to start a
conversion and drive the track/hold into its hold mode. At the
end of the conversion, the track/hold returns to its tracking
mode. It is principally intended for digital signal processing and
other applications where precise sampling in time is required.
In these applications, it is important that the signal sampling
occurs at exactly equal intervals to minimize errors due to
sampling uncertainty or jitter. For these cases, the CONVST
line is driven by a timer or some precise clock source.
The second mode is achieved by hard-wiring the CONVST line
low. This mode (Mode 2) is intended for use in systems where
the microprocessor has total control of the ADC, both initiating
the conversion and reading the data. CS and RD start a
conversion, and the microprocessor will normally be driven
into a wait state for the duration of conversion by BUSY/INT.
The AD7872 has one operating mode only: Mode 1, which uses
CONVST to start conversion.
DATA OUTPUT FORMATS
The AD7871 offers a choice of three data output formats: one
serial and two parallel. The parallel data formats include a
single 14-bit parallel word for 16-bit data buses and a two-byte
format for 8-bit data buses. The data format is controlled by the
14/8/CLK input. A logic high on this pin selects the 14-bit
parallel output format only. A logic low or −5 V applied to this
pin allows the user access to either serial or byte formatted data.
Three of the pins previously assigned to the four MSBs in
parallel form are now used for serial communications while the
fourth pin becomes a control input for the byte-formatted data.
The three possible data output formats can be selected in either
of the modes of operation.
The AD7872 is a serial output device only. The serial data
format is exactly the same as the AD7871.
Serial Output Format
Serial data is available on the AD7871 when the 14/8/CLK input
is at 0 V or −5 V and in this case the DB12/SSTRB, DB11/SCLK
and DB10/SDATA pins assume their serial functions. The
AD7872 is a serial output device only. The serial function on
both devices is identical. Serial data is available during
conversion with a word length of 16 bits; two leading zeros,
followed by the 14-bit conversion result starting with the MSB.
The data is synchronized to the serial clock output (SCLK) and
is framed by the serial strobe (SSTRB). Data is clocked out on a
low to high transition of the serial clock and is valid on the
falling edge of this clock while the SSTRB output is low. SSTRB
goes low at the start of conversion and the first serial data bit
(which is the first leading zero) is valid on the first falling edge
of SCLK. All the serial lines are open-drain outputs and require
external pull-up resistors.
The serial clock out is derived from the ADC master clock
source which may be internal or external. Normally, SCLK is
required during the serial transmission only. In these cases it
can be shut down (that is, placed into three-state) at the end of
the conversion to allow multiple ADCs to share a common
serial bus. However, some serial systems require a serial clock
that runs continuously. Both options are available on the
AD7871 and AD7872. With the 14/8/CLK input on the
AD7871 at −5 V, the serial clock (SCLK) runs continuously;
when 14/8/CLK is at 0 V, SCLK goes into three-state at the end
of transmission. The CONTROL pin on the AD7872 performs
the same function. When this is at 0 V, SCLK is noncontinuous
and when it is at −5 V, SCLK is continuous.
The SCLK, SDATA, and SSTRB lines are open-drain outputs. If
these are required to drive capacitive loads in excess of 35 pF,
buffering is recommended.
Rev. F | Page 12 of 25
Data Sheet
AD7871/AD7872
Figure 16 shows the Mode 1 timing diagram for a 14-bit parallel
data output format (14/8/CLK = 5 V). A read to the AD7871 at
the end of conversion accesses all 14 bits of data at the same
time. Serial data is not available for this data output format.
MODE 1 INTERFACE
A conversion is initiated by a low going pulse on the CONVST
input. The rising edge of this CONVST pulse starts the
conversion and drives the track-and-hold amplifier into its hold
mode. The BUSY/INT status output assumes its INT function
in this mode. INT is normally high and goes low at the end of
conversion. This INT line can be used to interrupt the
microprocessor. A read operation to the AD7871 accesses the
data and the INT line is reset high on the falling edge of CS and
RD. The CONVST input must be high when CS and RD are
brought low for the AD7871 to operate correctly in this mode.
It is important, especially in systems where the conversion start
(CONVST) pulse is asynchronous to the microprocessor, to
ensure that a parallel or byte data read is not attempted during a
conversion. Trying to read data during a conversion can cause
errors to the conversion in progress. Avoid pulsing the CONVST
line a second time before the conversion ends because it can
cause errors in the conversion result. In applications where
precise sampling is not critical, the CONVST pulse can be
generated from the microprocessor WR line OR-gated with the
AD7871 CS input. In some applications, depending on power
supply turn-on time, the AD7871/AD7872 may perform a
conversion on power-up. In this case, the INT line on the
AD7871 will power up low, and a dummy read to the device will
be required to reset the INT line before starting conversion.
t1
TRACK-AND-HOLD
GOES INTO HOLD
CONVST
CS
t4
t2
t3
TRACK-AND-HOLD RETURNS
TO TRACK AND
ACQUISITION BEGINS
INT
tCONVERT
t5
t7
t6
THREE-STATE
DATA
VALID
DATA
DB13 TO DB0
Figure 16. Mode 1 Timing Diagram, 14-Bit Parallel
The Mode 1 function timing diagram for byte and serial data is
shown in Figure 17. INT goes low at the end of conversion and
is reset high by the first falling edge of CS and RD. This first
read at the end of the conversion can either access the low byte
or high byte of data depending on the status of HBEN
(Figure 17 shows low byte for example only). The diagram
shows both the SCLK output going into three-state at the end of
transmission and a continuously running clock (dashed line).
t1
TRACK-AND-HOLD GOES INTO HOLD
CONVST
HBEN 1
DON’T CARE
t9
t8
CS
t2
RD
t4
t3
TRACK-AND-HOLD RETURNS TO TRACK.
SIGNAL ACQUISITION BEGINS
t5
INT
tCONVERT
t6
THREE-STATE
DATA
t7
VALID
DATA
DB7 TO DB0
VALID
DATA
DB11 TO DB8
SSTRB2
t10
t11
t13
SCLK3
t12
SDATA
LEADING
ZEROS
DB13
DB12
t14
DB11
DB10
DB0
SERIAL DATA
t2, t3, t4, t8, AND t9 ARE THE SAME FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.
2EXTERNAL
4.7kΩ PULL-UP RESISTOR.
2kΩ PULL-UP RESISTOR. CONTINUOUS SCLK (DASHED LINE) WHEN 14/8/CLK
(CONTROL) = –5V; NONCONTINUOUS WHEN 14/8/CLK (CONTROL) = 0V.
3EXTERNAL
Figure 17. Mode 1 Timing Diagram, Byte or Serial Read
Rev. F | Page 13 of 25
12889-015
1TIMES
12889-014
RD
AD7871/AD7872
Data Sheet
interface is that it allows the microprocessor to start the
conversion, wait and then read data with a single read
instruction. The user does not have to worry about servicing
interrupts or ensuring that software delays are long enough to
avoid the reading during conversion.
MODE 2 INTERFACE
The second interface mode is achieved by hard wiring
CONVST low and the conversion is initiated by taking CS low
while HBEN is low. The track-and-hold amplifier goes into the
hold mode on the falling edge of CS. In this mode, the BUSY/
INT pin assumes its BUSY function. BUSY goes low at the start
of the conversion, stays low during the conversion and returns
high when the conversion is complete. It is normally used in
parallel interfaces to drive the microprocessor into a wait state
for the duration of conversion.
The Mode 2 timing diagram for byte and serial data is shown in
Figure 19. For 2-byte data read, the lower byte (DB0 to DB7)
has to be accessed first because HBEN must be low to start the
conversion. The ADC behaves like slow memory for this first
read, but the second read to access the upper byte of data is a
normal read. Operation to the serial functions is identical
between Mode 1 and Mode 2. The timing diagram of Figure 19
shows SCLK going into three-state or running continuously
(dashed line).
Figure 18 shows the Mode 2 timing diagram for the 14-bit
parallel data output format (14/8/CLK = 5 V). In this case, the
ADC behaves like slow memory. The major advantage of this
TRACK-AND-HOLD
GOES INTO HOLD
CS
t18
t15
RD
tCONVERT
t16
TRACK-AND-HOLD RETURNS TO TRACK.
SIGNAL ACQUISITION BEGINS.
BUSY
t7
THREE-STATE
DATA
VALID
DATA
DB13 TO DB0
12889-016
t17
Figure 18. Mode 2 Timing Diagram, 14-Bit Parallel Read
HBEN1
t19
t20
TRACK-AND-HOLD
GOES INTO HOLD
CS
t18
t15
t3
RD
tCONVERT
t16
TRACK-AND-HOLD RETURNS TO TRACK.
SIGNAL ACQUISITION BEGINS
t7
BUSY
DATA
t7
t6
t17
THREE-STATE
VALID
DATA
DB7 TO DB0
VALID
DATA
DB13 TO DB8
SSTRB2
t10
t11
t13
SCLK3
t12
SDATA2
LEADING
ZEROS
t14
DB13
DB12
DB11
DB10
DB0
1TIMES t , t , t , t , AND t ARE THE
15 18 19 8
20
2EXTERNAL 4.7kΩ PULL-UP RESISTOR.
3CONTINUOUS
SAME FOR A HIGH BYTE READ AS FOR A LOW BYTE READ.
SCLK (DASHED LINE) WHEN 14/8/CLK (CONTROL) = –5V; NONCONTINUOUS WHEN 14/8/CLK (CONTROL) = 0V. EXTERNAL 2kΩ PULL-UP RESISTOR.
Figure 19. Mode 2 Timing Diagram, Byte or Serial Read
Rev. F | Page 14 of 25
12889-017
SERIAL DATA
Data Sheet
AD7871/AD7872
Signal-to-Noise Ratio (SNR)
SNR is the measured signal-to-noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (fS/2) excluding dc. SNR is
dependent upon the number of quantization levels used in the
digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to noise ratio for a
sine wave input is given by:
SNR(dB) = (6.02N + 1.76)
The output spectrum from the ADC is evaluated by applying a
sine wave signal of very low distortion to the VIN input, which is
sampled at an 83 kHz sampling rate. A Fast Fourier Transform
(FFT) plot is generated from which the SNR data can be
obtained. Figure 20 shows a typical 2048 point FFT plot of the
AD7871/AD7872, with an input signal of 10 kHz and a
sampling frequency of 83 kHz. The SNR obtained from this
graph is 80 dB. Note that the harmonics are included when
calculating the SNR.
INPUT FREQUENCY = 10kHz
SAMPLE FREQUENCY = 60kHz
SNR = 80dB
TA = 25°C
SIGNAL AMPLITUDE (dB)
–30
SNR 1.76
6.02
(2)
The effective number of bits for a device can be calculated
directly from its measured SNR. Figure 21 shows a typical plot
of effective number of bits vs. frequency for the
AD7871/AD7872 with a sampling frequency of 60 kHz.
14.0
SAMPLE FREQUENCY = 60kHz
TA = 25°C
13.5
13.0
12.5
12.0
0
10
20
30
FREQUENCY (kHz)
(1)
where N is the number of bits in the ADC. Thus, for an ideal
14-bit converter, SNR = 86 dB.
0
N
12889-019
The AD7871/AD7872 are specified and tested for dynamic
performance specifications as well as traditional dc
specifications such as INL and DNL. These ac specifications are
required for signal processing applications such as speech
recognition, spectrum analysis and high speed modems. These
applications require information on the effects on the spectral
content of the input signal. Therefore, the parameters for which
the AD7871/AD7872 is specified include SNR, harmonic
distortion, intermodulation distortion, and peak harmonics.
These terms are discussed in more detail in the following
sections.
get a measure of performance expressed in an effective number
of bits (N).
NUMBER (Bits)
DYNAMIC SPECIFICATIONS
Figure 21. Effective Number of Bits vs. Frequency
Harmonic Distortion
Harmonic distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7871/AD7872, total harmonic
distortion (THD) is defined as
V2 V3 V4 V5 V6
2
THD ( dB ) 20log
2
2
2
2
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5 and V6 are the rms amplitudes of the second
through the sixth harmonic.
The THD is also derived from the FFT plot of the ADC output
spectrum. Figure 22 shows how the THD varies with input
frequency.
110
–60
SAMPLE FREQUENCY = 60kHz
TA = 25°C
–90
100
0
10
20
FREQUENCY (kHz)
30
12889-018
–150
THD (dB)
–120
90
Figure 20. Fast Fourier Transform Plot
The formula given in Equation 1 relates the SNR to the number
of bits. Rewriting the formula, as in Equation 2, it is possible to
80
0
10
20
INPUT FREQUENCY (kHz)
Figure 22. Total Harmonic Distortion vs. Frequency
Rev. F | Page 15 of 25
30
12889-020
Effective Number of Bits
AD7871/AD7872
Data Sheet
Intermodulation Distortion
Parallel Read Interfacing
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Figure 24 and Figure 25 show interfaces to two different DSP
processors types. The AD7871 is operating in Mode 1, parallel
read for both interfaces. An external timer controls conversion
start asynchronously to the microprocessor. At the end of each
conversion the ADC BUSY/INT interrupts the microprocessor
and the conversion result is read from the ADC with the
following instruction:
Using the CCIF standard where two input frequencies near the
top end of the input bandwidth are used, the second- and thirdorder terms are of different significance. The second-order
terms are usually distanced in frequency from the original sine
waves while the third-order terms are usually at a frequency
close to the input frequencies. As a result, the second- and
third-order terms are specified separately. The calculation of the
intermodulation distortion is as per the THD specification,
where it is the ratio of the rms sum of the individual distortion
products to the rms amplitude of the fundamental expressed in
decibels. In this case, the input consists of two, equal amplitude,
low distortion sine waves. Figure 23 shows a typical IMD plot
for the AD7871/AD7872.
DSP 2: IN D,ADC
MR0 = DSP 1 MR0 Register
D = Data Memory Address
ADC = AD7871 Address
TIMER
DMA14
DMA0
ADDR
DECODE
DMS
CONVST
CS
5V
EN
14/8/CLK
IRQn
BUSY/INT
DMRD
IMD
ALL TERMS = –90.85dB
2ND ORDER TERM = –92.38dB
3RD ORDER TERM = –96.12dB
RD
DB13
DB0
DMD15
DATA BUS
DMD0
12889-022
–60
AD7871*
DSP 1
INPUT FREQUENCIES
F1 = 9.21kHz
F2 = 9.51kHz
SAMPLE FREQUENCY = 60kHz
TA = 25°C
–30
ADDRESS BUS
*ADDITIONAL PINS OMITTED FOR CLARITY.
–90
Figure 24. AD7871 to DSP 1 Parallel Interface
TIMER
–120
10
20
FREQUENCY (kHz)
30
12889-021
0
A15
A0
ADDRESS BUS
AD7871*
DSP 2
Figure 23. IMD Plot
CONVST
CS
ADDR
DECODE
Peak Harmonic or Spurious Noise
IS
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification will be
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, peak
will be a noise peak.
EN
5V
14/8/CLK
INTn
BUSY/INT
STRB
RD
R/W
D15
D0
DB13
DB0
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY.
MICROPROCESSOR INTERFACE
12889-023
SIGNAL AMPLITUDE (dB)
0
DSP 1 MR0 = DM(ADC)
Figure 25. AD7871 to DSP 2 Interface
The AD7871/AD7872 have a wide variety of interfacing
options. The AD7871 offers two operating modes and three
data-output formats, while the AD7872 is a dedicated serial
output device. The fast data access times on the parallel modes
of the AD7871 allow interfacing to the very fast DSPs. The
serial mode on both the AD7871 and AD7872 is compatible
with the serial port structures on all the popular DSPs.
Some applications may require that conversions be initiated by
the microprocessor rather than an external timer. One option is
to decode the AD7871 CONVST from the address bus so that a
write operation to the ADC starts a conversion. Data is read at
the end of conversion as described previously. Note that a read
operation must not be attempted during conversion.
Rev. F | Page 16 of 25
Data Sheet
AD7871/AD7872
Serial Interfacing
AD7872 to DSP Type 2 Serial Interface
Both the AD7871 and the AD7872 have an identical serial
interface. The diagrams that follow show the AD7872 interfaces
only, but the AD7871 could just as easily be used in these
circuits. Figure 26, Figure 27, and Figure 28 show the AD7872
connected to three popular DSPs. In all three interfaces,
CONVST is used to start the conversion because this does not
activate the parallel bus. Thus, the microprocessor can continue
to use its parallel bus regardless of the state of the AD7872. The
interfaces show a timer driving the CONVST input but this
could be generated from a decoded address if required.
Figure 27 shows a serial interface between the AD7872 and DSP
Type 2. The AD7872 is configured for continuous clock
operation. Note that the ADC will not interface correctly to a
DSP if it is configured for a noncontinuous clock. Data is
clocked into the data receive register (DRR) of a DSP during
conversion. As with the previous interfaces, when a 16-bit word
is received by the DSP it generates an internal interrupt to read
the data from the DRR.
AD7872*
TIMER
+5V
AD7872 to DSP Type 1 Serial Interface
DSP
TYPE 2
4.7kΩ
2kΩ
CONTROL
4.7kΩ
SSTRB
FSR
CLKR
SCLK
DR
SDATA
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 27. AD7872 to DSP Type 2 Interface
AD7872 to a DSP Microcomputer Serial Interface
Figure 28 shows a serial interface between the AD7872 and a
DSP microcomputer. The AD7872 is configured for continuous
clock operation. Data is clocked into the serial port register of
the microcomputer during conversion. As with the previous
interfaces, when a 16-bit data word is received by a DSP
microcomputer an internal microprocessor interrupt is
generated and the data is read from the serial port register.
AD7872*
AD7872*
CONVST
+5V
CONTROL
4.7kΩ
2kΩ
SCK
SCLK
SRD
SDATA
*ADDITIONAL PINS OMITTED FOR CLARITY.
–5V
4.7kΩ
2kΩ
FSR
SCLK
DR
12889-024
DSP
TYPE 1
DSP
MICROCOMPUTER
TIMER
CONVST
CONTROL
4.7kΩ
SSTRB
SCLK
SDATA
*ADDITIONAL PINS OMITTED FOR CLARITY.
12889-026
5V
TIMER
12889-025
Figure 26 shows a serial interface between the AD7872 and DSP
Type 1. The interface arrangement is two-wire with the AD7872
configured for noncontinuous clock operation CONTROL =
0 V). DSP Type 1 is configured for normal mode asynchronous
operation with gated clock. It is set up for a 16-bit word with
SCK as an input and the FSL control bit set to a 0. In this
configuration, the DSP Type 1 assumes valid data on the first
falling edge of SCK. Because the AD7872 provides valid data on
this first edge, there is no need for a strobe or framing pulse for
the data. SCLK and SDATA are three-stated when the AD7872
is not performing a conversion. During conversion, data is valid
on the SDATA output of the AD7872 and is clocked into the
Receive Data Shift Register of DSP Type 1. When this register
has received 16 bits of data, it generates an internal interrupt on
DSP Type 1 to read the data from the register.
CONVST
–5V
Figure 28. AD7872 to a DSP Microcomputer Serial Interface
Figure 26. AD7872 to DSP Type 1 Interface
DSP Type 1 and AD7872 can also be configured for continuous
clock operation. In this case a strobe pulse is required by DSP
Type 1 to indicate when data is valid. The SSTRB output of the
AD7872 is inverted and applied to the SC1 input of DSP
Type 1 to provide this strobe pulse. All other conditions and
connections are the same as for the gated clock operation.
STANDALONE OPERATION
The AD7871 can be used in its Mode 2, parallel mode for
standalone operation. In this case, conversion is initiated with a
pulse to the CS input. This pulse must be longer than the
conversion time of the ADC. The BUSY output is used to drive
the RD input. Data is latched from the AD7871 DB0 to DB11
outputs to an external latch on the rising edge of BUSY.
Rev. F | Page 17 of 25
AD7871/AD7872
Data Sheet
APPLICATIONS INFORMATION
Good printed circuit board (PCB) layout is as important as the
circuit design itself in achieving high speed ADC performance.
The AD7871/AD7872 is required to make bit decisions on an
LSB size of 366 μV. Thus, the designer has to be conscious of
noise both in the ADC itself and in the preceding analog
circuitry. Switching mode power supplies are not recommended
as the switching spikes will feed through to the comparator
causing noisy code transitions. Other causes of concern are
ground loops and digital feedthrough from microprocessors.
These are factors that influence any ADC; a proper PCB layout
that minimizes these effects is essential for best performance.
LAYOUT HINTS
Ensure that the layout for the PCB has the digital and analog
signal lines separated as much as possible. Take care not to run
a digital track alongside an analog signal track. Guard (screen)
the analog input with AGND.
Establish a single point analog ground (star ground) separate
from the logic system ground at the AD7871/AD7872 AGND
pin or as close as possible to the AD7871/AD7872. Connect all
other grounds and the AD7871/AD7872 DGND to this single
analog ground point. Do not connect any other digital grounds
to this analog ground point.
DATA ACQUISITION BOARD
Figure 31 shows the AD7871/AD7872 in a data acquisition
circuit. The corresponding PCB layout has three interface ports:
one serial and two parallel. Note that the AD7871/AD7872
serial lines are buffered by a 74HC244. This allows long lines
with large capacitive loads to be driven. One of the parallel
ports is directly compatible with the DSP processor evaluation
board expansion connector.
The only additional component required for a full data
acquisition system is an antialiasing filter. There is a component
grid provided near the analog input on the PCB, which may be
used for such a filter or any other input conditioning circuitry.
To facilitate this option, there is a shorting plug (labelled LK1
on the PCB) on the analog input track. If this shorting plug is
used, the analog input connects to the buffer amplifier driving
the AD7871/AD7872; if this shorting plug is omitted, a wire
link can be used to connect the analog input to the PCB
component grid.
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC, so
make the foil width for these tracks as wide as possible. The use
of ground planes minimizes impedance paths and also guards
the analog circuitry from digital noise. The circuit layout of
Figure 33 and Figure 34 have both analog and digital ground
planes that are kept separated and joined together only at the
AD7871/AD7872 AGND pin.
NOISE
Keep the input signal leads to VIN and signal return leads from
AGND as short as possible to minimize input noise coupling. In
applications where this is not possible, use a shielded cable
between the source and the ADC. Reduce the ground circuit
impedance as much as possible because any potential difference
in grounds between the signal source and the ADC appears as
an error voltage in series with the input signal.
Rev. F | Page 18 of 25
SKT4 is a 26-way (2-row) IDC connector. This contains the
same signal contacts as SKT6 except for EDMACK, which is
connected to SKT6 only. It also contains decoded R/W and
STRB inputs necessary for DSP processor interfacing.
2
STRB
3
4
NC
CS
5
6
NC
NC
7
8
BUSY/INT
DB12/SSTRB
9
10
DB13/HBEN
DB10/SDATA
11
12
DB11/SCLK
DB8/LOW
13
14
HB9/LOW
DB6/LOW
15
16
DB7/LOW
DB4/DB12
17
18
DB5/DB13
DB2/DB10
19
20
DB3/DB11
DB0/DB8
21
22
DB1/DB9
5V
23
24
5V
GND
25
26
GND
NC = NO CONNECT
5V
NC
DGND
NC = NO CONNECT
12889-028
NC
5
9
Figure 30. SKT5 Pinout
POWER SUPPLY CONNECTIONS
The PCB requires two analog power supplies and one 5 V logic
supply. The analog supplies are labelled V+ and V−, and the
range for both supplies is 12 V to 15 V. Connection to the 5 V
digital supply is made through any of the SKT4 to SKT6
connectors. The ±5 V supply required by the AD7871/AD7872
is generated from voltage regulators on the V+ and V− power
supplies input (IC6 and IC7 in Figure 31).
Table 7.
Plug
LK1
LK2
LK3
LK4
LK5
LK6
LK7
Description
Connects the analog input to a buffer amplifier. The
analog input may also be connected to a component
grid for signal conditioning.
Selects either the AD7871/AD7872 internal clock or an
external clock source.
Configures the AD7871 14/8/CLK input for the
appropriate serial or parallel interface.
Connects the AD7871 RD input directly to the two
parallel connectors or to a decoded STRB and R/W input.
Connects the R3 pull-up resistor to SSTRB.
Connects the R4 pull-up resistor to SCLK.
Connects the R5 pull-up resistor to SDATA.
Remove LK5 to LK7 for parallel interfacing.
12889-027
1
4
8
There are seven shorting plug options, which must be set before
using the board. These are outlined in Table 7.
SKT1, SKT2, and SKT3 are three BNC connectors providing
connections for the analog input, the CONVST input and an
external clock.
RD
3
7
SHORTING PLUG OPTIONS
SKT5 is a 5-way D-type connector meant for serial interfacing
only. An inverted DB11/SCLK output is also provided on this
connector for systems that accept data on a rising clock edge.
R/W
2
6
NC
SKT6 is a 96-contact (3-row) Eurocard connector that is
directly compatible with the DSP processor evaluation board
prototype expansion connector. The expansion connector on
the DSP processor has eight decoded chip enable outputs
labeled ECE1 to ECE8. ECE6 is used to drive the AD7871 CS
input on the board. To avoid selecting the on-board RAM
sockets at the same time, remove LK6 on the DSP processor
board. In addition, the DSP processor expansion connector has
four interrupts labelled EIRQ0 to EIRQ3. The AD7871 BUSY/
INT output connects to EIRQ0. There is a single wait state
generator connected to EDMACK to allow the AD7871 to
interface to the faster versions of the DSP processor.
1
DB11/SCLK
There are two parallel connectors labeled SKT4 and SKT6, and
one serial connector labeled SKT5. A shorting plug option (LK3
in Figure 31) configures the ADC for the appropriate interface.
DB11/SCLK
INTERFACE CONNECTIONS
DB10/SDATA
AD7871/AD7872
DB12/SSTRB
Data Sheet
Figure 29. SKT4 Pinout
Rev. F | Page 19 of 25
AD7871/AD7872
IN
OUT
IC7
79L05
GND
VDD
C5
10µF
VDD
C6
0.1µF
CONVST
CONVST
IC2/IC3
AD7871/
AD7872
A
CLK
V+
SKT2
LK2
B
SKT6
ADSP-2100
CONNECTOR
CLK
SKT3
+5V
VCC
VSS
CS
ANALOG
INPUT
±3V LK1
C1
10µF
C3
10µF
C4
0.1µF
C19
10nF
VCC
EDMACK
CLR
Q
IC5
CLK
74HC74
D
VSS
VCC
R3 R4
IC4
R1
IC4
CLK OUT
LK5 LK6
R2
LK7
DMRD
EIRQ0
DMD15
DB13/HBEN
DMD14
DB12/SSTRB
DMD13
DB11/SCLK
DMD12
DB10/SDATA
DGND
DMD11
DB9/LOW
DATA BUS
DB0/DB8
DMD4
VSS
IN
OUT
IC6
79L05
GND
HC244
VSS
VDD
C7
10µF
DGND
2A3 2A1 2A2
2G IC8 VCC
2Y3 2Y2 2Y1
C8
0.1µF
SKT4 25 26 5 23 24 13-23 3
8
1 10 2
9 12 11
PARALLEL COMMUNICATIONS PORT
3
1
2
4
9 5
Figure 32. PCB Silkscreen for Figure 31
B7
A9
B11
B12
B13
B14
B15
B23
A32
SKT5
SERIAL COMMUNICATIONS PORT
Figure 31. Data Acquisition Circuit Using the AD7871/AD7872
Rev. F | Page 20 of 25
C6
VCC
12889-030
V–
B6
R5
BUSY/INT
AGND
C22
VCC
IC4
LK4
B
RD
IC4
VCC
VCC
C
A
CREF
LK3
B
14/8/CLK
CONTROL
VIN
AD711
V–
A
C2
0.1µF
IC1
SKT1
A31
ECE6
12889-029
V+
Data Sheet
AD7871/AD7872
12889-031
Data Sheet
12889-032
Figure 33. PCB Component Side Layout for Figure 31
Figure 34. PCB Solder Side Layout for Figure 31
Rev. F | Page 21 of 25
AD7871/AD7872
Data Sheet
OUTLINE DIMENSIONS
0.775
0.755
0.735
0.100
BSC
0.210
MAX
1
8
0.280
0.250
0.240
TOP VIEW
0.325
0.310
0.300
0.195
0.130
0.115
SIDE VIEW
0.015
MIN
0.150
0.130
0.115
0.022
0.018
0.015
0.015
GAUGE
PLANE
END VIEW
SEATING
PLANE
0.021
0.016
0.011
0.070
0.045 0.060
0.039 0.055
0.030
0.012
0.010
0.008
0.430
MAX
03-07-2014-D
9
16
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MS-001-BB
Figure 35. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches
1.450
1.440
28
PIN 1
INDICATOR
15
0.550
0.530
1
14
TOP VIEW
0.606
0.594
SIDE VIEW
0.175
0.120
SEATING
PLANE
0.060
0.020
0.020
0.015
0.070
0.060
0.050
0.105
0.095
0.015
GAUGE
PLANE
0.005
MIN
COMPLIANT TO JEDEC STANDARDS MS-011
Figure 36. 28-Lead Plastic Dual In-Line Package [PDIP]
Wide Body
(N-28-3)
Dimensions shown in inches
Rev. F | Page 22 of 25
END VIEW
15°
8°
0.012
0.010
0.008
01-13-2015-A
0.200
MAX
Data Sheet
AD7871/AD7872
0.005 (0.13) MIN
0.098 (2.49) MAX
16
9
1
PIN 1
8
0.310 (7.87)
0.220 (5.59)
0.100 (2.54) BSC
0.840 (21.34) MAX
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
0.070 (1.78) PLANE
0.030 (0.76)
15°
0°
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 37. 16-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-16)
Dimensions shown in inches and (millimeters)
0.005 (0.13)
MIN
0.100 (2.54)
MAX
28
15
0.610 (15.49)
0.500 (12.70)
1
14
PIN 1
1.490 (37.85) MAX
0.620 (15.75)
0.590 (14.99)
0.015 (0.38)
MIN
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.026 (0.66)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78) SEATING
0.030 (0.76) PLANE
15°
0°
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 38. 28-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-28-2)
Dimensions shown in inches and (millimeters)
Rev. F | Page 23 of 25
0.018 (0.46)
0.008 (0.20)
030106-A
0.225(5.72)
MAX
AD7871/AD7872
Data Sheet
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
1
10.65 (0.4193)
10.00 (0.3937)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
8°
0°
0.33 (0.0130)
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
03-27-2007-B
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 39. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
0.180 (4.57)
0.165 (4.19)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
4
5
PIN 1
IDENTIFIER
26
25
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
TOP VIEW
(PINS DOWN)
11
12
0.020 (0.51)
MIN
0.032 (0.81)
0.026 (0.66)
19
18
0.456 (11.582)
SQ
0.450 (11.430)
0.495 (12.57)
SQ
0.485 (12.32)
0.120 (3.04)
0.090 (2.29)
0.430 (10.92)
0.390 (9.91)
BOTTOM
VIEW
(PINS UP)
0.045 (1.14)
R
0.025 (0.64)
COMPLIANT TO JEDEC STANDARDS MO-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 40. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28)
Dimensions shown in inches and (millimeters)
Rev. F | Page 24 of 25
042508-A
0.048 (1.22)
0.042 (1.07)
Data Sheet
AD7871/AD7872
ORDERING GUIDE
Model1, 2, 3, 4
AD7871JNZ
AD7871JPZ
AD7871JPZ-REEL
AD7871KPZ
AD7871TQ
AD7872ANZ
AD7872BRZ
AD7872BRZ-REEL
AD7872JNZ
AD7872JRZ
AD7872JRZ-REEL
AD7872KNZ
AD7872KRZ
AD7872KRZ-REEL
AD7872TQ
Temperature Range
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
Package Description
28-Lead PDIP
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead CERDIP
16-Lead PDIP
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead PDIP
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead PDIP
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead CERDIP
1
Z = RoHS Compliant Part.
To order MIL-STD-883, Class B, processed parts, add /883B to part number. Contact local sales office for military data sheet.
3
Contact local sales office for LCCC availability.
4
The AD787xTQ models are available to /883B processing only.
2
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12889-0-11/18(F)
Rev. F | Page 25 of 25
Package Option
N-28-3
P-28
P-28
P-28
Q-28-2
N-16
RW-16
RW-16
N-16
RW-16
RW-16
N-16
RW-16
RW-16
Q-16
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