AD7923SRU-EP

4-Channel, 200 kSPS 12-Bit ADC with Sequencer in 16-Lead TSSOP AD7923-EP Enhanced Product FEATURES FUNCTIONAL BLOCK DIAGRAM Fast throughput rate: 200 kSPS Specified for AVDD of 2.7 V to 5.25 V Low power 3.6 mW max at 200 kSPS with 3 V supply 7.5 mW max at 200 kSPS with 5 V supply 4 (single-ended) inputs with sequencer Wide input bandwidth 70 dB min SNR at 50 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®-/QSPI™-/MICROWIRE™-/DSPcompatible Shutdown mode: 0.5 μA max 16-lead TSSOP package AV DD REFIN VIN0 • • • • • • • • • • • • • VIN3 T/H 12-BIT SUCCESSIVE APPROXIMATION ADC INPUT MUX SCLK DOUT CONTROL LOGIC SEQUENCER DIN ENHANCED PRODUCT FEATURES CS APPLICATIONS AD7923-EP VDRIVE GND Figure 1. The AD7923-EP features four single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. The serial clock (SCLK) frequency determines the conversion time for the AD7923-EP because this is used as the master clock to control the conversion. The conversion time can be as short as 800 ns with a 20 MHz SCLK. Additional application and technical information can be found in the AD7923 data sheet. Aerospace and defense Milcom Avionics Unmanned systems GENERAL DESCRIPTION The AD7923-EP is a 12-bit, high speed, low power, 4-channel, successive approximation (SAR) ADC. It operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 200 kSPS. It contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 MHz. The conversion process and data acquisition are controlled by CS and the serial clock, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS; the conversion is also initiated at this point. PRODUCT HIGHLIGHTS 1. 2. 3. 4. The AD7923-EP uses advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, it consumes 1.2 mA maximum with 3 V supplies and 1.5 mA maximum with 5 V supplies. Through the configuration of the control register, the analog input range can be selected as 0 V to REFIN or 0 V to 2 × REFIN, with either straight binary or twos complement output coding. Rev. A 10190-001 Supports defense and aerospace applications (AQEC standard) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Product change notification Qualification data available on request 5. High Throughput with Low Power Consumption. The AD7923-EP offers up to 200 kSPS throughput rates. At the maximum throughput rate with 3 V supplies, the AD7923-EP dissipates just 3.6 mW of power. Four Single-Ended Inputs with a Channel Sequencer. Single-Supply Operation with VDRIVE Function. The VDRIVE function allows the serial interface to connect directly to either 3 V or 5 V processor systems independent of AVDD. Flexible Power/Serial Clock Speed Management. The serial clock determines the conversion rate, allowing the conversion time to reduce through the serial clock speed increase. The device also features various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 μA maximum when in full shutdown. No Pipeline Delay. The device features a SAR ADC with accurate control of the sampling instant via a CS input and once off conversion control. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD7923-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6 Enhanced Product Features ............................................................ 1 ESD Caution...................................................................................6 General Description ......................................................................... 1 Pin Configuration and Function Description ...............................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................8 Product Highlights ........................................................................... 1 Outline Dimensions ..........................................................................9 Specifications..................................................................................... 3 Ordering Guide .............................................................................9 Timing Specifications .................................................................. 5 REVISION HISTORY 4/2018—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Added Enhanced Product Features Section.................................. 1 Changes to Ordering Guide ............................................................ 9 10/2011—Revision 0: Initial Version Rev. A | Page 2 of 9 Enhanced Product AD7923-EP SPECIFICATIONS AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted. Temperature range (EP version): −55°C to +125°C. Table 1. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) Signal-to-Noise (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Channel to Channel Isolation Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity 0 V to REFIN Input Range Offset Error Offset Error Match Gain Error Gain Error Match 0 V to 2 × REFIN Input Range Positive Gain Error Positive Gain Error Match Zero Code Error Zero Code Error Match Negative Gain Error Negative Gain Error Match ANALOG INPUT Input Voltage Range DC Leakage Current Input Capacitance REFERENCE INPUT REFIN Input Voltage DC Leakage Current REFIN Input Impedance EP Version 1 Unit 70 69 69 70 −77 −73 −78 −76 dB min dB min dB min dB min dB max dB max dB max dB max −90 −90 10 50 −85 8.2 1.6 dB typ dB typ ns typ ps typ dB typ MHz typ MHz typ 12 ±1 −0.9/+1.5 Bits LSB max LSB max ±8 ±0.5 ±1.5 ±0.5 LSB max LSB max LSB max LSB max Test Conditions/Comments fIN = 50 kHz sine wave, fSCLK = 20 MHz At 5 V, –40°C to +85°C At 5 V, 85°C to 125°C, typ 70 dB At 3 V typ 70 dB, –40°C to +125°C At 5 V typ, −84 dB At 3 V typ,−77 dB At 5 V typ, −86 dB At 3 V typ, −80 dB fA = 40.1 kHz, fB = 41.5 kHz fIN = 400 kHz at 3 dB At 0.1 dB Guaranteed no missed codes to 12 bits Straight binary output coding Typ ±0.5 LSB −REFIN to +REFIN biased about REFIN with twos complement output coding ±1.5 ±0.5 ±8 ±0.5 ±1 ±0.5 LSB max LSB max LSB max LSB max LSB max LSB max 0 to REFIN 0 to 2 × REFIN ±1 20 V V µA max pF typ Range bit set to 1 Range bit set to 0, AVDD = 4.75 V to 5.25 V 2.5 ±1 36 V µA max kΩ typ ±1% specified performance Rev. A | Page 3 of 9 Typ ±0.8 LSB fSAMPLE = 200 kSPS AD7923-EP Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN 2 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance2 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVDD VDRIVE IDD During Conversion Normal Mode (Static) Normal Mode (Operational) fSAMPLE = 200 kSPS Using Auto Shutdown Mode fSAMPLE = 200 kSPS Auto Shutdown (Static) Full Shutdown Mode Power Dissipation Normal Mode (Operational) fSAMPLE = 200 kSPS Auto Shutdown (Static) Full Shutdown Mode 1 2 Enhanced Product EP Version 1 Unit Test Conditions/Comments 0.7 × VDRIVE 0.3 × VDRIVE ±1 10 V min V max µA max pF max VDRIVE – 0.2 0.4 ±1 1 Twos Complement Straight (Natural) Binary V min V max µA max pF max 800 300 300 200 ns max ns max ns max kSPS max 2.7/5.25 2.7/5.25 V min/max V min/max 2.7 2.0 600 1.5 1.2 900 650 0.5 0.5 mA max mA max µA typ mA max mA max µA typ µA typ µA max µA max Digital I/Ps = 0 V or VDRIVE AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz AVDD = 2.7 V to 5.25 V, SCLK on or off AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz AVDD = 4.75 V to 5.25 V, fSAMPLE = 200 kSPS AVDD = 2.7 V to 3.6 V, fSAMPLE = 200 kSPS SCLK on or off (20 nA typ) SCLK on or off (20 nA typ) 7.5 3.6 2.5 1.5 2.5 1.5 mW max mW max µW max µW max µW max µW max AVDD = 5 V, fSCLK = 20 MHz AVDD = 3 V, fSCLK = 20 MHz AVDD = 5 V AVDD = 3 V AVDD = 5 V AVDD = 3 V Typ 10 nA, VIN = 0 V or VDRIVE ISOURCE = 200 µA, AVDD = 2.7 V to 5.25 V ISINK = 200 µA Coding bit set to 0 Coding bit set to 1 Temperature range: EP Version: −55°C to +125°C. Sample tested at 25°C to ensure compliance. Rev. A | Page 4 of 9 16 SCLK cycles with SCLK at 20 MHz Sinewave input Full-scale step Input Enhanced Product AD7923-EP TIMING SPECIFICATIONS AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted. 1 Table 2. Parameter fSCLK 2 tCONVERT tQUIET AVDD = 3 V 10 20 16 × tSCLK 50 t2 t3 3 t43 t5 t6 t7 t8 4 t9 t10 t11 t12 10 35 40 0.4 × tSCLK 0.4 × tSCLK 10 15/45 10 5 20 1 Limit at TMIN, TMAX AVDD = 5 V Unit 10 kHz min 20 MHz max 16 × tSCLK 50 ns min 10 30 40 0.4 × tSCLK 0.4 × tSCLK 10 15/35 10 5 20 1 ns min ns max ns max ns min ns min ns min ns min/max ns min ns min ns min µs max Description Minimum quiet time required between CS rising edge and start of next conversion CS to SCLK set up time Delay from CS until DOUT three-state disabled Data access time after SCLK falling edge SCLK low pulse width SCLK high pulse width SCLK to DOUT valid hold time SCLK falling edge to DOUT high impedance DIN set up time prior to SCLK falling edge DIN hold time after SCLK falling edge Sixteenth SCLK falling edge to CS high Power-Up time from full power-down/auto shutdown mode Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 The mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t8, is the true bus relinquish time of the device and is independent of the bus loading. 1 200µA 1.6V CL 50pF 200µA IOH 10190-002 TO OUTPUT PIN IOL Figure 2. Load Circuit for Digital Output Timing Specification Rev. A | Page 5 of 9 AD7923-EP Enhanced Product ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND VDRIVE to AGND Analog Input Voltage to AGND Digital Input Voltage to AGND Digital Output Voltage to AGND REFIN to AGND Input Current to Any Pin Except Supplies 1 Operating Temperature Range (EP Version) Storage Temperature Range Junction Temperature TSSOP Package, Power Dissipation θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Pb-free Temperature, Soldering Reflow ESD 1 Rating −0.3 V to +7 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to +7 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V ±10 mA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION −55°C to +125°C −65°C to +150°C 150°C 450 mW 150.4°C/W (TSSOP) 27.6°C/W (TSSOP) 215°C 220°C 260(+0)°C 1.5 kV Transient currents of up to 100 mA do not cause SCR latchup. Rev. A | Page 6 of 9 Enhanced Product AD7923-EP PIN CONFIGURATION AND FUNCTION DESCRIPTION SCLK 1 16 AGND DIN 2 15 VDRIVE 14 DOUT CS 3 AGND 4 AD7923-EP AVDD 5 TOP VIEW (Not to Scale) AVDD 6 11 VIN1 REFIN 7 10 VIN2 AGND 8 13 AGND 9 VIN3 10190-003 12 VIN0 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic SCLK 2 DIN 3 CS 4, 8, 13, 16 5, 6 AGND 7 REFIN 12 to 9 VIN0 to VIN3 14 DOUT 15 VDRIVE AVDD Description Serial Clock. Logic Input. SCLK provides the serial clock for accessing data for the device. This clock input is also used as the clock source for the AD7923-EP conversion process. Data In. Logic Input. Data to be written to the control register is provided on this input and is clocked into the register on the falling edge of SCLK. Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7923-EP and framing the serial data transfer. Analog Ground. Ground reference point for all analog circuitry on the AD7923-EP. All analog input signals and any external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. Analog Power Supply Input. The AVDD range for the AD7923-EP is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range, AVDD should be from 4.75 V to 5.25 V. Reference Input for the AD7923-EP. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. Analog Input 0 through Analog Input 3. Four single-ended analog input channels that are multiplexed into the onchip track-and-hold. The analog input channel to be converted is selected by using the Address Bits ADD1 and ADD0 of the control register. The address bits in conjunction with the SEQ1 and SEQ0 bits allow the sequencer to be programmed. The input range for all input channels can extend from 0 V to REFIN or from 0 V to 2 × REFIN as selected via the range bit in the control register. Any unused input channels must be connected to AGND to avoid noise pickup. Data Out. Logic Output. The conversion result from the AD7923-EP is provided on this output pin as a serial data stream. The AD7923-EP serial data stream consists of two leading 0s, and two address bits indicating which channel the conversion result corresponds to, followed by 12 bits of conversion data, MSB first. The output coding can be selected as straight binary or twos complement via the coding bit in the control register. The data bits are clocked out of the AD7923-EP on the SCLK falling edge. Logic Power Supply Input. The voltage supplied at this pin determines at which voltage the serial interface operates. Rev. A | Page 7 of 9 AD7923-EP Enhanced Product TYPICAL PERFORMANCE CHARACTERISTICS AVDD = VDRIVE = 5V TEMP = 25°C 0.8 0.6 INL ERROR (LSB) –30 SNR (dB) 1.0 4096 POINT FFT AVDD = 4.75V fSAMPLE = 200kSPS fIN = 50 kHz SINAD = 70.714dB THD = –82.853dB SFDR = –84.815dB –10 –50 –70 0.4 0.2 0 –0.2 –0.4 –0.6 –90 20 30 40 50 60 70 FREQUENCY (kHz) 80 90 100 –1.0 0 512 1024 1.0 –55 fSAMPLE = 200kSPS THD (dB) –70 RIN = 1000Ω RIN = 100Ω RIN = 10Ω –85 3584 4096 3072 3584 4096 0.4 0.2 0 –0.2 –0.4 –0.6 –90 –0.8 RIN = 50Ω 100 INPUT FREQUENCY (kHz) 10190-005 –95 10 3072 0.6 –75 –80 2560 AVDD = VDRIVE = 5V TEMP = 25°C 0.8 TA = 25°C AVDD = 5.25V RANGE = 0V TO REFIN DNL ERROR (LSB) –65 2048 CODE Figure 6. Typical INL Figure 4. Dynamic Performance at 200 kSPS –60 1536 10190-006 10 10190-004 0 10190-007 –0.8 –110 Figure 5. THD vs. Analog Input Frequency for Various Source Impedances Rev. A | Page 8 of 9 –1.0 0 512 1024 1536 2048 CODE 2560 Figure 7. Typical DNL Enhanced Product AD7923-EP OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 8° 0° SEATING PLANE 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 8. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7923SRU-EP AD7923SRU-EP-RL7 AD7923SRUZ-EP AD7923SRUZ-EP-RL7 1 2 Temperature Range −55°C to +125°C −55°C to +125°C −55°C to +125°C −55°C to +125°C Linearity Error (LSB) 2 ±1 ±1 ±1 ±1 Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] Z = RoHS Compliant Part Linearity error refers to integral linearity error. ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10190-0-4/18(A) Rev. A | Page 9 of 9 Package Option RU-16 RU-16 RU-16 RU-16