AD8019ARU

a DSL Line Driver with Power-Down AD8019 FEATURES Low Distortion, High Output Current Amplifiers Operate from 12 V to ⴞ12 V Power Supplies, Ideal for High-Performance ADSL CPE, and xDSL Modems Low Power Operation 9 mA/Amp (Typ) Supply Current Digital (1-Bit) Power-Down Voltage Feedback Amplifiers Low Distortion Out-of-Band SFDR –80 dBc @ 100 kHz into 100 ⍀ Line High Speed 175 MHz Bandwidth (–3 dB), G = +1 400 V/␮s Slew Rate High Dynamic Range VOUT to within 1.2 V of Power Supply PIN CONFIGURATIONS 8-Lead SOIC (R-8) AD8019ARU NC 1 14 NC OUT1 2 13 +VS –IN2 –IN1 3 12 OUT2 +IN2 +IN1 4 11 –IN2 –VS 5 10 +IN2 PWDN 6 9 NC NC 7 8 DGND 1 8 +VS –IN1 2 7 OUT2 +IN1 3 6 –VS 4 5 TE OUT1 NC = NO CONNECT B SO The AD8019 is a low cost xDSL line driver optimized to drive a minimum of 13 dBm into a 100 Ω load while delivering outstanding distortion performance. The AD8019 is designed on a 24 V high-speed bipolar process enabling the use of ± 12 V power supplies or 12 V only. When operating from a single 12 V supply the highly efficient amplifier architecture can typically deliver 170 mA output current into low impedance loads through a 1:2 turns ratio transformer. Hybrid designs using ± 12 V supplies enable the use of a 1:1 turns ratio transformer, minimizing attenuation of the receive signal. The AD8019 typically draws 9 mA/ amplifier quiescent current. A 1-bit digital power down feature reduces the quiescent current to approximately 1.6 mA/amplifier. O Figure 1 shows typical Out of Band SFDR performance under ADSL CPE (upstream) conditions. SFDR is measured while driving a 13 dBm ADSL DMT signal into a 100 Ω line with 50 Ω back termination. 10dB/DIV LE APPLICATIONS ADSL, VDSL, HDSL, and Proprietary xDSL USB, PCI, PCMCIA Modems, and Customer Premise Equipment (CPE) PRODUCT DESCRIPTION AD8019AR 14-Lead TSSOP (RU-14) 132.5 –80dBc 137.5 FREQUENCY – kHz 142.5 Figure 1. Out-of-Band SFDR; VS = ± 12 V; 13 dBm Output Power into 200 Ω, Upstream The AD8019 comes in thermally enhanced 8-lead SOIC and 14-lead TSSOP packages. The 8-lead SOIC is pin-compatible with the AD8017 12 V line driver. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 (@ 25ⴗC, VS = 12 V, RL = 25 ⍀, RF = 500 ⍀, TMIN = –40ⴗC, TMAX = +85ⴗC, unless AD8019–SPECIFICATIONS otherwise noted.) Conditions Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Out-of-Band SFDR MTPR Input Voltage Noise Input Current Noise Crosstalk DC PERFORMANCE Input Offset Voltage G = +5 G = +1, VOUT < 0.4 V p-p, RL = 100 Ω G = +2, VOUT < 0.4 V p-p, RL = 100 Ω VOUT < 0.4 V p-p, RL = 100 Ω G = +5, VOUT < 0.4 V p-p, RL = 100 Ω VOUT = 4 V p-p Noninverting, VOUT = 4 V p-p Noninverting, VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p 175 70 VOUT = 3 V p-p (Differential) 100 kHz, RL(DM) = 50 Ω 500 kHz, RL(DM) = 50 Ω 100 kHz, RL(DM) = 50 Ω 500 kHz, RL(DM) = 50 Ω 144 kHz–1.1 MHz, Differential R L = 70 Ω 25 kHz–138 kHz, Differential R L = 70 Ω f = 100 kHz f = 100 kHz f = 1 MHz, G = +2 TMIN–TMAX Input Offset Voltage Match Open-Loop Gain TMIN–TMAX VOUT = 6 V p-p, RL = 25 Ω TMIN–TMAX B SO INPUT CHARACTERISTICS Input Resistance Input Capacitance +Input Bias Current TMIN–TMAX –Input Bias Current TMIN–TMAX +Input Bias Current Match TMIN–TMAX –Input Bias Current Match CMRR Input CM Voltage Range O OUTPUT CHARACTERISTICS Output Resistance Output Voltage Swing Output Current Short Circuit Current1 POWER SUPPLY Supply Current/Amp Operating Range Power Supply Rejection Ratio LOGIC LEVELS tON tOFF PWDN = “1” Voltage PWDN = “0” Voltage PWDN = “1” Bias Current PWDN = “0” Bias Current Typ Max TMIN–TMAX ∆VCM = –4 V to +4 V RL = 25 Ω SFDR –80 dBc into 25 Ω at 100 kHz PWDN = 5 V TMIN–TMAX PWDN = 0 V Dual Supply ∆±VS = +1.0 V to –1.0 V 72 72 –3 –4 –1.5 –1.8 –1.0 –1.5 –0.5 –0.8 71 2 MHz MHz MHz MHz MHz MHz V/µs ns ns –78 –74 –85 –80 –80 –72 8 0.9 –80 dBc dBc dBc dBc dBc dBc nV/√Hz pA√Hz dB 8 10 1 2 80 80 10 0.5 +1 –0.5 –0.2 +0.1 20 23 12 17 +3 +4 +1.5 +1.8 +1.0 +1.5 +0.5 +0.8 74 10 0.8 ± 4.0 65 MΩ pF µA µA µA µA µA µA µA µA dB V Ω V mA mA 10.5 14.5 2.0 ± 6.0 mA mA mA V dB +VS 0.5 ns ns V V µA µA 200 400 9 mV mV mV mV dB dB +4.8 0.2 –4.8 175 Unit 35 180 75 6 35 50 450 5.5 40 TE 0.1 dB Bandwidth Min LE Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth 68 VPWDN = 0 V to 3 V; VIN = 10 MHz, G = +5 120 80 1.8 220 –100 NOTES 1 This device is protected from overheating during a short-circuit by a thermal shutdown circuit. Specifications subject to change without notice. –2– REV. 0 AD8019 (@ 25ⴗC, VS = ⴞ12 V, RL = 100 ⍀, RF = 500 ⍀, TMIN = –40ⴗC, TMAX = +85ⴗC, unless otherwise noted.) Conditions 0.1 dB Bandwidth Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Out-of-Band SFDR MTPR Input Voltage Noise Input Current Noise Crosstalk DC PERFORMANCE Input Offset Voltage G = +5 G = +1, VOUT < 0.4 V p-p G = +2, VOUT < 0.4 V p-p VOUT < 0.4 V p-p VOUT = 4 V p-p Noninverting, VOUT = 4 V p-p Noninverting, VOUT = 2 V p-p 0.1%, VOUT = 2 V p-p 175 70 VOUT = 16 V p-p (Differential) 100 kHz, RL(DM) = 200 Ω 500 kHz, RL(DM) = 200 Ω 100 kHz, RL(DM) = 200 Ω 500 kHz, RL(DM) = 200 Ω 144 kHz–500 kHz, Differential R L = 200 Ω 25 kHz–138 kHz, Differential R L = 200 Ω f = 100 kHz f = 100 kHz f = 1 MHz, G = +2 TMIN–TMAX Input Offset Voltage Match Open-Loop Gain TMIN–TMAX VOUT = 18 V p-p, RL = 100 Ω TMIN–TMAX B SO INPUT CHARACTERISTICS Input Resistance Input Capacitance +Input Bias Current TMIN–TMAX –Input Bias Current TMIN–TMAX +Input Bias Current Match TMIN–TMAX –Input Bias Current Match CMRR Input CM Voltage Range O OUTPUT CHARACTERISTICS Output Resistance Output Voltage Swing Output Current Short Circuit Current1 POWER SUPPLY Supply Current/Amp Operating Range Power Supply Rejection Ratio LOGIC LEVELS tON tOFF PWDN = “1” Voltage PWDN = “0” Voltage PWDN = “1” Bias Current PWDN = “0” Bias Current TMIN–TMAX ∆VCM = –10 V to +10 V RL = 100 Ω SFDR –80 dBc into 100 Ω at 100 kHz PWDN = High TMIN–TMAX PWDN = Low Dual Supply ∆±VS = +1.0 V to –1.0 V 86 –3 –3.8 –1.5 –1.7 –1.0 –2.4 –1.0 –2.5 71 –10 Max 35 180 75 5.5 50 400 5.5 40 MHz MHz MHz MHz MHz V/µs ns ns –80 –72 –85 –80 –80 –73 8 0.9 –85 dBc dBc dBc dBc dBc dBc nV/√Hz pA√Hz dB 5 10 1 2 92 90 10 0.5 –0.5 –0.2 +0.2 +0.1 20 12 18 mV mV mV mV dB dB +3 +3.8 +1.5 +1.7 +1.0 +2.4 +1.0 +2.5 MΩ pF µA µA µA µA µA µA µA µA dB V 76 +10 +10.8 Ω V mA mA 10 11.5 1.75 ± 12 mA mA mA V dB +VS 0.5 ns ns V V µA µA 0.2 –10.8 125 170 800 9 ± 4.0 61 Unit 0.8 64 VPWDN = 0 V to 3 V; VIN = 10 MHz, G = +5 120 80 1.8 220 –100 NOTES 1 This device is protected from overheating during a short-circuit by a thermal shutdown circuit. Specifications subject to change without notice. REV. 0 Typ TE DYNAMIC PERFORMANCE –3 dB Bandwidth Min LE Parameter –3– AD8019 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V Internal Power Dissipation TSSOP-14 Package2 . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 W SOIC-8 Package3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . . ± VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ± VS Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C The maximum power that can be safely dissipated by the AD8019 is limited by the associated rise in junction temperature. The maximum safe junction temperature for a plastic encapsulated device is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. The output stage of the AD8019 is designed for maximum load current capability. As a result, shorting the output to common can cause the AD8019 to source or sink 500 mA. To ensure proper operation, it is necessary to observe the maximum power derating curves. Direct connection of the output to either power supply rail can destroy the device. TE NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device on a four-layer board with 10 inches 2 of 1 oz. copper at 85°C 14-lead TSSOP package: θJA = 90°C/W. 3 Specification is for device on a four-layer board with 10 inches 2 of 1 oz. copper at 85°C 8-lead SOIC package: θJA = 100°C/W. 2.0 B SO TSSOP 1.5 LE MAXIMUM POWER DISSIPATION – W 2.5 1.0 SOIC 0.5 0 –40 –30 –20 –10 0 10 20 30 40 50 AMBIENT TEMPERATURE – ⴗC 60 70 80 Figure 2. Plot of Maximum Power Dissipation vs. Temperature for AD8019 for TJ = 150 °C ORDERING GUIDE Temperature Range Package Description Package Option AD8019ARU AD8019ARU-Reel AD8019ARU-EVAL AD8019AR AD8019AR-Reel AD8019AR-EVAL –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 14-Lead TSSOP 14-Lead TSSOP Evaluation Board 8-Lead SOIC 8-Lead SOIC Evaluation Board RU-14 RU-14 Reel ARU-EVAL R-8 R-8 Reel AR EVAL O Model CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8019 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 Typical Performance Characteristics–AD8019 124⍀ +VS 499⍀ VOUT RL +VIN +VO 50⍀ 0.1␮F VIN 500⍀ 49.9⍀ + +VS 0.1␮F + 10␮F 0.1␮F 47␮F 55⍀ 0.1␮F 0.1␮F 55⍀ + 10␮F RL 500⍀ 50⍀ –VO –VIN –VS –VS TPC 4. Differential Test Circuit; G = +10 TE TPC 1. Single-Ended Test Circuit; G = +5 100 100 80 80 60 60 VOLTS – mV 40 20 0 –20 –40 0 –20 –40 –60 –60 –80 –80 0 100 200 300 400 500 600 700 B SO –100 –100 20 LE VOUT – mV 40 –100 –100 0 100 TIME – ns 4 3 1 O VOUT – Volts 2 0 –1 300 400 500 600 TIME – ns 0 –1 0 100 200 300 400 500 600 700 TIME – ns TPC 3. 4 V Step Response; G = +5, VS = ± 6 V, RL = 25 Ω, Single-Ended REV. 0 1 –4 –100 700 700 2 –3 200 600 3 –3 100 500 4 –2 0 400 TPC 5. 100 mV Step Response; G = +5, VS = ± 12 V, RL = 100 Ω, Single-Ended –2 –4 –100 300 TIME – 100ns/DIV VOUT – Volts TPC 2. 100 mV Step Response; G = +5, VS = ± 6 V, RL = 25 Ω, Single-Ended 200 TPC 6. 4 V Step Response; G = +5, VS = ± 12 V, RL = 100 Ω, Single-Ended –5– –20 –20 –30 –30 –40 –40 DISTORTION – dBc DISTORTION – dBc AD8019 –50 –60 2ND –70 3RD –50 3RD –60 –70 –80 –80 –90 –90 2ND –100 0.01 0.1 1 –100 0.01 5 0.1 1 5 FREQUENCY – MHz TE FREQUENCY – MHz TPC 7. Distortion vs. Frequency; VS = ± 12 V, RL = 200 Ω, Differential, VO = 16 V p-p TPC 10. Distortion vs. Frequency; VS = ± 6 V, RL = 50 Ω, Differential, VO = 3 V p-p –30 –20 –30 LE –40 DISTORTION – dBc DISTORTION – dBc –40 –50 –60 3RD HARMONIC –70 2ND HARMONIC B SO –80 –90 –100 50 75 100 125 150 175 200 –50 –60 –70 2ND –90 –100 0 2 –20 6 8 10 12 14 16 18 20 TPC 11. Distortion vs. Output Voltage; f = 100 kHz, VS = ± 6 V, G = +10, RL = 50 Ω, Differential O –30 4 DIFFERENTIAL OUTPUT VOLTAGE – V p-p PEAK OUTPUT CURRENT – mA TPC 8. Distortion vs. Peak Output Current; VS = ± 6 V; RL = 10 Ω; f = 100 kHz; Single-Ended; Second Harmonic 3RD –80 –10 –20 –30 DISTORTION – dBc DISTORTION – dBc –40 –50 –60 2ND HARMONIC –70 3RD HARMONIC –40 –50 2ND –60 –70 –80 –80 3RD –90 –90 –100 50 –100 –110 75 100 125 150 175 200 225 250 0 PEAK OUTPUT CURRENT – mA 2 4 6 8 10 12 14 16 18 20 DIFFERENTIAL OUTPUT VOLTAGE – V p-p TPC 9. Distortion vs. Peak Output Current; VS = ± 12 V; RL = 25 Ω; f = 100 kHz; Single-Ended; Second Harmonic TPC 12. Distortion vs. Output Voltage; f = 500 kHz, VS = ± 6 V, G = +10, RL = 50 Ω, Differential –6– REV. 0 AD8019 –20 11 –30 8 5 OUTPUT VOLTAGE – dBV DISTORTION – dBc –40 –50 –60 –70 2ND 3RD –80 2 –1 –4 –7 –10 –13 –90 –16 –100 –19 0 5 10 15 20 25 30 35 40 45 50 10 1 TE 0 –10 –20 LE –10 –20 –40 CMRR – dB –30 –50 –60 2ND 3RD –70 –40 –50 909⍀ –60 –80 –90 –100 –110 0 B SO DISTORTION – dBc –30 5 10 15 20 25 30 35 40 45 –70 –80 –90 0.01 50 TPC 14. Distortion vs. Output Voltage; f = 500 kHz, VS = ± 12 V, G = +10, RL = 200 Ω, Differential O 1.1 1.0 VOH +25ⴗC 0.7 VOH VOL VOL +85ⴗC 0.6 0.5 0.1 VOH 1 VOUT 50⍀ 909⍀ 1 10 FREQUENCY – MHz 100 1000 11 8 5 –40ⴗC 0.9 0.8 0.1 909⍀ 50⍀ TPC 17. CMRR vs. Frequency; VS = ± 12 V, RL = 100 Ω OUTPUT VOLTAGE – dBV 1.2 909⍀ VIN 50⍀ DIFFERENTIAL OUTPUT VOLTAGE – V p-p OUTPUT SATURATION VOLTAGE – Volts 1000 TPC 16. Output Voltage vs. Frequency; VS = ± 12 V, RL = 100 Ω; G = +5 TPC 13. Distortion vs. Output Voltage; f = 100 kHz, VS = ± 12 V, G = +10, RL = 200 Ω, Differential 10 2 –1 –4 –7 –10 –13 VOL –16 100 –19 1000 LOAD CURRENT – mA TPC 15. Output Saturation Voltage vs. Load; VS = ± 12 V, VS = ± 6 V REV. 0 100 FREQUENCY – MHz DIFFERENTIAL OUTPUT VOLTAGE – V p-p 1 10 100 FREQUENCY – MHz 1000 TPC 18. Output Voltage vs. Frequency; VS = ± 6 V, RL = 100 Ω; G = +5 –7– AD8019 –10 –20 –20 –30 –40 CROSSTALK – dB –PSRR –50 +PSRR –60 –50 –60 –70 –70 –80 –80 –90 –90 0.01 0.1 1 10 FREQUENCY – MHz 100 –100 0.01 1000 TPC 19. PSRR vs. Frequency; RL = 100 Ω 100 0.1 1 10 FREQUENCY – MHz 120 500⍀ 110 100 LE 1 1 GAIN – dB +INOISE 1 10 FREQUENCY – kHz 100 0.1 1000 O 6.8pF 50⍀ 50⍀ 135 40 90 PHASE 45 10 0 0 –10 –20 0.001 0.01 0.1 1 10 FREQUENCY – MHz 100 –45 1000 VIN VOUT 6.8pF 1.1k⍀ 1.1k⍀ VIN 180 50 2mV/DIV ⴞ0.1% 2mV/DIV ⴞ0.1% VOUT 1.1k⍀ 50⍀ 50⍀ TPC 23. Open-Loop Gain and Phase vs. Frequency TPC 20. Noise vs. Frequency VIN 225 50⍀ 30 B SO 0.1 50⍀ AOL 60 20 –INOISE 10⍀ 270 2k⍀ 70 INOISE – pA Hz VNOISE – nV Hz 80 10 0.1 0.01 50⍀ 10⍀ 90 10 1000 TPC 22. Crosstalk vs. Frequency, VS = ± 12 V, VS = ± 6 V; G = +2; VIN = 10 dBm 100 VNOISE 100 PHASE – Degrees –40 TE PSRR – dB –30 1.1k⍀ 50⍀ VOUT 50⍀ VIN 50⍀ 20ns/DIV VOUT 50⍀ 20ns/DIV TPC 24. Settling Time 0.1%; VS = ± 6 V, RL = 100 Ω, VOUT = 2 V p-p TPC 21. Settling Time 0.1%; VS = ± 12 V, RL = 100 Ω, VOUT = 2 V p-p –8– REV. 0 AD8019 1000 VOUT VIN = 1V/DIV VOUT = 2V/DIV OUTPUT IMPEDANCE – ⍀ 100 10 0V 1 VIN 0.1 0.01 0V 1 10 FREQUENCY – MHz 0.1 100 –200 0 400 800 1200 1600 TIME – ns TE 0.001 0.01 TPC 25. Output Impedance vs. Frequency; VS = ± 12 V; VS = ± 6 V TPC 28. Overload Recovery; VS = ± 6 V, G = +5, RL = 100 Ω VIN = 2V/DIV VOUT = 5V/DIV VIN = 1V/DIV VOUT = 2V/DIV VOUT LE VOUT 0V 0V VIN VIN 0V –100 B SO 0V 0 100 300 400 500 TIME – ns 200 600 700 800 900 TPC 26. Overload Recovery; VS = ± 12 V, G = +5, RL =100 Ω O 0V VIN 0V –100 0 100 200 300 400 500 TIME – ns 600 700 800 900 TPC 27. Overload Recovery; VS = ±12 V, G = +5, RL = 100 Ω REV. 0 0 400 800 TIME – ns 1200 1600 TPC 29. Overload Recovery; VS = ± 6 V, G = +5, RL = 100 Ω VIN = 2V/DIV VOUT = 5V/DIV VOUT –200 –9– AD8019 0 –30 –10 –40 –20 13dBm 13dBm –30 –40 SFDR – dBc MTPR – dBc –50 12dBm –50 –60 11dBm 12dBm –70 11dBm –60 –80 –70 10dBm 10dBm –80 1.0 1.1 1.2 1.3 1.4 1.5 1.6 –90 1.0 1.7 1.1 1.2 1.3 1.4 TURNS RATIO – N 1.5 1.6 1.7 TE TURNS RATIO – N TPC 30. MTPR vs. Turns Ratio; VS = ± 6 V, RL = 100 Ω Line TPC 32. SFDR vs. Turns Ratio; VS = ± 6 V, RL = 100 Ω Line –50 –30 18dBm –55 –40 18dBm LE –50 SFDR – dBc MTPR – dBc –60 17dBm –60 16dBm –65 17dBm –70 –75 –80 –80 1.0 B SO 13dBm –70 1.1 1.2 1.3 1.4 1.5 1.6 1.7 TURNS RATIO – N 16dBm –90 1.0 1.1 13dBm 1.2 1.3 1.4 1.5 1.6 1.7 TURNS RATIO – N TPC 33. SFDR vs. Turns Ratio; VS = ± 12 V, RL = 100 Ω Line O TPC 31. MTPR vs. Turns Ratio; VS = ± 12 V, RL = 100 Ω Line –85 –10– REV. 0 AD8019 GENERAL INFORMATION +VS The AD8019 is a voltage feedback amplifier with high output current capability. As a voltage feedback amplifier, the AD8019 features lower current noise and more applications flexibility than current feedback designs. It is fabricated on Analog Devices’ proprietary High Voltage eXtra Fast Complementary Bipolar Process (XFCB-HV), which enables the construction of PNP and NPN transistors with similar fTs in the 4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. These features enable the construction of high-frequency, low-distortion amplifiers. +VO –VS –VS Figure 3. Simplified Differential Driver Remembering that each output device only dissipates for half the time gives a simple integral that computes the power for each device: A digitally programmable logic pin (PWDN) is available on the TSSOP-14 package. It allows the user to select between two operating conditions, full on and shutdown. The DGND pin is the logic reference. The threshold for the PWDN pin is typically 1.8 V above DGND. If the power-down feature is not being used, it is better to tie the DGND pin to the lowest potential that the AD8019 is tied to and place the PWDN pin at a potential at least 3 V higher than that of the DGND pin, but lower than the positive supply voltage. TE 1  (2 VO )  ∫ (VS – VO ) × 2  RL  The total supply power can then be computed as: 2 PTOT = 4 (VS ∫ |VO | − ∫ VO ) × In this differential driver, VO is the voltage at the output of one amplifier, so 2 VO is the voltage across RL. RL is the total impedance seen by the differential driver, including back termination. Now, with two observations the integrals are easily evaluated. First, the integral of VO2 is simply the square of the rms value of VO. Second, the integral of | VO | is equal to the average rectified value of VO, sometimes called the mean average deviation, or MAD. It can be shown that for a DMT signal, the MAD value is equal to 0.8 times the rms value. B SO Careful attention must be paid to decoupling the power supply. High quality capacitors with low equivalent series resistance (ESR) such as multilayer ceramic capacitors (MLCCs) should be used to minimize supply voltage ripple and power dissipation. In addition, 0.1 µF MLCC decoupling capacitors should be located no more than 1/8 inch away from each of the power supply pins. A large, usually tantalum, 10 µF to 47 µF capacitor is required to provide good decoupling for lower frequency signals and to supply current for fast, large signal changes at the AD8019 outputs. PTOT = 4 (0.8 VO rms VS – VO rms2 ) × 1 + 2 α IQ VS + POUT RL For the AD8019 operating on a single 12 V supply and delivering a total of 16 dBm (13 dBm to the line and 3 dBm to the matching network) into 17.3 Ω (100 Ω reflected back through a 1:1.7 transformer plus back termination), the dissipated power is: = 332 mW + 40 mW POWER DISSIPATION It is important to consider the total power dissipation of the AD8019 in order to properly size the heat sink area of an application. Figure 3 is a simple representation of a differential driver. With some simplifying assumptions we can estimate the total power dissipated in this circuit. If the output current is large compared to the quiescent current, computing the dissipation in the output devices and adding it to the quiescent power dissipation will give a close approximation of the total power dissipation in the package. A factor α (~0.6-1) corrects for the slight error due to the Class A/B operation of the output stage. It can be estimated by subtracting the quiescent current in the output stage from the total quiescent current and ratioing that to the total quiescent current. For the AD8019, α = 0.833. O 1 + 2 α IQ VS + POUT 2 LE The AD8019 can be powered with a good quality (i.e., low-noise) supply anywhere in the range from +12 V to ± 12 V. In order to optimize the ADSL upstream drive capability of 13 dBm and maintain the best Spurious Free Dynamic Range (SFDR), the AD8019 circuit should be powered with a well-regulated supply. REV. 0 –VO RL POWER-DOWN FEATURE POWER SUPPLY AND DECOUPLING +VS = 372 mW Using these calculations and a θJA of 90°C/W for the TSSOP package and 100°C/W for the SOIC, Tables I–IV show junction temperature versus power delivered to the line for several supply voltages while operating with an ambient temperature of 85°C. The shaded areas indicate operation at a junction temperature over the absolute maximum rating of 150°C, and should be avoided. Table I. Junction Temperature vs. Line Power and Operating Voltage for TSSOP PLINE, dBm ⴞ12 13 14 15 16 17 18 132 134 136 139 141 143 –11– VSUPPLY ⴞ12.5 134 137 139 141 144 147 ⴞ13 137 139 141 144 147 150 AD8019 Table II. Junction Temperature vs. Line Power and Operating Voltage for SOIC VSUPPLY PLINE, dBm ⴞ12 ⴞ12.5 ⴞ13 13 14 15 16 17 18 137 140 142 145 147 150 140 142 145 148 150 153 143 145 148 151 154 157 Evaluation Board The AD8019 is available installed on an evaluation board for both package styles. Figures 8 and 9 show the schematics for the TSSOP evaluation board. The receiver circuit on these boards is typically unpopulated. Requesting samples of the AD8022AR, along with either of the AD8019 evaluation boards, will provide the capability to evaluate the AD8019 along with other Analog Devices products in a typical transceiver circuit. The evaluation circuits have been designed to replicate the CPE side analog transceiver hybrid circuits. Table III. Junction Temperature vs. Line Power and Operating Voltage for TSSOP TE The circuit mentioned above is designed using a 1-transformer transceiver topology including a line receiver, line driver, line matching network, an RJ11 jack for interfacing to line simulators, and differential inputs. VSUPPLY +12 +13 13 14 15 16 115 116 118 120 118 119 121 123 AC-coupling capacitors of 0.1 µF, C8, and C10, in combination with 10 kΩ, resistors R24 and R25, will form a 1st order highpass pole at 160 Hz. Transformer Selection LE PLINE, dBm Customer premise ADSL requires the transmission of a 13 dBm (20 mW) DMT signal. The DMT signal has a crest factor of 5.3, requiring the line driver to provide peak line power of 560 mW. 560 mW peak line power translates into a 7.5 V peak voltage on a 100 Ω telephone line. Assuming that the maximum low distortion output swing available from the AD8019 line driver on a ± 12 V supply is 20 V and taking into account the power lost due to the termination resistance, a step-up transformer with turns ratio of 1:1 is adequate for most applications. If the modem designer desires to transmit more than 13 dBm down the twisted pair, a higher turns ratio can be used for the transformer. This trade-off comes at the expense of higher power dissipation by the line driver as well as increased attenuation of the downstream signal that is received by the transceiver. Table IV. Junction Temperature vs. Line Power and Operating Voltage for SOIC VSUPPLY +12 +13 13 14 15 16 118 120 122 124 121 123 125 128 B SO PLINE, dBm energy and make the circuit less susceptible to RF interference. Adherence to stripline design techniques for long signal traces (greater than about 1 inch) is recommended. Thermal stitching, which connects the outer layers to the internal ground plane(s), can help to utilize the thermal mass of the PCB to draw heat away from the line driver and other active components. LAYOUT CONSIDERATIONS O As is the case with all high-speed applications, careful attention to printed circuit board layout details will prevent associated board parasitics from becoming problematic. Proper RF design technique is mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low-impedance return path. Removing the ground plane on all layers from the areas near the input and output pins will reduce stray capacitance, particularly in the area of the inverting inputs. The signal routing should be short and direct in order to minimize parasitic inductance and capacitance associated with these traces. Termination resistors and loads should be located as close as possible to their respective inputs and outputs. Input and output traces should be kept as far apart as possible to minimize coupling (crosstalk) though the board. Wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize balanced performance. When running differential signals over a long distance, the traces on the PCB should be close together or any differential wiring should be twisted together to minimize the area of the loop that is formed. This will reduce the radiated In the simplified differential drive circuit shown in Figure 7, the AD8019 is coupled to the phone line through a step-up transformer with a 1:1 turns ratio. R1 and R2 are back termination or line matching resistors, each 50 Ω (100 Ω/(2 × 12)) where 100 Ω is the approximate phone line impedance. A transformer reflects impedance from the line side to the IC side as a value inversely proportional to the square of the turns ratio. The total differential load for the AD8019, including the termination resistors, is 200 Ω. Even under these conditions the AD8019 provides low distortion signals to within 2 V of the power supply rails. One must take care to minimize any capacitance present at the outputs of a line driver. The sources of such capacitance can include, but are not limited to EMI suppression capacitors, overvoltage protection devices and the transformers used in the hybrid. Transformers have two kinds of parasitic capacitances, distributed, or bulk capacitance, and interwinding capacitance. Distributed capacitance is a result of the capacitance created between each adjacent winding on a transformer. Interwinding capacitance is the capacitance that exists between the windings on the primary and secondary sides of the transformer. The existence of these capacitances is unavoidable, but in specifying –12– REV. 0 AD8019 from other subbands, regardless of whether the corruption comes from an adjacent subband or harmonics of other subbands. a transformer, one should do so in a way to minimize them in order to avoid operating the line driver in a potentially unstable environment. Limiting both distributed and interwinding capacitance to less than 20 pF each should be sufficient for most applications. Conventional methods of expressing the output signal integrity of line drivers such as single tone harmonic distortion or THD, two-tone Intermodulation Distortion (IMD) and third order intercept (IP3) become significantly less meaningful when amplifiers are required to process DMT and other heavily modulated waveforms. A typical ADSL upstream DMT signal can contain as many as 27 carriers (subbands or tones) of QAM signals. Multi-Tone Power Ratio (MTPR) is the relative difference between the measured power in a typical subband (at one tone or carrier) versus the power at another subband specifically selected to contain no QAM data. In other words, a selected subband (or tone) remains open or void of intentional power (without a QAM signal) yielding an empty frequency bin. MTPR, sometimes referred to as the ‘empty bin test,’ is typically expressed in dBc, similar to expressing the relative difference between single tone fundamentals and second or third harmonic distortion components. Measurements of MTPR are typically made on the line side or secondary side of the transformer. Stability Enhancements TE Voltage feedback amplifiers may exhibit sensitivity to capacitance present at the inverting input. Parasitic capacitance, as small as several picofarads, in combination with the high-impedance of the input can create a pole that can dramatically decrease the phase margin of the amplifier. In the case of the AD8019, a compensation capacitor of 10 pF–20 pF in parallel with the feedback resistor will form a zero that can serve to cancel out the effects of the parasitic capacitance. Placing 100 Ω in series with each of the noninverting inputs serves to isolate the inputs from each other and from any high frequency signals that may be coupled into the amplifier via the midsupply bias. It may also be necessary to configure the line driver as two separate, noninverting amplifiers rather than a single differential driver. When doing this, the two gain resistors can share an ac coupling capacitor of 0.1 µF to minimize any dc errors. 20 Receive Channel Considerations LE Adhering to previously mentioned layout techniques will also be of assistance in keeping the amplifier stable. 0 B SO POWER – dBm A transformer used at the output of the differential line driver to step up the differential output voltage to the line has the inverse effect on signals received from the line. A voltage reduction or attenuation equal to the inverse of the turns ratio is realized in the receive channel of a typical bridge hybrid. The turns ratio of the transformer may also be dictated by the ability of the receive circuitry to resolve low-level signals in the noisy twisted pair telephone plant. While higher turns ratio transformers boost transmit signals to the appropriate level, they also effectively reduce the received signal to noise ratio due to the reduction in the received signal strength. Using a transformer with as low a turns ratio as possible will limit degradation of the received signal. The AD8022, a dual amplifier with typical RTI voltage noise of only 2.5 nV/√Hz and a low supply current of 4 mA/amplifier is recommended for the receive channel. O DMT Modulation, Multi-Tone Power Ratio (MTPR) and Out-of-Band SFDR ADSL systems rely on Discrete Multi-Tone (or DMT) modulation to carry digital data over phone lines. DMT modulation appears in the frequency domain as power contained in several individual frequency subbands, sometimes referred to as tones or bins, each of which are uniformly separated in frequency. A uniquely encoded, Quadrature Amplitude Modulation (QAM)like signal occurs at the center frequency of each subband or tone. See Figure 4 for an example of a DMT waveform in the frequency domain, and Figure 5 for a time domain waveform. Difficulties will exist when decoding these subbands if a QAM signal from one subband is corrupted by the QAM signal(s) REV. 0 –20 –40 –60 –80 0 100 50 FREQUENCY – kHz 150 Figure 4. DMT Waveform in the Frequency Domain MTPR versus transformer turns ratio is depicted in TPCs 30 and 31 and covers a variety of line power ranging from 10 dBm to 18 dBm. As the turns ratio increases, the driver hybrid can deliver more undistorted power to the load due to the high output current capability of the AD8019. Significant degradation of MTPR will occur if the output of the driver swings to the rails, causing clipping at the DMT voltage peaks. Driving DMT signals to such extremes not only compromises “in band” MTPR, but will also produce spurs that exist outside of the frequency spectrum containing the transmitted signal. “Outof-band” spurious free dynamic range (SFDR) can be defined as the relative difference in amplitude between these spurs and a tone in one of the upstream bins. Compromising out-of-band SFDR is the equivalent of increasing near-end cross talk (NEXT). Regardless of terminology, maintaining out-of-band SFDR while reducing NEXT will improve the overall performance of the modems connected at either end of the twisted pair. –13– AD8019 Generating DMT Signals 4 At this time, DMT-modulated waveforms are not typically menu-selectable items contained within arbitrary waveform generators. Even using (AWG) software to generate DMT signals, AWGs that are available today may not deliver DMT signals sufficient in performance with regard to MTPR due to limitations in the D/A converters and output drivers used by AWG manufacturers. Similar to evaluating single-tone distortion performance of an amplifier, MTPR evaluation requires a DMT signal generator capable of delivering MTPR performance better than that of the driver under evaluation. Generating DMT signals can be accomplished using a Tektronics AWG 2021 equipped with Option 4, (12-/24-bit, TTL Digital Data Out), digitally coupled to Analog Devices’ AD9754, a 14-bit TxDAC®, buffered by an AD8002 amplifier configured as a differential driver. Note that the DMT waveforms, available on the Analog Devices website, www.analog.com, or similar. WFM files are needed to produce the necessary digital data required to drive the TxDAC from the optional TTL Digital Data output of the TEK AWG2021. 3 VOLTS 2 –2 0.10 0.15 0.20 Figure 5. DMT Signal in the Time Domain LE 10k⍀ 0.05 TE –3 –0.25 –0.20 –0.15 –0.10 –0.05 0 TIME – ms 0.1␮F 100⍀ 0 –1 +12V 0.1␮F 1 10␮F R1 17.3⍀ 301⍀ 50⍀ RL = 100⍀ POUT 16dBm B SO VIN 6V 0.1␮F 0.1␮F LINE POWER 13dBm 50⍀ 301⍀ R2 17.3⍀ 10k⍀ 1:1.7 TRANSFORMER 100⍀ 0.1␮F Figure 6. Recommended Application Circuit for Single +12 V Supply +12V 0.1␮F O 0.1␮F 10␮F 100⍀ 10k⍀ R1 12.4⍀ 301⍀ 50⍀ RL = 100⍀ POUT 16dBm VIN 0.1␮F LINE POWER 13dBm 50⍀ 301⍀ R2 12.4⍀ 10k⍀ 0.1␮F 1:1 TRANSFORMER 100⍀ –12V 0.1␮F 10␮F Figure 7. Recommended Application Circuit for ± 12 V Supply TxDAC is a registered trademark of Analog Devices, Inc. –14– REV. 0 REV. 0 –15– Figure 8. TSSOP Noninverting DSL Evaluation Board Schematic R17 5k⍀ R16 5k⍀ TP3 VCC S6 P4 3 P4 2 P4 1 S5 3 B C19 0.1␮F VCC-2 S3 1 P3 S4 2 3 P3 P3 1 R31 0⍀ VCC B JP3 A 2 3 1 JP4 A 2 VCC R30 0⍀ C10 0.1␮F C28 DNI TP18 TP17 TP11 R15 50⍀ R11 50⍀ C8 0.1␮F 7 VCC;8 VEE;4 U2 AD8022 R7 DNI R6 DNI 5 6 2 3 R12 DNI R14 100⍀ R34 DNI R5 DNI R33 DNI A C5 0.1␮F JP7 3 A B 2 R41 DNI U2 AD8022 VCC;8 VEE;4 1 R29 10k⍀ 1 R40 DNI 13 C13 0.1␮F R18 301⍀ R13 DNI C16 DNI R10 DNI R9 DNI C1 DNI U1 12 10 +V 13 VCC 2 C3 DNI VCC-2 R23 DNI C2 DNI 3 TP4 TP5 C18 DNI 2 A JP6 1 B R39 DNI R21 DNI R4 DNI 100⍀ 1WATT R37 DNI C12 DNI C27 DNI C22 DNI C11 DNI TP7 TB1 1 4 3 2 1 L5 BEAD TP23 TP24 C7 DNI C29 DNI JP5 R36 DNI R35 DNI *DNI : DO NOT INSTALL TB1 3 TB1 2 VCCIN T1 NC = 5,6 DNI + C4 10␮F 25V + C21 0.1␮F C26 0.1␮F TP25 TP26 L1 BEAD C14 10␮F 25V TE B TP9 PR2 PR1 LE R3 DNI R20 DNI R28 DNI 1 R1 TP8 TP6 A R22 DNI AD8019 5 VEE R19 301⍀ 11 –V R42 DNI 2 –V AD8019 5 U1 VEE R2 50⍀ 3 4 +V VCC B SO VCC-2 R24 10k⍀ R8 100⍀ O TP10 R38 DNI R32 100⍀ VEE U2 DECOUPLING C17 DNI TP12 U1 DECOUPLING C20 0.1␮F 7 8 P1 VCC C23 DNI 1 2 3 4 5 6 U2 DECOUPLING TP19 TP2 TP1 C6 DNI C9 DNI U1 DECOUPLING C15 0.01␮F 7 8 9 10 AD8019 AD8019 VCC R25 VAL 9 NC4 R26 VAL 1 JP1 A 2 B 3 AD8019 U1 6 PWDN C24 VAL DGND NC1 8 1 NC2 NC3 7 14 TE R27 VAL Figure 9. DSL Driver Input Control Circuit LE Figure 11. TSSOP Evaluation Board Silkscreen Bottom B SO AGND 2 Figure 12. TSSOP Evaluation Board Power Plane O Figure 10. TSSOP Evaluation Board Silkscreen Top AGND –16– REV. 0 TE AD8019 Figure 15. Ground Plane Bottom B SO LE Figure 13. Solder Mask Top O Figure 14. Solder Mask Bottom REV. 0 –17– Figure 16. Assembly Top TE AD8019 Figure 17. Ground Plane Top O B SO LE Figure 18. Assembly Bottom –18– REV. 0 O B SO LE TE AD8019 Figure 19. Board Fabrication REV. 0 –19– AD8019 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead TSSOP (RU-14) 14 C02551–1.5–4/01(0) 0.201 (5.10) 0.193 (4.90) 8 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 7 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) TE 0.0256 (0.65) BSC 0.0079 (0.20) 0.0035 (0.090) 8ⴗ 0ⴗ 0.028 (0.70) 0.020 (0.50) LE SEATING PLANE 0.0433 (1.10) MAX 8-Lead SOIC (R-8) 0.1968 (5.00) 0.1890 (4.80) 8 1 5 4 0.2440 (6.20) 0.2284 (5.80) B SO 0.1574 (4.00) 0.1497 (3.80) PIN 1 0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) 0.102 (2.59) 0.094 (2.39) 8ⴗ 0.0098 (0.25) 0ⴗ 0.0500 (1.27) 0.0160 (0.41) 0.0075 (0.19) 0.0192 (0.49) 0.0138 (0.35) PRINTED IN U.S.A. O SEATING PLANE 0.0196 (0.50) ⴛ 45ⴗ 0.0099 (0.25) –20– REV. 0