AD8057

Low Cost, High Performance Voltage Feedback, 325 MHz Amplifiers AD8057/AD8058 FEATURES Low Cost Single (AD8057) and Dual (AD8058) High Speed 325 MHz –3 dB Bandwidth (G = +1) 1000 V/ s Slew Rate Gain Flatness 0.1 dB to 28 MHz Low Noise 7 nV/√Hz Low Power 5.4 mA/Amplifier Typical Supply Current @ 5 V Low Distortion –85 dBc @ 5 MHz, RL = 1 k Wide Supply Range from 3 V to 12 V Small Packaging AD8057 Available in SOIC-8 and SOT-23-5 AD8058 Available in SOIC-8 and MSOP APPLICATIONS Imaging DVD/CD Photodiode Preamp A-to-D Driver Professional Cameras Filters CONNECTION DIAGRAMS (TOP VIEW) RT-5 (SOT-23-5) AD8057 5 R-8 (SOIC) VOUT 1 –VS 2 +IN 3 +VS NC 1 –IN 2 +IN 3 8 7 6 NC +VS VOUT NC 4 –IN (Not to Scale) –VS 4 AD8057 (Not to Scale) 5 NC = NO CONNECT RM-8 (MSOP) R-8 (SOIC) AD8058 OUT1 –IN1 +IN1 –VS 1 2 3 4 8 7 6 5 +VS OUT2 –IN2 +IN2 (Not to Scale) GENERAL DESCRIPTION The AD8057 (single) and AD8058 (dual) are very high performance amplifiers with a very low cost. The balance between cost and performance make them ideal for many applications. The AD8057 and AD8058 will reduce the need to qualify a variety of specialty amplifiers. The AD8057 and AD8058 are voltage feedback amplifiers with the bandwidth and slew rate normally found in current feedback amplifiers. The AD8057 and AD8058 are low power amplifiers having low quiescent current and a wide supply range from 3 V to 12 V. They have noise and distortion performance required for high end video systems as well as dc performance parameters rarely found in high speed amplifiers. The AD8057 and AD8058 are available in standard SOIC packaging as well as tiny SOT-23-5 (AD8057) and MSOP (AD8058) packages. These amplifiers are available in the industrial temperature range of –40°C to +85°C. GAIN (dB) 5 4 3 2 1 0 –1 G = +5 –2 –3 G = +10 –4 –5 1 100 10 FREQUENCY (MHz) 1000 G = +2 G = +1 Figure 1. Small Signal Frequency Response R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD8057/AD8058–SPECIFICATIONS Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Conditions (@ TA = 25 C, VS = 5 V, RL = 100 unless otherwise noted.) , RF = 0 , Gain = +1, Min AD8057/AD8058 Typ Max 325 95 175 30 850 1150 30 –85 –62 –68 –35 –60 7 0.7 0.01 0.02 0.15 0.01 30 1 2.5 3 0.5 3.0 5 Unit MHz MHz MHz MHz V/µs V/µs ns dBc dBc dB dBm dB nV/√Hz pA/√Hz % % Degree Degree ns mV mV µV/°C µA µA µA dB dB MΩ pF V dB V V pF V mA mA dB Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion SFDR Third Order Intercept Crosstalk, Output to Output Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error Overload Recovery DC PERFORMANCE Input Offset Voltage G = +1, VO = 0.2 V p-p G = –1, VO = 0.2 V p-p G = +1, VO = 2 V p-p G = +1, VO = 0.2 V p-p G = +1, VO = 2 V Step, RL = 2 kΩ G = +1, VO = 4 V Step, RL = 2 kΩ G = +2, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ f = 5 MHz, VO = 2 V p-p, RL = 150 Ω f = 5 MHz, VO = 2 V p-p f = 5 MHz, G = +2 f = 100 kHz f = 100 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 1 kΩ NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 1 kΩ VIN = 200 mV p-p, G = +1 TMIN to TMAX Input Offset Voltage Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current for AD8057 Quiescent Current for AD8058 Power Supply Rejection Ratio Specifications subject to change without notice. 2.5 ± 0.75 VO = ± 2.5 V, RL = 2 kΩ VO = ± 2.5 V, RL = 150 Ω 50 50 55 52 10 2 +Input R L = 1 kΩ VCM = ± 2.5 V RL = 2 kΩ RL = 150 Ω 30% Overshoot –4.0 48 –4.0 +4.0 60 +4.0 ± 3.9 30 ± 5.0 6.0 14.0 59 7.5 15 VS = ± 5 V to ± 1.5 V 54 –2– R EV. B AD8057/AD8058 SPECIFICATIONS Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% (@ TA = 25 C, VS = 5 V, RL = 100 Conditions , RF = 0 , Gain = +1, unless otherwise noted.) Min AD8057/AD8058 Typ Max 300 155 28 700 35 –75 –54 –60 7 0.7 0.05 0.05 0.10 0.02 1 2.5 3 0.5 3.0 50 45 55 52 10 2 ± 0.9 to ± 3.4 60 0.9 to 4.1 1.2 to 3.8 30 5.0 5.4 13.5 58 5 Unit MHz MHz MHz V/µs ns dBc dBc dB nV/√Hz pA/√Hz % % Degree Degree mV mV µV/°C µA µA µA dB dB MΩ pF V dB V V pF V mA mA dB G = +1, VO = 0.2 V p-p G = +1, VO = 2 V p-p VO = 0.2 V p-p G = +1, VO = 2 V Step, RL = 2 kΩ G = +2, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, RL = 1 kΩ fC = 20 MHz, VO = 2 V p-p, RL = 1 kΩ f = 5 MHz, G = +2 f = 100 kHz f = 100 kHz NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 1 kΩ NTSC, G = +2, RL = 150 Ω NTSC, G = +2, RL = 1 kΩ NOISE/HARMONIC PERFORMANCE Total Harmonic Distortion Crosstalk, Output to Output Input Voltage Noise Input Current Noise Differential Gain Error Differential Phase Error DC PERFORMANCE Input Offset Voltage TMIN to TMAX Input Offset Voltage Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current for AD8057 Quiescent Current for AD8058 Power Supply Rejection Ratio Specifications subject to change without notice. 2.5 0.75 VO = ± 1.25 V, RL = 2 kΩ to Midsupply VO = ± 1.25 V, RL = 150 Ω to Midsupply +Input R L = 1 kΩ VCM = ± 2.5 V R L = 2 kΩ RL = 150 Ω 30% Overshoot 48 7.0 14 54 R EV. B –3– AD8057/AD8058 ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION Supply Voltage (+VS to –VS) . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 SOIC Package (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 W SOT-23-5 Package (RT) . . . . . . . . . . . . . . . . . . . . . . . 0.5 W MSOP Package (RM) . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ± VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ± 4.0 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range (R) . . . . . . . . . –65°C to +125°C Operating Temperature Range (A Grade) . . . –40°C to +85°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead SOIC Package: JA = 160°C/W 5-Lead SOT-23-5 Package: JA = 240°C/W 8-Lead MSOP Package: JA = 200°C/W The maximum power that can be safely dissipated by the AD8057/AD8058 is limited by the associated rise in junction temperature. Exceeding a junction temperature of 175°C for an extended period can result in device failure. While the AD8057/ AD8058 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150°C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves. 2.0 TJ = 150 C MAXIMUM POWER DISSIPATION (W) 1.5 8-LEAD SOIC 1.0 8-LEAD MSOP 0.5 SOT-23-5 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE ( C) 70 80 90 Figure 2. Plot of Maximum Power Dissipation vs. Temperature ORDERING GUIDE Model AD8057AR AD8057ACHIPS AD8057AR-REEL AD8057AR-REEL7 AD8057ART-R2 AD8057ART-REEL AD8057ART-REEL7 AD8057ARTZ-REEL7* AD8058AR AD8058ACHIPS AD8058AR-REEL AD8058AR-REEL7 AD8058ARZ-REEL7* AD8058ARM AD8058ARM-REEL AD8058ARM-REEL7 AD8058ARMZ-REEL7* *Lead free Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 8-Lead Narrow Body SOIC Die 8-Lead SOIC, 13" Reel 8-Lead SOIC, 7" Reel 5-Lead SOT-23 5-Lead SOT-23, 13" Reel 5-Lead SOT-23, 7" Reel 5-Lead SOT-23, 7" Reel 8-Lead Narrow Body SOIC Die 8-Lead SOIC, 13" Reel 8-Lead SOIC, 7" Reel 8-Lead SOIC, 7" Reel 8-Lead MSOP 8-Lead MSOP, 13" Reel 8-Lead MSOP, 7" Reel 8-Lead MSOP, 7" Reel Package Option R-8 Waffle Pak R-8 R-8 RT-5 RT-5 RT-5 RT-5 R-8 Waffle Pak R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 Branding Standard N/A Standard Standard H7A H7A H7A H7A Standard N/A Standard Standard Standard H8A H8A H8A H8A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8057/AD8058 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– R EV. B Typical Performance Characteristics–AD8057/AD8058 4.5 4.0 3.5 (+) OUTPUT VOLTAGE 0.0 –1.5V SWING RL = 150 –0.5 –1.0 –2.5V SWING RL = 150 ABS (–) OUTPUT –1.5 –2.0 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 0 10 VOLTS –2.5 –3.0 –3.5 –4.0 –4.5 –5V SWING RL = 150 100 1k 10k LOAD RESISTANCE ( ) 100k –5.0 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE ( C) 50 60 70 80 85 TPC 1. Output Swing vs. Load Resistance TPC 4. Negative Output Voltage Swing vs. Temperature –3.0 –3.5 6 4 –4.0 –4.5 –ISUPPLY (mA) 2 VOS (mV) –5.0 –5.5 –6.0 –6.5 –7.0 –7.5 –8.0 –40 –30 –20 –10 0 –I SUPPLY @ 1.5V VOS @ 0 VOS @ 1.5V 5V –ISUPPLY @ 5V –2 –4 10 20 30 40 TEMPERATURE ( C) 50 60 70 80 85 –6 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE ( C) 50 60 70 80 TPC 2. –ISUPPLY vs. Temperature TPC 5. VOS vs. Temperature 5.0 4.5 +5V SWING RL = 150 4.0 3.5 3.5 3.0 AVOL @ 5V 2.5 AVOL (mV/V) 3.0 2.0 1.5 VOLTS AVOL @ 2.5V 2.5 2.0 +2.5V SWING RL = 150 1.5 1.0 +1.5V SWING RL = 150 0.5 0.0 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE ( C) 50 60 70 80 85 1.0 0.5 0 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE ( C) 50 60 70 80 85 TPC 3. Positive Output Voltage Swing vs. Temperature TPC 6. Open-Loop Gain vs. Temperature R EV. B –5– AD8057/AD8058 0.00 –0.10 0.01 F +VS 4.7 F –0.20 –0.30 HP8130A PULSE GENERATOR TR/TF = 1ns VIN 50 0.001 F VOUT IB ( A) –0.40 +IB @ –0.50 –0.60 –0.70 +IB @ –I B @ –I B @ 5V 1.5V 5V 2.5V –I B @ 2.5V +IB @ 1.5V AD8057/58 4.7 F 0.01 F 0.001 F 1k –VS –0.80 –40 –30 –20 –10 0 10 20 30 40 TEMPERATURE ( C) 50 60 70 80 85 TPC 10. Test Circuit G = +1, RL = 1 kΩ for TPCs 11 and 12 TPC 7. Input Bias Current vs. Temperature 4 100mV 3 PSRR @ PSRR (mV/V) 1.5V 5V 20mV/ DIV 2 1 –100mV 0 –40 –30 –20 –10 4ns/DIV 0 10 20 30 40 TEMPERATURE ( C) 50 60 70 80 85 TPC 8. PSRR vs. Temperature TPC 11. Small Signal Step Response G = +1, R L = 1 k Ω , VS = ± 5 V 5V 0 –10 –20 PSRR (dB) –PSRR VS = –30 2.5V 1V/DIV +PSRR VS = –40 2.5V –50 –5V 4ns/DIV –60 0.1 1 10 FREQUENCY (MHz) 100 1000 TPC 9. ± PSRR vs. Frequency TPC 12. Large Signal Step Response G = +1, RL = 1 kΩ, VS = ± 5.0 V –6– R EV. B AD8057/AD8058 5 1k +VS 4.7 F 4 3 2 0.01 F HP8130A PULSE GENERATOR TR/TF = 1ns VIN 1k 50 0.001 F VOUT 4.7 F 0.01 F 0.001 F 1k GAIN (dB) 1 0 –1 G = +5 –2 –3 G = +10 –4 –5 1 100 10 FREQUENCY (MHz) 1000 G = +2 G = +1 AD8057/58 –VS TPC 13. Test Circuit G = –1, RL = 1 kΩ for TPCs 14 and 15 TPC 16. Small Signal Frequency Response, VOUT = 0.2 V p-p 5 4 100mV 3 2 GAIN (dB) 1 0 –1 –2 –3 –4 –5 1 G = +10 10 100 FREQUENCY (MHz) 1000 G = +5 G = +1 20mV/ DIV 0V G = +2 –100mV 4ns/DIV TPC 14. Small Signal Step Response G = –1, RL = 1 kΩ TPC 17. Large Signal Frequency Response, VOUT = 2 V p-p 5 4 5V 3 2 GAIN (dB) 1 0 –1 –2 G = –5 –3 –4 –5 1 G = –10 G = –2 G = –1 1V/DIV –5V 4ns/DIV 10 100 FREQUENCY (MHz) 1000 TPC 15. Large Signal Step Response G = –1, RL = 1 kΩ TPC 18. Large Signal Frequency Response R EV. B –7– AD8057/AD8058 0.5 0.4 0.3 0.2 GAIN (dB) 5.0 RISE TIME AND FALL TIME (ns) VOUT = 0.2V G = +2 RL = 1.0k RF = 1.0k 4.5 4.0 3.5 3.0 2.5 2.0 FALL TIME 1.5 RISE TIME 1.0 0.5 0.0 0 1 2 VOUT (V p-p) 3 4 0.1 0.0 –0.1 –0.2 –0.3 –0.4 –0.5 1 100 10 FREQUENCY (MHz) 1000 TPC 19. 0.1 dB Flatness G = +2 TPC 22. Rise Time and Fall Time vs. VOUT, G = +1, RL = 1 k Ω, R F = 0 Ω –50 5 DISTORTION (dBc) –70 THD SECOND RISE TIME AND FALL TIME (ns) –60 4 3 RISE TIME 2 FALL TIME 1 –80 THIRD –90 –100 –110 0.1 1 10 FREQUENCY (MHz) 100 0 0 1 2 VOUT (V p-p) 3 4 TPC 20. Distortion vs. Frequency, RL = 150 Ω TPC 23. Rise Time and Fall Time vs. VOUT, G = +2, RL = 100 Ω, RF = 402 Ω –40 0.4% –50 VOUT = –1V TO + 1V OR +1V TO –1V G = +2 RL = 100 /1k 0.3% 20MHz DISTORTION (dBc) 0.2% 0.1% –60 0.0% –0.1% 5MHz –0.2% –0.3% –0.4% –70 –80 0.0 0 0.4 0.8 1.2 1.6 2.0 2.4 VOUT (V p-p) 2.8 3.2 3.6 4.0 10 20 30 40 50 60 TIME (ns) TPC 21. Distortion vs. VOUT @ 20 MHz, 5 MHz, RL = 150 Ω, VS = ± 5.0 V TPC 24. Settling Time –8– R EV. B AD8057/AD8058 1.8V INPUT SIGNAL 2.5V OUTPUT RESPONSE 500mV/ DIV 200mV/ DIV INPUT SIGNAL = 0.6V 0V VS = 2.5V RL = 1k G = +1 OUTPUT SIGNAL 1.7V VS = 2.5V R1 = 1k G = +4 20ns/DIV 20ns/DIV TPC 25. Input Overload Recovery, VS = ± 2.5 V TPC 28. Output Overload Recovery, VS = ± 2.5 V VS = 5.0V RL = 1k G = +1 INPUT SIGNAL 5V 5.0V 1V/DIV OUTPUT SIGNAL = 4.0V 4.5V VS = 5.0V R1 = 1k G = +4 500mV/ DIV 0V 20ns/DIV 20ns/DIV 37ns TPC 26. Output Overload Recovery, VS = ± 5.0 V TPC 29. Output Overload Recovery, VS = ± 5.0 V 0 –10 0 –20 –20 CROSSTALK (dB) –40 CMRR (dB) –30 –60 SIDE B DRIVEN –80 SIDE A DRIVEN –40 –50 –60 –100 –70 0.1 1 10 FREQUENCY (MHz) 100 –120 0.1 1 10 FREQUENCY (MHz) 100 TPC 27. CMRR vs. Frequency TPC 30. Crosstalk (Output-to-Output) vs. Frequency R EV. B –9– AD8057/AD8058 0.015 0.010 0.005 0.000 –0.005 –0.010 –0.015 DIFFERENTIAL PHASE (Degrees) 0.00 0.00 0.02 0.03 0.05 0.07 0.09 0.10 0.11 0.12 0.13 DIFFERENTIAL GAIN (%) 0.00 –0.00 0.00 0.00 –0.00 –0.00 –0.00 –0.00 –0.00 –0.00 –0.00 VS = 5.0V RL = 150 0.01 0.00 –0.01 –0.02 –0.03 –0.04 –0.05 DIFFERENTIAL PHASE (Degrees) 0.00 0.01 0.03 0.05 0.07 0.09 0.11 0.12 0.12 0.13 0.13 DIFFERENTIAL GAIN (%) 0.00 –0.00 –0.00–0.01 –0.01 –0.01 –0.01 –0.01 –0.02 –0.03 –0.04 VS = +5V RL = 150 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 VS = 5.0V RL = 150 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 VS = +5V RL = 150 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th a. a. 0.015 0.010 0.005 0.000 –0.005 –0.010 –0.015 DIFFERENTIAL GAIN (%) 0.00 0.00 0.00 0.01 0.01 0.00 0.00 0.00 –0.00 –0.01 –0.01 VS = 5.0V RL = 1k 0.01 0.00 –0.01 –0.02 –0.03 –0.04 –0.05 DIFFERENTIAL GAIN (%) 0.00 0.01 –0.00–0.01 –0.01 –0.01 –0.02 –0.02 –0.03 –0.04 –0.05 VS = +5V RL = 1k 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 DIFFERENTIAL PHASE (Degrees) 0.00 0.00 0.00 –0.00 –0.00 –0.00 –0.01 –0.01 –0.01 –0.01 –0.01` VS = 5.0V RL = 1k 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 DIFFERENTIAL PHASE (Degrees) 0.00 –0.00 0.00 0.00 –0.00 –0.00 –0.00 –0.00 –0.01 –0.01 –0.02 VS = +5V RL = 1k 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th b. TPC 31. Differential Gain and Differential Phase One Back Terminated Load (150 Ω) (Video Op Amps Only) b. TPC 33. Differential Gain and Differential Phase, a. RL = 150 Ω, b. RL = 1 kΩ 180 100 135 80 PHASE (Degrees) 90 60 OPEN-LOOP GAIN (dB) 10 45 40 0 20 VNOISE (nV/ Hz) 1 –45 0 –90 0.01 0.1 1 10 FREQUENCY (MHz) 100 –20 1000 0.1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M TPC 32. Open-Loop Gain and Phase vs. Frequency TPC 34. Voltage Noise vs. Frequency –10– R EV. B AD8057/AD8058 100 100 10 10 ZOUT ( ) INOISE (pA/ Hz) 1 1 0.1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M 0.1 0.1 1 10 FREQUENCY (MHz) 100 1000 TPC 35. Current Noise vs. Frequency TPC 36. Output Impedance vs. Frequency APPLICATIONS Driving Capacitive Loads Table I. Recommended Value for Resistors R S, RF, RG vs. Capacitive Load, CL, Which Results in 30% Overshoot When driving a capacitive load, most op amps will exhibit overshoot in their pulse response. Figure 3 shows the relationship between the capacitive load that results in 30% overshoot and the closed-loop gain of an AD8058. It can be seen that, under the Gain = +2 condition, the device is stable with capacitive loads of up to 69 pF. In general, to minimize peaking or to ensure device stability for larger values of capacitive loads, a small series resistor, RS, can be added between the op amp output and the load capacitor, CL, as shown in Figure 4. For the setup shown in Figure 4, the relationship between RS and CL was empirically derived and is shown in Table I. 500 Gain 1 2 3 4 5 10 RF (Ω ) 100 100 100 100 100 100 RG (Ω ) 100 50 33.2 25 11 CL w/RS = 0 Ω (pF) 11 51 104 186 245 870 RF +2.5V 0.1 F 10 F CL w/RS = 2.4 Ω (pF) 13 69 153 270 500 1580 RG 400 AD8058 VIN = 200mV p-p 50k 0.1 F RS FET PROBE VOUT CL 300 CL (pF) 10 F 200 –2.5V RS = 2.4 Figure 4. Capacitive Load Drive Circuit 100 RS = 0 0 1 2 3 CLOSED-LOOP GAIN 4 5 + OVERSHOOT 29.0% 200mV 100mV Figure 3. Capacitive Load Drive vs. Closed-Loop Gain –100mV –200mV 100mV/DIV 50ns/DIV Figure 5. Typical Pulse Response with CL = 65 pF, Gain = +2, and VS = ± 2.5 V R EV. B –11– AD8057/AD8058 Video Filter Differential A-to-D Driver Some composite video signals that are derived from a digital source contain some clock feedthrough that can cause problems with downstream circuitry. This clock feedthrough is usually at 27 MHz, which is a standard clock frequency for both NTSC and PAL video systems. A filter that passes the video band and rejects frequencies at 27 MHz can be used to remove these frequencies from the video signal. Figure 6 shows a circuit that uses an AD8057 to create a single 5 V supply, 3-pole Sallen-Key filter. This circuit uses a single RC pole in front of a standard 2-pole active section. To shift the dc operating point to midsupply, ac coupling is provided by R4, R5, and C4. C2 680pF RF 1k +5V + 10 F As system supply voltages are dropping, many ADCs provide differential analog inputs to increase the dynamic range of the input signal while still operating on a low supply voltage. Differential driving can also reduce second and other even-order distortion products. Analog Devices offers an assortment of 12- and 14-bit high speed converters that have differential inputs and can be run from a single 5 V supply. These include the AD9220, AD9221, AD9223, AD9224, and AD9225 at 12 bits, and the AD9240, AD9241, and AD9243 at 14 bits. Although these devices can operate over a range of common-mode voltages at their analog inputs, they work best when the common-mode voltage at the input is at the midsupply or 2.5 V. Op amp architectures that require upwards of 2 V of headroom at the output have significant problems when trying to drive such ADCs while operating with a 5 V positive supply. The low headroom output design of the AD8057 and AD8058 make them ideal for driving these types of ADCs. The AD8058 can be used to make a dc-coupled, single-endedto-differential driver for one of these ADCs. Figure 8 is a schematic of such a circuit for driving an AD9225, 12-bit, 25 MSPS ADC. 1k +5V + 10 F 50 VINA REF +2.5V + 10 F +5V +5V C4 0.1 F C3 36pF R4 10k R5 10k 2 0.1 F 7 6 R1 200 R2 499 C1 100pF R3 49.9 3 AD8057 4 Figure 6. Low-Pass Filter for Video 0.1 F 0.1 F Figure 7 shows a frequency sweep of this filter. The response is down 3 dB at 5.7 MHz, so it passes the video band with little attenuation. The rejection at 27 MHz is 42 dB, which provides more than a factor of 100 in suppression of the clock components at this frequency. 10 1k VIN 1k 0V 3 8 AD8058 2 1k 1 AD9225 1k 6 1k 50 VINB 0 –10 1k AD8058 5 4 7 LOG MAGNITUDE (dB) –20 0.1 F –30 –40 –50 –60 –70 –80 –90 100k –5V 1k 10 F + Figure 8. Schematic Circuit for Driving AD9225 1M 10M FREQUENCY (Hz) 100M Figure 7. Video Filter Response In this circuit, one of the op amps is configured in the inverting mode, while the other is in the noninverting mode. However, to provide better bandwidth matching, each op amp is configured for a noise gain of +2. The inverting op amp is configured for a gain of –1, while the noninverting op amp is configured for a gain of +2. Each of these produces a noise gain of +2, which is only determined by the inverse of the feedback ratio. The input signal to the noninverting op amp is divided by 2 in order to normalize its level and make it equal to the inverting output. –12– R EV. B AD8057/AD8058 For 0 V input, the outputs of the op amps want to be at 2.5 V, which is the midsupply level of the ADCs. This is accomplished by first taking the 2.5 V reference output of the ADC and dividing it by two by a pair of 1 kΩ resistors. The resulting 1.25 V is applied to each op amp’s positive input. This voltage is then multiplied by the gain of +2 of the op amps to provide a 2.5 V level at each output. The assumption for this circuit is that the input signal is bipolar with respect to ground and the circuit must be dc-coupled. This implies the existence of a negative supply elsewhere in the system. This circuit uses –5 V as the negative supply for the AD8058. If the AD8058 negative supply were tied to ground, there would be a problem at the input of the noninverting op amp. The input common-mode voltage can only go to within 1 V of the negative rail. Since this circuit requires that the positive inputs operate with a 1.25 V bias, there is not enough room to swing this voltage in the negative direction. The inverting stage does not have this problem because its common-mode input voltage remains fixed at 1.25 V. If dc coupling is not required, various ac coupling techniques can be used to eliminate this problem. Layout The AD8057 and AD8058 are high speed op amps and should be used in a board layout that follows standard high speed design rules. All the signal traces should be as short and direct as possible. In particular, the parasitic capacitance on the inverting input of each device should be kept to a minimum to avoid excessive peaking and other undesirable performance. The power supplies should be bypassed very close to the power pins of the package with 0.1 µF in parallel with a larger, approximately 10 µF tantalum capacitor. These capacitors should be connected to a ground plane that is either on an inner layer or fills the area of the board that is not used for other signals. R EV. B –13– AD8057/AD8058 OUTLINE DIMENSIONS 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 8-Lead Standard Small Outline Package [SOIC] (R-8) Dimensions shown in millimeters and (inches) 3.00 BSC 5.00 (0.1968) 4.80 (0.1890) 8 5 4 8 5 3.00 BSC 1 4 4.90 BSC 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 5.80 (0.2284) PIN 1 0.65 BSC 0.15 0.00 0.38 0.22 COPLANARITY 0.10 1.10 MAX 8 0 0.80 0.60 0.40 0.25 (0.0098) 0.10 (0.0040) 1.27 (0.0500) BSC 1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.17 (0.0067) 0.50 (0.0196) 0.25 (0.0099) 45 0.23 0.08 SEATING PLANE COPLANARITY SEATING 0.10 PLANE 0.51 (0.0201) 0.31 (0.0122) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MO-187AA COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 5-Lead Small Outline Transistor Package [SOT-23] (RT-5) Dimensions shown in millimeters 2.90 BSC 5 4 1.60 BSC 1 2 3 2.80 BSC PIN 1 0.95 BSC 1.30 1.15 0.90 1.90 BSC 1.45 MAX 0.22 0.08 10 5 0 0.60 0.45 0.30 0.15 MAX 0.50 0.30 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-178AA –14– R EV. B AD8057/AD8058 Revision History Location 8/03—Data Sheet changed from REV. A to REV. B. Page Renumbered Figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Change to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 R EV. B –15– –16– C01064–0–8/03(B)