AD808-622BRZRL7

a Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD808 frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition. FEATURES Meets CCITT G.958 Requirements for STM-4 Regenerator—Type A Meets Bellcore TR-NWT-000253 Requirements for OC-12 Output Jitter: 2.5 Degrees RMS 622 Mbps Clock Recovery and Data Retiming Accepts NRZ Data, No Preamble Required Phase-Locked Loop Type Clock Recovery— No Crystal Required Quantizer Sensitivity: 4 mV Level Detect Range: 10 mV to 40 mV, Programmable Single Supply Operation: +5 V or –5.2 V Low Power: 400 mW 10 KH ECL/PECL Compatible Output Package: 16-Lead Narrow 150 mil SOIC The AD808 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD808. The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.5 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance. PRODUCT DESCRIPTION The AD808 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 622 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-12 or SDH STM-4 fiber optic receiver. The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater. The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output. Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency. The AD808 consumes 400 mW and operates from a single power supply at either +5 V or –5.2 V. The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee FUNCTIONAL BLOCK DIAGRAM CF1 PIN CF2 QUANTIZER COMPENSATING ZERO FDET NIN S LOOP FILTER PHASE-LOCKED LOOP VCO THRADJ SIGNAL LEVEL DETECTOR CLKOUTP CLKOUTN FDET LEVEL DETECT COMPARATOR/ BUFFER RETIMING DEVICE DATAOUTP DATAOUTN AD808 SDOUT REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD808–SPECIFICATIONS (T = T A Parameter QUANTIZER–DC CHARACTERISTICS Input Voltage Range Input Sensitivity, VSENSE Input Overdrive, VOD Input Offset Voltage Input Current Input RMS Noise Input Peak-to-Peak Noise QUANTIZER–AC CHARACTERISTICS Upper –3 dB Bandwidth Input Resistance Input Capacitance Pulsewidth Distortion LEVEL DETECT Level Detect Range Response Time Hysteresis (Electrical) SDOUT Output Logic High SDOUT Output Logic Low PHASE-LOCKED LOOP NOMINAL CENTER FREQUENCY CAPTURE RANGE TRACKING RANGE STATIC PHASE ERROR (See Figure 7) SETUP TIME (tSU) HOLD TIME (t H) PHASE DRIFT JITTER JITTER TOLERANCE JITTER TRANSFER Peaking (Figure 14) Bandwidth Acquisition Time C D = 0.1 µF C D = 0.47 µF POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT PECL OUTPUT VOLTAGE LEVELS Output Logic High, V OH Output Logic Low, V OL SYMMETRY (Duty Cycle) Recovered Clock Output, Pin 5 OUTPUT RISE / FALL TIMES Rise Time (t R) Fall Time (t F) CLOCK SKEW (tRCS) MIN to TMAX , VS = VMIN to VMAX, CD = 0.47 mF, unless otherwise noted) Condition Min @ PIN or N IN PIN–NIN, Figure 1, BER = ≤ 1 × 10 –10 Figure 1, BER = ≤ 1 × 10 –10 2.5 10 5 Max Units VS 4.0 2.0 1.0 10 100 1.5 V mV mV mV µA µV mV 600 800 10 2 50 MHz kΩ pF ps 6.5 13 28.5 0.1 10 18 40 BER = ≤ 1 × 10–10 BER = ≤ 1 × 10–10 RTHRESH = 22.1 kΩ RTHRESH = 6.98 kΩ RTHRESH = 0 Ω DC Coupled RTHRESH = 22.1 kΩ (See Figure 8) RTHRESH = 6.98 kΩ RTHRESH = 0 Ω Load = +3.2 mA Load = –3.2 mA 3.0 3.0 4.0 Typ 5 5.1 7.0 4.7 0.2 13.5 23 45.5 1.5 9.0 9.0 10.0 0.4 622.08 620 620 27 –1 PRN Sequence Figure 2 Figure 2 240 Bits, No Transitions 27 –1 PRN Sequence 223 –1 PRN Sequence f = 30 Hz f = 300 Hz f = 25 kHz f = 250 kHz f = 5 MHz 22 550 700 24 1.7 0.28 0.18 CD = 0.47 µF 2.5 2.5 3000 300 3.7 0.56 0.45 0.04 333 624 624 81 900 1050 50 3.6 3.6 450 mV mV mV µs dB dB dB V V MHz MHz MHz Degrees ps ps Degrees Degrees rms Degrees rms Unit Intervals Unit Intervals Unit Intervals Unit Intervals Unit Intervals dB kHz 2 × 106 8 × 106 3 × 106 Bit Periods 12 × 106 Bit Periods 5.5 Volts 55 80 100 mA TA = +25°C Referenced to VCC ρ = 1/2, TA = +25°C, VCC = 5 V, VEE = GND –1.2 –2.2 –1.0 –2.0 –0.7 –1.7 Volts Volts 55 % 20%–80% 80%–20% Positive Number Indicates Clock Leading Data 174 136 350 315 500 500 ps ps –100 130 250 ps 223 –1 PRN Sequence, TA = +25°C VCC = 5 V, VEE = GND VMIN to V MAX VCC = 5.0 V, VEE = GND, TA = +25°C 4.5 45 Specifications subject to change without notice. –2– REV. 0 AD808 PIN FUNCTION DESCRIPTIONS ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . . VCC + 0.6 V Maximum Junction Temperature . . . . . . . . . . . . . . . . +165°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . 1500 V NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics: 16-Lead Narrow Body SOIC Package: θ JA = 110°C/Watt. OUTPUT NOISE 1 0 INPUT (V) OFFSET OVERDRIVE SENSITIVITY Figure 1. Input Sensitivity, Input Overdrive Pin No. Mnemonic Description 1 DATAOUTN Differential Retimed Data Output 2 DATAOUTP Differential Retimed Data Output 3 VCC2 Digital VCC for ECL Outputs 4 CLKOUTN Differential Recovered Clock Output 5 CLKOUTP Differential Recovered Clock Output 6 VCC1 Digital VCC for Internal Logic 7 CF1 Loop Damping Capacitor 8 CF2 Loop Damping Capacitor 9 AV EE Analog VEE 10 THRADJ Level Detect Threshold Adjust 11 AVCC1 Analog VCC for PLL 12 NIN Quantizer Differential Input 13 PIN Quantizer Differential Input 14 AVCC2 Analog VCC for Quantizer 15 SDOUT Signal Detect Output 16 VEE Digital VEE for Internal Logic PIN CONFIGURATION DATAOUT 50% (PIN 2) HOLD TIME tH CLKOUT 50% (PIN 5) SETUP TIME DATAOUTN 1 16 VEE DATAOUTP 2 15 SDOUT 14 AVCC2 VCC2 3 tSU CLKOUTN 4 AD808 PIN TOP VIEW CLKOUTP 5 12 NIN (Not to Scale) VCC1 6 11 AVCC1 tRCS RECOVERED CLOCK SKEW Figure 2. Setup and Hold Time 13 CF1 7 10 THRADJ CF2 8 9 AVEE ORDERING GUIDE Model Temperature Range Package Description Package Option AD808-622BR AD808-622BRRL7 AD808-622BRRL –40°C to +85°C –40°C to +85°C –40°C to +85°C 16-Pin Narrowbody SOIC 750 Pieces, 7" Reel 2500 Pieces, 13" Reel R-16A R-16A R-16A CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD808 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE AD808 Tracking Range DEFINITION OF TERMS Maximum, Minimum and Typical Specifications This is the range of input data rates over which the AD808 will remain in lock. Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for that parameter. If a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribution. This procedure is intended to tolerate production variations: if the mean shifts by 1.5 standard deviations, the remaining 4.5 standard deviations still provide a failure rate of only 3.4 parts per million. For all tested parameters, the test limits are guardbanded to account for tester variation to thus guarantee that no device is shipped outside of data sheet specifications. Capture Range This is the range of input data rates over which the AD808 will acquire lock. Static Phase Error This is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. Gate delays between the signals that define static phase error, and IC input and output signals prohibit direct measurement of static phase error. Data Transition Density, ρ Input Sensitivity and Input Overdrive Sensitivity and Overdrive specifications for the Quantizer involve offset voltage, gain and noise. The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure 1. This is a measure of the number of data transitions, from “0” to “1” and from “1” to “0,” over many clock periods. ρ is the ratio (0 ≤ ρ ≤ 1) of data transitions to bit periods. For sufficiently large positive input voltage the output is always Logic 1 and similarly, for negative inputs, the output is always Logic 0. However, the transitions between output Logic Levels 1 and 0 are not at precisely defined input voltage levels, but occur over a range of input voltages. Within this Zone of Confusion, the output may be either 1 or 0, or it may even fail to attain a valid logic state. The width of this zone is determined by the input voltage noise of the quantizer (1.5 mV at the 1 × 10–10 confidence level). The center of the Zone of Confusion is the quantizer input offset voltage (1 mV typ). Input Overdrive is the magnitude of signal required to guarantee correct logic level with 1 × 10–10 confidence level. This is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms or Unit Intervals (UI). Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. Jitter on the recovered clock causes jitter on the retimed data. Jitter Output Jitter This is the jitter on the retimed data, in degrees rms, due to a specific pattern or some pseudorandom input data sequence (PRN Sequence). Jitter Tolerance Jitter Tolerance is a measure of the AD808’s ability to track a jittery input data signal. Jitter on the input data is best thought of as phase modulation, and is usually specified in unit intervals. With a single-ended PIN-TIA (Figure 3), ac coupling is used and the inputs to the Quantizer are dc biased at some commonmode potential. Observing the Quantizer input with an oscilloscope probe at the point indicated shows a binary signal with average value equal to the common-mode potential and instantaneous values both above and below the average value. It is convenient to measure the peak-to-peak amplitude of this signal and call the minimum required value the Quantizer Sensitivity. Referring to Figure 1, since both positive and negative offsets need to be accommodated, the Sensitivity is twice the Overdrive. The AD808 Quantizer has 4 mV Sensitivity typical. The PLL must provide a clock signal that tracks the phase modulation in order to accurately retime jittered data. In order for the VCO output to have a phase modulation that tracks the input jitter, some modulation signal must be generated at the output of the phase detector. The modulation output from the phase detector can only be produced by a phase error between its data input and its clock input. Hence, the PLL can never perfectly track jittered data. However, the magnitude of the phase error depends on the gain around the loop. At low frequencies, the integrator of the AD808 PLL provides very high gain, and thus very large jitter can be tracked with small phase errors between input data and recovered clock. At frequencies closer to the loop bandwidth, the gain of the integrator is much smaller, and thus less input jitter can be tolerated. The AD808 output will have a bit error rate less than 1 × 10–10 when in lock and retiming input data that has the CCITT G.958 specified jitter applied to it. With a differential TIA (Figure 3), Sensitivity seems to improve from observing the Quantizer input with an oscilloscope probe. This is an illusion caused by the use of a single-ended probe. A 2 mV peak-to-peak signal appears to drive the AD808 Quantizer. However, the single-ended probe measures only half the signal. The true Quantizer input signal is twice this value since the other Quantizer input is a complementary signal to the signal being observed. Jitter Transfer (Refer to Figure 14) Response Time The AD808 exhibits a low-pass filter response to jitter applied to its input data. Response time is the delay between removal of the input signal and indication of Loss of Signal (LOS) at SDOUT. The response time of the AD808 (1.5 µs maximum) is much faster than the SONET/SDH requirement (3 µs ≤ response time ≤ 100 µs). In practice, the time constant of the ac coupling at the Quantizer input determines the LOS response time. Bandwidth This describes the frequency at which the AD808 attenuates sinusoidal input jitter by 3 dB. Peaking This describes the maximum jitter gain of the AD808 in dB. Nominal Center Frequency This is the frequency at which the VCO will oscillate with the loop damping capacitor, CD, shorted. –4– REV. 0 AD808 Damping Factor, ζ is useful to bypass the common mode of the preamp to the positive supply as well, if this is an option. Note, it is not necessary to use capacitive coupling of the input signal with the AD808. Figure 14 shows the input common-mode voltage can be externally set. Damping factor, ζ describes the compensation of the second order PLL. A larger value of ζ corresponds to more damping and less peaking in the jitter transfer function. Acquisition Time This is the transient time, measured in bit periods, required for the AD808 to lock onto input data from its free-running state. AVCC 500V Symmetry—Recovered Clock Duty Cycle 500V PIN Symmetry is calculated as (100 × on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its “0” level and its “1” level. 5kV OUT 5kV NIN AVEE 4mVp-p VCM SCOPE PROBE a. Quantizer Differential Input Stage AD808 QUANTIZER INPUT 1.2V +VBE BINARY OUTPUT 6kV THRADJ 80kV AVEE VCM b. Threshold Adjust a. Single-Ended Input Application VCC1 VCM 2mVp-p IOH SCOPE PROBE 30V SDOUT AD808 QUANTIZER 30V +INPUT IOL BINARY OUTPUT –INPUT VEE c. Signal Detect Output (SDOUT) VCM VCC2 b. Differential Input Application 140V Figure 3. (a–b) Single-Ended and Differential Input Applications DIFFERENTIAL OUTPUT The AD808 has internal circuits to set the common-mode voltage at the quantizer inputs PIN (Pin 13) and NIN (Pin 12) as shown in Figure 4a. This allows very simple capacitive coupling of the signal from the preamp in the AD808 as shown in Figure 3. The internal common-mode potential is a diode drop (approximately 0.8 V) below the positive supply as shown in Figure 4a. Since the common mode is referred to the positive supply, it REV. 0 140V 7.8mA VEE d. PLL Differential Output Stage—DATAOUT(N), CLKOUT(N) Figure 4. (a–d) Simplified Schematics –5– 90000 180 80000 160 70000 140 60000 120 SAMPLES RTHRESH – V AD808–Typical Performance Characteristics 50000 40000 100 80 30000 60 20000 40 10000 20 0 0 4 6 8 10 12 SIGNAL DETECT VOLTAGE – mV 14 2.00 16 8.0 200 7.5 180 4.00 4.67 5.33 LOS HYSTERESIS – dB 6.00 6.67 TEST CONDITIONS WORST CASE: –408C 160 RTH = 0 140 6.5 SAMPLES ELECTRICAL HYSTERESIS – dB 3.33 Figure 8. Histogram LOS Hysteresis 22.1 kΩ RTHRESH (All Temperature All Supply) Figure 5. Signal Detect Voltage vs. RTHRESH 7.0 2.67 RTH = 5k 6.0 5.5 120 100 80 60 5.0 RTH = 7k 40 4.5 20 4.0 –40 –20 0 20 40 60 80 0 95 1.44 1.80 TEMPERATURE – 8C Figure 6. Signal Detect Hysteresis vs. Temperature 2.16 2.52 2.88 3.24 JITTER – Degrees 3.60 3.96 Figure 9. Output Jitter Histogram 12 100 258C 10 JITTER TOLERANCE – UI 858C SAMPLES 8 6 4 10 –408C SONET MASK 1 2 0 0 8 17 25 33 42 STATIC PHASE – Degrees 50 0.1 1 58 Figure 7. Histogram of Static Phase –40 @ 4.4 V 10 100 1k 10k 100k JITTER FREQUENCY – Hz 1M 10M Figure 10. Jitter Tolerance vs. Frequency –6– REV. 0 AD808 THEORY OF OPERATION Quantizer DATA INPUT The quantizer (comparator) has three gain stages, providing a net gain of 350. The quantizer takes full advantage of the Extra Fast Complementary Bipolar (XFCB) process. The input stage uses a folded cascode architecture to virtually eliminate pulse width distortion, and to handle input signals with commonmode voltage as high as the positive supply. The input offset voltage is factory trimmed and is typically less than 1 mV. XFCB’s dielectric isolation allows the different blocks within this mixedsignal IC to be isolated from each other, hence the 4 mV Sensitivity is achieved. Traditionally, high speed comparators are plagued by crosstalk between outputs and inputs, often resulting in oscillations when the input signal approaches 10 mV. The AD808 quantizer toggles at 2 mV (4.0 mV sensitivity) at the input without making bit errors. When the input signal is lowered below 2 mV, circuit performance is dominated by input noise, and not crosstalk. PIN POSITIVE PEAK DETECTOR LEVEL SHIFT DOWN NEGATIVE PEAK DETECTOR LEVEL SHIFT UP 1 S RECOVERED CLOCK OUTPUT RETIMING DEVICE RETIMED DATA OUTPUT Figure 12. PLL Block Diagram The frequency detector delivers pulses of current to the charge pump to either raise or lower the frequency of the VCO. During the frequency acquisition process the frequency detector output is a series of pulses of width equal to the period of the VCO. These pulses occur on the cycle slips between the data frequency and the VCO frequency. With a maximum density data pattern (1010 . . . ), every cycle slip will produce a pulse at the frequency detector output. However, with random data, not every cycle slip produces a pulse. The density of pulses at the frequency detector output increases with the density of data transitions. The probability that a cycle slip will produce a pulse increases as the frequency error approaches zero. After the frequency error has been reduced to zero, the frequency detector output will have no further pulses. At this point the PLL begins the process of phase acquisition, with a settling time of roughly 2000 bit periods. Jitter caused by variations of density of data transitions (pattern jitter) is virtually eliminated by use of a new phase detector (patented). Briefly, the measurement of zero phase error does not cause the VCO phase to increase to above the average run rate set by the data frequency. The jitter created by a 27–1 pseudorandom code is 1/2 degree, and this is small compared to random jitter. The jitter bandwidth for the PLL is 0.06% of the center frequency. This figure is chosen so that sinusoidal input jitter at 350 Hz will be attenuated by 3 dB. The damping ratio of the PLL is user programmable with a single external capacitor. At 622 MHz, a damping ratio of 5 is obtained with a 0.47 µF capacitor. More generally, the damping ratio scales as (fDATA × CD)1/2. IHYS A lower damping ratio allows a faster frequency acquisition; generally the acquisition time scales directly with the capacitor value. However, at damping ratios approaching one, the acquisition time no longer scales directly with capacitor value. The acquisition time has two components: frequency acquisition and phase acquisition. The frequency acquisition always scales with capacitance, but the phase acquisition is set by the loop bandwidth of the PLL and is independent of the damping ratio. In practice the acquisition time is dominated by the frequency acquisition. The fractional loop bandwidth of 0.06% should give an acquisition time of 2000 bit periods. However, the actual acquisition time is several million bit periods and is comprised mostly of the time needed to slew the voltage on the damping capacitor to final value. SDOUT Figure 11. Signal Level Detect Circuit Block Diagram Phase-Locked Loop The phase-locked loop recovers clock and retimes data from NRZ data. The architecture uses a frequency detector to aid initial frequency acquisition; refer to Figure 12 for a block diagram. Note the frequency detector is always in the circuit. When the PLL is locked, the frequency error is zero and the frequency detector has no further effect. Since the frequency detector is always in the circuit, no control functions are needed to initiate acquisition or change mode after acquisition. REV. 0 S VCO The input to the signal detect circuit is taken from the first stage of the quantizer. The input signal is first processed through a gain stage. The output from the gain stage is fed to both a positive and a negative peak detector. The threshold value is subtracted from the positive peak signal and added to the negative peak signal. The positive and negative peak signals are then compared. If the positive peak, POS, is more positive than the negative peak, NEG, the signal amplitude is greater than the threshold, and the output, SDOUT, will indicate the presence of signal by remaining low. When POS becomes more negative than NEG, the signal amplitude has fallen below the threshold, and SDOUT will indicate a loss of signal (LOS) by going high. The circuit provides hysteresis by adjusting the threshold level higher by a factor of two when the low signal level is detected. This means that the input data amplitude needs to reach twice the set LOS threshold before SDOUT will signal that the data is again valid. This corresponds to a 3 dB optical hysteresis. NIN S+1 FDET Signal Detect THRESHOLD AD808 BIAS COMPARATOR STAGES + & CLOCK RECOVERY PLL + ITHR FDET –7– AD808 Center Frequency Clamp (Figure 13) An N-channel FET circuit can be used to bring the AD808 VCO center frequency to within ± 10% of 622 MHz when SDOUT indicates a Loss of Signal (LOS). This effectively reduces the frequency acquisition time by reducing the frequency error between the VCO frequency and the input data frequency at clamp release. The N-FET can have “on” resistance as high as 1 kΩ and still attain effective clamping. However, the chosen N-FET should have greater than 10 MΩ “off” resistance and less than 100 nA leakage current (source and drain) so as not to alter normal PLL performance. 1 DATAOUTN VEE 16 2 DATAOUTP SDOUT 15 4 CLKOUTN PIN 13 5 CLKOUTP NIN 12 6 VCC1 N_FET CD 0.11 0.07 0.04 DIV START 36.00m STOP 30Hz ST: 3.07 min RANGE: R= 500.000Hz 100 000.000Hz 0, T= 0dBm Figure14. Jitter Transfer vs. CD AVCC1 11 7 CF1 8 CF2 PEAK 0.047 0.10 0.47 DIV 20.00m RBW: AVCC2 14 3 VCC2 CD THRADJ 10 AD808 AVEE 9 Figure 13. Center Frequency Clamp Schematic C1 0.1mF R1 R2 100V 100V J1 C3 0.1mF DATAOUTN R9 154V R5 100V 1 DATAOUTN R6 100V J3 C5 0.1mF CLKOUTN R7 100V C7 CLKOUTP J4 C6 0.1mF R4 R3 100V 100V C2 0.1mF C8 TP1 R11 154V R12 CD 154V TP2 16 AVCC2 14 4 CLKOUTN PIN 13 5 CLKOUTP NIN 12 6 V CC1 7 CF1 8 CF2 SDOUT SDOUT 15 3 VCC2 R8 100V J5 C12 0.1mF VEE 2 DATAOUTP DATAOUTP J2 C4 0.1mF TP7 TP8 50V STRIP LINE EQUAL LENGTH R10 154V AVCC1 11 R13 301V C9 AVEE 9 NIN C14 0.1mF J7 C10 TP5 VECTOR PINS SPACED FOR RN55C TYPE RESISTOR; COMPONENT SHOWN FOR REFERENCE ONLY TP6 NOTE: RTHRESH NOTE: INTERCONNECT RUN UNDER DUT C11 TP3 10mF TP4 +5V GND R16 3.65kV R15 49.9V C13 0.1mF J6 PIN THRADJ 10 AD808 R14 49.9V C7–C10 ARE 0.1µF BYPASS CAPACITORS RIGHT ANGLE SMA CONNECTOR OUTER SHELL TO GND PLANE VECTOR PINS SPACED THROUGH-HOLE CAPACITOR ON VECTOR CUPS; COMPONENT SHOWN FOR REFERENCE ONLY ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT TPxo TEST POINTS ARE VECTORBOARD K24A/M PINS Figure 15. Evaluation Board Schematic –8– REV. 0 AD808 Loop Damping Capacitor, C D USING THE AD808 A ceramic capacitor may be used for the loop damping capacitor. Using a 0.47 µF, ± 20% capacitor provides < 0.1 dB jitter peaking. Acquisition Time This is the transient time, measured in bit periods, that required for the AD808 to lock onto the input data from its free running state. AD808 Output Squelch Circuit A simple P-channel FET circuit can be used in series with the Output Signal ECL Supply (VCC2, Pin 3) to squelch clock and data outputs when SDOUT indicates a loss of signal (Figure 16). The VCC2 supply pin draws roughly 72 mA (14 mA for each of 4 ECL loads, plus 16 mA for all 4 ECL output stages). This means that selection of a FET with ON RESISTANCE of 0.5 Ω will affect the common mode of the ECL outputs by only 36 mV. Ground Planes The use of one ground plane for connections to both analog and digital grounds is recommended. Power Supply Connections The use of a 10 µF capacitor between VCC and ground is recommended. The +5 V power supply connection to VCC2 should be carefully isolated. The VCC2 pin is used inside the AD808 to provide the CLKOUT and DATAOUT signals. Use a 0.1 µF decoupling capacitor between IC power supply input and ground. This decoupling capacitor should be positioned as closed to the IC as possible. Refer to the schematic in Figure 15 for advised connections. 5V Transmission Lines Use 50 Ω transmission line for PIN, NIN, CLKOUT, and DATAOUT signals. 1 DATAOUTN VEE 16 2 DATAOUTP SDOUT 15 AVCC2 14 3 VCC2 BYPASS CAP Terminations Use metal, thick-film, 1% termination resistors for PIN, NIN, CLKOUT, and DATAOUT signals. These termination resistors must be positioned as close to the IC as possible. 4 CLKOUTN PIN 13 5 CLKOUTP NIN 12 6 VCC1 7 CF1 8 CF2 Use individual connections, not daisy chained, for connections from the +5 V to load resistors for PIN, NIN, CLKOUT, and DATAOUT signals. REV. 0 TO VCC1, AVCC, AVCC2 P_FET AVCC1 11 THRADJ 10 AD808 AVEE 9 Figure 16. Squelch Circuit Schematic –9– AD808 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Small Outline IC Package (R-16A) 0.3937 (10.00) 0.3859 (9.80) 0.1574 (4.00) 0.1497 (3.80) 16 9 1 8 PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0500 SEATING (1.27) PLANE BSC 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) –10– 0.0196 (0.50) x 458 0.0099 (0.25) 88 08 0.0500 (1.27) 0.0160 (0.41) REV. 0 –11– –12– PRINTED IN U.S.A. C3262–8–1/98