AD8124ACPZ

Triple Differential Receiver with 200 Meter Adjustable Cable Equalization AD8124 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VPEAK VPOLE VOFFSET VGAIN AD8124 –INR OUTR +INR –ING OUTG +ING –INB OUTB +INB –INCMP1 OUTCMP1 +INCMP1 –INCMP2 OUTCMP2 +INCMP2 09601-001 Compensates cables to 200 meters for wideband video All resolutions through UXGA Fast rise and fall times 8 ns with 2 V step at 200 meters of UTP cable 37 dB peak gain at 100 MHz Two frequency response gain adjustment pins High frequency peaking adjustment (VPEAK) Broadband flat gain adjustment (VGAIN) Pole location adjustment pin (VPOLE) Compensates for variations between cables Can be optimized for either UTP or coaxial cable DC output offset adjust (VOFFSET) Low output offset voltage: 24 mV Compensates both RGB and YPbPr Two on-chip comparators with hysteresis Can be used for common-mode sync extraction Available in 40-lead, 6 mm × 6 mm LFCSP Figure 1. APPLICATIONS Keyboard-video-mouse (KVM) Digital signage RGB video over UTP cables Professional video projection and distribution HD video Security video GENERAL DESCRIPTION The AD8124 is a triple, high speed, differential receiver and equalizer that compensates for the transmission losses of UTP and coaxial cables up to 200 meters in length. Various gain stages are summed together to best approximate the inverse frequency response of the cable. Logic circuitry inside the AD8124 controls the gain functions of the individual stages so that the lowest noise can be achieved at short-to-medium cable lengths. This technique optimizes its performance for low noise, short-tomedium range applications, while at the same time provides the high gain bandwidth required for longer cable equalization (up to 200 meters). Each channel features a high impedance differential input that is ideal for interfacing directly with the cable. The AD8124 has three control pins for optimal cable compensation, as well as an output offset adjust pin. Two voltage-controlled pins are used to compensate for different cable lengths; the VPEAK pin controls the amount of high frequency peaking and the VGAIN pin adjusts the broadband flat gain, which compensates for the low frequency flat cable loss. For added flexibility, an optional pole adjustment pin, VPOLE, allows movement of the pole locations, allowing for the compensation of different gauges and types of cable as well as variations between different cables and/or equalizers. The VOFFSET pin allows the dc voltage at the output to be adjusted, adding flexibility for dc-coupled systems. The AD8124 is available in a 6 mm × 6 mm, 40-lead LFCSP and is rated to operate over the extended temperature range of −40°C to +85°C. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8124 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 11 Applications ....................................................................................... 1 Basic Operation .......................................................................... 11 Functional Block Diagram .............................................................. 1 Comparators ............................................................................... 11 General Description ......................................................................... 1 Sync Pulse Extraction Using Comparators ............................. 12 Revision History ............................................................................... 2 Using the VPEAK, VPOLE, VGAIN, and VOFFSET Inputs ................... 12 Specifications..................................................................................... 3 Using the AD8124 with Coaxial Cable.................................... 13 Absolute Maximum Ratings ............................................................ 5 Driving 75 Ω Video Cable with the AD8124.......................... 13 Thermal Resistance ...................................................................... 5 Driving a Capacitive Load......................................................... 13 Maximum Power Dissipation ..................................................... 5 Power Supply Filtering ............................................................... 13 ESD Caution .................................................................................. 5 Layout and Power Supply Decoupling Considerations ......... 14 Pin Configuration and Function Description .............................. 6 Power-Down ............................................................................... 14 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 15 Theory of Operation ...................................................................... 10 Ordering Guide .......................................................................... 15 Input Common-Mode Voltage Range Considerations ......... 10 REVISION HISTORY 12/15—Rev. 0 to Rev. A Changes to Figure 3 .......................................................................... 6 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 15 1/11—Revision 0: Initial Version Rev. A | Page 2 of 15 Data Sheet AD8124 SPECIFICATIONS TA = 25°C, VS = ±5 V, RL = 150 Ω, Belden Cable (BL-7987R), VOFFSET = 0 V, VPEAK, VGAIN, and VPOLE are set to recommended settings shown in Figure 16, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE 10% to 90% Rise/Fall Time Settling Time to 2% –3 dB Large Signal Bandwidth Integrated Output Voltage Noise INPUT DC PERFORMANCE Input Voltage Range Maximum Differential Voltage Swing Voltage Gain Common-Mode Rejection Ratio (CMRR) Input Resistance Input Capacitance Input Bias Current VOFFSET Pin Current VGAIN Pin Current VPEAK Pin Current VPOLE Pin Current ADJUSTMENT PINS VPEAK Input Voltage Range VPOLE Input Voltage Range VGAIN Input Voltage Range VOFFSET to OUT Gain Maximum Flat Gain OUTPUT CHARACTERISTICS Output Voltage Swing Output Offset Voltage Output Offset Voltage Drift POWER SUPPLY Operating Voltage Range Positive Quiescent Supply Current Negative Quiescent Supply Current Supply Current Drift, ICC/IEE Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Power Down, VIH (Minimum) Power Down, VIL (Maximum) Positive Supply Current, Powered Down Negative Supply Current, Powered Down Test Conditions/Comments Min Typ Max Unit VOUT = 2 V step, 200 meters Cat-5 VOUT = 2 V step, 200 meters Cat-5 VOUT = 2 V p-p,