AD8145

High Speed, Triple Differential Receiver with Comparators AD8145 FEATURES High speed: 500 MHz, 2000 V/μs @ G = 1, VO = 2 V p-p 0.1 dB flatness out to 75 MHz High CMRR: 69 dB @ 10 MHz High differential input impedance: 1 MΩ Wide input common-mode range: ± 3.8 V (±5 V supplies) On-chip gain-setting resistors Can be configured for gain of 1 or 2 Fast settling: 15 ns to 0.1% @ 2 V p-p Low input referred noise: 13nV/√Hz Disable feature Small packaging: 32-lead, 5 mm × 5 mm LFCSP FUNCTIONAL BLOCK DIAGRAM GAIN_B DIS/PD REF_B IN+_B IN–_B GND GND 25 24 32 31 30 29 28 27 GND REF_G GAIN_G IN+_G IN–_G REF_R GAIN_R GND 1 R + – R + – – C – VS– 26 GND OUT_B OUT_G OUT_R VS+ COMPB_IN+ COMPB_IN– GND + R + 2 C R 23 3 22 4 21 5 AD8145 C R + – R – 11 12 13 14 15 16 20 APPLICATIONS RGB video receivers YPbPr video receivers KVM (keyboard, video, mouse) UTP (unshielded twisted pair) receivers 6 19 B A 18 7 8 9 + 17 10 GND IN+_R COMPA_IN+ COMPA_IN– IN–_R COMPA_OUT COMPB_OUT GND Figure 1. GENERAL DESCRIPTION The AD8145 is a triple, low cost, differential-to-single-ended receiver specifically designed for receiving red-green-blue (RGB) video signals over twisted pair cable or differential printed circuit board traces. It can also be used to receive any type of analog signal or high speed data transmission. Two auxiliary comparators with hysteresis are provided, which can be used to decode video sync signals that are encoded on the received common-mode voltages, to receive digital signals, or as general-purpose comparators. The AD8145 can be used in conjunction with the AD8133 or AD8134 triple differential drivers to provide a complete low cost solution for RGB over Category 5 UTP cable applications, including KVM. The excellent common-mode rejection (69 dB @ 10 MHz) of the AD8145 allows for the use of low cost, unshielded twisted pair cables in noisy environments. The AD8145 can be configured for a differential-to-singleended gain of 1 or 2 by connecting the GAIN pin of each channel to its respective output (G = 1) or connecting it to a reference voltage (G = 2), which is normally grounded. A REF input is provided on each channel that allows designers to level shift the output signals. The AD8145 is available in a 5 mm × 5 mm, 32-lead LFCSP and is rated to work over the extended industrial temperature range of −40°C to +105°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 06307-001 AD8145 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Description .............................. 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 14 Applications..................................................................................... 15 Overview ..................................................................................... 15 Basic Closed-Loop Gain Configurations ................................ 15 Terminating the Input................................................................ 16 Input Clamping........................................................................... 17 Printed Circuit Board Layout Considerations ....................... 18 Driving a Capacitive Load......................................................... 19 Power-Down ............................................................................... 19 Comparators ............................................................................... 20 Sync Pulse Extraction Using Comparators............................. 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8145 SPECIFICATIONS TA = 25°C, VS = ±5 V, REF = 0 V, RL = 150 Ω, CL = 2 pF, G = 1, TMIN to TMAX = −40°C to +105°C, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Conditions VOUT = 0.2 V p-p VOUT = 2 V p-p VOUT = 0.2 V p-p, G = 2 VOUT = 2 V p-p, G = 2 VOUT = 2 V p-p VOUT = 2 V p-p, G = 2 VOUT = 2 V p-p VOUT = 2 V p-p, G = 2 VOUT = 2 V p-p, 0.1% Min Typ 530 500 200 200 75 100 2100 2100 15 20 −67 −88 −62 13 0.25 0.1 81 90 69 41 ±3.5 ±2.5 1 1.3 1 2 1.985 7.0 −18 −3.4 25 −65 2.020 1.0 −0.9 300 3.55 50 195/−230 Max Unit MHz MHz MHz MHz MHz MHz V/μs V/μs ns ns dBc dBc dB nV/√Hz % Degrees dB dB dB V V MΩ MΩ pF pF V/V mV μV/°C μA nA/°C nA V mA mA Bandwidth for 0.1 dB Flatness Slew Rate Settling Time Output Overdrive Recovery NOISE/DISTORTION Second Harmonic Third Harmonic Crosstalk Input Voltage Noise (RTI) Differential Gain Error Differential Phase Error INPUT CHARACTERISTICS Common-Mode Rejection VOUT = 2 V p-p, 1 MHz VOUT = 2 V p-p, 1 MHz VOUT = 2 V p-p, 10 MHz f ≥ 10 kHz NTSC, 200 IRE, RL ≥ 150 Ω NTSC, 200 IRE, RL ≥ 150 Ω DC, VCM = −3.5 V to +3.5 V VCM = 1 V p-p, f = 10 MHz VCM = 1 V p-p, f = 100 MHz V+IN − V−IN = 0 V Differential Common mode Differential Common mode DC, G = 2 G=2 TMIN to TMAX TMIN to TMAX (+IN, −IN) −400 −4.04 Short to GND, source/sink 1.955 −17.5 6 Common-Mode Voltage Range Differential Operating Range Resistance Capacitance DC PERFORMANCE Closed-Loop Gain Output Offset Voltage Input Bias Current (+IN, −IN) Input Bias Current Drift Input Offset Current OUTPUT PERFORMANCE Voltage Swing Output Current Short-Circuit Current Rev. 0 | Page 3 of 24 AD8145 Parameter COMPARATOR PERFORMANCE VOH VOL Input Offset Voltage Hysteresis Width Input Bias Current Propagation Delay, tPLH Propagation Delay, tPHL Rise Time Fall Time POWER-DOWN PERFORMANCE Power-Down VIH Power-Down VIL Power-Down IIH Power-Down IIL Power-Down Assert Time POWER SUPPLY Operating Range Quiescent Current, Positive Supply Quiescent Current, Negative Supply PSRR, Positive Supply PSRR, Negative Supply Disabled DC DC Conditions R L = 1 kΩ R L = 1 kΩ Min 3.205 Typ 3.310 0.390 ±2.5 18 1.5 6 6 6 2 VS+ − 1.65 VS+ − 2.65 0.5 −250 1 4.5 Disabled −52 −13.9 48.5 16 −43.5 −11 −79 −68 11 57.5 19.5 Max Unit V V mV mV μA ns ns ns ns V V μA μA μs V mA mA mA mA dB dB 0.420 10% to 90% 10% to 90% −70 −57 Rev. 0 | Page 4 of 24 AD8145 TA = 25°C, VS = ±2.5 V, REF = 0 V, RL = 1 kΩ, CL = 2 pF, G = 1, TMIN to TMAX = −40°C to +105°C, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Conditions VOUT = 0.2 V p-p VOUT = 2 V p-p VOUT = 0.2 V p-p, G = 2, RL = 150 Ω VOUT = 2 V p-p, G = 2, RL = 150 Ω VOUT = 2 V p-p VOUT = 2 V p-p, G = 2, RL = 150 Ω VOUT = 2 V p-p VOUT = 2 V p-p, G = 2, RL = 150 Ω VOUT = 2 V p-p, 0.1% Min Typ 450 425 180 180 53 100 2000 2000 16 10 −71 −76 −62 13 78 86 72 43 ±1.25 ±1.6 1 1.3 1 2 1.985 −4.5 −18 −3.5 25 −60 2.016 2 −0.9 300 1.3 25 100/−100 VS+ − 1.5 VS+ − 2.5 0.25 50 1 Max Unit MHz MHz MHz MHz MHz MHz V/μs V/μs ns ns dBc dBc dB nV/√Hz dB dB dB V V MΩ MΩ pF pF V/V mV μV/°C μA nA/°C nA V mA mA V V μA μA μs Bandwidth for 0.1 dB Flatness Slew Rate Settling Time Output Overdrive Recovery NOISE/DISTORTION Second Harmonic Third Harmonic Crosstalk Input Voltage Noise (RTI) INPUT CHARACTERISTICS Common-Mode Rejection VOUT = 1 V p-p, 1 MHz VOUT = 1 V p-p, 1 MHz VOUT = 1 V p-p, 10 MHz f ≥ 10 kHz DC, VCM = −3.5 V to +3.5 V VCM = 1 V p-p, f = 10 MHz VCM = 1 V p-p, f = 100 MHz V+IN − V−IN = 0 V Differential Common mode Differential Common mode DC, G = 2 G=2 TMIN to TMAX TMIN to TMAX (+IN, −IN) −400 RL = 150 Ω/1 kΩ Short to GND, source/sink −1.35 1.960 −13.5 −6 Common-Mode Voltage Range Differential Operating Range Resistance Capacitance DC PERFORMANCE Closed-Loop Gain Output Offset Voltage Input Bias Current (+IN, −IN) Input Bias Current Drift Input Offset Current OUTPUT PERFORMANCE Voltage Swing Output Current Short-Circuit Current POWER-DOWN PERFORMANCE Power-Down VIH Power-Down VIL Power-Down IIH Power-Down IIL Power-Down Assert Time Rev. 0 | Page 5 of 24 AD8145 Parameter POWER SUPPLY Operating Range Quiescent Current, Positive Supply Quiescent Current, Negative Supply PSRR, Positive Supply PSRR, Negative Supply Disabled DC DC Conditions Min 4.5 Disabled −43.5 −12.5 40 13.5 −36 −10 −83 −67 Typ Max 11 47 16 Unit V mA mA −73 −62 dB dB Rev. 0 | Page 6 of 24 AD8145 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating 12 V See Figure 2 –65°C to +125°C –40°C to +105°C 300°C 150°C Maximum Power Dissipation The maximum safe power dissipation in the AD8145 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8145. Exceeding a junction temperature of 150°C for an extended period of time can result in changes in the silicon devices, potentially causing failure. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. For each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. The power dissipated due to all of the loads is equal to the sum of the power dissipation due to each individual load. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces, through-holes, ground, and power planes reduces the θJA. The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface, which is thermally connected to a copper plane to achieve the specified θJA. Figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 32-lead LFCSP (47°C/W) on a JEDEC standard 4-layer board with the underside paddle soldered to a pad, which is thermally connected to a PCB plane. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in the circuit board with its exposed paddle soldered to a pad on the PCB surface, which is thermally connected to a copper plane. Table 4. Thermal Resistance Package Type 5 mm × 5 mm, 32-Lead LFCSP 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 06307-002 θJA 47 θJC 8.5 Unit °C/W MAXIMUM POWER DISSIPATION (W) ESD CAUTION 0 –40 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board Rev. 0 | Page 7 of 24 AD8145 PIN CONFIGURATION AND FUNCTION DESCRIPTION 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 GND IN–_B IN+_B GAIN_B REF_B DIS/PD VS– GND GND REF_G GAIN_G IN+_G IN–_G REF_R GAIN_R GND 1 2 3 4 5 6 7 8 PIN 1 INDICATOR TOP VIEW (Not to Scale) AD8145 GND OUT_B OUT_G OUT_R VS+ COMPB_IN+ COMPB_IN– GND Figure 3. 32-Lead LFCSP Pin Configuration Table 5. 32-Lead LFCSP Pin Function Descriptions Pin No. 1, 8, 9,16, 17, 24, 25, 32 2 3 4 5 6 7 10 11 12 13 14 15 18 19 20 21 22 23 26 27 28 29 30 31 Exposed Underside Pad Mnemonic GND REF_G GAIN_G IN+_G IN−_G REF_R GAIN_R IN+_R IN−_R COMPA_IN+ COMPA_INCOMPA_OUT COMPB_OUT COMPB_INCOMPB_IN+ VS+ OUT_R OUT_G OUT_B VS− DIS/PD REF_B GAIN_B IN+_B IN−_B GND Description Signal Ground and Thermal Plane Connection. (See the Absolute Maximum Ratings section.) Reference Input, Green Channel. Gain Connection, Green Channel. Noninverting Input, Green Channel. Inverting Input, Green Channel. Reference Input, Red Channel. Gain Connection, Red Channel. Noninverting Input, Red Channel. Inverting Input, Red Channel. Positive Input, Comparator A. Negative Input, Comparator A. Output, Comparator A. Output, Comparator B. Negative Input, Comparator B. Positive Input, Comparator B. Positive Power Supply. Output, Red Channel. Output, Green Channel. Output, Blue Channel. Negative Power Supply. Disable/Power Down. Reference Input, Blue Channel. Gain Connection, Blue Channel. Noninverting Input, Blue Channel. Inverting Input, Blue Channel. Signal Ground and Thermal Plane Connection. Rev. 0 | Page 8 of 24 06307-003 NOTES 1. EXPOSED PAD ON UNDERSIDE OF DEVICE MUST BE CONNECTED TO GROUND. GND IN+_R IN–_R COMPA_IN+ COMPA_IN– COMPA_OUT COMPB_OUT GND 9 10 11 12 13 14 15 16 AD8145 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, G = 1, RL = 150 Ω, CL = 2 pF, REF = midsupply, VS = ±5 V, TA = 25°C. Refer to the circuit in Figure 35. 3 2 +5V 1 0 GAIN (dB) 3 2 1 +5V ±5V GAIN (dB) 0 –1 –2 –3 –4 –5 –6 VOUT = 2V p-p 1 10 100 ±5V –1 –2 –3 –4 –5 –6 06307-004 1 10 100 1000 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 4. Small Signal Frequency Response at Various Power Supplies, G = 1 Figure 7. Large Signal Frequency Response at Various Power Supplies, G = 1 9 8 7 6 GAIN (dB) GAIN (dB) 9 8 7 6 5 4 3 2 1 +5V ±5V 5 4 3 +5V 2 1 0 –1 1 VOUT = 0.2V p-p 06307-005 ±5V 0 10 100 1000 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 5. Small Signal Frequency Response at Various Power Supplies, G = 2 Figure 8. Large Signal Frequency Response at Various Power Supplies, G = 2 3 2 1 0 GAIN (dB) GAIN (dB) 3 2 1 0 G G G G = 2, = 2, = 1, = 1, CL = 10 + 2pF, RSNUB = 20Ω CL = 0 + 2pF, RSNUB = 0Ω CL = 10 + 2pF, RSNUB = 20Ω CL = 0 + 2pF, RSNUB = 0Ω –1 –2 –3 –4 –5 –6 VOUT = 0.2V p-p 06307-006 –1 –2 –3 –4 –5 –6 –7 1 G G G G = 2, = 2, = 1, = 1, CL = 10 + 2pF, RSNUB = 20Ω CL = 0 + 2pF, RSNUB = 0Ω CL = 10 + 2pF, RSNUB = 20Ω CL = 0 + 2pF, RSNUB = 0Ω VOUT = 2V p-p 1 10 100 1000 06307-009 –7 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 6. Small Signal Frequency Response at Various Gains and 10 pF Capacitive Load Buffered by 20 Ω Resistor Figure 9. Large Signal Frequency Response at Various Gains and 10 pF Capacitive Load Buffered by 20 Ω Resistor Rev. 0 | Page 9 of 24 06307-008 –1 VOUT = 2V p-p 06307-007 –7 VOUT = 0.2V p-p –7 AD8145 3 2 1 0 GAIN (dB) GAIN (dB) 3 2 G=1 1 0 –1 G=2 –2 –3 –4 –5 VOUT = 0.2V p-p 06307-010 G=1 –1 –2 G=2 –3 –4 –5 –6 –7 1 –6 10 100 1000 1 10 100 1000 06307-013 –7 VOUT = 2V p-p FREQUENCY (MHz) FREQUENCY (MHz) Figure 10. Small Signal Frequency Response at Various Gains Figure 13. Large Signal Frequency Response at Various Gains 0.5 0.4 0.3 0.2 GAIN (dB) G = 1, VS = +5V 1000 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 1 VOUT = 2V p-p 06307-011 INPUT VOLTAGE NOISE (nV/ Hz) G = 1, VS = ±5V 100 G = 2, VS = +5V G = 2, VS = ±5V 10 100 1000 0.1 1 10 100 1000 10000 100000 FREQUENCY (MHz) FREQUENCY (kHz) Figure 11. 0.1 dB Flatness for Various Power Supplies and Gains Figure 14. Input Referred Voltage Noise vs. Frequency 110 100 COMMON-MODE REJECTION (dB) 4 3 2 1 0 –1 –2 RL = OPEN CIRCUIT G=1 VS = ±5V 90 80 70 60 50 40 30 20 06307-012 VS = +5V VS = ±5V OUTPUT VOLTAGE (V) –3 –4 –5 1 10 FREQUENCY (MHz) 100 1000 –4 –3 –2 –1 0 1 2 3 4 5 DIFFERENTIAL INPUT VOLTAGE (V) Figure 12. Common-Mode Rejection vs. Frequency at Various Supplies Figure 15. Differential Input Operating Range Rev. 0 | Page 10 of 24 06307-047 10 0.1 06307-046 10 0.01 AD8145 150 1.5 100 BLACK = +5V GRAY = ±5V VOLTAGE (mV) 1.0 BLACK = +5V GRAY = ±5V 0.5 VOLTAGE (V) 50 0 0 –50 –0.5 –100 VOUT = 0.2V p-p 06307-016 –1.0 VOUT = 2V p-p 30 40 50 TIME (ns) 60 70 80 90 100 0 10 20 30 40 50 TIME (ns) 60 70 80 90 100 06307-019 06307-021 06307-020 –150 0 10 20 –1.5 Figure 16. Small Signal Transient Response at Various Power Supplies, G = 1 Figure 19. Large Signal Transient Response at Various Power Supplies, G = 1 150 1.5 100 BLACK = +5V GRAY = ±5V VOLTAGE (mV) 1.0 BLACK = +5V GRAY = ±5V 0.5 VOLTAGE (V) 50 0 0 –50 –0.5 –100 VOUT = 0.2V p-p 0 10 20 30 40 50 TIME (ns) 60 70 80 90 100 06307-017 –1.0 VOUT = 2V p-p –1.5 0 10 20 30 40 50 TIME (ns) 60 70 80 90 100 –150 Figure 17. Small Signal Transient Response at Various Power Supplies, G = 2 Figure 20. Large Signal Transient Response at Various Power Supplies, G = 2 150 G = 1, CL = 0 + 2pF, RSNUB = 0Ω G = 1, CL = 10 + 2pF, RSNUB = 20Ω 100 1.5 G = 1, CL = 0 + 2pF, RSNUB = 0Ω G = 1, CL = 10 + 2pF, RSNUB = 20Ω 1.0 VOLTAGE (mV) 50 VOLTAGE (V) 0.5 VOUT = 0.2V p-p VOUT = 2V p-p 0 0 –50 –0.5 –100 G = 2, CL = 0 + 2pF, RSNUB = 0Ω G = 2, CL = 10 + 2pF, RSNUB = 20Ω 0 10 20 30 40 50 TIME (ns) 60 70 80 90 100 06307-018 –1.0 G = 2, CL = 0 + 2pF, RSNUB = 0Ω G = 2, CL = 10 + 2pF, RSNUB = 20Ω 0 10 20 30 40 50 TIME (ns) 60 70 80 90 100 –150 –1.5 Figure 18. Small Signal Transient Response at Various Gains and 10 pF Capacitive Load Buffered by 20 Ω Resistor Figure 21. Large Signal Transient Response at Various Gains and 10 pF Capacitive Load Buffered by 20 Ω Resistor Rev. 0 | Page 11 of 24 AD8145 2.0 1.6 INPUT 1.2 0.8 VOLTAGE (V) 0.5 OUTPUT 0.4 0.3 SLEW RATE (V/µs) 4500 4000 3500 3000 2500 2000 1500 1000 500 06307-048 06307-049 06307-027 06307-026 POSITIVE SLEW RATE 0.2 ERROR (%) 0.4 0 –0.4 –0.8 –1.2 –1.6 –2.0 0 5 10 15 20 25 TIME (ns) 30 35 40 45 ERROR 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 50 NEGATIVE SLEW RATE 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE (V p-p) Figure 22. Settling Time Figure 25. Slew Rate vs. Input Voltage Swing –50 –50 –60 –70 DISTORTION (dBc) –55 VS = +5V DISTORTION (dBc) –60 –80 VS = ±5V –90 –100 –110 –65 VS = ±5V –70 VS = +5V –75 VOUT = 2V p-p 1 10 FREQUENCY (MHz) 100 06307-023 –80 0.1 VOUT = 2V p-p –120 0.1 1 10 FREQUENCY (MHz) 100 Figure 23. Second Harmonic Distortion vs. Frequency and Power Supplies, VO = 2 V p-p, G = 1 –50 VOUT = 2V p-p Figure 26. Third Harmonic Distortion vs. Frequency and Power Supplies, VO = 2 V p-p, G = 1 –50 –60 VS = +5V –70 –55 DISTORTION (dBc) DISTORTION (dBc) –60 VS = ±5V –80 –90 –100 –110 VOUT = 2V p-p –120 0.1 –65 –70 VS = ±5V –75 VS = +5V 1 10 FREQUENCY (MHz) 100 06307-024 –80 0.1 1 10 FREQUENCY (MHz) 100 Figure 24. Second Harmonic Distortion vs. Frequency and Power Supplies, VO = 2 V p-p, G = 2 Figure 27. Third Harmonic Distortion vs. Frequency and Power Supplies, VO = 2 V p-p, G = 2 Rev. 0 | Page 12 of 24 AD8145 65 60 55 SUPPLY CURRENT (mA) RL = OPEN CIRCUIT 5 4 3 ICC (±5V) 2 VOLTAGE (V) 50 45 40 35 30 25 20 –40 –20 0 20 IEE (±5V) 1 0 –1 –2 –3 –4 G=2 +5V 2 × VIN ±5V OUTPUT ±5V 2 × VIN 100 150 200 250 300 350 400 450 500 06307-030 06307-032 IEE (±2.5V) +5V OUTPUT ICC (±2.5V) 40 60 80 100 120 06307-050 15 –60 –5 0 50 TEMPERATURE (°C) TIME (ns) Figure 28. Power Supply Current vs. Temperature Figure 31. Output Overdrive Recovery 10 0 –10 –20 PSRR (dB) 10 0 –10 –20 PSRR (dB) –30 –40 –50 –60 –70 –80 BLACK = +5V GRAY = ±5V –30 –40 –50 –60 –70 –80 BLACK = ±2.5V GRAY = ±5V 06307-029 –90 0.01 0.1 1 10 100 1000 –90 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 29. Positive Power Supply Rejection Ratio vs. Frequency Figure 32. Negative Power Supply Rejection Ratio vs. Frequency 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 –15 VOUT (V) VIN (mV) Figure 30. Comparator Hysteresis 06307-051 –10 –5 0 5 10 15 Rev. 0 | Page 13 of 24 AD8145 THEORY OF OPERATION The AD8145 amplifiers use an architecture called active feedback, which differs from that of conventional op amps. The most obvious differentiating feature is the presence of two separate pairs of differential inputs compared to a conventional op amp’s single pair. Typically, for the active-feedback architecture, one of these input pairs is driven by a differential input signal, while the other is used for the feedback. This active stage in the feedback path is where the term active feedback is derived. The AD8145 has an internal feedback resistor from each amplifier output to the negative input of its feedback input stage. This limits the possible closed-loop gain configurations for the AD8145. The active feedback architecture offers several advantages over a conventional op amp in several types of applications. Among these are excellent common-mode rejection, wide input commonmode range, and a pair of inputs that are high impedance and completely balanced in a typical application. In addition, while an external feedback network establishes the gain response as in a conventional op amp, its separate path makes it entirely independent of the signal input. This eliminates any interaction between the feedback and input circuits, which traditionally causes problems with CMRR in conventional differential-input op amp circuits. Another advantage of active feedback is the ability to change the polarity of the gain merely by switching the differential inputs. A high input impedance inverting amplifier can therefore be made. Besides high input impedance, a unity-gain inverter with the AD8145 has noise gain of unity, producing lower output noise and higher bandwidth than op amps that have noise gain equal to 2 for a unity-gain inverter. The two differential input stages of the AD8145 are each transconductance stages that are well matched. These stages convert the respective differential input voltages to internal currents. The currents are then summed and converted to a voltage, which is buffered to drive the output. The compensation capacitor is included in the summing circuit. When the feedback path is closed around the part, the output drives the feedback input to that voltage which causes the internal currents to sum to zero. This occurs when the two differential inputs are equal and opposite; that is, their algebraic sum is zero. In a closed-loop application, a conventional op amp has its differential input voltage driven to near zero under nontransient conditions. The AD8145 generally has differential input voltages at each of its input pairs, even under equilibrium conditions. As a practical consideration, it is necessary to internally limit the differential input voltage with a clamp circuit. Thus, the input dynamic ranges are limited to about 2.5 V for the AD8145 (see the Specifications section for more detail). For this and other reasons, it is not recommended to reverse the input and feedback stages of the AD8145, even though some apparently normal functionality may be observed under some conditions. Rev. 0 | Page 14 of 24 AD8145 APPLICATIONS OVERVIEW The AD8145 contains three independent active feedback amplifiers that can be effectively applied as differential line receivers for red-green-blue (RGB) signals or component video signals, such as YPbPr, transmitted over unshielded twisted pair (UTP) cable. The AD8145 also contains two general-purpose comparators with hysteresis that can be used to receive digital signals or to extract video synchronization pulses from received commonmode signals that contain encoded synchronization signals. The comparators, which receive power from the positive supply, are referenced to GND and require greater than 4.5 V on the positive supply for proper operation. If the comparators are not used, then a split ±2.5 V can be used with the amplifiers operating normally. The AD8145 includes a power-down feature that can be asserted to reduce the supply current when a particular device is not in use. –5V +5V 0.01µF VIN OUT REF VOUT VREF R R C GAIN 0.01µF Figure 33. Basic Gain = 1 Circuit: VOUT = VIN + VREF The gain equation for the circuit in Figure 33 is VOUT = VIN + VREF (1) In this configuration, the voltage applied to the REF pin appears at the output with a gain of 1. Figure 34 illustrates one way to operate an AD8145 amplifier with a gain of 2. +5V BASIC CLOSED-LOOP GAIN CONFIGURATIONS Each amplifier in the AD8145 comprises two transconductance amplifiers—one for the input signal and one for negative feedback. It is important to note that the closed-loop gain of the amplifier used in the signal path is defined as the single-ended output voltage of the amplifier divided by its differential input voltage. Therefore, each amplifier in the AD8145 provides differentialto-single-ended gain. Additionally, the amplifier used for feedback has two high impedance inputs—the feedback input, where the negative feedback is applied, and the REF input, which can be used as an independent single-ended input to apply a dc offset to the output signal. The AD8145 contains on-chip feedback networks between each amplifier output and its respective feedback input. Closed-loop gain of an amplifier is set to 1 by connecting the amplifier output directly to its respective GAIN pin. Doing this places the onchip resistors and capacitor in parallel across the amplifier output and feedback pin. The small feedback capacitor mitigates the effects of summing-node capacitance, which is most problematic in the unity gain case. Closed-loop gain of an amplifier is set to 2 by connecting the respective GAIN pin to a reference voltage, often directly to ground. In Figure 1, R = 350 Ω and C = 2 pF. Some basic gain configurations implemented with an AD8145 amplifier are shown in Figure 33 through Figure 36. 0.01µF VIN REF VREF VOUT C GAIN R R 06307-035 0.01µF –5V Figure 34. Basic Gain = 2 Circuit: VOUT = 2(VIN + VREF) The gain equation for the circuit in Figure 34 is VOUT = 2(VIN + VREF) (2) Rev. 0 | Page 15 of 24 06307-034 AD8145 To achieve unity gain from VREF to VOUT in this configuration, divide VREF by the same factor used in the feedback loop; the divider resistors, RD, need not be the same values used in the internal feedback loop. Figure 35 illustrates this approach. +5V TERMINATING THE INPUT One of the key benefits of the active feedback architecture is the separation that exists between the differential input signal and the feedback network. Because of this separation, the differential input maintains its high CMRR and provides high differential and common-mode input impedances, making line termination a simple task. Most applications that use the AD8145 involve transmitting broadband video signals over 100 Ω UTP cable and use dc-coupled terminations. The two most common types of dc-coupled terminations are differential and common-mode. Differential termination of 100 Ω UTP is implemented by simply connecting a 100 Ω resistor across the amplifier input, as shown in Figure 37. +5V 0.01µF VIN RD VREF RD REF VOUT C R R 06307-036 GAIN 0.01µF –5V Figure 35. Basic Gain Circuit: VOUT = 2VIN + VREF 0.01µF 100Ω UTP The gain equation for the circuit in Figure 35 is VOUT = 2VIN + VREF (3) Another configuration that provides the same gain equation as Equation 3 is shown in Figure 36. In this configuration, it is important to keep the source resistance of VREF much smaller than 350 Ω to avoid gain errors. +5V 100Ω VIN OUT REF VOUT R R C GAIN 0.01µF 0.01µF –5V 06307-038 VIN Figure 37. Differential-Mode Termination with G = 1 REF VOUT C R VREF –5V R 06307-037 GAIN 0.01µF Some applications require common-mode terminations for common-mode currents generated at the transmitter. In these cases, the 100 Ω termination resistor is split into two 50 Ω resistors. The required common-mode termination voltage is applied at the tap between the two resistors. In many of these applications, the common-mode tap is connected to ground (VTERM (CM) = 0). This scheme is illustrated in Figure 38. +5V Figure 36. Basic Gain Circuit: VOUT = 2VIN + VREF For stability reasons, the inductance of the trace connected to the REF pin must be kept to less than 10 nH. The typical inductance of 50 Ω traces on the outer layers of the FR-4 boards is 7 nH/in, and on the inner layers, it is typically 9 nH/in. Vias must be accounted for as well. The inductance of a typical via in a 0.062 inch board is on the order of 1.5 nH. If longer traces are required, a 200 Ω resistor should be placed in series with the trace to reduce the Q-factor of the inductance. In many dual-supply applications, VREF can be directly connected to ground right at the device. 0.01µF 100Ω UTP 50Ω 50Ω VTERM (CM) REF VIN OUT VOUT R R C GAIN 0.01µF –5V Figure 38. Common-Mode Termination with G = 1 Rev. 0 | Page 16 of 24 06307-039 AD8145 INPUT CLAMPING The differential input that is assigned to receive the input signal includes clamping diodes that limit the differential input swing to approximately 5.5 V p-p at 25°C. Because of this, the input and feedback stages should never be interchanged. The supply current drawn by the AD8145 has a strong dependence on input signal magnitude because the input transconductance stages operate with differential input signals that can be up to a few volts peak-to-peak. This behavior is distinctly different from that of traditional op amps, where the differential input signal is driven to essentially 0 V by negative feedback. For most applications, including receiving RGB video signals, the input signal magnitudes encountered are well within the safe operating limits of the AD8145 over its full power supply and operating temperature ranges. In some extreme applications where large differential and/or common-mode voltages are encountered, external clamping may be necessary. Another application in which external common-mode clamping is sometimes required is when an unpowered AD8145 receives a signal from an active driver. In this case, external diodes are required when the current drawn by the internal ESD diodes cannot be kept to less than 5 mA. Figure 39 shows a general approach to external differentialmode clamping. POSITIVE CLAMP NEGATIVE CLAMP + RS RT RS REF OUT VOUT +5V A diode is a simple example of such a clamp. Schottky diodes generally have lower clamping voltages than typical signal diodes. The clamping voltage should be larger than the largest expected signal amplitude, with enough margin to ensure that the received signal passes without being distorted. A simple way to implement a clamp is to use a number of diodes in series. The resultant clamping voltage is then the sum of the clamping voltages of individual diodes. A 1N4448 diode has a forward voltage of approximately 0.70 V to 0.75 V at typical current levels that are seen when it is being used as a clamp, and 2 pF maximum capacitance at 0 V bias. (The capacitance of a diode decreases as its reverse bias voltage is increased.) The series connection of two 1N4448 diodes, therefore, has a clamping voltage of 1.4 V to 1.5 V. Figure 40 shows how to limit the differential input voltage applied to an AD8145 amplifier to ±1.4 V to ±1.5 V (2.8 V p-p to 3.0 V p-p). Note that the capacitance of the two series diodes is half that of one diode. Different numbers of series diodes can be used to obtain different clamping voltages. RT is the differential termination resistor, and the series resistances, RS, limit the current into the diodes. The series resistors should be highly matched in value to preserve high frequency CMRR. +5V POSITIVE CLAMP + VIN – RS RT RS REF OUT VOUT NEGATIVE CLAMP 0.01µF 0.01µF VIN – R R R R C GAIN C GAIN 0.01µF –5V 0.01µF –5V 06307-040 Figure 40. Using Two 1N4448 Diodes in Series as a Clamp Figure 39. Differential-Mode Clamping with G = 1 The positive and negative clamps are nonlinear devices that exhibit very low impedance when the voltage across them reaches a critical threshold (clamping voltage), thereby limiting the voltage across the AD8145 input. The positive clamp has a positive threshold, and the negative clamp has a negative threshold. There are many other nonlinear devices that can be used as clamps. The best choice for a particular application depends upon the desired clamping voltage, response time, parasitic capacitance, and other factors. When using external differential-mode clamping, it is important to ensure that the series resistors (RS), the sum of the parasitic capacitance of the clamping devices, and the input capacitance of the AD8145 are small enough to preserve the desired signal bandwidth. Rev. 0 | Page 17 of 24 06307-041 AD8145 Figure 41 shows a specific example of external common-mode clamping. V+ 2 3 RS HBAT-540C VIN RT 1 V– V+ 2 RS 3 REF OUT VOUT +5V + 0.01µF – Typically, the input signals are received over 100 Ω differential transmission lines. A 100 Ω differential transmission line is readily realized on the printed circuit board using two wellmatched, closely-spaced, 50 Ω single-ended traces that are coupled through the ground plane. The traces that carry the single-ended output signals are most often 75 Ω for video signals. Output signal connections should include series termination resistors that are matched to the impedance of the line they are driving. When driving high impedance loads over very short traces, impedance matching is not required. In these cases, small series resistors should be used to buffer the capacitance presented by the load. Broadband power supply decoupling networks should be placed as close as possible to the supply pins. Small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended for bulk supply decoupling. HBAT-540C 1 V– R R C GAIN 0.01µF –5V 06307-042 Minimizing Parasitic Feedback Reactances Parasitic trace capacitance and inductance are both reduced in the unity-gain configuration when the feedback trace that connects the OUT pin to the GAIN pin is reduced in length. Removing the copper from all planes below the trace reduces trace capacitance, but increases trace inductance, since the loop area formed by the trace and ground plane is increased. A reasonable compromise that works well is to void all copper directly under the feedback trace and component pads with margins on each side approximately equal to one trace width. Combining this technique with minimizing trace length is effective in keeping parasitic trace reactance in the unity-gain feedback loop to a minimum. Figure 41. External Common-Mode Clamping The series resistances, RS, limit the current in each leg, and the Schottky diodes limit the voltages on each input to approximately 0.3 V to 0.4 V over the positive power supply, V+, and to 0.3 V to 0.4 V below the negative power supply, V−. The maximum value of RS is determined by the required signal bandwidth, the line impedance, and the effective differential capacitance due to the AD8145 inputs and the diodes. As with the differential clamp, the series resistors should be highly matched in value to preserve high frequency CMRR. PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS The two most important issues with regard to printed circuit board (PCB) layout are minimizing parasitic signal trace reactances in the feedback network and providing sufficient thermal relief. Excessive parasitic reactances in the feedback network cause excessive peaking in the frequency response of the amplifier and excessive overshoot in its step response due to a reduction in phase margin. Oscillation occurs when these parasitic reactances are increased to a critical point where the phase margin is reduced to zero. Minimizing these reactances is important to obtain optimal performance from the AD8145. General high speed layout practices should be adhered to when applying the AD8145. Controlled impedance transmission lines are required for incoming and outgoing signals, referenced to a ground plane. Maximizing Heat Removal A 5 × 5 array of thermal vias works well to connect the exposed paddle to internal ground planes. The vias should be placed inside the PCB pad that is soldered to the exposed paddle, and should connect to all ground planes. The AD8145 includes ground connections on its corner pins. These pins can be used to provide additional heat removal from the AD8145 by connecting them between the PCB pad that is soldered to the exposed paddle and a ground plane on the component side of the board. This layout technique lowers the overall package thermal resistance. Use of this technique is not required, but it does result in a lower junction temperature. Designs must often conform to design for manufacturing (DFM) rules that stipulate how to lay out PCBs in such a way as to facilitate the manufacturing process. Some of these rules require thermal relief on pads that connect to planes, and the rules may limit the extent to which this technique can be used. Rev. 0 | Page 18 of 24 AD8145 DRIVING A CAPACITIVE LOAD The AD8145 typically drives either high impedance loads over short PCB traces, such as crosspoint switch inputs, or doubly terminated coaxial cables. A gain of 1 is commonly used in the high impedance case since the 6 dB transmission line termination loss is not incurred. A gain of 2 is required when driving cables to compensate for the 6 dB termination loss. In all cases, the output must drive the parasitic capacitance of the feedback loop, conservatively estimated to be 1 pF, in addition to the capacitance presented by the actual load. When driving a high impedance input, it is recommended that a small series resistor be used to buffer the input capacitance of the device being driven. Clearly, the resistor value must be small enough to preserve the required bandwidth. In the ideal doubly terminated cable case, the AD8145 output sees a purely resistive load. In reality, there is some residual capacitance, and this is buffered by the series termination resistor. Figure 42 illustrates the high impedance case, and Figure 43 illustrates the cabledriving case. VREF R R C GAIN +5V 0.01µF VIN OUT REF RS CIN 0.01µF –5V Figure 42. Buffering the Input Capacitance of a High-Z Load with G = 1 +5V POWER-DOWN The power-down feature is intended to be used to reduce power consumption when a particular device is not in use, and does not place the output in a high-Z state when asserted. The power-down feature is asserted when the voltage applied to the power-down pin drops to approximately 2 V below the positive supply. The AD8145 is enabled by pulling the power-down pin to the positive supply. VIN 0.01µF OUT RS REF VREF CS RL C GAIN R R 06307-044 0.01µF –5V Figure 43. Driving a Doubly Terminated Cable with G = 2 Rev. 0 | Page 19 of 24 06307-043 AD8145 COMPARATORS In addition to general-purpose applications, the two on-chip comparators can be used to decode video sync pulses from the received common-mode voltages, or to receive differential digital information. Built-in hysteresis helps to eliminate false triggers from noise. The comparator outputs are designed to drive source-terminated transmission lines. The source termination technique uses a resistor in series with each comparator output such that the sum of the comparator source resistance (≈ 20 Ω) and the series resistor equals the transmission line characteristic impedance. The load end of the transmission line is high impedance. When the signal is launched into the source termination, its initial value is one-half of its source value, since its amplitude is divided by two by the voltage divider formed by the source termination and the transmission line. At the load, the signal experiences nearly 100% positive reflection due to the high impedance load, and is restored to nearly its full value. This technique is commonly used in PCB layouts that involve high speed digital logic. An internal linear voltage regulator derives power for the comparators from the positive supply; therefore, the AD8145 must always have a minimum positive supply voltage of 4.5 V. not embedded in the color signals, it is advantageous to transmit them using a simple scheme that encodes them among the three common-mode voltages of the RGB signals. The AD8134 triple differential driver is a natural complement to the AD8145 and performs the sync pulse encoding with the necessary circuitry on-chip. The AD8134 encoding equations are given in Equation 4, Equation 5, and Equation 6. Red VCM = K V −H 2 [ ] ] (4) (5) (6) Green VCM = Blue VCM = where: K −2 V 2 [ K V +H 2 [ ] Red VCM, Green VCM, and Blue VCM are the transmitted commonmode voltages of the respective color signals. K is an adjustable gain constant that is set by the AD8134. V and H are the vertical and horizontal sync pulses, defined with a weight of −1 when the pulses are in their low states, and a weight of +1 when they are in their high states. The AD8134 data sheet contains further details regarding the encoding scheme. Figure 44 illustrates how the AD8145 comparators can be used to extract the horizontal and vertical sync pulses that are encoded on the RGB common-mode voltages by the AD8134. SYNC PULSE EXTRACTION USING COMPARATORS The AD8145 is particularly useful in keyboard, video, mouse (KVM) applications. KVM networks transmit and receive computer video signals, which typically comprise red, green, and blue (RGB) video signals and separate horizontal and vertical sync signals. Because the sync signals are separate and RECEIVED RED VIDEO 50Ω RED CMV 50Ω RS HSYNC 1kΩ 50Ω GREEN CMV 50Ω 47pF 1kΩ 50Ω BLUE CMV 50Ω 06307-045 47pF 475Ω RS VSYNC RECEIVED GREEN VIDEO RECEIVED BLUE VIDEO Figure 44. Extracting Sync Signals from Received Common-Mode Signal Rev. 0 | Page 20 of 24 AD8145 OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 3.45 3.30 SQ 3.15 8 0.50 0.40 0.30 12° MAX 17 16 9 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 45. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-3) Dimensions shown in millimeters ORDERING GUIDE Model AD8145YCPZ-R2 1 AD8145YCPZ-RL1 AD8145YCPZ-R71 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Package Option CP-32-3 CP-32-3 CP-32-3 Z = Pb-free part. Rev. 0 | Page 21 of 24 AD8145 NOTES Rev. 0 | Page 22 of 24 AD8145 NOTES Rev. 0 | Page 23 of 24 AD8145 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06307-0-10/06(0) Rev. 0 | Page 24 of 24