AD8152JBPZ

FEATURES FUNCTIONAL BLOCK DIAGRAM VCC Low cost Low power: 2.5 V (outputs disabled) 34 × 34, fully differential, nonblocking array 3.2 Gbps per port NRZ data rate Wide power supply range: 2.5 V to 3.3 V LVTTL or LVCMOS level control inputs at 2.5 V to 3.3 V Low channel jitter: 45 ps p-p Drives a backplane directly Programmable output swing 100 mV to 1600 mV p-p differential 50 Ω on-chip input/output termination User controlled voltage at the load Minimizes power dissipation Dual rank latches Available in 256-ball BGA_ED package IN33P TO IN00P 34 34 34 × 34 DIFFERENTIAL SWITCH MATRIX VTTI IN33N TO IN00N D0 TO D5 34 MATRIX CONNECTION LATCHES OUTPUT LEVEL DACs OUT33P TO OUT00P VTTO 34 OUT33N TO OUT00N CONNECTION DECODE OUTPUT LEVEL LATCHES RESET CS A0 TO A6 RE CONTROL LOGIC WE AD8152 UPDATE VEE APPLICATIONS Fiber optic network switching High speed serial backplane routing to OC-48 with FEC Gigabit ethernet Digital video (HDTV) Data storage networks 02984-001 Data Sheet 34 × 34, 3.2 Gbps Asynchronous Digital Crosspoint Switch AD8152 Figure 1. GENERAL DESCRIPTION The AD8152 is a breakthrough cross point switch offering a large switch array (34 × 34) on very little power, typically 2.0 W. Additionally, the device operates at data rates up to 3.2 Gbps per port, making it suitable for Sonet/SDH OC-48 with forward error correction (FEC). The fully differential signal path of the AD8152 reduces jitter and crosstalk and allows the use of smaller single-ended voltage swings. The device is offered in a 256-ball BGA_ED package that operates over the industrial temperature range of 0°C to 85°C. The useful supply voltage range of the AD8152 allows the user to operate at LVPECL/CML data levels down to 2.5 V. The control interface is low voltage transistor transistor logic (LVTTL) or low voltage complementary metal-oxide (LVCMOS) compatible on 2.5 V to 3.3 V. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8152 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................9 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 14 General Description ......................................................................... 1 Test Circuits..................................................................................... 18 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 19 Revision History ............................................................................... 2 Control Pin Description ............................................................ 19 Specifications..................................................................................... 3 AD8152 Power Consumption .................................................. 22 Timing Specifications .................................................................. 4 Outputs ........................................................................................ 24 Absolute Maximum Ratings ............................................................ 8 Outline Dimensions ....................................................................... 25 Maximum Power Dissipation ..................................................... 8 Ordering Guide .......................................................................... 25 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 REVISION HISTORY 9/2019—Rev. A to Rev. B Updated Format .................................................................. Universal Removed Xstream ......................................................... Throughout Deleted Figure 2; Renumbered Sequentially ................................. 1 Changes to Features Section, General Description, and Figure 1.... 1 Deleted Thermal Characteristics Parameters, Table 1................. 2 Changed Electrical Characteristics Section to Specifications Section ................................................................................................ 3 Added Timing Specifications Section, Table 3; Renumbered Sequentially, and Endnote 1, Table 4.............................................. 4 Moved Table 2 and Table 4 to Table 6 ............................................... 4 Changes to Timing Specifications Section, Table 2, Table 4, and Table 5 ................................................................................................ 4 Moved Table 7 to Table 11 ............................................................... 5 Added Endnote 1 to Table 10 .......................................................... 5 Changes to Endnote 1, Table 9, and Table 7 to Table 11 ............. 5 Added Timing Diagrams Section ................................................... 6 Moved Figure 2 to Figure 4 ............................................................. 6 Moved Figure 5 and Figure 6 .......................................................... 7 Added Thermal Resistance Section and Table 13 ........................ 8 Changes to Table 12 and Figure 7 ................................................... 8 Changes to Figure 8 .......................................................................... 9 Changes to Table 14 ........................................................................ 10 Changes to Figure 16 and Figure 18............................................. 15 Changes to Figure 21 Caption, Figure 22, Figure 23 Caption, Figure 25 Caption, and Figure 26 ................................................. 16 Added Test Circuits Section .......................................................... 18 Changes to Figure 31 to Figure 33 ................................................ 18 Changed Control Interface Section to Theory of Operation Section, A[6:0] Inputs Section to A0 to A6 Inputs Section, D[5:0] Inputs Section to D5 to D0 Inputs Section ..................... 19 Changes to Output Addressing Section, Connection and Output Current Programming Section, Using the Data Bus Section, and Register Control Signals Section .................................................. 20 Deleted Evaluation Board and PCB Layout Hints Section, Figure 10, and Figure 11 ................................................................ 21 Changed Input/Output Coupling Section to Internal Input/Output Termination Section .............................................. 21 Changes to Internal Input/Output Termination Section, Input Coupling Section, and Output Coupling Section ...................... 21 Deleted Figure 12 to Figure 14, Board Construction or Stack-Up Section, and Bypass Capacitor Layout Section ........................... 22 Changes to AD8152 Power Consumption Section .................... 22 Deleted Figure 15, Figure 16, and Connections for Testing Section .............................................................................................. 23 Changes to Input Termination Resistors Section and Input Stage Section .............................................................................................. 23 Deleted Evaluation Board Control Software Section and Figure 14 .......................................................................................... 24 Changes to Power Saving Consideration Section .......................... 24 Deleted Figure 18............................................................................ 25 Moved Ordering Guide Section ...................................................... 25 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 Deleted Figure 19............................................................................ 26 Deleted Figure 20............................................................................ 27 Deleted Figure 21............................................................................ 28 Deleted Figure 22............................................................................ 29 Deleted Figure 23............................................................................ 30 1/2003—Rev. 0 to Rev. A Edits to Specifications .......................................................................2 9/2002—Revision 0: Initial Version Rev. B | Page 2 of 25 Data Sheet AD8152 SPECIFICATIONS At 25°C, VCC = 2.5 V to 3.3 V, VEE = 0 V, load resistor (RL) = 50 Ω, and differential output swing = 800 mV p-p, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE Maximum Data Rate/Channel Nonreturn to Zero (NRZ) Channel Jitter Root Mean Square (RMS) Channel Jitter Propagation Delay Propagation Delay Match Output Rise and Fall Time INPUT CHARACTERISTICS Input Voltage Swing Input Voltage Range Input Bias Current Input Capacitance OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage Range Output Current (IOUT) Output Capacitance TERMINATION CHARACTERISTICS Resistance Temperature Coefficient POWER SUPPLY Operating Range VCC Quiescent Current VCC VEE LOGIC INPUT CHARACTERISTICS Input High (VIH) Input Low (VIL) Input High (VIH) Input Low (VIL) LOGIC OUTPUT CHARACTERISTICS Output High (VOH) Output Low (VOL) Output High (VOH) Output Low (VOL) Test Conditions/Comments Min Typ Max 3.2 Data rate ≤ 3.2 Gbps; PRBS 223 − 1 20% to 80% Single-ended (see Figure 22) Common-mode (see Figure 23) Gbps 45