Zero Drift, Digitally Programmable
Instrumentation Amplifier
AD8231
Data Sheet
14
CS
13
A1
11
IN-AMP
3
10
4
9
OUTA
REF
06586-001
6
+INB
5
–VS
OP
AMP
AD8231
SDN
+VS
8
NC
LOGIC
OUTB
+INA
2
12
7
–INA
1
–INB
NC
15
16
Digitally/pin-programmable gain
G = 1, 2, 4, 8, 16, 32, 64, or 128
Specified from −40°C to +125°C
50 nV/°C maximum input offset drift
10 ppm/°C maximum gain drift
Excellent dc performance
80 dB minimum CMR, G = 1
15 µV maximum input offset voltage
500 pA maximum bias current
0.7 µV p-p noise (0.1 Hz to 10 Hz)
Good ac performance
2.7 MHz bandwidth, G = 1
1.1 V/μs slew rate
Rail-to-rail output
Shutdown/multiplex
Extra op amp
Single-supply range: 3 V to 5 V
Dual-supply range: ±1.5 V to ±2.5 V
Qualified for automotive applications
A0
FUNCTIONAL BLOCK DIAGRAM
A2
FEATURES
Figure 1.
Table 1. Instrumentation and Difference Amplifiers by
Category
High
Performance
AD8221
AD82201
AD8222
AD82241
APPLICATIONS
Pressure and strain transducers
Thermocouples and RTDs
Programmable instrumentation
Industrial controls
Weigh scales
Automotive controls
1
Low
Cost
AD623 1
AD85531
High
Voltage
AD628
AD629
Mil
Grade
AD620
AD621
AD524
AD526
AD624
Low
Power
AD6271
Digital
Gain
AD82311
AD8250
AD8251
AD85551
AD85561
AD85571
Rail-to-rail output.
GENERAL DESCRIPTION
The AD8231 is a low drift, rail-to-rail, instrumentation amplifier
with software-programmable gains of 1, 2, 4, 8, 16, 32, 64, or 128.
The gains are programmed via digital logic or pin strapping.
The AD8231 is ideal for applications that require precision
performance over a wide temperature range, such as industrial
temperature sensing and data logging. Because the gain setting
resistors are internal, maximum gain drift is only 10 ppm/°C for
gains of 1 to 32. Because of the auto-zero input stage, maximum
input offset is 15 µV and maximum input offset drift is just
50 nV/°C. CMRR is 80 dB for G = 1, increasing to 110 dB at
higher gains.
Rev. E
The AD8231 also includes an uncommitted op amp that can be
used for additional gain, differential signal driving, or filtering.
Like the in-amp, the op amp has an auto-zero architecture, railto-rail input, and rail-to-rail output.
The AD8231 includes a shutdown feature that reduces current
to a maximum of 1 µA. In shutdown, both amplifiers also have
a high output impedance, which allows easy multiplexing of
multiple amplifiers without additional switches.
The AD8231 is specified over the extended industrial temperature range of −40°C to +125°C. It is available in a 4 mm × 4 mm
16-lead LFCSP.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8231
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Selection ............................................................................. 18
Applications ....................................................................................... 1
Reference Terminal .................................................................... 18
Functional Block Diagram .............................................................. 1
Layout .......................................................................................... 19
General Description ......................................................................... 1
Input Bias Current Return Path ............................................... 19
Revision History ............................................................................... 2
Input Protection ......................................................................... 19
Specifications..................................................................................... 3
RF Interference ........................................................................... 20
Absolute Maximum Ratings ............................................................ 7
Common-Mode Input Voltage Range ..................................... 20
Thermal Resistance ...................................................................... 7
Reducing Noise ........................................................................... 20
Maximum Power Dissipation ..................................................... 7
Applications Information .............................................................. 21
ESD Caution .................................................................................. 7
Differential Output .................................................................... 21
Pin Configuration and Function Descriptions ............................. 8
Multiplexing ................................................................................ 21
Typical Performance Characteristics ............................................. 9
Using the AD8231 with Bipolar Supplies ................................ 21
Instrumentation Amplifier Performance Curves ..................... 9
Sallen Key Filter .......................................................................... 22
Operational Amplifier Performance Curves .......................... 15
Outline Dimensions ....................................................................... 23
Performance Curves Valid for Both Amplifiers ..................... 17
Ordering Guide .......................................................................... 23
Theory of Operation ...................................................................... 18
Automotive Products ................................................................. 23
Amplifier Architecture .............................................................. 18
REVISION HISTORY
10/2017—Rev. D to Rev. E
Changed CP-16-17 to CP-16-23 .................................. Throughout
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
3/2017—Rev. C to Rev. D
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
12/2014—Rev. B to Rev. C
Changes to Figure 12 to Figure 14 Captions ............................... 10
Changes to Figure 19 and Figure 20............................................. 11
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
4/2011—Rev. A to Rev. B
Changes to Features Section and Applications Section ............... 1
Added Exposed Pad Notation to Outline Dimensions ............. 23
Changes to Ordering Guide .......................................................... 23
Added Automotive Products Section........................................... 23
Inserted Figure 9; Renumbered Sequentially.............................. 10
Inserted Figure 16, and Figure 18 to Figure 20; Renumbered
Sequentially ..................................................................................... 11
Inserted Figure 24; Renumbered Sequentially ........................... 12
Deleted Figure 28 and Figure 29; Renumbered Sequentially ... 13
Inserted Figure 33 and Figure 34; Renumbered Sequentially .. 14
Inserted Figure 41 to Figure 46; Renumbered Sequentially ..... 16
Inserted Figure 48; Renumbered Sequentially ........................... 17
Changes to Gain Selection Section and Figure 50 ..................... 18
Added Input Protection Section ................................................... 19
Added Reducing Noise Section .................................................... 20
Changes to Multiplexing Section ................................................. 21
Added Using the AD8231 with Bipolar Supplies Section ......... 21
Added Sallen Key Filter Section ................................................... 22
Changes to Ordering Guide .......................................................... 23
5/2007—Revision 0: Initial Version
9/2007—Rev. 0 to Rev. A
Changes to Features and General Description ............................. 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Typical Performance Characteristics Layout ............ 9
Inserted Figure 3 to Figure 8; Renumbered Sequentially ............ 9
Rev. E | Page 2 of 24
Data Sheet
AD8231
SPECIFICATIONS
VS = 5 V, VREF = 2.5 V, G = 1, RL = 10 kΩ, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INSTRUMENTATION AMPLIFIER
Offset Voltage
Input Offset, VOSI
Average Temperature Drift
Output Offset, VOSO
Average Temperature Drift
Input Currents
Input Bias Current
Conditions
Min
Typ
Max
Unit
4
0.01
15
0.05
15
0.05
30
0.5
µV
µV/°C
µV
µV/°C
250
500
5
100
0.5
pA
nA
pA
nA
0.05
0.8
%
%
10
20
30
ppm/°C
ppm/°C
ppm/°C
ppm
ppm
VOS RTI = VOSI + VOSO/G
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
Input Offset Current
Gains
Gain Error
G=1
G = 2 to 128
Gain Drift
G = 1 to 32
G = 64
G = 128
Linearity
CMRR
G=1
G=2
G=4
G=8
G = 16
G = 32
G = 64
G = 128
Noise
Input Voltage Noise, eni
Output Voltage Noise, eno
Current Noise
Other Input Characteristics
Common-Mode Input Impedance
Power Supply Rejection Ratio
Input Operating Voltage Range
Reference Input
Input Impedance
Voltage Range
20
TA = −40°C to +125°C
1, 2, 4, 8, 16, 32, 64, or 128
TA = −40°C to +125°C
3
4
10
3
5
0.2 V to 4.8 V, 10 kΩ load
0.2 V to 4.8 V, 2 kΩ load
80
86
92
98
104
110
110
110
en = √(eni2 + (eno/G)2), VIN+, VIN− = 2.5 V
f = 1 kHz
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz
f = 10 Hz
100
0.05
dB
dB
dB
dB
dB
dB
dB
dB
32
27
39
0.7
58
50
70
1.1
20
nV/√Hz
nV/√Hz
nV/√Hz
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
µV p-p
fA/√Hz
10||5
115
4.95
GΩ||pF
dB
V
+5.2
kΩ
V
28
−0.2
Rev. E | Page 3 of 24
AD8231
Parameter
Dynamic Performance
Bandwidth
G=1
G=2
Gain Bandwidth Product
G = 4 to 128
Slew Rate
Output Characteristics
Output Voltage High
Output Voltage Low
Short-Circuit Current
Digital Interface
Input Voltage Low
Input Voltage High
Setup Time to CS High
Hold Time after CS High
OPERATIONAL AMPLIFIER
Input Characteristics
Offset Voltage, VOS
Temperature Drift
Input Bias Current
Data Sheet
Conditions
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 5 V
RL = 10 kΩ to 5 V
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
Min
4.9
4.8
Typ
MHz
MHz
7
1.1
MHz
V/µs
4.94
4.88
60
80
70
V
V
mV
mV
mA
1.0
V
V
ns
ns
15
0.06
500
5
100
0.5
4.95
120
120
110
20
0.4
µV
µV/°C
pA
nA
pA
nA
V
V/mV
dB
dB
nV/√Hz
µV p-p
1
0.5
MHz
V/µs
4.96
4.92
60
80
70
V
V
mV
mV
mA
5
0.01
250
Input Offset Current
20
TA = −40°C to +125°C
Output Voltage Low
0.05
100
100
100
f = 0.1 Hz to 10 Hz
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 5 V
RL = 10 kΩ to 5 V
Short-Circuit Current
BOTH AMPLIFIERS
Power Supply
Quiescent Current
Quiescent Current (Shutdown)
4.9
4.8
4
0.01
Rev. E | Page 4 of 24
100
200
4.0
50
20
TA = −40°C to +125°C
Unit
2.7
2.5
TA = −40°C to +125°C
Input Voltage Range
Open-Loop Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Voltage Noise Density
Voltage Noise
Dynamic Performance
Gain Bandwidth Product
Slew Rate
Output Characteristics
Output Voltage High
Max
100
200
5
1
mA
µA
Data Sheet
AD8231
VS = 3.0 V, VREF = 1.5 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.
Table 3.
Parameter
INSTRUMENTATION AMPLIFIER
Offset Voltage
Input Offset, VOSI
Average Temperature Drift
Output Offset, VOSO
Average Temperature Drift
Input Currents
Input Bias Current
Conditions
Min
Typ
Max
Unit
4
0.01
15
0.05
15
0.05
30
0.5
µV
µV/°C
µV
µV/°C
250
500
5
100
0.5
pA
nA
pA
nA
0.05
0.8
%
%
10
20
30
ppm/°C
ppm/°C
ppm/°C
VOS RTI = VOSI + VOSO/G
TA = −40°C to +125°C
Input Offset Current
Gains
Gain Error
G=1
G = 2 to 128
Gain Drift
G = 1 to 32
G = 64
G = 128
CMRR
G=1
G=2
G=4
G=8
G = 16
G = 32
G = 64
G = 128
Noise
Input Voltage Noise, eni
Output Voltage Noise, eno
Current Noise
Other Input Characteristics
Common-Mode Input Impedance
Power Supply Rejection Ratio
Input Operating Voltage Range
Reference Input
Input Impedance
Voltage Range
20
TA = −40°C to +125°C
1, 2, 4, 8, 16, 32, 64, or 128
TA = −40°C to +125°C
3
4
10
80
86
92
98
104
110
110
110
en = √(eni2 + (eno/G)2)
VIN+, VIN− = 2.5 V, TA = 25°C
f = 1 kHz
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz, TA = −40°C
f = 1 kHz, TA = 125°C
f = 0.1 Hz to 10 Hz
f = 10 Hz
100
0.05
dB
dB
dB
dB
dB
dB
dB
dB
40
35
48
0.8
72
62
83
1.4
20
nV/√Hz
nV/√Hz
nV/√Hz
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
µV p-p
fA/√Hz
10||5
115
2.95
GΩ||pF
dB
V
+3.2
kΩ||pF
V
28
−0.2
Rev. E | Page 5 of 24
AD8231
Parameter
Dynamic Performance
Bandwidth
G=1
G=2
Gain Bandwidth Product
G = 4 to 128
Slew Rate
Output Characteristics
Output Voltage High
Output Voltage Low
Short-Circuit Current
Digital Interface
Input Voltage Low
Input Voltage High
Setup Time to CS High
Hold Time after CS High
OPERATIONAL AMPLIFIERS
Input Characteristics
Offset Voltage, VOS
Temperature Drift
Input Bias Current
Data Sheet
Conditions
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 3 V
RL = 10 kΩ to 3 V
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
TA = −40°C to +125°C
Min
2.9
2.8
Typ
MHz
MHz
7
1.1
MHz
V/µs
2.94
2.88
60
80
40
V
V
mV
mV
mA
0.7
V
V
ns
ns
15
0.06
500
5
100
0.5
2.95
120
120
110
27
0.6
µV
µV/°C
pA
nA
pA
nA
V
V/mV
dB
dB
nV/√Hz
µV p-p
1
0.5
MHz
V/µs
2.96
2.82
60
80
40
V
V
mV
mV
mA
5
0.01
250
Input Offset Current
20
TA = −40°C to +125°C
Output Voltage Low
0.05
100
100
100
f = 0.1 Hz to 10 Hz
RL = 100 kΩ to ground
RL = 10 kΩ to ground
RL = 100 kΩ to 3 V
RL = 10 kΩ to 3 V
Short-Circuit Current
BOTH AMPLIFIERS
Power Supply
Quiescent Current
Quiescent Current (Shutdown)
2.9
2.8
3.5
0.01
Rev. E | Page 6 of 24
100
200
2.3
60
20
TA = −40°C to +125°C
Unit
2.7
2.5
TA = −40°C to +125°C
Input Voltage Range
Open-Loop Gain
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Voltage Noise Density
Voltage Noise
Dynamic Performance
Gain Bandwidth Product
Slew Rate
Output Characteristics
Output Voltage High
Max
100
200
4.5
1
mA
µA
Data Sheet
AD8231
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
Supply Voltage
Output Short-Circuit Current
Input Voltage (Common-Mode)
Differential Input Voltage
Storage Temperature Range
Operational Temperature Range
Package Glass Transition Temperature
ESD (Human Body Model)
ESD (Charged Device Model)
ESD (Machine Model)
Rating
6V
Indefinite1
−VS − 0.3 V to +VS + 0.3 V
−VS − 0.3 V to +VS + 0.3 V
–65°C to +150°C
–40°C to +125°C
130°C
1.5 kV
1.5 kV
0.2 kV
For junction temperatures between 105°C and 130°C, short-circuit operation
beyond 1000 hours can impact part reliability.
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 5.
Thermal Pad
Soldered to Board
Not Soldered to Board
θJA
54
96
Unit
°C/W
°C/W
The θJA values in Table 5 assume a 4-layer JEDEC standard
board. If the thermal pad is soldered to the board, it is also
assumed it is connected to a plane. θJC at the exposed pad
is 6.3°C/W.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the AD8231 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 130°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a temperature of 130°C for an
extended period can result in a loss of functionality.
ESD CAUTION
Rev. E | Page 7 of 24
AD8231
Data Sheet
13 CS
14
16 A2
15 A1
PIN 1
INDICATOR
A0
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC 1
11 –VS
10 OUTA (IN-AMP OUT)
9
REF
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD CAN BE CONNECTED TO THE NEGATIVE
SUPPLY (–VS) OR LEFT FLOATING.
06586-002
(OP AMP OUT) OUTB 8
TOP VIEW
(Not to Scale)
SDN 5
NC 4
–INB 7
(IN-AMP +IN) +INA 3
12 +VS
AD8231
+INB 6
(IN-AMP –IN) –INA 2
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
Mnemonic
NC
−INA (IN-AMP −IN)
+INA (IN-AMP +IN)
NC
SDN
+INB
−INB
OUTB (OP AMP OUT)
REF
10
11
12
13
14
15
16
OUTA (IN-AMP OUT)
−VS
+VS
CS
A0
A1
A2
EPAD
Description
No Connect.
Instrumentation Amplifier Negative Input.
Instrumentation Amplifier Positive Input.
No Connect.
Shutdown.
Operational Amplifier Positive Input.
Operational Amplifier Negative Input.
Operational Amplifier Output.
Instrumentation Amplifier Reference Pin. It should be driven with a low impedance. Output is
referred to this pin.
Instrumentation Amplifier Output.
Negative Power Supply. Connect to ground in single-supply applications.
Positive Power Supply.
Chip Select. Enables digital logic interface.
Gain Setting Bit (LSB).
Gain Setting Bit.
Gain Setting Bit (MSB).
Exposed Pad. Can be connected to the negative supply (−VS) or left floating.
Rev. E | Page 8 of 24
Data Sheet
AD8231
TYPICAL PERFORMANCE CHARACTERISTICS
INSTRUMENTATION AMPLIFIER PERFORMANCE CURVES
1000
1400
N: 5956
MEAN: –48.0779
1200 SD: 21.0433
N: 5956
MEAN: 0.977167
SD: 11.8177
800
1000
HITS
HITS
600
400
800
600
400
200
–40
–20
0
20
40
80
60
100
CMRR (µV/V)
0
–500 –400 –300 –200 –100
Figure 3. Instrumentation Amplifier CMR Distribution, G = 1
9
N: 5956
MEAN: 2.06788
700 SD: 1.07546
8
NUMBER OF AMPLIFIERS
600
400
300
200
100
300
400
500
N: 40
MEAN: –8.31
SD: 6
7
6
5
4
3
2
1
–5
0
5
10
15
0
06586-101
–10
VOSI (µV)
–50
–40
–30
–20
–10
0
10
20
30
40
50
INPUT OFFSET DRIFT (nV/°C)
Figure 7. Instrumentation Amplifier Input Offset Voltage Drift,
−40°C to +125°C
Figure 4. Instrumentation Amplifier Input Offset Voltage Distribution
16
800
N: 40
MEAN: –0.003
14 SD: 0.061
600
12
NUMBER OF AMPLIFIERS
N: 5956
MEAN: 10.3901
700 SD: 3.9553
500
HITS
200
06586-104
HITS
500
400
300
200
10
8
6
4
2
100
–20
–10
0
VOSO (µV)
10
20
30
0
–0.5
06586-102
0
–30
100
Figure 6. Instrumentation Amplifier Gain Distribution, G = 1
800
0
–15
0
GAIN ERROR (µV/V)
06586-103
–60
Figure 5. Instrumentation Amplifier Output Offset Voltage Distribution
–0.4 –0.3 –0.2 –0.1
0
0.1
0.2
OUTPUT OFFSET DRIFT (µV/°C)
0.3
0.4
0.5
06586-105
–80
06586-100
0
–100
200
Figure 8. Instrumentation Amplifier Output Offset Drift, −40°C to +125°C
Rev. E | Page 9 of 24
AD8231
6
VREF = MIDSUPPLY
VCM = MIDSUPPLY
0V, 4.96V
1000
500
3V
0
5
4
5V SINGLE SUPPLY
0V, 2.96V
2
3V SINGLE SUPPLY
1
0
20
40
60
80
100
120
TEMPERATURE (°C)
0
06586-106
–20
Figure 9. Instrumentation Amplifier Bias Current vs. Temperature
0
2
3
4
5
6
Figure 12. Instrumentation Amplifier Input Common-Mode Range vs.
Output Voltage, All Gains, VREF = 0 V
6
INPUT COMMON-MODE VOLTAGE (V)
1.5
1.0
0.5
0
–0.5
–1.0
+VS = +2.5V
–VS = –2.5V
VREF = 0V
–2.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
VCM (V)
4 0.02V, 4.22V
5V SINGLE SUPPLY
1.5V, 2.96V
3
2 0.02V, 2.22V
4.98V, 3.22V
2.98V, 2.22V
4.98V, 1.78V
3V SINGLE SUPPLY
1
2.98V, 0.78V
0.02V, 0.78V
1.5V, 0.04V
0
0
06586-006
–1.5
1.5V, 4.96V
5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
06586-004
BIAS CURRENT (nA)
1
OUTPUT VOLTAGE (V)
2.0
Figure 13. Instrumentation Amplifier Input Common-Mode Range vs.
Output Voltage, All Gains, VREF = 1.5 V
Figure 10. Instrumentation Amplifier Bias Current vs.
Common-Mode Voltage, 5 V
6
1.0
INPUT COMMON-MODE VOLTAGE (V)
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
+VS = +1.5V
–VS = –1.5V
VREF = 0V
–0.8
–1.0
–1.5
–1.2
–0.9
–0.6
–0.3
0
0.3
0.6
0.9
1.2
VCM (V)
Figure 11. Instrumentation Amplifier Bias Current vs.
Common-Mode Voltage, 3 V
1.5
2.5V, 4.96V
5
5V SINGLE SUPPLY
4
4.98V, 3.72V
0.02V, 3.72V
3
2.5V, 2.96V
2.98V, 2.72V
2
0.02V, 1.72V
3V SINGLE
SUPPLY
0.02V, 1.28V
2.5V, 0.04V
4.98V,1.28V
1
2.98V, 0.28V
0
0
06586-007
BIAS CURRENT (nA)
2.92V, 1.5V
0V, 0.04V
5V
–500
–40
4.92V, 2.5V
3
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (V)
4.0
4.5
5.0
06586-005
BIAS CURRENT (pA)
1500
06586-003
INPUT COMMON-MODE VOLTAGE (V)
2000
Data Sheet
Figure 14. Instrumentation Amplifier Input Common-Mode Range vs.
Output Voltage, All Gains, VREF = 2.5 V
Rev. E | Page 10 of 24
Data Sheet
AD8231
50
40
G = 64
10
G = 16
=1
=1
=8
=8
= 128
= 128
G=8
20
CMRR (µV/V)
G=4
10
G=2
G=1
0
–10
5
0
–5
–15
–40
100
REPRESENTATIVE SAMPLES
–20
–40
–20
0
20
40
1k
10k
100k
1M
10M
FREQUENCY (Hz)
06586-009
–30
Figure 15. Instrumentation Amplifier Gain vs. Frequency
G
G
G
G
G
G
G
G
800
600
400
80
100
120
Figure 18. Instrumentation Amplifier CMRR vs. Temperature
140
=1
=2
=4
=8
= 16
= 32
= 64
= 128
G = 128
120
G=8
POSITIVE PSRR (dB)
1000
60
TEMPERATURE (°C)
06586-118
–10
–20
GAIN DRIFT (ppm)
G
G
G
G
G
G
15
G = 32
30
GAIN (dB)
20
G = 128
200
0
–200
–400
100
G=1
80
60
40
–600
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
0
06586-116
–1000
–40
1
10
100
Figure 16. Instrumentation Amplifier Gain Drift vs. Temperature
10k
100k
Figure 19. Instrumentation Amplifier Positive PSRR vs. Frequency
140
140
G = 128
G = 128
120
120
NEGATIVE PSRR (dB)
G=8
G=8
100
G=1
80
100
80
G=1
60
40
60
40
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 17. Instrumentation Amplifier CMRR vs. Frequency
0
1
10
100
1k
100k
100k
FREQUENCY (Hz)
Figure 20. Instrumentation Amplifier Negative PSRR vs. Frequency
Rev. E | Page 11 of 24
06586-147
20
06586-010
CMRR (dB)
1k
FREQUENCY (Hz)
06586-146
20
–800
AD8231
Data Sheet
G = +128, 0.4µV/DIV
1s/DIV
06586-012
G = +1, 1µV/DIV
10
1
0.1
0.01
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 21. Instrumentation Amplifier 0.1 Hz to 10 Hz Noise
100
06586-107
CURRENT NOISE (pA/ Hz)
100
Figure 24. Instrumentation Amplifier Current Noise Spectral Density
G = +1
G = +8
G = +128
90
80
NOISE (nV/ Hz)
70
60
50
40
30
10
20mV/DIV
10
1
100
1k
FREQUENCY (Hz)
Figure 22. Instrumentation Amplifier Voltage Noise Spectral Density vs.
Frequency, 5 V, 1 Hz to 1000 Hz
1000
Figure 25. Instrumentation Amplifier Small Signal Pulse Response, G = 1,
RL = 2 kΩ, CL = 500 pF
G = +1
G = +8
G = +128
900
5µs/DIV
06586-011
0
06586-013
20
300pF
NO
LOAD
500pF
800pF
800
NOISE (nV/ Hz)
700
600
500
400
300
100
20mV/DIV
1
10
100
1k
FREQUENCY (Hz)
10k
100k
4µs/DIV
06586-008
0
06586-014
200
Figure 23. Instrumentation Amplifier Voltage Noise Spectral Density vs.
Frequency, 5 V, 1 Hz to 1 MHz
Figure 26. Instrumentation Amplifier Small Signal Pulse Response for Various
Capacitive Loads, G = 1
Rev. E | Page 12 of 24
Data Sheet
AD8231
G = +8
G = +32
G = +128
2V/DIV
10µs/DIV
0.001%/DIV
Figure 27. Instrumentation Amplifier Small Signal Pulse Response, G = 4, 16,
and 128, RL = 2 kΩ, CL = 500 pF
100µs/DIV
06586-018
20mV/DIV
06586-015
17.6µs TO 0.01%
21.4µs TO 0.001%
Figure 30. Instrumentation Amplifier Large Signal Pulse Response,
G = 128, VS = 5 V
25
SETTLING TIME (µs)
20
2V/DIV
3.95µs TO 0.01%
4µs TO 0.001%
0.001%
15
0.01%
10
0
1
10
100
1k
06586-019
10µs/DIV
1k
06586-020
0.001%/DIV
06586-016
5
GAIN (V/V)
Figure 28. Instrumentation Amplifier Large Signal Pulse Response,
G = 1, VS = 5 V
Figure 31. Instrumentation Amplifier Settling Time vs.
Gain for a 4 V p-p Step, VS = 5 V
25
0.001%
20
SETTLING TIME (µs)
2V/DIV
3.75µs TO 0.01%
3.8µs TO 0.001%
15
0.01%
10
0.001%/DIV
10µs/DIV
06586-017
5
0
1
10
100
GAIN (V/V)
Figure 29. Instrumentation Amplifier Large Signal Pulse Response,
G = 8, VS = 5 V
Figure 32. Instrumentation Amplifier Settling Time vs.
Gain for a 2 V p-p Step, VS = 3 V
Rev. E | Page 13 of 24
AD8231
Data Sheet
+VS
–0.4
–0.6
–0.8
–1.0
1.0
0.8
0.6
0.4
0.2
–0.4
–0.6
–0.8
–1.0
1.0
0.8
0.6
0.4
1
10
100
OUTPUT CURRENT (mA)
Figure 33. Instrumentation Amplifier Output Voltage Swing vs.
Output Current, VS = 3 V
–VS
0.1
1
10
100
OUTPUT CURRENT (mA)
Figure 34. Instrumentation Amplifier Output Voltage Swing vs.
Output Current, VS = 5 V
Rev. E | Page 14 of 24
06586-134
0.2
06586-133
–VS
0.1
–40°C
+25°C
+85°C
+125°C
–0.2
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
–0.2
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
+VS
–40°C
+25°C
+85°C
+125°C
Data Sheet
AD8231
–100
60
–110
40
–120
76° PHASE
MARGIN
20
–130
0
–140
RL = 10kΩ
CL = 200pF
100
1k
10k
100k
1M
800pF
1nF
1.5nF
20mV/DIV
–150
10M
FREQUENCY (Hz)
60
–110
40
–120
72° PHASE
MARGIN
20
–130
0
–140
RL = 10kΩ
CL = 200pF
–20
10
100
1k
10k
100k
1M
–150
10M
FREQUENCY (Hz)
Figure 36. Operational Amplifier Open-Loop Gain and Phase vs.
Frequency, VS = 3 V
800pF
1nF
OUTPUT VOLTAGE (0.5V/DIV)
–100
OPEN-LOOP PHASE SHIFT (Degrees)
80
1nF║2kΩ
1.5nF║2kΩ
TIME (5µs/DIV)
Figure 39. Operational Amplifier Large Signal Transient Response, VS = 5 V
NO
LOAD
2nF
OUTPUT VOLTAGE (0.5V/DIV)
NO
LOAD
1.5nF
20mV/DIV
NO
LOAD
06586-022
–90
Figure 38. Operational Amplifier Small Signal Response for
Various Capacitive Loads, VS = 3 V
5µs/DIV
1nF║2kΩ
1.5nF║2kΩ
06586-023
OPEN-LOOP GAIN (dB)
Figure 35. Operational Amplifier Open-Loop Gain and Phase vs.
Frequency, VS = 5 V
100
5µs/DIV
TIME (5µs/DIV)
Figure 37. Operational Amplifier Small Signal Response for
Various Capacitive Loads, VS = 5 V
06586-026
–20
10
300pF
06586-024
80
NO
LOAD
06586-025
–90
OPEN-LOOP PHASE SHIFT (Degrees)
100
06586-021
OPEN-LOOP GAIN (dB)
OPERATIONAL AMPLIFIER PERFORMANCE CURVES
Figure 40. Operational Amplifier Large Signal Transient Response, VS = 3 V
Rev. E | Page 15 of 24
Data Sheet
1000
+VS
900
–0.2
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
800
700
600
500
400
300
200
100
–0.8
–1.0
1.0
0.8
0.6
0.4
100
100k
10k
1k
–0.2
OUTPUT VOLTAGE SWING (V)
REFERRED TO SUPPLY VOLTAGES
+VS
2.0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0
–0.2
–40
3V
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–0.4
–0.6
–0.8
–1.0
1.0
0.8
0.6
0.4
1
10
100
OUTPUT CURRENT (mA)
Figure 45. Operational Amplifier Output Voltage Swing vs.
Output Current, VS = 5 V
400
140
300
120
+PSRR
200
100
PSRR (dB)
100
VS = ±2.5V
–100
VS = ±1.5V
–200
80
–PSRR
60
40
20
–2
–1
0
1
2
3
VCM (V)
06586-109
–300
–400
–3
–40°C
+25°C
+85°C
+125°C
–VS
0.1
Figure 42. Operational Amplifier Bias Current vs. Temperature
0
100
0.2
5V
06586-108
0.2
10
Figure 44. Operational Amplifier Output Voltage Swing vs.
Output Current, VS = 3 V
2.2
1.8
1
OUTPUT CURRENT (mA)
06586-144
10
06586-145
1
Figure 41. Operational Amplifier Voltage Spectral Noise Density vs. Frequency
BIAS CURRENT (nA)
–0.6
0.2
FREQUENCY (Hz)
BIAS CURRENT (pA)
–0.4
–VS
0.1
06586-141
0
–40°C
+25°C
+85°C
+125°C
0
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 46. Operational Amplifier Power Supply Rejection Ratio
Figure 43. Operational Amplifier Bias Current vs. Common Mode
Rev. E | Page 16 of 24
06586-148
SPECTRAL NOISE DENSITY (nV/ Hz)
AD8231
Data Sheet
AD8231
PERFORMANCE CURVES VALID FOR BOTH AMPLIFIERS
7
160
+125°C
6
CHANNEL SEPARATION (dB)
–40°C
3
2
1
G=1
100
80
60
40
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VSUPPLY (V)
5.9
Figure 47. Supply Current vs. Supply Voltage
0
10
SOURCE CHANNEL: OP AMP AT G = 1
100
1k
10k
FREQUENCY (Hz)
Figure 48. Channel Separation vs. Frequency
Rev. E | Page 17 of 24
100k
06586-149
0
2.7
120
20
06586-028
ISUPPLY (mA)
+25°C
4
G = 128
140
+85°C
5
G=8
AD8231
Data Sheet
THEORY OF OPERATION
CS
A0
A1
A2
SDN
OUTB
–INA
14kΩ
A1
14kΩ
–INB
A4
+INB
OUTA
A3
14kΩ
AD8231
+VS
–VS
06586-031
+INA
14kΩ
A2
REF
Figure 49. Simplified Schematic
AMPLIFIER ARCHITECTURE
Table 7. Truth Table for AD8231 Gain Settings
The AD8231 is based on the classic 3-op amp topology. This
topology has two stages: a preamplifier to provide amplification,
followed by a difference amplifier to remove the common-mode
voltage. Figure 49 shows a simplified schematic of the AD8231.
The preamp stage is composed of Amplifier A1, Amplifier A2,
and a digitally controlled resistor network. The second stage is a
gain of 1 difference amplifier composed of Amplifier A3 and
four 14 kΩ resistors. A1, A2, and A3 are all zero drift, rail-torail input, rail-to rail-output amplifiers.
CS
The AD8231 also includes a free operational amplifier. Like
the other amplifiers in the AD8231, it is a zero drift, rail-to-rail
input, rail-to-rail output architecture.
GAIN SELECTION
The gain of the AD8231 is set by voltages applied to the A0, A1,
and A2 pins. To change the gain, the CS pin must be driven
low. When the CS pin is driven high, the gain is latched, and
voltages at the A0 to A2 pins have no effect. Because the CS pin
is level sensitive rather than edge sensitive, it can also be tied
permanently low. Table 7 shows the different gain settings.
A2
Low
Low
Low
Low
High
High
High
High
X
A1
Low
Low
High
High
Low
Low
High
High
X
A0
Low
High
Low
High
Low
High
Low
High
X
Gain
1
2
4
8
16
32
64
128
No change
REFERENCE TERMINAL
The output voltage of the AD8231 is developed with respect to
the potential on the reference terminal, which is useful when
the output signal needs to be offset to a midsupply level. For
example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8231 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or −VS by more than 0.3 V.
For best performance, source impedance to the REF terminal
should be kept below 1 Ω. As shown in Figure 49, the reference
terminal, REF, is at one end of a 14 kΩ resistor. Additional
impedance at the REF terminal adds to this 14 kΩ resistor
and results in amplification of the signal connected to the
positive input, causing a CMRR error.
The time required for a gain change is dominated by the settling
time of the amplifier. The AD8231 takes about 200 ns to switch
gains, after which the amplifier begins to settle. Refer to Figure 28
through Figure 32 to determine the settling time for different gains.
CORRECT
INCORRECT
VREF
+
+
AD8231
AD8231
IN-AMP
–
REF
IN-AMP
–
REF
VREF
+
AD8231
OP AMP
–
Figure 50. Driving the Reference (REF)
Rev. E | Page 18 of 24
06586-032
The AD8231 design makes it extremely robust over temperature.
The AD8231 uses an internal thin film resistor to set the gain.
Because all of the resistors are on the same die, gain temperature
drift performance and CMRR drift performance are better than
can be achieved with topologies using external resistors. The
AD8231 also uses an auto-zero topology to null the offsets of all its
internal amplifiers. Because this topology continually corrects for
any offset errors, offset temperature drift is nearly nonexistent.
Low
Low
Low
Low
Low
Low
Low
Low
High
Data Sheet
AD8231
INCORRECT
LAYOUT
CORRECT
+VS
The AD8231 is a high precision device. To ensure optimum
performance at the PCB level, care must be taken in the design
of the board layout. The AD8231 pinout is arranged in a logical
manner to aid in this task.
+VS
AD8231
AD8231
REF
Power Supplies
The AD8231 should be decoupled with a 0.1 µF bypass capacitor
between the two supplies. This capacitor should be placed as close
as possible to Pin 11 and Pin 12, either directly next to the pins or
beneath the pins on the backside of the board. The auto-zero
architecture of the AD8231 requires a low ac impedance between
the supplies. Long trace lengths to the bypass capacitor increase
this impedance, which results in a larger input offset voltage.
REF
–VS
–VS
TRANSFORMER
TRANSFORMER
+VS
+VS
AD8231
A stable dc voltage should be used to power the instrumentation
amplifier. Noise on the supply pins can adversely affect
performance.
AD8231
REF
REF
10MΩ
Package Considerations
–VS
The AD8231 comes in a 4 mm × 4 mm LFCSP. Beware of
blindly copying the footprint from another 4 mm × 4 mm
LFCSP part; it cannot have the same thermal pad size and leads.
Refer to the Outline Dimensions section to verify that
the PCB symbol has the correct dimensions. Space between
the leads and thermal pad should be kept as wide as possible
for the best bias current performance.
–VS
THERMOCOUPLE
THERMOCOUPLE
+VS
+VS
C
C
C
1
fHIGH-PASS = 2πRC
AD8231
REF
R
C
AD8231
REF
–VS
–VS
06586-033
R
Thermal Pad
The AD8231 4 mm × 4 mm LFCSP comes with a thermal pad.
This pad is connected internally to −VS. The pad can either be
left unconnected or connected to the negative supply rail. For
high vibration applications, a landing is recommended.
INPUT PROTECTION
Because the AD8231 dissipates little power, heat dissipation
is rarely an issue. If improved heat dissipation is desired (for
example, when ambient temperatures are near 125°C or when
driving heavy loads), connect the thermal pad to the negative
supply rail. For the best heat dissipation performance, the
negative supply rail should be a plane in the board. See the
Thermal Resistance section for thermal coefficients with and
without the pad soldered.
All terminals of the AD8231 are protected against ESD. In
addition, the input structure allows for dc overload conditions
a diode drop above the positive supply and a diode drop below
the negative supply. Voltages beyond these limits cause the ESD
diodes to conduct and current to flow. If overvoltage events are
anticipated, an external resistor should be used in series with
each of the inputs to limit the current to below 10 mA. Currents
up to 100 mA can be sustained for a few seconds.
INPUT BIAS CURRENT RETURN PATH
Note that if either input is brought below the negative supply
to the point where the ESD diode turns on, the AD8231 output
can phase-reverse.
The input bias current of the AD8231 must have a return path
to common. When the source, such as a thermocouple, cannot
provide a return current path, one should be created, as shown
in Figure 51.
CAPACITIVELY COUPLED
CAPACITIVELY COUPLED
Figure 51. Creating an IBIAS Path
Rev. E | Page 19 of 24
AD8231
Data Sheet
RF INTERFERENCE
RF rectification is often a problem when amplifiers are used in
applications where there are strong RF signals. The disturbance
can appear as a small dc offset voltage. High frequency signals
can be filtered with a low-pass, RC network placed at the
input of the instrumentation amplifier, as shown in Figure 52.
The filter limits the input signal bandwidth according to the
following relationship
FilterFreqDiff
1
2 R(2CD CC )
FilterFreqCM
1
2 RCC
Because the AD8231 has no 1/f noise, reducing the bandwidth
corresponds directly to less noise. Table 8 shows the AD8231
performance at a gain of 1 at different bandwidths, assuming a
2-pole Butterworth filter roll off.
Bandwidth
(Hz)
1
3.2
10
32
100
320
1k
3.2 k
10 k
32 k
+VS
0.1µF
10µF
CC
1nF
+INA
4.02kΩ
CD
10nF
VOUT
AD8231
R
REF
–INA
4.02kΩ
REDUCING NOISE
Table 8. AD8231 noise at various bandwidths
where CD ≥ 10CC.
R
If more common-mode range is required, the simplest solution is
to apply less gain in the instrumentation amplifier. The extra op
amp can be used to provide another gain stage after the in-amp.
Because the AD8231 has good offset and noise performance at low
gains, applying less gain in the instrumentation amplifier generally
has a limited impact on the overall system performance.
CC
1nF
0.1µF
06586-034
10µF
–VS
Figure 52 shows an example where the differential filter frequency
is approximately 2 kHz, and the common-mode filter frequency
is approximately 40 kHz.
Values of R and CC should be chosen to minimize RFI. Mismatch
between the R × CC at the positive input and the R × CC at the
negative input degrades the CMRR of the AD8231. By using a
value of CD that is ten times larger than the value of CC, the
effect of the mismatch is reduced and performance is improved.
The AD8231 has two clocks: an auto-zero clock at 3.4 kHz and
a commutating clock at 54 kHz. While the auto-zero clock has
negligible energy and can generally be ignored, the commutating
clock has enough energy to significantly affect the noise of the
part. Therefore, in applications where low noise is critical, limiting
the bandwidth of the system below 54 kHz is recommended.
The 3-op amp architecture of the AD8231 applies gain and then
removes the common-mode voltage. Therefore, internal nodes
in the AD8231 experience a combination of both the gained
signal and the common-mode signal. This combined signal can
be limited by the voltage supplies even when the individual input
and output signals are not. To determine whether the signal could
be limited, refer to Figure 12 through Figure 14 or use the
following formula
2
SNR Differential
Output2
dB
Bits
154.3
25.3
149.2
24.5
144.3
23.7
139.2
22.8
137.63
22.0
129.2
21.2
124.3
20.3
119.2
19.5
117.3
18.7
109.2
17.9
SNR for single-ended output configuration calculated with output signal of
4.8 V p-p, which corresponds to 1.697 V rms.
2
SNR for differential output configuration calculated with output signal of
9.6 V p-p, which corresponds to 3.397 V rms.
COMMON-MODE INPUT VOLTAGE RANGE
VDIFF Gain
SNR
Single-Ended1
dB
Bits
148.3
24.3
143.2
23.5
138.3
22.7
133.2
21.8
128.3
21.0
123.2
20.2
118.3
19.3
113.2
18.5
108.3
17.7
103.2
16.9
1
Figure 52. RFI Suppression
VS 0.04 V VCM
Noise
(μV rms)
0.07
0.12
0.21
0.37
0.66
1.17
2.07
3.71
6.55
11.73
VS 0.04 V
Rev. E | Page 20 of 24
Data Sheet
AD8231
APPLICATIONS INFORMATION
DIFFERENTIAL OUTPUT
Figure 53 shows how to create a differential output in-amp
using the AD8231 uncommitted op amp. Because this
configuration makes use of the reference terminal of the
in-amp, errors from the op amp and resistor mismatch result in
common-mode errors, rather than differential errors. Because
common-mode errors are typically rejected by the next device
in the signal chain, this circuit configuration adds almost no
extra error.
3
IN-AMP
–IN
2
10
+OUT
REF
9
4.99kΩ
VREF
7
4.99kΩ
6
+
–
OP AMP
8
–OUT
06586-035
+IN
Figure 53. Differential Output Using Operational Amplifier
MULTIPLEXING
The outputs of both the AD8231 in-amp and op amp are high
impedance in the shutdown state. This feature allows several
AD8231s to be multiplexed together without any external
switches. Figure 54 shows an example of such a configuration.
All the outputs are connected together and only one amplifier is
turned on at a time. This feature is analogous to the high-Z
mode of the digital tristate logic.
The resistors in the AD8231 instrumentation amplifier create a
resistive path from the output to the reference pin of about
100 kΩ. If a higher output impedance in shutdown mode is
desired, the reference pin can be driven with the op amp of
the AD8231. In this configuration, the output impedance in
shutdown is several GΩ, and many thousand AD8231s can
theoretically be multiplexed in such a way.
The AD8231 can enter and leave shutdown mode very quickly.
However, when the amplifier wakes up and reconnects its input
circuitry, the voltage at its internal input nodes changes dramatically. It takes time for the output of the amplifier to settle. Refer
to Figure 28 through Figure 32 to determine the settling time
for different gains. This settling time limits how quickly the
AD8231 can be multiplexed with the SDN pin.
USING THE AD8231 WITH BIPOLAR SUPPLIES
SDN0
The AD8231 can be used with bipolar supplies as long as the
maximum voltage drop between the supply rails is kept below
6 V and all input voltages are kept within the supply rails.
With bipolar supplies, the acceptable levels for the digital inputs
A0, A1, A2, CS, and SDN shift. Table 9 shows acceptable values
for low and high signals for both single and dual supplies.
SDN1
Table 9. Digital Pin Thresholds
SDN2
06586-036
SDN3
Supply Voltage (V)
0 to 5
0 to 3
−2.5 to +2.5
−1.5 to +1.5
Figure 54. Four AD8231s in Multiplexing Configuration
Rev. E | Page 21 of 24
Low
Min (V) Max (V)
0
+1
0
+0.8
−2.5
−1.5
−1.5
−0.7
High
Min (V) Max (V)
4
5
2.2
3
1.5
2.5
0.7
1.5
AD8231
Data Sheet
When operating the AD8231 on dual supplies, a level-shift is
typically needed from standard single-supply control logic. One
easy way to accomplish the level-shift is through a single-pole,
double-throw switch, such as the ADG633. Figure 55 shows an
application schematic for ±2.5 V operation.
VDIGITAL
VDD
+2.5V
Note that in addition to setting the peaking of the filter, the
ratio R3/R4 also sets the dc gain: G = 1 + R3/R4. If lower dc
gain is required, replace R1 with a voltage divider, where the
output resistance of the divider is equal to the required value of R1.
Figure 56 shows a bias point connected to R4 and the in-amp
reference. The filter stage amplifies the signal around this bias
point. The bias point is typically midsupply and should be low
impedance.
Table 10. Recommended Component Values for Butterworth
Low-Pass Filter in Figure 56
+2.5V
–2.5V
+2.5V
VDIGITAL
–2.5V
VDD
A0
DIGITAL
CONTROL
A1
(FPGA,
MICROCONTROLLER,
ETC.)
EN
GND
A0 A1 A2
+VS
A2
ADG633
VSS GND
+2.5V
SDN
–VS
–2.5V
CS
AD8231
3 dB
Freq
32 Hz
100 Hz
320 Hz
1 kHz
3.2 kHz
10 kHz
32 kHz
Sallen Key
R1, R2 C1, C2
(kΩ)
(nF)
499
10
158
10
49.9
10
158
1
49.9
1
15.8
1
4.99
1
OPTIONAL POLE
06586-055
–2.5V
VDIGITAL IS THE DIGITAL SUPPLY VOLTAGE. IT CAN BE
ANY VOLTAGE BETWEEN 2.5V AND 9.5V.
SALLEN KEY
(TWO POLE)
R6
Figure 55. Converting Single-Supply Control Signals to Dual Supply.
R7
C4
IN-AMP
REF
SALLEN KEY FILTER
BIAS
POINT
The extra op amp in the AD8231 can be used to create a 2-pole
Sallen Key filter. Such a filter can remove excess noise or
perform antialiasing before an analog-to-digital converter.
Figure 56 shows how to create a 2-pole low-pass Butterworth
filter. Components R1, R2, C1, and C2 set the frequency of the
filter. The ratio of R3 and R4 sets the peaking of the filter. If R4
equals 10 kΩ, R3 should equal 5.9 kΩ for an optimum 2-pole
response.
Optional Poles
Before In-Amp
After Op Amp
R6, R7
C4
R5
C3
(kΩ)
(nF)
(kΩ)
(nF)
499
4.7
49.9
100
158
4.7
16
100
49.9
4.7
4.99
100
158
0.47
1.6
100
49.9
0.47
0.499
100
15.8
0.47
0.16
100
4.99
0.47
0.049
100
R1
R2
C2
OPTIONAL POLE
C1
R5
OP AMP
R3
C3
R4
BIAS
POINT
06586-056
–2.5V
Figure 56. Butterworth Low-Pass Filter (Dotted Sections Indicate Optional Poles)
Depending on the circuitry before and after the AD8231,
a 3-pole filter can be possible. If the previous stage has a small
output impedance, an additional pole can be added before the
in amp (R6, R7, and C4). If the following stage has a high input
impedance, an additional pole can be added after the op amp
(R5 and C3). Peaking from the Sallen Key stage should be
higher to compensate for the extra attenuation of the third pole;
both R3 and R4 should be 10 kΩ for optimum response.
Rev. E | Page 22 of 24
Data Sheet
AD8231
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.65
BSC
13
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
16
1
12
2.25
2.10 SQ
1.95
EXPOSED
PAD
9
TOP VIEW
PKG-004025/5112
0.80
0.75
0.70
SIDE VIEW
SEATING
PLANE
0.70
0.60
0.50
4
5
8
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
10-11-2017-B
PIN 1
INDICATOR
0.35
0.30
0.25
Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75mm Package Height
(CP-16-23)
Dimensions shown in millimeters
ORDERING GUIDE
Model1,2
AD8231ACPZ-R7
AD8231ACPZ-RL
AD8231ACPZ-WP
AD8231WACPZ-RL
AD8231-EVALZ
1
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead LFCSP, 7” Tape and Reel
16-Lead LFCSP, 13” Tape and Reel
16-Lead LFCSP, Waffle Pack
16-Lead LFCSP, 13” Tape and Reel
Evaluation Board
Package Option
CP-16-23
CP-16-23
CP-16-23
CP-16-23
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD8231W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices, Inc. account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
Rev. E | Page 23 of 24
AD8231
Data Sheet
NOTES
©2007–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06586-0-10/17(E)
Rev. E | Page 24 of 24
工商网监
湘ICP备2023018690号
