AD8305ACPZ-R2

100 dB Range (10 nA to 1 mA) Logarithmic Converter AD8305 Data Sheet FUNCTIONAL BLOCK DIAGRAM Optimized for fiber optic photodiode interfacing Measures current over 5 decades Law conformance 0.1 dB from 10 nA to 1 mA Single- or dual-supply operation (3 V to 12 V total) Full log-ratio capabilities Nominal slope of 10 mV/dB (200 mV/decade) Nominal intercept of 1 nA (set by external resistor) Optional adjustment of slope and intercept Complete and temperature stable Rapid response time for a given current level Miniature 16-lead chip scale package (LFCSP 3 mm × 3 mm) Low power: ~5 mA quiescent current VP 0.20 log10 VPOS VRDZ VOUT 80kΩ VREF 200kΩ 2.5V 20kΩ 0.5V BIAS GENERATOR COMM SCAL IREF VBE2 VBIAS Q2 Q1 IPD – + 14.2kΩ TEMPERATURE COMPENSATION VBE1 INPT VSUM IPD 1nA ILOG BFIN 451Ω VLOG 6.69kΩ COMM 0.5V COMM VNEG 03053-001 FEATURES Figure 1. APPLICATIONS Optical power measurement Wide range baseband logarithmic compression Measurement of current and voltage ratios Optical absorbance measurement GENERAL DESCRIPTION The AD83051 is an inexpensive microminiature logarithmic converter optimized for determining optical power in fiber optic systems. It uses an advanced implementation of a classic translinear (junction based) technique to provide a large dynamic range in a versatile and easily used form. A single-supply voltage of between 3 V and 12 V is adequate; dual supplies may optionally be used. The low quiescent current (typically 5 mA) permits use in battery-operated applications. The input current, IPD, of 10 nA to 1 mA applied to the INPT pin is the collector current of an optimally scaled NPN transistor, which converts this current to a voltage (VBE) with a precise logarithmic relationship. A second such converter is used to handle the reference current (IREF) applied to pin IREF. These input nodes are biased slightly above ground (0.5 V). This is generally acceptable for photodiode applications where the anode does not need to be grounded. Similarly, this bias voltage is easily accounted for in generating IREF. The output of the logarithmic front end is available at Pin VLOG. The basic logarithmic slope at this output is nominally 200 mV/decade (10 mV/dB). Thus, a 100 dB range corresponds to an output change of 1 V. When this voltage (or the buffer output) is applied to an ADC that permits an external reference voltage to be employed, the AD8305 voltage reference output of 2.5 V at Pin VREF can be used to improve the scaling accuracy. Suitable ADCs include the AD7810 (serial 10-bit), AD7823 (serial 8-bit), and AD7813 (parallel, 8-bit or 10-bit). Other values of the logarithmic slope can be provided using a simple external resistor network. 1 The logarithmic intercept (also known as the reference current) is nominally positioned at 1 nA by the use of the externally generated current, IREF, of 10 µA, provided by a 200 kΩ resistor connected between VREF, at 2.5 V, and the reference input, IREF, at 0.5 V. The intercept can be adjusted over a wide range by varying this resistor. The AD8305 can also operate in a log ratio mode, with the numerator current applied to INPT and the denominator current applied to IREF. A buffer amplifier is provided for driving a substantial load, for use in raising the basic slope of 10 mV/dB to higher values, as a precision comparator (threshold detector), or in implementing low-pass filters. Its rail-to-rail output stage can swing to within 100 mV of the positive and negative supply rails, and its peak current sourcing capacity is 25 mA. It is a fundamental aspect of translinear logarithmic converters that the small signal bandwidth falls as the current level diminishes, and the low frequency noise-spectral density increases. At the 10 nA level, the bandwidth of the AD8305 is about 50 kHz and increases in proportion to IPD up to a maximum value of about 15 MHz. Using the buffer amplifier, the increase in noise level at low currents can be addressed by using it to realize low-pass filters of up to three poles. The AD8305 is available in a 16-lead LFCSP package and is specified for operation from −40°C to +85°C. Protected by U.S. Patent No. 5,519,308. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8305 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Managing Intercept and Slope .................................................. 12  Applications ....................................................................................... 1  Response Time and Noise Considerations ............................. 12  Functional Block Diagram .............................................................. 1  Power Supply Sequencing ......................................................... 12  General Description ......................................................................... 1  Applications Information .............................................................. 14  Revision History ............................................................................... 2  Calibration ....................................................................................... 15  Specifications..................................................................................... 3  Using a Negative Supply ................................................................ 16  Absolute Maximum Ratings............................................................ 4  Log-Ratio Applications .................................................................. 17  ESD Caution .................................................................................. 4  Reversing the Input Polarity ........................................................ 18  Pin Configuration and Function Descriptions ............................. 5  Characterization Methods ............................................................. 19  Typical Performance Characteristics ............................................. 6  Evaluation Board ............................................................................ 21  General Structure ........................................................................... 11  Outline Dimensions ....................................................................... 24  Theory .......................................................................................... 11  Ordering Guide .......................................................................... 24  REVISION HISTORY 9/2017—Rev. B to Rev. C Changed CP-16-2 to CP-16-27 .................................... Throughout Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 4/2010—Rev. A to Rev. B Updated Data Sheet ............................................................ Universal Change to Figure 2 and Table 3 ...................................................... 5 Added Power Supply Sequencing Section ................................... 12 Added Figure 34; Renumbered Sequentially .............................. 12 Changes to Ordering Guide .......................................................... 24 3/2003—Rev. 0 to Rev. A Changes to TPC 3 ............................................................................. 4 Changes to TPC 18 ........................................................................... 6 Changes to Figure 3 ........................................................................ 11 Changes to Figure 8 ........................................................................ 13 Updated Outline Dimensions ....................................................... 18 Rev. C | Page 2 of 24 Data Sheet AD8305 SPECIFICATIONS VP = 5 V, VN = 0 V, TA = 25°C, RREF = 200 kΩ, and VRDZ connected to VREF, unless otherwise noted. Table 1. Parameter INPUT INTERFACE Specified Current Range, IPD Input Current Min/Max Limits Reference Current, IREF, Range Summing Node Voltage Temperature Drift Input Offset Voltage LOGARITHMIC OUTPUT Logarithmic Slope Conditions Pin 4, INPT, Pin 3, IREF Flows toward INPT pin Flows toward INPT pin Flows toward IREF pin Internally preset; may be altered by the user −40°C < TA < +85°C VINPT − VSUM, VIREF − VSUM Pin 9, VLOG −40°C < TA < +85°C Logarithmic Intercept 1 Law Conformance Error Wideband Noise 2 Small Signal Bandwidth2 Maximum Output Voltage Minimum Output Voltage Output Resistance REFERENCE OUTPUT Voltage With Reference to Ground Maximum Output Current Incremental Output Resistance OUTPUT BUFFER Input Offset Voltage Input Bias Current Incremental Input Resistance Output Range Incremental Output Resistance Peak Source/Sink Current Small Signal Bandwidth Slew Rate POWER SUPPLY Positive Supply Voltage Quiescent Current Negative Supply Voltage (Optional) 1 2 −40°C < TA < +85°C 10 nA < IPD < 1 mA IPD > 1 µA IPD > 1 µA Min Typ Max 10 1 10 10 0.46 0.5 0.015 −20 190 185 0.3 0.1 Limited by VN = 0 V 4.375 1 0.54 +20 200 1 0.1 0.7 0.7 1.7 0.01 5 210 215 1.7 2.5 0.4 5.625 Unit nA mA mA nA mA V mV/°C mV mV/dec mV/dec nA nA dB mV√Hz MHz V V kΩ Pin 2, VREF −40°C < TA < +85°C Sourcing (grounded load) Load current < 10 mA Pin 10, BFIN; Pin 11, SCAL; Pin 12, VOUT 2.435 2.4 2.5 V V mA Ω +20 mV mA MΩ V Ω mA MHz V/µs 12 6.5 V mA V 20 2 −20 Flowing out of Pin 10 or Pin 11 0.4 35 VP − 0.1 0.5 25 15 15 RL = 1 kΩ to ground Load current < 10 mA GAIN = 1 0.2 V to 4.8 V output swing Pin 8, VPOS; Pin 6 and Pin 7, VNEG (VP − VN) ≤ 12 V 3 (VP − VN) ≤ 12 V −5.5 Other values of logarithmic intercept can be achieved by adjusting RREF. Output noise and incremental bandwidth are functions of input current, measured using output buffer connected for GAIN = 1. Rev. C | Page 3 of 24 2.565 2.6 5 5.4 0 AD8305 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VP − VN Input Current Internal Power Dissipation θJA1 Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) 1 Rating 12 V 20 mA 500 mW 30°C/W 125°C −40°C to +85°C −65°C to +150°C 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION With package die paddle soldered to thermal pad containing nine vias connected to inner and bottom layers. Rev. C | Page 4 of 24 Data Sheet AD8305 13 COMM 15 COMM 14 COMM 16 COMM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 12 VOUT VRDZ 1 VREF 2 AD8305 11 SCAL IREF 3 TOP VIEW (Not to Scale) 10 BFIN 9 VLOG NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO GROUND. 03053-002 VPOS 8 VNEG 7 VNEG 6 VSUM 5 INPT 4 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic VRDZ 2 3 4 VREF IREF INPT 5 6, 7 8 9 10 11 12 13 to 16 VSUM VNEG VPOS VLOG BFIN SCAL VOUT COMM EPAD Function Top of a Resistive Divider Network that Offsets VLOG to Position the Intercept. Normally connected to VREF; may also be connected to ground when bipolar outputs are to be provided. Reference Output Voltage of 2.5 V. Accepts (Sinks) Reference Current, IREF. Accepts (Sinks) Photodiode Current, IPD. Usually connected to photodiode anode such that photo current flows into INPT. Guard Pin. Used to shield the INPT current line and for optional adjustment of the INPT and IREF node potential. Optional Negative Supply, VN (this pin is usually grounded; for details of usage, see the Applications section. Positive Supply, (VP − VN ) ≤ 12 V. Output of the Logarithmic Front End. Buffer Amplifier Noninverting Input. Buffer Amplifier Inverting Input. Buffer Output. Analog Ground. The exposed pad must be soldered to ground. Rev. C | Page 5 of 24 AD8305 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VP = 5 V, VN = 0 V, RREF = 200 kΩ, TA = 25°C, unless otherwise noted. 1.0 –40°C +25°C +85°C 1.0 VLOG (V) ERROR; dB (10mV/dB) 1.2 0.8 0.6 0°C +70°C 0.4 1µ 100n 10µ IPD (A) 100µ 1m 10m 0°C +25°C –40°C 10n 100n 2.0 1.6 10µ 1µ IPD (A) 100µ 1m 10m TA = –40°C, 0°C, +25°C, +70°C, +85°C VN = 0V 1.5 1.4 ERROR; dB (10mV/dB) 1.0 0°C +70°C 1.2 VLOG ( V) –0.5 Figure 6. Law Conformance Error vs. IPD (at IREF = 10 µA) for Multiple Temperatures, Normalized to 25°C TA = –40°C, 0°C, +25°C, +70°C, +85°C VN = 0V –40°C 1.0 +25°C +85°C 0.8 0.6 +85°C +70°C 0.5 0 –0.5 +25°C –1.0 0.4 0°C –1.5 0.2 100µ 1m 10m –2.0 1n 03053-004 1µ 10µ IREF (A) 100n 10n –40°C 10n 100n 1µ 10µ IPD (A) 100µ 1m 10m Figure 7. Law Conformance Error vs. IREF (at IPD = 10 µA) for Multiple Temperatures, Normalized to 25°C Figure 4. VLOG vs. IREF for Multiple Temperatures 0.5 1.8 0.4 1.6 0.3 1.4 ERROR; dB (10mV/dB) 10µA 1.2 VLOG (V) 0 –2.0 1n 03053-003 10n 1.8 1.0 +70°C –1.5 Figure 3. VLOG vs. IPD for Multiple Temperatures 0 1n +85°C 0.5 –1.0 0.2 0 1n TA = –40°C, 0°C, +25°C, +70°C, +85°C VN = 0V 1.5 03053-006 1.4 2.0 TA = –40°C, 0°C, +25°C, +70°C, +85°C VN = 0V 03053-007 1.6 10nA 100nA 0.8 1µA 0.6 10µA 1mA 0.1 0 –0.1 1µA –0.2 10nA 100µA 0.4 100µA 0.2 100nA –0.3 1mA 10n 100n 10µ 1µ IPD (A) 100µ 1m 10m –0.5 1n 03053-005 0 1n Figure 5. VLOG vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA) 10n 100n 1µ 10µ IPD (A) 100µ 1m 10m 03053-008 –0.4 0.2 Figure 8. Law Conformance Error vs. IPD for Multiple Values of IREF (Decade Steps from 10 nA to 1 mA) Rev. C | Page 6 of 24 Data Sheet AD8305 0.5 1.8 0.4 1.6 10nA ERROR; dB (10mV/dB) 1.4 1µA 1.0 1mA 100µA 10µA 1µA 0.8 0.6 100nA 10nA 0.4 0.2 10µA 0.1 0 –0.1 –0.2 100µA 1mA –0.3 0.2 –0.4 10µ 1µ IREF (A) 100n 100µ 1m 10m –0.5 1n 03053-009 10n Figure 9. VLOG vs. IREF for Multiple Values of IPD (Decade Steps from 10 nA to 1 mA) 10n 100n 1µ 10µ IREF (A) 100µ 1m 10m 03053-012 VLOG (V) 1.2 0 1n 100nA 0.3 Figure 12. Law Conformance Error vs. IREF for Multiple Values of IPD (Decade Steps from 10 nA to 1 mA) 0.5 1.4 +3V, 0V 0.4 +5V, 0V +12V, 0V 1.2 100µA TO 1mA:T-RISE = 22,000 03053-029 COUNT Figure 28. Intercept Drift vs. Temperature (3σ to Either Side of Mean of 1 nA) 2.46 0 –0.015 –0.010 –0.005 0 0.005 VINPT – VSUM VOLTAGE (V) 0.010 0.015 03053-032 0 03053-028 –350 –40 –30 –20 –10 03053-031 1000 –250 Figure 32. Distribution of Offset Voltage (VINPT − VSUM) Sample >22,000 Rev. C | Page 10 of 24 Data Sheet AD8305 GENERAL STRUCTURE The AD8305 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems, and is also useful in many nonoptical applications. These notes explain the structure of this unique style of translinear log amp. Figure 33 is a simplified schematic showing the key elements. BIAS GENERATOR PHOTODIODE INPUT CURRENT IPD 2.5V 80kΩ 0.5V IREF IREF VREF 20kΩ VBE1 VBE2 0.5V 44µA/dec VRDZ 14.2kΩ 451Ω VLOG 0.5V VBE1 Q2 VBE2 6.69kΩ 03053-033 Q1 VBE = kT/qIn(IC/IS) (1) IC is its collector current. IS is a scaling current, typically only 10−17 A. kT/q is the thermal voltage, proportional to absolute temperature (PTAT) and is 25.85 mV at 300 K. COMM VSUM The base emitter voltage of a bipolar junction transistor (BJT) can be expressed by Equation 1, which immediately shows its basic logarithmic nature: where: TEMPERATURE COMPENSATION (SUBTRACT AND DIVIDE BY T × K INPT THEORY COMM VNEG (NORMALLY GROUNDED) Figure 33. Simplified Schematic The photodiode current, IPD, is received at Pin INPT. The voltage at this node is essentially equal to those on the two adjacent guard pins, VSUM and IREF, due to the low offset voltage of the JFET op amp. Transistor Q1 converts the input current IPD to a corresponding logarithmic voltage, as shown in Equation 1. A finite positive value of VSUM is needed to bias the collector of Q1 for the usual case of a single-supply voltage. This is internally set to 0.5 V, that is, one fifth of the reference voltage of 2.5 V appearing on Pin VREF. The resistance at the VSUM pin is nominally 16 kΩ; this voltage is not intended as a general bias source. The AD8305 also supports the use of an optional negative supply voltage, VN, at Pin VNEG. When VN is −0.5 V or more negative, VSUM may be connected to ground; thus, INPT and IREF assume this potential. This allows operation as a voltageinput logarithmic converter by the inclusion of a series resistor at either or both inputs. Note that the resistor setting IREF needs to be adjusted to maintain the intercept value. It should also be noted that the collector-emitter voltages of Q1 and Q2 are now the full VN, and effects due to self-heating causes errors at large input currents. The input dependent, VBE1, of Q1 is compared with the reference VBE2 of a second transistor, Q2, operating at IREF. This is generated externally, to a recommended value of 10 µA. However, other values over a several-decade range can be used with a slight degradation in law conformance (see Figure 3). The current, IS, is never precisely defined and exhibits an even stronger temperature dependence, varying by a factor of roughly a billion between −35°C and +85°C. Thus, to make use of the BJT as an accurate logarithmic element, both of these temperature dependencies must be eliminated. The difference between the base-emitter voltages of a matched pair of BJTs, one operating at the photodiode current IPD and the second operating at a reference current IREF, can be written as: VBE1 − VBE2 = kT/q In(IC/IS) − kT/q In(IREF/IS) = In(10)kT/qlog10(IPD/IREF) = 59.5 mVlog10(IPD/IREF)(T = 300 K) (2) The uncertain and temperature dependent saturation current IS, which appears in Equation 1, has thus been eliminated. To eliminate the temperature variation of kT/q, this difference voltage is processed by what is essentially an analog divider. Effectively, it puts a variable under Equation 2. The output of this process, which also involves a conversion from voltagemode to current-mode, is an intermediate, temperaturecorrected current: ILOG = IY log10(IPD/IREF) (3) where IY is an accurate, temperature-stable scaling current that determines the slope of the function (the change in current per decade). For the AD8305, IY is 44 µA, resulting in a temperature independent slope of 44 mA/decade, for all values of IPD and IREF. This current is subsequently converted back to a voltagemode output, VLOG, scaled 200 mV/decade. It is apparent that this output should be zero for IPD = IREF and would need to swing negative for smaller values of input current. To avoid this, IREF would need to be as small as the smallest value of IPD. However, it is impractical to use such a small reference current as 1 nA. Accordingly, an offset voltage is added to VLOG to shift it upward by 0.8 V when Pin VRDZ is directly connected to VREF. This has the effect of moving the intercept to the left by four decades, from 10 µA to 1 nA: ILOG = IY log10(IPD/IINTC) (4) where IINTC is the operational value of the intercept current. To disable this offset, Pin VRDZ should be grounded, then the intercept IINTC is simply IREF. Because values of IPD < IINTC result in a negative VLOG, a negative supply of sufficient value is Rev. C | Page 11 of 24 AD8305 Data Sheet RESPONSE TIME AND NOISE CONSIDERATIONS required to accommodate this situation (see the Using a Negative Supply section). The voltage, VLOG, is generated by applying ILOG to an internal resistance of 4.55 kΩ, formed by the parallel combination of a 6.69 kΩ resistor to ground and the 14.2 kΩ resistor to the VRDZ pin. When the VLOG pin is unloaded and the intercept repositioning is disabled by grounding VRDZ, the output current, ILOG, generates a voltage at the VLOG pin of VLOG = ILOG × 4.55 kΩ = 44 µA × 4.55 kΩ × log10(IPD/IREF) = VY log10(IPD/IREF) (5) where VY = 200 mV/decade, or 10 mV/dB. Note that any resistive loading on VLOG lowers this slope and also result in an overall scaling uncertainty due to the variability of the onchip resistors. Consequently, this practice is not recommended. VLOG may also swing below ground when dual supplies (VP and VN) are used. When VN = −0.5 V or larger, the input pins INPT and IREF may now be positioned at ground level by simply grounding VSUM. MANAGING INTERCEPT AND SLOPE The response time and output noise of the AD8305 are fundamentally a function of the signal current, IPD. For small currents, the bandwidth is proportional to IPD, as shown in Figure 15. The output low frequency voltage-noise spectraldensity is a function of IPD (Figure 17) and also increases for small values of IREF. Details of the noise and bandwidth performance of translinear log amps can be found in the AD8304 data sheet. POWER SUPPLY SEQUENCING Some applications may result in the presence of large input signal current (>1 mA) prior to the AD8305 being powered on. In such cases, it is recommended that power supply sequencing be implemented such that the AD8305 is powered on prior to the photodiode or current source. In those applications where it is not possible to implement supply sequencing, VSUM should be driven externally by a low impedance source. In applications where a low impedance bias source is not readily available, the circuit shown in Figure 34 can be used. +VP When using a single supply, VRDZ should be directly connected to VREF to allow operation over the entire five-decade input current range. As noted previously, this introduces an accurate offset voltage of 0.8 V at the VLOG pin, equivalent to four decades, resulting in a logarithmic transfer function that can be written as VLOG = VY log10(104 × IPD/IREF) = VY log10 (IPD/IINTC) +VBIAS VPOS IPD INPT C1 R1 (6) where IINTC = IREF/104. Thus, the effective intercept current IINTC is only one tenthousandth of IREF, corresponding to 1 nA when using the recommended value of IREF = 10 mA. +VS VSUM The slope can be reduced by attaching a resistor to the VLOG pin. This is strongly discouraged, in view of the fact that the onchip resistors do not ratio correctly to the added resistance. Also, it is rare that one would want to lower the basic slope of 10 mV/dB; if this is needed, it should be effected at the low impedance output of the buffer, which is provided to avoid such miscalibration and also allow higher slopes to be used. The AD8305 buffer is essentially an uncommitted op amp with rail-to-rail output swing, good load-driving capabilities, and a unity-gain bandwidth of >12 MHz. In addition to allowing the introduction of gain, using standard feedback networks and thereby increasing the slope voltage VY, the buffer can be used to implement multipole low-pass filters, threshold detectors, and a variety of other functions. Further details of these can be found in the AD8304 data sheet. ≈0.5V RB + VBE – β IE 2N2907 IC VNEG COMM C2 03053-049 RA Figure 34. VSUM Biasing Circuit for Applications Where Large Input Signals Are Present Prior to AD8305 Power-On The 2N2907 transistor used in Figure 34 is a common PNP-type switching transistor. Ra and Rb are selected such that the voltage at the base of the transistor is ~0.5 V. In general, VS × [Rb/(Ra + Rb)] should equal approximately 0.5 V. Setting Ra = 5 kΩ and Rb = 1 kΩ, results in 500 µA of additional quiescent current for a 3 V supply under normal operation. Larger resistor values may be used for this divider network by choosing a transistor with a higher β than the 2N2907. Given a typical Vbe of 0.7 V, the voltage at VSUM is ~1.2 V when the AD8305 is off and a large input signal is being applied. Once the AD8305 is powered on the voltage at VSUM is pulled down to its nominal value of 0.5 V. The circuit in Figure 34 is tested for 3 V to 5 V positive supplies over the full temperature range for the AD8305. C1, and R1 are the components that make up Rev. C | Page 12 of 24 Data Sheet AD8305 the input compensation network and C2 is the recommended bypassing capacitor on VSUM. If board space limits the amount of external circuitry to the AD8305 it is possible to eliminate the transistor in Figure 34 and connect the resistor divider directly to VSUM. In this case the bias voltage at VSUM and INPT is set by the resistor values selected for the divider, not the internal biasing of the AD8305. Rev. C | Page 13 of 24 AD8305 Data Sheet APPLICATIONS INFORMATION The AD8305 is easy to use in optical supervisory systems and in similar situations where a wide ranging current is to be converted to its logarithmic equivalent, which is represented in decibel terms. Basic connections for measuring a single-current input are shown in Figure 35, which also includes various nonessential components. +5V 0.5 log10 VPOS VRDZ VOUT VREF 20kΩ 0.5V 80kΩ 2.5V VBE2 Q2 Q1 14.2kΩ TEMPERATURE COMPENSATION ILOG BFIN 451Ω VLOG CFLT 10nF 6.69kΩ COMM 0.5V 1nF – + VBE1 VSUM 1nF 8kΩ SCAL IPD INPT 1kΩ The optional capacitor from VLOG to ground forms a singlepole low-pass filter in combination with the 4.55 kΩ resistance at this pin. For example, using a CFLT of 10 nF, the −3 dB corner frequency is 3.5 kHz. Such filtering is useful in minimizing the output noise, particularly when IPD is small. Multipole filters are more effective in reducing the total noise; examples are provided in the AD8304 data sheet. 12kΩ COMM IREF 1kΩ 1nF BIAS GENERATOR VNEG COMM 03053-034 200kΩ VBIAS IPD 1nA Because the basic scaling at VLOG is 0.2 V/decade, and a swing of 4 V at the buffer output would correspond to 20 decades, it is often useful to raise the slope to make better use of the rail-to-rail voltage range. For illustrative purposes, the circuit in Figure 35 provides an overall slope of 0.5 V/ decade (25 mV/dB). Thus, using IREF = 10 µA, VLOG runs from 0.2 V at IPD = 10 nA to 1.4 V at IPD = 1 mA while the buffer output runs from 0.5 V to 3.5 V, corresponding to a dynamic range of 120 dB (electrical, that is, 60 dB optical power). Figure 35. Basic Connections for Fixed Intercept Use The 2 V difference in voltage between the VREF and INPT pins in conjunction with the external 200 kΩ resistor RREF provide a reference current, IREF, of 10 µA into Pin IREF. Connecting pin VRDZ to VREF raises the voltage at VLOG by 0.8 V, effectively lowering the intercept current, IINTC, by a factor of 104 to position it at 1 nA. A wide range of other values for IREF, from under 100 nA to over 1 mA, may be used. The effect of such changes is shown in Figure 5. Any temperature variation in RREF must be taken into account when estimating the stability of the intercept. Also, the overall noise increases when using very low values of IREF. In fixed intercept applications, there is little benefit in using a large reference current, since this only compresses the low current end of the dynamic range when operated from a single supply, here shown as 5 V. The capacitor between VSUM and ground is recommended to minimize the noise on this node and to help provide a clean reference current. The dynamic response of this overall input system is influenced by the external RC networks connected from the two inputs (INPT, IREF) to ground. These are required to stabilize the input systems over the full current range. The bandwidth changes with the input current due to the widely varying pole frequency. The RC network adds a zero to the input system to ensure stability over the full range of input current levels. The network values shown in Figure 35 usually suffice, but some experimentation may be necessary when the photodiode capacitance is high. Although the two current inputs are similar, some care is needed to operate the reference input at extremes of current (