AD8312

Preliminary Technical Data FEATURES Complete RF Detector Function Typical Range : −45 dBm to 0 dBm re 50 Ω Frequency Response from 100 MHz to 2.7 GHz Temperature-Stable Linear-in-dB Response Accurate to 2.7 GHz Rapid Response: 70 ns to a 10 dB Step Low Power: 12 mW at 2.7 V 100 MHz−2.7 GHz, 45 dB RF Log Detector AD8312 Its high sensitivity allows measurement at low power levels, thus reducing the amount of power that needs to be coupled to the detector. It is essentially a voltage-responding device, with a typical signal range of 1.25 mV to 224 mV rms or −45 dBm to 0 dBm re 50 Ω. For convenience, the signal is internally ac-coupled, using a 5 pF capacitor to a load of 3 kΩ in shunt with 2 pF. This highpass coupling, with a corner at approximately 16 MHz, determines the lowest operating frequency. Thus, the source may be dc-grounded. The AD8312 output, called VOUT, increases from close to ground to about 1.2 V as the input signal level increases from 1.25 mV to 224 mV. This output is intended for use in measurement mode. Consult the Applications section of this data sheet for information on use in this mode. A capacitor may be connected between the VOUT and CFLT pins when it is desirable to increase the time inter val over which averaging of the input waveform occurs. The AD8312 is available in a 6-lead wafer-level chip scale package, 1.0 mm x 1.5 mm, and consumes 4.5 mA from a 2.7 V to 5.5 V supply. APPLICATIONS Cellular Handsets (GSM, CDMA, WCDMA) RSSI and TSSI for Wireless Terminal Devices Transmitter Power Measurement PRODUCT DESCRIPTION The AD8312 is a complete low cost subsystem for the measurement of RF signals in the frequency range of 100 MHz to 2.7 GHz, with a typical dynamic range of 45 dB, intended for use in a wide variety of cellular handsets and other wireless devices. It provides a wider dynamic range and better accuracy than possible using discrete diode detectors. In particular, its temperature stability is excellent over the full operating range of −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM Figure 1. PrA 10/29/2004 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD8312 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 General Description ....................................................................... 10 Preliminary Technical Data Applications..................................................................................... 11 Basic Connections ...................................................................... 11 Evaluation Board ........................................................................ 11 Outline Dimensions ....................................................................... 13 Ordering Guide .......................................................................... 13 Rev. PrA| Page 2 of 13 Preliminary Technical Data SPECIFICATIONS Table 1. VS = 3 V, CFLT = open, TA = 25°C, 52.3 Ω termination resistor at RFIN, unless otherwise noted. Parameter SIGNAL INPUT INTERFACE Specified Frequency Range Input Voltage Range Equivalent Power Range DC Resistance to COMM MEASUREMENT MODE f = 0.1 GHz Input Impedance ± 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity TA = +25°C −40°C < TA < +85°C ± 1 dB Error ± 1 dB Error Conditions RFIN (Pin 6) Internally AC-Coupled 52.3 Ω External Termination VOUT (Pin 2) shorted to VSET (Pin 3), Sinusoidal Input Signal 3020 || 1.35 48 40 2 -46 21.0 -50.4 0.85 0.22 - 0.0002 - 0.0050 903 || 1.16 50 40 2 -48 20.3 -51.4 0.839 0.226 - 0.0036 -0.0010 440 || 1.14 46 38 -3 -49 19.4 -51.8 0.815 0.229 -0.0044 -0.0027 Min 0.1 1.25 –45 100 Typ Max 2.7 224 0 AD8312 Unit GHz mV rms dBm kΩ PIN = –10 dBm PIN = –40 dBm PIN = –10 dBm 25°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +25°C Ω || pF dB dB dBm dBm mV/dB dBm V V dB/°C dB/°C Ω || pF dB dB dBm dBm mV/dB dBm V V dB/°C dB/°C Ω || pF dB dB dBm dBm mV/dB dBm V V dB/°C dB/°C f = 0.9 GHz Input Impedance ± 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity TA = +25°C −40°C < TA < +85°C ± 1 dB Error ± 1 dB Error PIN = –10 dBm PIN = –40 dBm PIN = –10 dBm 25°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +25°C f = 1.9 GHz Input Impedance ± 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity TA = +25°C −40°C < TA < +85°C ± 1 dB Error ± 1 dB Error PIN = –10 dBm PIN = –40 dBm PIN = –10 dBm 25°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +25°C Rev. PrA| Page 3 of 13 AD8312 Parameter f = 2.5 GHz Input Impedance ± 1 dB Dynamic Range Maximum Input Level Minimum Input Level Slope Intercept Output Voltage - High Power In Output Voltage - Low Power In Temperature Sensitivity Conditions Preliminary Technical Data Min Typ 365 || 1.1 44 36 -4 -48 18.85 -51 0.774 0.205 +0.0053 -0.0047 0.02 2.2 VS – 1 2/1 100 tbd 120 85 10 tbd 2.7 –40°C ≤ TA ≤ +85°C 3.0 4.2 4.3 5.5 Max Unit Ω || pF dB dB dBm dBm mV/dB dBm V V dB/°C dB/°C V V V mA µV uV/√Hz ns ns kΩ µA V mA mA TA = +25°C −40°C < TA < +85°C ± 1 dB Error ± 1 dB Error OUTPUT INTERFACE Minimum Output Voltage Maximum Output Voltage1 General Limit Available Output Current Residual RF (at 2f) Output Noise Fall Time Rise Time VSET INTERFACE Input Resistance Bias Current Source POWER INTERFACE Supply Voltage Quiescent Current vs. Temperature PIN = –10 dBm PIN = –40 dBm PIN = –10 dBm 25°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +25°C VOUT (Pin 2) No Signal at RFIN, RL ≥ 10 kΩ RL ≥ 10 kΩ 2.7 V ≤ VS ≤ 5.5 V Sourcing/Sinking f = 0.1 GHz (Worst Condition) RF Input = 2.2 GHz, –10 dBm, fNOISE = 100 kHz, CFLT open Input Level = off to 0 dBm, 90% to 10% Input Level = 0 dBm to off, 10% to 90% VSET (Pin 3) RFIN = −10 dBm; VSET = 1.2V VPOS (Pin 1) 1 Increased output possible when using an attenuator between VOUT and VSET to raise the slope. Rev. PrA| Page 4 of 13 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VPOS VOUT, VSET Input Voltage Equivalent Power Internal Power Dissipation θJA (WLCSP) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Value 5.5 V 0 V, VPOS 1.6 V rms +17 dBm TBD mW TBD°C/W 125°C –40°C to +85°C –65°C to +150°C 260°C AD8312 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrA| Page 5 of 13 AD8312 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Preliminary Technical Data Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin 1 2 3 4 5 6 Mnemonic VPOS VOUT VSET CFLT COMM RFIN Function Positive supply voltage (VS), 2.7 V to 5.5 V. Logarithmic output. Output voltage increases with increasing input amplitude. Setpoint input. Connect VSET to VOUT for measurement-mode operation. Connection for an external capacitor to slow the response of the output. Capacitor is connected between CFLT and VOUT. Device Common (Ground) RF Input Rev. PrA| Page 6 of 13 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS 1.4 1.3 1.2 1.1 1 0.9 AD8312 2.8 2.4 2 1.6 1.2 0.8 Error - dB 0.4 0 -0.4 -0.8 -1.2 -1.6 -2 -2.4 -2.8 -55 -45 -35 -25 -15 -5 5 Vout - Volts 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -65 PIN-dBm Figure 3. VOUT and Log Conformance vs. Input Amplitude at 50 MHz; −40°C, +25°C, and +85°C Figure 6. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz; −40°C, +25°C, and +85°C 1.4 1.3 1.2 1.1 1 0.9 2.8 2.4 2 1.6 1.2 0.8 Error - dB 0.4 0 -0.4 -0.8 -1.2 -1.6 -2 -2.4 -2.8 -55 -45 -35 -25 -15 -5 5 Vout - Volts 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -65 PIN-dBm Figure 4. VOUT and Log Conformance vs. Input Amplitude at 100 MHz; −40°C, +25°C, and +85°C Figure 7. VOUT and Log Conformance vs. Input Amplitude at 2.2 GHz; −40°C, +25°C, and +85°C 1.4 1.3 1.2 1.1 1 0.9 2.8 2.4 2 1.6 1.2 0.8 Vout - Volts 1.4 1.3 1.2 1.1 1 0.9 2.8 2.4 2 1.6 1.2 0.8 Error - dB 0.4 0 -0.4 -0.8 -1.2 -1.6 -2 -2.4 -2.8 -55 -45 -35 -25 -15 -5 5 Vout - Volts Error - dB 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.4 0 -0.4 -0.8 -1.2 -1.6 -2 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 -2.4 0 -2.8 -55 -45 -35 -25 -15 -5 5 -65 -65 PIN-dBm PIN-dBm Figure 5. VOUT and Log Conformance vs. Input Amplitude at 900 MHz; −40°C, +25°C, and +85°C Figure 8. VOUT and Log Conformance vs. Input Amplitude at 2.5 GHz; −40°C, +25°C, and +85°C Rev. PrA| Page 7 of 13 AD8312 Preliminary Technical Data 2.8 2.4 2 1.6 1.2 0.8 Error - dB 0.4 0 -0.4 -0.8 -1.2 -1.6 -2 -2.4 -2.8 -64 -60 -56 -52 -48 -44 -40 -36 -32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 PIN-dBm Figure 9. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 50 MHz Figure 12. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 1.9 GHz 2.8 2.4 2 1.6 1.2 0.8 Error - dB 0.4 0 -0.4 -0.8 -1.2 -1.6 -2 -2.4 -2.8 -64 -60 -56 -52 -48 -44 -40 -36 -32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 PIN-dBm Figure 10. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 100 MHz Figure 13. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 2.2 GHz 2.8 2.4 2 1.6 1.2 0.8 2.8 2.4 2 1.6 1.2 0.8 Error - dB 0.4 0 -0.4 -0.8 -1.2 -1.6 -2 -2.4 -2.8 Error - dB -60 -56 -52 -48 -44 -40 -36 -32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 0.4 0 -0.4 -0.8 -1.2 -1.6 -2 -2.4 -2.8 -64 -64 -60 -56 -52 -48 -44 -40 -36 -32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 PIN-dBm PIN-dBm Figure 11. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 900 MHz Figure 14. Distribution of Error over Temperature after Ambient Normalization vs. Input Amplitude at 2.5 GHz Rev. PrA| Page 8 of 13 Preliminary Technical Data AD8312 Figure 15. VOUT Response Time, RF O ff to 0 dBm Figure 18. Power-On and Power-Off Response Figure 16. Test Setup for Pulse Response Figure 19. Test Setup for Power-On and Power-Off Response Figure 17. Input Impedance vs. Frequency; No Termination Resistor on RFIN Figure 20. Noise Spectral Density of Output; CFLT = Open Rev. PrA| Page 9 of 13 AD8312 GENERAL DESCRIPTION The AD8312 is a logarithmic amplifier (log amp) similar in design to the AD8313; further details about the structure and function may be found in the AD8313 data sheet and other log amps produced by Analog Devices. Figure 21 shows the main features of the AD8312 in block schematic form. The AD8312 combines two key functions needed for the measurement of signal level over a moderately wide dynamic range. First, it provides the amplification needed to respond to small signals, in a chain of four amplifier/limiter cells, each having a small-signal gain of 10 dB and a bandwidth of approximately 3.5 GHz. At the output of each of these amplifier stages is a full-wave rectifier, essentially a square-law detector cell, that converts the RF signal voltages to a fluctuating current having an average value that increases with signal level. A further passive detector stage is added ahead of the first stage. Thus, there are five detectors, each separated by 10 dB, spanning some 50 dB of dynamic range. The output of these detector cells is in the form of a differential current, making their summation a simple matter. It can easily be shown that such summation closely approximates a logarithmic function. This result is then converted to a voltage, at pin VOUT, through a high-gain stage. In measurement modes, this output is connected back to a voltage-to-current (V–I) stage, in such a manner that VOUT is a logarithmic measure of the RF input voltage, with a slope and intercept controlled by the design. For a fixed termination resistance at the input of the AD8312, a given voltage corresponds to a certain power level. Preliminary Technical Data The external termination added ahead of the AD8312 determines the effective power scaling. This will often take the form of a simple resistor (52.3 Ω will provide a net 50 Ω input) but more elaborate matching networks may be used. This impedance determines the logarithmic intercept, the input power for which the output would cross the baseline (VOUT = zero) if the function were continuous for all values of input. Since this is never the case for a practical log amp, the intercept refers to the value obtained by the minimum-error straight-line fit to the actual graph of VOUT versus PIN. The quoted values assume a sinusoidal (CW) signal. Where there is complex modulation, as in CDMA, the calibration of the power response needs to be adjusted accordingly. Where a true power (waveform-independent) response is needed, the use of an rmsresponding detector, such as the AD8361, should be considered. However, the logarithmic slope, the amount by which the output VOUT changes for each decibel of input change (voltage or power) is, in principle, independent of waveform or termination impedance. In practice, it usually falls off somewhat at higher frequencies, due to the declining gain of the amplifier stages and other effects in the detector cells. For the AD8312, the slope at low frequencies is nominally 21.3 mV/dB, falling almost linearly with frequency to about 19.2 mV/dB at 2.5 GHz. These values are sensibly independent of temperature and almost totally unaffected by the supply voltage from 2.7 V to 5.5 V. Figure 21. Block Schematic Rev. PrA| Page 10 of 13 Preliminary Technical Data APPLICATIONS BASIC CONNECTIONS Figure 22 shows connections for the basic measurement mode. A supply voltage of 2.7 V to 5.5 V is required. The supply to the VPOS pin should be decoupled with a low inductance 0.1 µF surface mount ceramic capacitor. A series resistor of about 10 Ω may be added; this resistor will slightly reduce the supply voltage to the AD8312 (maximum current into the VPOS pin is approximately 9 mA when VOUT is delivering 5 mA). Its use should be avoided in applications where the power supply voltage is ver y low (i.e., 2.7 V). A series inductor will provide similar power supply filtering with minimal drop in supply voltage. AD8312 0.9 GHz, and only slightly less at higher frequencies up to 2.5 GHz. At a slope of 21.5 mV/dB, this would amount to an output span of 967 mV. Figure 23 shows the transfer function for VOUT at a supply voltage of 3 V, and input frequency of 0.9 GHz. The load resistance on VOUT should not be lower than 10 kΩ in order that the full-scale output of 1 V can be generated with the limited available current of 200 µA max. Figure 23 shows the logarithmic conformance under the same conditions. Figure 22. Basic Connections for Operation in Measurement Mode Figure 23. VOUT and Log Conformance Error vs. Input Level vs. Input Level The AD8312 has an internal input coupling capacitor. This eliminates the need for external ac-coupling. A broadband input match is achieved in this example by connecting a 52.3 Ω resistor between RFIN and ground. This resistance combines with the internal input impedance of approximately 3 kΩ to give an overall broadband input resistance of 50 Ω. The measurement mode is selected by connecting VSET to VOUT, which establishes a feedback path and sets the logarithmic slope to its nominal value. The peak voltage range of the measurement extends from −45 dBm to 0 dBm at EVALUATION BOARD Figure 24 shows the schematic of the AD8312 evaluation board. The layout and silkscreen of the component and circuit sides are shown in Figure 25 to Figure 28. The board is powered by a single supply in the range, 2.7 V to 5.5 V. The power supply is decoupled by a single 0.1 µF capacitor. Table 4 details the various configuration options of the evaluation board. Figure 24. Evaluation Board Schematic Rev. PrA| Page 11 of 13 AD8312 Preliminary Technical Data Figure 25. Layout of Component Side ( WLCSP) Figure 27. Silkscreen of Component Side ( WLCSP) Figure 26. Layout of Circuit Side ( WLCSP)) Figure 28. Silkscreen of Circuit Side ( WLCSP) Table 4. Evaluation Board Configuration Options Component VPOS, GND C2 R1 R2, R4 C3 R3, R8, C4 R7 R5, R6 Function Supply and Ground Vector Pins Power Supply Decoupling: The nominal supply decoupling consists of a 0.1 µF capacitor (C1). Input Interface: The 52.3 Ω resistor in position R1 combines with the AD8312’s internal input impedance to give a broadband input impedance of around 50 Ω. Slope Adjust: By installing resistors in R2 and R4, the nominal slope of 20 mV/dB can be changed. See Slope Adjust discussion for more details. Filter Capacitor. The response time of VOUT can be modified by placing a capacitor between CFLT (Pin 4) and VOUT. Output Interface: R3, R8, and C4 can be used to check the response of VOUT to capacitive and resistive loading. R3/R8 can be used to attenuate VOUT. VSET Interface: R7 can be used to reduce capacitive loading from transmission lines. Alternate Interface: R5 and R6 allow for VOUT and VSET to be accessible from the edge connector Default Condition Not Applicable C2 = 0.1 µF (Size 0603) R1 = 52.3 Ω (Size 0603) R2 = Open (Size 0402) R4 = 0 Ω (Size 0402) C3 = Open (Size 0603) R3 = 1kΩ (Size 0603) R8 = C4 = open (Size 0402) R7 = 1kΩ (Size 0603) R5 = R6 = Open (Size 0402) Rev. PrA| Page 12 of 13 Preliminary Technical Data OUTLINE DIMENSIONS AD8312 Figure 29. Wafer-level Chip Scale Package Dimensions shown in mm ORDERING GUIDE AD8312 Products AD8312ACPZ-REEL71 AD8312ACPZ-WP AD8312-EVAL 1 Temperature Package –40°C to +85°C –40°C to +85°C Package Description 6-Lead Wafer-level Chip Scale Package, 7” Tape and Reel 6-Lead WLCSP, Waffle Pack Evaluation Board Package Outline CB-6 CB-6 Branding Information Q00 Q00 Ordering Quantity tbd tbd Z = Pb-free part. Rev. PrA| Page 13 of 13 PR05260-0-11/04(PrA)