AD8362_1

50 Hz to 3.8 GHz 65 dB TruPwr™ Detector AD8362 FEATURES Complete fully calibrated measurement/control system Accurate rms-to-dc conversion from 50 Hz to 3.8 GHz Input dynamic range of >65 dB: −52 dBm to +8 dBm in 50 Ω Waveform and modulation independent, such as GSM/CDMA/TDMA Linear-in-decibels output, scaled 50 mV/dB Law conformance error of 0.5 dB All functions temperature and supply stable Operates from 4.5 V to 5.5 V at 24 mA Power-down capability to 1.3 mW FUNCTIONAL BLOCK DIAGRAM DECL CHPF INHI x2 INLO VOUT VTGT x2 ACOM CLPF VSET APPLICATIONS Power amplifier linearization/control loops Transmitter power controls Transmitter signal strength indication (TSSI) RF instrumentation VREF AD8362 BIAS VPOS 02923-001 COMM PWDN Figure 1. GENERAL DESCRIPTION The AD8362 is a true rms-responding power detector that has a 65 dB measurement range. It is intended for use in a variety of high frequency communication systems and in instrumentation requiring an accurate response to signal power. It is easy to use, requiring only a single supply of 5 V and a few capacitors. It can operate from arbitrarily low frequencies to over 3.8 GHz and can accept inputs that have rms values from 1 mV to at least 1 V rms, with large crest factors, exceeding the requirements for accurate measurement of CDMA signals. The input signal is applied to a resistive ladder attenuator that comprises the input stage of a variable gain amplifier (VGA). The 12 tap points are smoothly interpolated using a proprietary technique to provide a continuously variable attenuator, which is controlled by a voltage applied to the VSET pin. The resulting signal is applied to a high performance broadband amplifier. Its output is measured by an accurate square-law detector cell. The fluctuating output is then filtered and compared with the output of an identical squarer, whose input is a fixed dc voltage applied to the VTGT pin, usually the accurate reference of 1.25 V provided at the VREF pin. The difference in the outputs of these squaring cells is integrated in a high gain error amplifier, generating a voltage at the VOUT pin with rail-to-rail capabilities. In a controller mode, this low noise output can be used to vary the gain of a host system’s RF amplifier, thus balancing the setpoint against the input power. Optionally, the voltage at VSET can be a replica of the RF signal’s amplitude modulation, in which case the overall effect is to remove the modulation component prior to detection and lowpass filtering. The corner frequency of the averaging filter can be lowered without limit by adding an external capacitor at the CLPF pin. The AD8362 can be used to determine the true power of a high frequency signal having a complex low frequency modulation envelope, or simply as a low frequency rms voltmeter. The high-pass corner generated by its offset-nulling loop can be lowered by a capacitor added on the CHPF pin. Used as a power measurement device, VOUT is strapped to VSET. The output is then proportional to the logarithm of the rms value of the input. In other words, the reading is presented directly in decibels and is conveniently scaled 1 V per decade, or 50 mV/dB; other slopes are easily arranged. In controller modes, the voltage applied to VSET determines the power level required at the input to null the deviation from the setpoint. The output buffer can provide high load currents. The AD8362 has 1.3 mW power consumption when powered down by a logic high applied to the PWDN pin. It powers up within about 20 μs to its nominal operating current of 20 mA at 25°C. The AD8362 is supplied in a 16-lead TSSOP for operation over the temperature range of −40°C to +85°C. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved. AD8362 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Equivalent Circuits ........................................................................... 8 Typical Performance Characteristics ............................................. 9 Characterization Setup .................................................................. 15 Equipment ................................................................................... 15 Analysis........................................................................................ 15 Circuit Description......................................................................... 16 Square Law Detection ................................................................ 16 Voltage vs. Power Calibration ................................................... 17 Offset Elimination...................................................................... 18 Time-Domain Response of the Closed Loop ......................... 18 Operation in RF Measurement Mode.......................................... 19 Basic Connections...................................................................... 19 Device Disable ............................................................................ 19 Recommended Input Coupling................................................ 19 Operation at Low Frequencies.................................................. 20 Choosing a Value for CHPF...................................................... 21 Choosing a Value for CLPF....................................................... 21 Adjusting VTGT to Accommodate Signals with Very High Crest Factors ............................................................................... 22 Altering the Slope....................................................................... 22 Temperature Compensation and Reduction of Transfer Function Ripple .......................................................................... 23 Temperature Compensation at Various WiMAX Frequencies up to 3.8 GHz........................................................................................ 24 Operation in Controller Mode ................................................. 26 RMS Voltmeter with 90 dB Dynamic Range .......................... 27 AD8362 Evaluation Board ............................................................ 28 Outline Dimensions ....................................................................... 31 Ordering Guide .......................................................................... 31 Replaced Circuit Description Section ......................................... 15 Changes to Operation in RF Measurement Mode Section ...... 18 Deleted Using the AD8362 Section ............................................. 20 Deleted Main Modes of Operation Section................................ 22 Changes to Operation in Controller Mode Section .................. 23 Changes to AD8362 Evaluation Board Section.......................... 25 Deleted General Applications Section......................................... 29 3/04—Rev. A to Rev. B Updated Format .................................................................Universal Changes to Specifications.................................................................3 Changes to the Offset Elimination Section................................. 16 Changes to the Operation at Low Frequencies Section ............ 17 Changes to the Time-Domain Response of the Closed Loop Section.................................................................................... 17 Changes to Equation 13................................................................. 24 Changes to Table 5 ......................................................................... 31 6/03—Rev. 0 to Rev. A Updated Ordering Guide .................................................................5 Change to Analysis Section........................................................... 12 Updated AD8362 Evaluation Board Section .............................. 26 2/03—Revision 0: Initial Version REVISION HISTORY 6/07—Rev. C to Rev. D Changes to Features, General Description.................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 6 Added Figure 21 to Figure 25........................................................ 11 Changes to Equipment Section..................................................... 15 Changes to Circuit Description Section ...................................... 16 Changes to Single-Ended Input Drive Section ........................... 19 Changes to Choosing a Value for CHPF section........................ 21 Changes to Choosing a Value for CLPF section......................... 21 Changes to Figure 57...................................................................... 23 Changes to Figure 58...................................................................... 24 Added Temperature Compensation at Various WiMAX Frequencies up to 3.8 GHz Section .............................................. 24 Changes to Ordering Guide .......................................................... 31 9/05—Rev. B to Rev. C Changes to Specifications................................................................ 3 Changes to Table 3 ........................................................................... 7 Deleted Figure 16 to Figure 18; Renumbered Sequentially ...... 10 Changes to Figure 32 and Figure 33 ............................................ 13 Rev. D | Page 2 of 32 AD8362 SPECIFICATIONS VS = 5 V, T = 25°C, ZO = 50 Ω, differential input drive via balun 1 , VTGT connected to VREF, VOUT tied to VSET, unless otherwise noted. Table 1. Parameter OVERALL FUNCTION Maximum Input Frequency Input Power Range (Differential) Nominal Low End of Range Nominal High End of Range Input Voltage Range (Differential) Nominal Low End of Range Nominal High End of Range Input Power Range (S-Sided) Nominal Low End of Range Nominal High End of Range Input Voltage Range (S-Sided) Nominal Low End of Range Nominal High End of Range Input Power Range (S-Sided) Nominal Low End of Range Nominal High End of Range Output Voltage Range Nominal Low End of Range Nominal High End of Range Output Scaling (Log Slope) Law Conformance Error RF INPUT INTERFACE Input Resistance OUTPUT INTERFACE Available Output Range Absolute Voltage Range Nominal Low End of Range Nominal High End of Range Source/Sink Current Slew Rate Rising Slew Rate Falling Rise Time, 10% to 90% Fall Time, 90% to 10% Wideband Noise VSET INTERFACE Nominal Input Voltage Range Input Resistance Scaling (Log Slope) Scaling (Log Intercept) VOLTAGE REFERENCE Output Voltage Temperature Sensitivity Output Resistance Conditions Min Typ 3.8 dB referred to 50 Ω impedance level, f ≤ 2.7 GHz, into 1:4 balun1 −52 8 RMS voltage at input terminals, f ≤ 2.7 GHz, into input of the device 1.12 1.12 Single-ended drive, CW input, f ≤ 2.7 GHz, into input resistive network 2 −40 0 RMS voltage at input terminals, f ≤ 2.7 GHz 2.23 2.23 Single-ended drive, CW input, f ≥ 2.7 GHz, into matched input network 3 −35 12 4 RL ≥ 200 Ω to ground In general, VS − 0.1 V Over central 60 dB range, f ≤ 2.7 GHz Pin INHI, Pin INLO, ac-coupled, at low frequencies Single-ended drive, with respect to DECL Differential drive Pin VOUT RL ≥ 200 Ω to ground Measurement mode, f = 900 MHz, PIN = −52 dBm Measurement mode, f = 900 MHz, PIN = +8 dBm VOUT held at VS/2, to 1% change CL = open CL = open 0.2 V to 1.8 V, CLPF = Open 1.8 V to 0.2 V, CLPF = Open CLPF = 1000 pF, fSPOT ≤ 100 kHz Pin VSET To ±1 dB error f = 900 MHz f = 900 MHz, into 1:4 balun Pin VREF 25°C −40°C ≤ TA ≤ +85°C 100 4.9 50 ±0.5 100 200 0.1 0.32 3.44 48 60 5 45 0.4 70 0.5 46 −64 −77 1.225 68 50 −60 −73 1.25 0.08 8 3.75 54 −56 −69 1.275 4.9 0.48 3.52 mV V mV/dB dB Ω Ω V V V mA V/μs V/μs ns μs nV/√Hz V kΩ mV/dB dBm dBV V mV/°C Ω dBm dBm mV rms V rms dBm dBm mV rms V rms dBm dBm Max Unit GHz Rev. D | Page 3 of 32 AD8362 Parameter RMS TARGET INTERFACE Nominal Input Voltage Range Input Bias Current Incremental Input Resistance POWER-DOWN INTERFACE Logic Level to Enable Logic Level to Disable Input Current Enable Time Disable Time POWER SUPPLY INTERFACE Supply Voltage Quiescent Current Supply Current 900 MHz Dynamic Range Conditions Pin VTGT Measurement range = 60 dB, to ±1 dB error VTGT = 1.25 V VTGT = 0 V Pin PWDN Logic low enables Logic high disables Logic high Logic low From PWDN low to VOUT within 10% of final value, CLPF = 1000 pF From PWDN high to VOUT within 10% of final value, CLPF = 1000 pF Pin VPOS Min 0.625 −28 −52 52 1 3 230 5 14.5 2.5 4.5 When disabled Error referred to best-fit line (linear regression) ±1.0 dB linearity, CW input ±0.5 dB linearity, CW input Deviation from output at 25°C −40°C < TA < +85°C, PIN = −45 dBm −40°C < TA < +85°C, PIN = −20 dBm −40°C < TA < +85°C, PIN = +5 dBm 46 −64 5.5 dB peak-to-rms ratio (IS95 reverse link) 12.0 dB peak-to-rms ratio (W-CDMA 4 channels) 18.0 dB peak-to-rms ratio (W-CDMA 15 channels) Error referred to best-fit line (linear regression) ±1 dB linearity, CW input ±0.5 dB linearity, CW input Deviation from output at 25°C −40°C < TA < +85°C, PIN = −45 dBm −40°C < TA < +85°C, PIN = −20 dBm −40°C < TA < +85°C, PIN = +5 dBm 5 20 0.2 5.5 22 Typ Max 2.5 Unit V μA μA kΩ V V μA μA ns μs V mA mA 65 62 −1.7 −1.4 −1.0 50 −60 0.2 0.2 0.5 dB dB dB dB dB mV/dB dBm dB dB dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Deviation from CW Response 54 −56 1.9 GHz Dynamic Range 65 62 −0.6 −0.5 −0.3 51 −59 0.2 0.2 0.5 dB dB dB dB dB mV/dB dBm dB dB dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Deviation from CW Response 5.5 dB peak-to-rms ratio (IS95 reverse link) 12.0 dB peak-to-rms ratio (W-CDMA 4 channels) 18.0 dB peak-to-rms ratio (W-CDMA 15 channels) Error referred to best-fit line (linear regression) ±1.0 dB linearity, CW input ±0.5 dB linearity, CW input Deviation from output at 25°C −40°C < TA < +85°C, PIN = −45 dBm −40°C < TA < +85°C, PIN = −20 dBm −40°C < TA < +85°C, PIN = +5 dBm 2.2 GHz Dynamic Range 65 65 −1.8 −1.6 −1.3 50.5 −61 0.2 0.2 0.5 dB dB dB dB dB mV/dB dBm dB dB dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Deviation from CW Response 5.5 dB peak-to-rms ratio (IS95 reverse link) 12.0 dB peak-to-rms ratio (W-CDMA 4 channels) 18.0 dB peak-to-rms ratio (W-CDMA 15 channels) Rev. D | Page 4 of 32 AD8362 Parameter 2.7 GHz Dynamic Range Conditions Error referred to best-fit line (linear regression) ±1.0 dB linearity, CW input ±0.5 dB linearity, CW input Deviation from output at 25°C −40°C < TA < +85°C, PIN = −40 dBm −40°C < TA < +85°C, PIN = −15 dBm −40°C < TA < +85°C, PIN = +5 dBm Min Typ Max Unit 63 62 −5.3 −5.5 −4.8 50.5 −58 0.2 0.2 0.4 dB dB dB dB dB mV/dB dBm dB dB dB Deviation vs. Temperature Logarithmic Slope Logarithmic Intercept Deviation from CW Response 3.65 GHz Dynamic Range Deviation vs. Temperature 5.5 dB peak-to-rms ratio (IS95 reverse link) 12.0 dB peak-to-rms ratio (W-CDMA 4 channels) 18.0 dB peak-to-rms ratio (W-CDMA 15 channels) Single-ended drive3 Error referred to best-fit line (linear regression) ±1.0 dB linearity, CW input ±0.5 dB linearity, CW input Deviation from output at 25°C −40°C < TA < +85°C, PIN = −35 dBm −40°C < TA < +85°C, PIN = −15 dBm −40°C < TA < +85°C, PIN = +10 dBm 51 50 −3 −3.5 −3.5 51.7 −45 dB dB dB dB dB mV/dB dBm Logarithmic Slope Logarithmic Intercept 1 2 1:4 balun transformer, M/A-COM ETC 1.6-4-2-3. See Figure 48. 3 See Figure 50. 4 The limitation of the high end of the power range is due to the test equipment not the device under test. Rev. D | Page 5 of 32 AD8362 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VPOS Input Power (Into Input of Device) Equivalent Voltage Internal Power Dissipation θJA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5.5 V 15 dBm 2 V rms 500 mW 125°C/W 125°C −40°C to +85°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. D | Page 6 of 32 AD8362 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COMM CHPF DECL INHI INLO DECL PWDN COMM 1 2 3 4 5 6 7 8 16 15 ACOM VREF VTGT VPOS VOUT VSET ACOM CLPF 02923-002 AD8362 TOP VIEW (Not to Scale) 14 13 12 11 10 9 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 8 2 3, 6 4, 5 7 9 10, 16 11 12 13 14 15 Mnemonic COMM CHPF DECL INHI , INLO PWDN CLPF ACOM VSET VOUT VPOS V TGT VREF Description Common Connection. Connect via low impedance to system common. Input HPF. Connect to common via a capacitor to determine 3 dB point of input signal high-pass filter. Decoupling Terminals for INHI and INLO. Connect to common via a large capacitance to complete input circuit. Differential Signal Input Terminals. Input Impedance = 200 Ω. Can also be driven single-ended, in which case, the input impedance reduces to 100 Ω. Disable/Enable Control Input. Apply logic high voltage to shut down the AD8362. Connection for Ground Referenced Loop Filter Integration (Averaging) Capacitor. Analog Common Connection for Output Amplifier. Setpoint Input. Connect directly to VOUT for measurement mode. Apply setpoint input to this pin for controller mode. RMS Output. In measurement mode, VOUT is normally connected directly to VSET. Connect to 5 V Power Supply. The logarithmic intercept voltage is proportional to the voltage applied to this pin. The use of a lower target voltage increases the crest factor capacity. Normally connected to VREF. General-Purpose Reference Voltage Output of 1.25 V. Usually connected only to VTGT. Equivalent Circuit Circuit A Circuit B Circuit C Circuit D Circuit E Rev. D | Page 7 of 32 AD8362 EQUIVALENT CIRCUITS VPOS ~35kΩ VSET RAIL-TO-RAIL OUTPUT VSET INTERFACE VPOS DECL VPOS 0.7V 2kΩ ~35kΩ ACOM VOUT ACOM 02923-006 COMM CLPF 02923-004 500Ω COMM COMM INHI 100Ω VGA 100Ω INLO Figure 4. Circuit B Figure 6. Circuit D VPOS 50kΩ VTGT 50kΩ SOURCE ONLY REF BUF ~0.35V VTGT INTERFACE GAIN = 0.12 02923-005 VPOS VOUT 13kΩ 5kΩ COMM ACOM 02923-007 VPOS 02923-003 ACOM DECL COMM COMM Figure 3. Circuit A Figure 5. Circuit C Figure 7. Circuit E Rev. D | Page 8 of 32 AD8362 TYPICAL PERFORMANCE CHARACTERISTICS 4.5 4.0 3.5 3.0 100MHz 2200MHz 4.0 3.6 3.2 2.8 VOUT (V) 3.0 2.4 1.8 ERROR IN VOUT (dB) 02923-013 02923-012 –40°C 1.2 0.6 0 –0.6 VOUT (V) 2.5 2.0 1.5 1.0 0.5 900MHz 2700MHz 2.4 2.0 1.6 1.2 0.8 0.4 +25°C –40°C +85°C +25°C +85°C –1.2 –1.8 –2.4 0 5 INPUT AMPLITUDE (dBm) 02923-008 0 5 10 15 Figure 8. Output Voltage (VOUT) vs. Input Amplitude (dBm), Frequencies: 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, and 2700 MHz; Sine Wave, Differential Drive Figure 11. VOUT and Law Conformance vs. Input Amplitude, Frequency 1900 MHz, Sine Wave, Temperatures: −40°C, +25°C, and +85°C 4.0 3.0 2.4 1.8 ERROR IN VOUT (dB) 3.0 2.5 2.0 1.5 3.6 3.2 2.8 VOUT (V) 100MHz –40°C 1.2 0.6 0 ERROR IN VOUT (dB) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 2.4 2.0 1.6 1.2 0.8 0.4 +85°C +25°C 0 5 +25°C +85°C –0.6 –1.2 2200MHz 900MHz 1900MHz –40°C –1.8 –2.4 –3.0 10 15 0 5 10 15 INPUT AMPLITUDE (dBm) Figure 9. Logarithmic Law Conformance vs. Input Amplitude, Frequencies: 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, and 2700 MHz; Sine Wave, Differential Drive 4.0 3.6 3.2 2.8 VOUT (V) 02923-009 2700MHz –3.0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBm) Figure 12. VOUT and Law Conformance vs. Input Amplitude, Frequency 2200 MHz, Sine Wave, Temperatures: −40°C, +25°C, and +85°C 3.0 2.4 4.0 3.5 1.8 –40°C ERROR IN VOUT (dB) 1.2 0.6 3.0 2.5 VOUT (V) CW 2.4 +25°C 2.0 1.6 1.2 0.8 0.4 0 +25°C –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBm) 0 5 +85°C +85°C –40°C IS95 REVERSE LINK W-CDMA 8-CHANNEL W-CDMA 15-CHANNEL 0 –0.6 –1.2 –1.8 –2.4 2.0 1.5 1.0 0.5 02923-010 –3.0 10 15 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBm) 0 5 10 15 Figure 10. VOUT and Law Conformance vs. Input Amplitude, Frequency 900 MHz, Sine Wave, Temperatures: −40°C, +25°C, and +85°C Figure 13. VOUT vs. Input Amplitude with Different Waveforms, CW, IS95 Reverse Link, W-CDMA 8-Channel, W-CDMA 15-Channel, Frequency 900 MHz Rev. D | Page 9 of 32 02923-011 1900MHz 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBm) –3.0 10 15 AD8362 3.0 2.5 2.0 1.5 4.0 3.5 3.0 W-CDMA 8-CHANNEL IS95 REVERSE LINK CW 2.5 ERROR IN VOUT (dB) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 VOUT (V) W-CDMA 15-CHANNEL 02923-014 2.0 1.5 1.0 0.5 02923-017 –3.0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBm) 0 5 10 15 0 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBm) 0 5 10 Figure 14. Output Error from CW Linear Reference vs. Input Amplitude with Different Waveforms, CW, IS95 Reverse Link, W-CDMA 8-Channel, W-CDMA 15-Channel, Frequency 900 MHz, VTGT = 1.25 V 3.0 2.5 2.0 1.5 Figure 17. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean, Sine Wave, Frequency 1900 MHz, Part-to-Part Variation 3.0 2.5 2.0 ERROR IN VOUT (dB) –40°C ERROR IN VOUT (dB) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 W-CDMA 4-CHANNEL CW W-CDMA 8-CHANNEL 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 02923-015 W-CDMA 15-CHANNEL +25°C +85°C 0 5 10 02923-018 02923-019 –3.0 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBm) 0 5 10 –3.0 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBm) Figure 15. Output Error from CW Linear Reference vs. Input Amplitude with Different W-CDMA Channel Loading, 4-Channel, 8-Channel, 15-Channel, Frequency 2200 MHz, VTGT = 1.25 V 4.0 3.5 3.0 2.5 Figure 18. Logarithmic Law Conformance vs. Input Amplitude, 3 Sigma to Either Side of Mean, Sine Wave, Frequency 900 MHz, Temperatures: −40°C, +25°C, and +85°C 3.0 2.5 2.0 1.5 ERROR IN VOUT (dB) –45°C 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 +85°C +25°C VOUT (V) 2.0 1.5 1.0 0.5 02923-016 –2.5 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBm) 0 5 10 0 –3.0 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBm) 0 5 10 Figure 16. VOUT vs. Input Amplitude, 3 Sigma to Either Side of Mean, Sine Wave, Frequency 900 MHz, Part-to-Part Variation Figure 19. Logarithmic Law Conformance vs. Input Amplitude, 3 Sigma to Either Side of Mean, Sine Wave, Frequency 1900 MHz, Temperatures: −40°C, +25°C, and +85°C Rev. D | Page 10 of 32 AD8362 3.0 2.5 2.0 1.5 ERROR IN VOUT (dB) 3.0 2.5 4 2 0 –2 –4 –6 –8 20 4.0 –40°C 3.5 +85°C +25°C –40°C 8 6 1.0 VOUT (V) 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 +85°C +25°C 02923-020 2.0 1.5 1.0 0.5 0 –60 0 5 10 –50 –40 –30 –20 –10 0 10 INPUT AMPLITUDE (dBm) INPUT AMPLITUDE (dBm) Figure 20. Logarithmic Law Conformance vs. Input Amplitude, 3 Sigma to Either Side of Mean, Sine Wave, Frequency 2200 MHz, Temperatures: −40°C, +25°C, and +85°C 4.0 3.5 3.0 2.5 +85°C +25°C –40°C 8 6 4 Figure 23. VOUT and Law Conformance vs. Input Amplitude for 15 Devices, Frequency 2800 MHz, Sine Wave, Temperatures: −40°C, +25°C, and +85°C, No Temperature Compensation, Single-Ended Drive, See Figure 50 4.0 3.5 3.0 8 +85°C +25°C –40°C 6 4 2 0 –2 –4 –6 –8 20 ERROR (dB) 2.0 1.5 1.0 0.5 0 –60 0 –2 –4 –6 –8 20 2.0 1.5 1.0 0.5 0 –60 02923-021 ERROR (dB) ERROR (dB) 02923-025 2 2.5 VOUT (V) VOUT (V) –50 –40 –30 –20 –10 0 10 –50 –40 –30 –20 –10 0 10 INPUT AMPLITUDE (dBm) INPUT AMPLITUDE (dBm) Figure 21. VOUT and Law Conformance vs. Input Amplitude for 15 Devices, Frequency 2350 MHz, Sine Wave, Temperatures: −40°C, +25°C, and +85°C, No Temperature Compensation, Single-Ended Drive, See Figure 50 4.0 3.5 3.0 2.5 +85°C +25°C –40°C 8 6 4 2 0 –2 –4 –6 –8 20 Figure 24. VOUT and Law Conformance vs. Input Amplitude for 15 Devices, Frequency 3450 MHz, Sine Wave, Temperatures: −40°C, +25°C, and +85°C, No Temperature Compensation, Single-Ended Drive, See Figure 50 4.0 3.5 3.0 8 6 4 2 0 –2 –4 –6 –8 20 ERROR (dB) 2.5 VOUT (V) 2.0 1.5 1.0 0.5 0 –60 VOUT (V) 2.0 1.5 1.0 0.5 0 –60 –50 –40 –30 –20 –10 0 10 02923-022 –50 –40 –30 –20 –10 0 10 INPUT AMPLITUDE (dBm) INPUT AMPLITUDE (dBm) Figure 22. VOUT and Law Conformance vs. Input Amplitude for 15 Devices, Frequency 2600 MHz, Sine Wave, Temperatures: −40°C, +25°C, and +85°C, No Temperature Compensation, Single-Ended Drive, See Figure 50 Figure 25. VOUT and Law Conformance vs. Input Amplitude for 15 Devices, Frequency 3650 MHz, Sine Wave, Temperatures: −40°C, +25°C, and +85°C, No Temperature Compensation, Single-Ended Drive, See Figure 50 Rev. D | Page 11 of 32 02923-024 02923-023 –3.0 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 ERROR (dB) AD8362 52.0 2.0 1.5 51.5 +85°C CHANGE IN INTERCEPT (dB) 1.0 1900MHz 0.5 0 –0.5 –1.0 –1.5 02923-029 02923-031 02923-030 51.0 SLOPE (mV) +25°C 900MHz 50.5 –40°C 50.0 49.5 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 49.0 02923-026 2200MHz –2.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) FREQUENCY (MHz) Figure 26. Logarithmic Slope vs. Frequency, Temperatures: −40°C, +25°C, and +85°C –53 –54 –55 –56 INTERCEPT (dBm) Figure 29. Change in Logarithmic Intercept vs. Temperature, 3 Sigma to Either Side of Mean, Frequencies: 900 MHz, 1900 MHz, and 2200 MHz 100 +85°C 80 –57 –59 –60 –61 –62 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 HITS 02923-027 –58 +25°C 60 –40°C 40 20 –63 0 48 49 FREQUENCY (MHz) 50 51 SLOPE (mV/dB) 52 53 Figure 27. Logarithmic Intercept vs. Frequency, Temperatures: −40°C, +25°C, and +85°C 3.0 2.5 2.0 1.5 900MHz Figure 30. Slope Distribution, Frequency 900 MHz 80 70 1900MHz CHANGE IN SLOPE (mV) 60 50 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 HITS 2200MHz 02923-028 40 30 20 10 –3.0 –40 –30 –20 –10 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 80 90 0 –61.0 –60.5 –60.0 –59.5 –59.0 INTERCEPT (dBm) –58.5 –58.0 Figure 28. Change in Logarithmic Slope vs. Temperature, 3 Sigma to Either Side of Mean, Frequencies: 900 MHz, 1900 MHz, and 2200 MHz Figure 31. Logarithmic Intercept Distribution, Frequency 900 MHz Rev. D | Page 12 of 32 AD8362 5.0 4.5 4.0 3.5 VOUT (V) 6 5.0 4.5 4.0 RF BURST ENABLE (V) 6 4 RF BURST ENABLE 2V/DIV 4 2 0 2V/DIV 2 0 –2 3.5 VOUT VOUT (V) 3.0 2.5 2.0 1.5 +2dBm –2 –10dBm –20dBm –30dBm –4 –6 –8 –10 –12 +2dBm –10dBm –20dBm –30dBm 3.0 2.5 2.0 1.5 1.0 0.5 –4 –6 –8 –10 –12 0.5V/DIV 1.0 0.5 0 0 2 4 6 8 10 12 TIME (µs) 14 16 18 0.5V/DIV 02923-032 0 2 4 6 8 10 12 TIME (ms) 14 16 18 Figure 32. Output Response to RF Burst Input for Various RF Input Levels, Carrier Frequency 900 MHz, CLPF = Open 5.0 4.5 4.0 3.5 6 Figure 35. Output Response Using Power-Down Mode for Various RF Input Levels, Carrier Frequency 900 MHz, CLPF = 0.1 μF 5.5 5.0 4.5 RF BURST ENABLE (V) 6 VPOS RF BURST ENABLE 2V/DIV 4 2 0 2V/DIV 4 2 0 –2 –4 4.0 +2dBm VOUT (V) 2.5 2.0 1.5 1.0 –10dBm VOUT (V) 3.0 –2 3.5 3.0 2.5 VOUT –4 –6 –8 –10 –20dBm –30dBm 1V/DIV 2.0 1.5 1.0 02923-033 +2dBm –10dBm –20dBm –30dBm –6 –8 –10 –12 0.5V/DIV 0.5 0 0 2 4 6 8 10 12 TIME (ms) 14 16 18 –12 –14 20 0 2 4 6 8 10 12 TIME (ms) 14 16 18 Figure 33. Output Response to RF Burst Input for Various RF Input Levels, Carrier Frequency 900 MHz, CLPF = 0.1 μF Figure 36. Output Response to Gating on Power Supply for Various RF Input Levels, Carrier Frequency 900 MHz, CLPF = 0 5.0 4.5 6 POWERDOWN 4.0 PIN 3.5 2V/DIV 4 2 VOUT VOUT (V) +2dBm –10dBm –20dBm 0 –2 –4 –6 –8 –10 –12 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 TIME (µs) 14 16 18 POWER-DOWN PIN (V) 100MHz 3GHz 0.5V/DIV –30dBm 02923-034 Figure 34. Output Response Using Power-Down Mode for Various RF Input Levels, Carrier Frequency 900 MHz, CLPF = 0 Figure 37. INHI, INLO Differential Input Impedance, 100 MHz to 3 GHz Rev. D | Page 13 of 32 02923-037 –14 20 02923-036 0 –14 20 POWER-DOWN PIN (V) 02923-035 –14 20 0 –14 20 POWER-DOWN PIN (V) AD8362 5 0 300 CHANGE IN VREF (mV) –5 –10 –15 –20 –25 –30 250 200 HITS –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 02923-038 150 100 50 TEMPERATURE (°C) 1.235 1.240 1.245 1.250 1.255 1.260 VREF (V) 1.265 1.270 Figure 38. Change in VREF vs. Temperature, 3 Sigma to Either Side of Mean Figure 39. VREF Distribution Rev. D | Page 14 of 32 02923-039 0 1.230 AD8362 CHARACTERIZATION SETUP EQUIPMENT The general hardware configuration used for most of the AD8362 characterization is shown in Figure 40. The signal source is a Rohde & Schwarz SMIQ03B. A 1:4 balun transformer is used to transform the single-ended RF signal to differential form. For frequencies above 3.0 GHz, an Agilent 8521A signal source was used. For the response measurements in Figure 32 and Figure 33, the configuration shown in Figure 41 is used. For Figure 34 and Figure 35, the configuration shown in Figure 42 is used. For Figure 36, the configuration shown in Figure 43 is used. CHARACTERIZATION BOARD 3dB RFIN VOUT TEK TDS5104 SCOPE TEK P5050 VOLTAGE PROBE C1 AD8362 COMM CHPF DECL ACOM VREF VTGT VPOS VOUT VSET ACOM CLPF 02923-041 SMT03 SIGNAL GENERATOR RF 50Ω INHI 3dB BALUN C2 C3 INLO DECL PWDN COMM HPE3631A POWER SUPPLY C4 AD8362 Figure 41. Response Measurement Setup for Modulated Pulse MULTIMETER HP34401A TEK TDS5104 SCOPE TEK P5050 VOLTAGE PROBE C1 02923-040 SMIQ03B RF SOURCE AD8362 COMM CHPF DECL ACOM VREF VTGT VPOS VOUT VSET ACOM CLPF C4 HPE3631A POWER SUPPLY PC CONTROLLER Figure 40. Primary Characterization Setup SMT03 SIGNAL GENERATOR RF 50Ω HP8112A PULSE GENERATOR INHI 3dB BALUN INLO C2 C3 DECL PWDN COMM ANALYSIS The slope and intercept are derived using the coefficients of a linear regression performed on data collected in its central operating range. Error is stated in two forms: error from the linear response to the CW waveform and output delta from 25°C performance. The error from linear response to the CW waveform is the decibel difference in output from the ideal output defined by the conversion gain and output reference. This is a measure of the linearity of the device response to both CW and modulated waveforms. The error in dB is calculated by Error (dB ) = VOUT − Slope × (PIN − PZ ) Slope Figure 42. Response Measurement Setup for Power-Down Step AD811 732Ω 50Ω HP8112A PULSE GENERATOR (1) AD8362 COMM C1 CHPF DECL INHI 3dB BALUN INLO C2 C3 SMT03 SIGNAL GENERATOR RF 50Ω DECL PWDN COMM VOUT VSET ACOM C4 ACOM VREF VTGT VPOS 0.01µF TEK TDS5104 SCOPE where PZ is the x intercept, expressed in dBm. Error from the linear response to the CW waveform is not a measure of absolute accuracy because it is calculated using the slope and intercept of each device. However, it verifies the linearity and the effect of modulation on the device response. Error from the 25°C performance uses the performance of a given device and waveform type as the reference; it is predominantly a measurement of output variation with temperature. TEK P5050 VOLTAGE PROBE 100pF Figure 43. Response Measurement Setup for Gated Supply Rev. D | Page 15 of 32 02923-043 CLPF 02923-042 AD8362 CIRCUIT DESCRIPTION The AD8362 is a fully calibrated, high accuracy, rms-to-dc converter providing a measurement range of over 65 dB. It is capable of operating from signals as low in frequency as a few hertz to at least 3.8 GHz. Unlike earlier rms-to-dc converters, the response bandwidth is completely independent of the signal magnitude. The −3 dB point occurs at about 3.5 GHz. The capacity of this part to accurately measure waveforms having a high peak-to-rms ratio (crest factor) is independent of either the signal frequency or its absolute magnitude, over a wide range of conditions. This unique combination allows the AD8362 to be used as a calibrated RF wattmeter covering a power ratio of >1,000,000:1, a power controller in closed-loop systems, a general-purpose rms-responding voltmeter, and in many other low frequency applications. The part comprises the core elements of a high performance AGC loop (see Figure 44), laser-trimmed during manufacturing to close tolerances while fully operational at a test frequency of 100 MHz. Its linear, wideband VGA provides a general voltage gain, GSET; this can be controlled in a precisely exponential (linearin-dB) manner over the full 68 dB range from −25 dB to +43 dB by a voltage, VSET. However, to provide adequate guardbanding, only the central 60 dB of this range, from −21 dB to +39 dB, is normally used. The Adjusting VTGT to Accommodate Signals with Very High Crest Factors section shows how this basic range can be shifted up or down. –25dB TO +43dB INHI VGA INLO VSIG X2 X2 ITGT × 0.06 VATG ACOM AMPLITUDE TARGET FOR VSIG VTGT The VGA gain has the form GSET = GO exp(−VSET/VGNS) where: GO is a basic fixed gain. VGNS is a scaling voltage that defines the gain slope (the dB change per volt). Note that the gain decreases with VSET. The VGA output is VSIG = GSETVIN = GOVIN exp(VSET/VGNS) where VIN is the ac voltage applied to the input terminals of the AD8362. As explained in the Recommended Input Coupling section, the input drive can either be single-sided or differential, although dynamic range is maximized with a differential input drive. The effect of high frequency imbalances when using a single-sided drive is less apparent at low frequencies (from 50 Hz to 500 MHz), but the peak input voltage capacity is always halved relative to differential operation. (3) (2) SQUARE LAW DETECTION The output of the variable gain amplifier (VSIG) is applied to a wideband square law detector, which provides a true rms response to this alternating signal that is essentially independent of waveform. Its output is a fluctuating current (ISQU) that has a positive mean value. This current is integrated by an on-chip capacitance (CF), which is usually augmented by an external capacitance (CLPF) to extend the averaging time. The resulting voltage is buffered by a gain of 5, dc-coupled amplifier whose rail-to-rail output (VOUT) can be used for either measurement or control purposes. In most applications, the AGC loop is closed via the setpoint interface pin, VSET, to which the VGA gain control voltage on VOUT is applied. In measurement modes, the closure is direct and local by a simple connection from the output of the VOUT pin to the VSET pin. In controller modes, the feedback path is around some larger system, but the operation is the same. The fluctuating current (ISQU) is balanced against a fixed setpoint target current (ITGT) using current mode subtraction. With the exact integration provided by the capacitor(s), the AGC loop equilibrates when MEAN(ISQU) = ITGT (4) MATCH WIDEBAND SQUARERS ISQU CHPF OFFSET NULLING GSET CF OUTPUT FILTER VOUT VSET SETPOINT INTERFACE CLPF INTERNAL RESISTORS SET BUFFER GAIN TO 5 VREF 1.25V BAND GAP REFERENCE CLPF EXTERNAL 02923-044 ACOM Figure 44. Basic Structure of the AD8362 The current, ITGT, is provided by a second-reference squaring cell whose input is the amplitude-target voltage VATG. This is a fraction of the voltage VTGT applied to a special interface, which accepts this input at the VTGT pin. Because the two squaring cells are electrically identical and are carefully implemented in the IC, process and temperature-dependent variations in the detailed behavior of the two square-law functions cancel. Accordingly, VTGT (and its fractional part VATG) determines the output that must be provided by the VGA for the AGC Rev. D | Page 16 of 32 AD8362 loop to settle. Because the scaling parameters of the two squarers are accurately matched, it follows that Equation 4 is satisfied only when MEAN(VSIG2) = VATG2 (5) In a formal solution, extract the square root of both sides to provide an explicit value for the root-mean-square (rms) value. However, it is apparent that by forcing this identity through varying the VGA gain and extracting the mean value by the filter provided by the capacitor(s), the system inherently establishes the relationship rms(VSIG) = VATG Substituting the value of VSIG from Equation 3, rms[GOVIN exp(−VSET/VGNS)] = VATG (7) As a measurement device, VIN is the unknown quantity and all other parameters can be fixed by design. To solve Equation 7, rms[GOVIN/VATG] = exp(VSET/VGNS) therefore, VOUT (V) At high frequencies, signal levels are commonly specified in power terms. In these circumstances, the source and termination impedances are an essential part of the overall scaling. For this condition, the output voltage can be expressed as VOUT = SLOPE × (PIN − PZ) where PIN and the intercept PZ are expressed in dBm. In practice, the response deviates slightly from the ideal straight line suggested by Equation 11. This deviation is called the law conformance error. In defining the performance of high accuracy measurement devices, it is customary to provide plots of this error. In general terms, it is computed by extracting the best straight line to the measured data using linear regression over a substantial region of the dynamic range and under clearly specified conditions. 3.0 3.8 3.5 3.2 2.9 2.6 2.5 (11) (6) (8) (9) –40°C 2.0 1.5 1.0 0.5 0 VSET = VGNS log[rms(VIN)/VZ] The quantity VZ = VATG/GO is defined as the intercept voltage because VSET must be 0 when rms (VIN) = VZ. When connected as a measurement device, the output of the buffer is tied directly to VSET, which closes the AGC loop. Making the substitution VOUT = VSET and changing the log base to 10, as needed in a decibel conversion, VOUT = VSLP log10[rms(VIN)/VZ] where VSLP is the slope voltage, that is, the change in output voltage for each decade of change in the input amplitude. Note that VSLP = VGNS log (10) = 2.303 VGNS. 2.3 2.0 1.7 1.4 1.1 0.8 0.5 0.2 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 INPUT AMPLITUDE (dBm) 0 5 +25°C –40°C +85°C –0.5 –1.0 +25°C +85°C –1.5 –2.0 –2.5 02923-045 –3.0 10 15 (10) Figure 45. Output Voltage and Law Conformance Error @ TA = −40°C, +25°C, and +85°C In the AD8362, VSLP is laser-trimmed to 1 V using a 100 MHz test signal. Because a decade corresponds to 20 dB, this slope can also be stated as 50 mV/dB. The Altering the Slope section explains how the effective value of VSLP can be altered by the user. The intercept, VZ, is also laser-trimmed to 224 μV (−60 dBm relative to 50 Ω). In an ideal system, VOUT would cross zero for an rms input of that value. In a single-supply realization of the function, VOUT cannot run fully down to ground; here, VZ is the extrapolated value. Figure 45 shows the output of the circuit of Figure 47 over the full input range. The agreement with the ideal function (law conformance) is also shown. This was determined by linear regression on the data points over the central portion of the transfer function for the +25°C data. The error at −40°C, +25°C, and +85°C was then calculated by subtracting the ideal output voltage at each input signal level from the actual output and dividing this quantity by the mean slope of the regression equation to provide a measurement of the error in decibels (scaled on the right-hand axis of Figure 45). The error curves generated in this way reveal not only the deviations from the ideal transfer function at a nominal temperature, but also the additional errors caused by temperature changes. Notice that there is a small temperature dependence in the intercept (the vertical position of the error plots). Figure 45 further reveals a periodic ripple in the conformance curves. This is due to the interpolation technique used to select the signals from the attenuator, not only at discrete tap points, but anywhere in between, thus providing continuous attenuation values. The selected signal is then applied to the 3.5 GHz, 40 dB fixed gain amplifier in the remaining stages of the VGA of the AD8362. VOLTAGE VS. POWER CALIBRATION The AD8362 can be used as an accurate rms voltmeter from arbitrarily low frequencies to microwave frequencies. For low frequency operation, the input is usually specified either in volts rms or in dBV (decibels relative to 1 V rms). Rev. D | Page 17 of 32 ERROR IN VOUT (dB) AD8362 An approximate schematic of the signal input section of the AD8362 is shown in Figure 46. The ladder attenuator is composed of 11 sections (12 taps), each of which progressively attenuates the input signal by 6.33 dB. Each tap is connected to a variable transconductance cell whose bias current determines the signal weighting given to that tap. The interpolator determines which stages are active by generating a discrete set of bias currents, each having a Gaussian profile. These are arranged to move from left to right, thereby determining the attenuation applied to the input signal as the gain is progressively lowered over the 69.3 dB range under control of the VSET input. The detailed manner in which the transconductance of adjacent stages varies as the virtual tap point slides along the attenuator accounts for the ripple observed in the conformance curves. Its magnitude is slightly temperature dependent and also varies with frequency (see Figure 10, Figure 11, and Figure 12). Notice that the system’s responses to signal inputs at INHI and INLO are not completely independent; these pins do not constitute a fully floating differential input. GAUSSIAN INTERPOLATOR ATTENUATION CONTROL TO FIXED GAIN STAGE most high frequency applications. When using the AD8362 in low frequency applications, the corner frequency can be reduced as needed by the addition of a capacitor from the CHPF pin to ground having a nominal value of 200 μF/Hz. For example, to lower the high-pass corner frequency to 150 Hz, a capacitance of 1.33 μF is required. The offset voltage varies depending on the actual gain at which the VGA is operating, and thus on the input signal amplitude. Baseline variations of this sort are a common aspect of all VGAs, but they are more evident in the AD8362 because of the method of its implementation, which causes the offsets to ripple along the gain axis with a period of 6.33 dB. When an excessively large value of CHPF is used, the offset correction process can lag the more rapid changes in the VGA’s gain, which in turn can increase the time required for the loop to fully settle for a given steady input amplitude. TIME-DOMAIN RESPONSE OF THE CLOSED LOOP The external low-pass averaging capacitance (CLPF) added at the output of the squaring cell is chosen to provide adequate filtering of the fluctuating detected signal. The optimum value depends on the application; as a guideline, a value of roughly 900 μF/Hz should be used. For example, a capacitance of 5 μF provides adequate filtering down to 180 Hz. Note that the fluctuation in the quasi-dc output of a squaring cell operating on a sine wave input is a raised cosine at twice the signal frequency, easing this filtering function. In the standard connections for the measurement mode, the VSET pin is tied to VOUT. For small changes in input amplitude (a few decibels), the time-domain response of this loop is essentially linear, with a 3 dB low-pass corner frequency of nominally fLP = 1/(CLPF × 1.1 kΩ). Internal time delays around this local loop set the minimum recommended value of this capacitor to about 300 pF, resulting in fLP = 3 MHz. When large and abrupt changes of input amplitude occur, the loop response becomes nonlinear and exhibits slew rate limitations. gm INHI gm gm gm DECL STAGE 1 6.33dB STAGE 2 6.33dB STAGE 11 6.33dB Figure 46. Simplified Input Circuit OFFSET ELIMINATION To address the small dc offsets that arise in the VGA, an offsetnulling loop is used. The high-pass corner frequency of this loop is internally preset to 1 MHz, which is sufficiently low for Rev. D | Page 18 of 32 02923-046 INLO AD8362 OPERATION IN RF MEASUREMENT MODE BASIC CONNECTIONS Basic connections for operating the AD8362 in measurement mode are shown in Figure 47. While the AD8362 requires a single supply of nominally 5 V, its performance is essentially unaffected by variations of up to ±10%. The supply is connected to the VPOS pin using the decoupling network also displayed in Figure 47. The capacitors used in this network must provide a low impedance over the full frequency range of the input and should be placed as close as possible to the VPOS pin. Two different capacitors are used in parallel to reduce the overall impedance because these have different resonant frequencies. The measurement accuracy is not critically dependent on supply decoupling because the high frequency signal path is confined to the relevant input pins. Lead lengths from both DECL pins to ground and from INHI/INLO to the input coupling capacitors should be as short as possible. All COMM pins should also connect directly to the ground plane. To place the device in measurement mode, connect VOUT to VSET and connect VTGT directly to VREF. The balun outputs must be ac-coupled to the input of the AD8362. The balun used in this example (M/A-COM ETC 1.6-4-2-3) is specified for operation from 0.5 GHz to 2.5 GHz. If a center-tapped, flux-coupled transformer is used, connect the center tap to the DECL pins, which are biased to the same potential as the inputs (~3.6 V). At lower frequencies where impedance matching is not necessary, the AD8362 can be driven from a low impedance differential source, remembering the inputs must be ac-coupled. Choosing Input Coupling Capacitors As noted, the inputs must be ac-coupled. The input coupling capacitors combine with the 200 Ω input impedance to create an input high pass corner frequency equal to fHP = 1/(200 × π × CC) (12) Typically, fHP should be set to at least one tenth the lowest input frequency of interest. Single-Ended Input Drive As previously noted, the input stages of the AD8362 are optimally driven from a fully balanced source, which should be provided wherever possible. In many cases, unbalanced sources can be applied directly to one or the other of the two input pins. The chief disadvantage of this driving method is a 10 dB to 15 dB reduction in dynamic range at frequencies above 500 MHz. Figure 48 illustrates one of many ways of coupling the signal source to the AD8362. Because the input pins are biased to about 3.6 V (for VS = 5 V), dc-blocking capacitors are required when driving from a grounded source. For signal frequencies >5 MHz, a value of 1 nF is adequate. While either INHI or INLO can be used, INHI is chosen here. AD8362 1 COMM DEVICE DISABLE The AD8362 is disabled by a logic high on the PWDN pin, which can be directly grounded for continuous operation. When enabled, the supply current is nominally 20 mA and essentially independent of supply voltage and input signal strength. When powered down by a logic low on PWDN, the supply current is reduced to 230 μA. RECOMMENDED INPUT COUPLING The full dynamic range of the AD8362, particularly at very high frequencies (above 500 MHz), is realized only when the input is presented to it in differential (balanced) form. In Figure 47, a transmission line balun is used at the input. Having a 1:4 impedance ratio (1:2 turns ratio), the 200 Ω differential input resistance of the AD8362 becomes 50 Ω at the input to the balun. VS 5V @ 24mA ACOM 16 VREF 15 VTGT 14 VPOS 13 VOUT 12 VSET 11 ACOM 10 02923-048 0.01µF 1nF RF INPUT 100Ω 1nF 1nF 1nF 2 CHPF 3 DECL 4 INHI 5 INLO 6 DECL 7 PWDN 8 COMM AD8362 1:4 Z-RATIO C10 1000pF 1 C8 1000pF C4 C6 1nF 100pF COMM CHPF DECL INHI INLO DECL PWDN COMM ACOM 16 VREF 15 VTGT 14 VPOS 13 VOUT 12 VSET 11 ACOM 10 C3 0.1µF 2 3 4 C1 0.1µF SIGNAL INPUT Z = 50Ω C2 1nF VOUT CLPF 9 T1 ETC1.6-4-2-3 C5 100pF C7 1nF 5 6 7 8 Figure 48. Input Coupling from a Single-Ended 50 Ω Source Figure 47. Basic Connections for RF Power Measurement Rev. D | Page 19 of 32 02923-047 CLPF 9 AD8362 An external 100 Ω shunt resistor combines with the internal 100 Ω single-ended input impedance to provide a broadband 50 Ω match. The unused input (in this case, INLO) is ac-coupled to ground. Figure 49 shows the transfer function of the AD8362 at various frequencies when the RF input is driven singleended. The results show that transfer function linearity at the top end of the range is degraded by the single-ended drive. 4.0 3.5 3.0 2.5 VOUT (V) 3.00 2.75 2.50 2.25 2.00 VOUT (V) 3.0 2.8GHz 3.45GHz 3.65GHz 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –5 0 5 10 15 02923-051 1.75 1.50 1.25 1.00 2.0 450MHz 1900MHz 2500MHz 900MHz 2140MHz 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 02923-049 0.75 0.50 0.25 ERROR (dB) 0 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –3.0 INPUT AMPLITUDE (dBm) 2.0 1.5 1.0 0.5 0 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 PIN (dBm) Figure 51. Transfer Function at Various Frequencies ≥2.7 GHz when the RF Input is Driven Single-Ended OPERATION AT LOW FREQUENCIES In conventional rms-to-dc converters based on junction techniques, the effective signal bandwidth is proportional to the signal amplitude. In contrast, the 3.5 GHz VGA bandwidth in the AD8362 is independent of its gain. Because this amplifier is internally dc-coupled, the system is also used as a high accuracy rms voltmeter at low frequencies, retaining its temperaturestable, decibel-scaled output (for example, in seismic, audio, and sonar instrumentation). While the AD8362 can be operated at arbitrarily low frequencies, an ac-coupled input interface must be maintained. In such cases, the input coupling capacitors should be large enough so that the lowest frequency components of the signal to be included in the measurement are minimally attenuated. For example, for a 3 dB reduction at 1.5 kHz, capacitances of 1 μF are needed because the input resistance is 100 Ω at each input pin (200 Ω differentially), and the calculation is 1/(2π × 1.5 kΩ × 100) = 1 μF. In addition, to lower the high-pass corner frequency of the VGA, a large capacitor must be connected between the CHPF pin and ground (see the Choosing a Value for CHPF section). More information on the operation of the AD8362 and other RF power detectors at low frequency is available in Application Note AN-691: Operation of RF Detector Products at Low Frequency. 0 5 –2.0 10 Figure 49. Transfer Function at Various Frequencies when the RF Input is Driven Single-Ended AD8362 1 0.01µF 1nF RF INPUT 2.7nH 1nF 1nF 1nF COMM CHPF DECL INHI INLO DECL PWDN COMM ACOM 16 VREF 15 VTGT 14 VPOS 13 VOUT 12 VSET 11 ACOM 10 02923-050 2 3 4 4.7nH 5 6 7 8 CLPF 9 Figure 50. Input Matching for Operation at Frequencies ≥2.7 GHz For operation at frequencies ≥2.7 GHz, some additional components are required to match the AD8362 input to 50 Ω (see Figure 50). As the operating frequency increases, there is also corresponding shifting in the operating power range (see Figure 51). Rev. D | Page 20 of 32 ERROR (dB) AD8362 CHOOSING A VALUE FOR CHPF The 3.5 GHz VGA of the AD8362 includes an offset cancellation loop, which introduces a high-pass filter effect in its transfer function. To properly measure the amplitude of the input signal, the corner frequency (fHP) of this filter must be well below that of the lowest input signal in the desired measurement bandwidth frequency. The required value of the external capacitor is given by CHPF = 200 μF/2(π)fHP (fHP in Hz) (13) For operation at frequencies as low as 100 kHz, set fHP to approximately 25 kHz (CHPF = 8 nF). For frequencies above approximately 2 MHz, no external capacitance is required because there is adequate internal capacitance on this node. modulation, which generates fluctuations in the output of the AD8362. Increasing CLPF also increases the step response of the AD8362 to a change at its input. Table 4 shows recommended values of CLPF for popular modulation schemes. In each case, CLPF is increased until residual output noise falls below 50 mV. A 10% to 90% step response to an input step is also listed. Where the increased response time is unacceptably high, CLPF must be reduced. If the output of the AD8362 is sampled by an ADC, averaging in the digital domain can further reduce the residual noise. Figure 52 shows how residual ripple and rise/fall time vary with filter capacitance when the AD8362 is driven by a single carrier W-CDMA signal (Test Model 1-64) at 2140 MHz. 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1.0 CHOOSING A VALUE FOR CLPF RESIDUAL RIPPLE (mV p-p) In the standard connections for the measurement mode, the VSET pin is tied to VOUT. For small changes in input amplitude such as a few decibels, the time-domain response of this loop is essentially linear with a 3 dB low-pass corner frequency of nominally fLP = 1/(CLPF × 1.1 kΩ). Internal time delays around this local loop set the minimum recommended value of this capacitor to about 300 pF, making fLP = 3 MHz. For operation at lower signal frequencies, or whenever the averaging time needs to be longer, use CLPF = 900 μF/2(π)fLP (fLP in Hz) (14) When the input signal exhibits large crest factors, such as a CDMA or W-CDMA signal, CLPF must be much larger than might seem necessary. This is due to the presence of significant low frequency components in the complex, pseudorandom RESIDUAL RIPPLE (mV p-p) FALL TIME (ms) RISE TIME (ms) RISE/FALL TIME (ms) 02923-052 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 FILTER CAPACITANCE (µF) 0.8 0.9 Figure 52. Residual Ripple, Rise and Fall Time vs. Filter Capacitance, Single Carrier W-CDMA Input Signal, Test Model 1-64 Table 4. Recommended CLPF Values for Various Modulation Schemes Modulation Scheme/Standard W-CDMA , Single-Carrier, Test Model 1-64 W-CDMA 4-Carrier, Test Model 1-64 CDMA2000, Single-Carrier, 9CH Test Model CDMA2000, 3-Carrier, 9CH Test Model WiMAX 802.16 (64QAM, 256 Subcarriers, 10 MHz Bandwidth) Crest Factor 12.0 dB 11.0 dB 9.1 dB 11.0 dB 14.0 dB CLPF 0.1 μF 0.1 μF 0.1 μF 0.1 μF 0.1 μF Residual Ripple 28 mV p-p 20 mV p-p 38 mV p-p 29 mV p-p 30 mV p-p Response Time (Rise/Fall) 10% to 90% 171 μs/1.57 ms 162 μs/1.55 ms 179 μs /1.55 ms 171 μs/1.55 ms 157 μs/1.47 ms Rev. D | Page 21 of 32 AD8362 ADJUSTING VTGT TO ACCOMMODATE SIGNALS WITH VERY HIGH CREST FACTORS An external direct connection between VREF (1.25 V) and VTGT sets up the internal target voltage, which is the rms voltage that must be provided by the VGA to balance the AGC feedback loop. In the default scheme, the VREF of 1.25 V positions this target to 0.06 × 1.25 V = 75 mV. In principle, however, VTGT can be driven by voltages that are larger or smaller than 75 mV. This technique can be used to move the intercept, which increases or decreases the input sensitivity of the device, or to improve the accuracy when measuring signals with large crest factors. For example, if this pin is supplied from VREF via a simple resistive attenuator of 1 kΩ:1 kΩ, the output required from the VGA is halved to 37.5 mV rms. Under these conditions, the effective headroom in the signal path that drives the squaring cell is doubled. In principle, this doubles the peak crest factor that can be handled by the system. Figure 53 and Figure 54 show the effect of varying VTGT on measurement accuracy when the AD8362 is swept with a series of signals with different crest factors, varying from CW with a crest factor of 3 dB, to a W-CDMA carrier (Test Model 1-64) with a crest factor of 10.6 dB. The crest factors of each signal are listed in the plots. In Figure 53, VTGT is set to its nominal value of 1.25 V, while in Figure 54, it is reduced to 0.625 V. 4.0 3.5 3.0 2.5 VOUT (V) 4.0 3.5 3.0 2.5 VOUT (V) 2.0 VOUT VOUT VOUT VOUT VOUT CW 64QAM WCDMA TM1-64 QPSK 256QAM 1.5 1.0 0.5 0 –0.5 ERROR QPSK 4dB CF ERROR 256QAM 8.2dB CF ERROR CW ERROR 64QAM 7.7dB CF ERROR WCDMA TM1-64 10.6dB CF 0 5 –1.0 –1.5 02923-054 2.0 1.5 1.0 0.5 0 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 PIN (dBm) –2.0 10 Figure 54. Transfer Function and Law Conformance for Signals with Varying Crest Factors, VTGT = 0.625 V, CLPF = 0.1 μF 2.0 VOUT CW VOUT 64QAM VOUT WCDMA TM1-64 VOUT QPSK VOUT 256QAM 1.5 1.0 0.5 0 –0.5 ERROR QPSK 4dB CF ERROR 256QAM 8.2dB CF ERROR CW ERROR 64QAM 7.7dB CF ERROR WCDMA TM1-64 10.6dB CF 0 5 –1.0 –1.5 Reducing VTGT also reduces the intercept. More significant in this case, however, is the behavior of the error curves. Note that in Figure 54 all of the error curves sit on one another, while in Figure 53, there is some vertical spreading. This suggests that VTGT should be reduced in those applications where a wide range of input crest factors are expected. As noted, VTGT can also be increased above its nominal level of 1.25 V. While this can be used to increase the intercept, it would have the undesirable effect of degrading measurement accuracy in situations where the crest factor of the signal being measured varies significantly. ALTERING THE SLOPE None of the changes in operating conditions discussed so far affects the logarithmic slope (VSLP) in Equation 10. This can readily be altered by controlling the fraction of VOUT that is fed back to the setpoint interface at the VSET pin. When the full signal from VOUT is applied to VSET, the slope assumes its nominal value of 50 mV/dB. It can be increased by including a voltage divider between these pins, as shown in Figure 55. AD8362 1 02923-053 2.0 1.5 1.0 0.5 ERROR (dB) COMM CHPF DECL INHI INLO DECL PWDN COMM ACOM 16 VREF 15 VTGT 14 VPOS 13 VOUT 12 VSET 11 ACOM 10 CLPF 9 R1 R2 02923-055 0 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5 PIN (dBm) –2.0 10 2 3 4 5 6 7 8 Figure 53. Transfer Function and Law Conformance for Signals with Varying Crest Factors, VTGT = 1.25 V VOUT Figure 55. External Network to Raise Slope Rev. D | Page 22 of 32 ERROR (dB) AD8362 Moderately low resistance values should be used to minimize scaling errors due to the 70 kΩ input resistance at the VSET pin. This resistor string also loads the output, and it eventually reduces the load-driving capabilities if very low values are used. To calculate the resistor values, use R1 = R2' (SD/50 − 1) where: SD is the desired slope, expressed in mV/dB. R2' is the value of R2 in parallel with 70 kΩ. For example, using R1 = 1.65 kΩ and R2 = 1.69 kΩ (R2' = 1.649 kΩ), the nominal slope is increased to 100 mV/dB. Note, however, that doubling the slope in this manner reduces the maximum input signal to approximately −10 dBm because of the limited swing of VOUT (4.9 V with a 5 V power supply). (15) VOUT (V) 4.0 3.5 3.0 2.5 2.0 1.5 ERROR (dB +25°C) 1.0 0.5 0 –60 VOUT (+25°C) VOUT (–40°C) VOUT (+85°C) –50 –40 –30 –20 –10 0 10 2 1 ERROR (dB –40°C) 0 –1 ERROR (dB +85°C) PIN (dBm) TEMPERATURE COMPENSATION AND REDUCTION OF TRANSFER FUNCTION RIPPLE The transfer function ripple and intercept drift of the AD8362 can be reduced using two techniques detailed in Figure 57. CLPF is reduced from its nominal value. For broadbandmodulated input signals, this results in increased noise at the output that is fed back to the VSET pin. The noise contained in this signal causes the gain of the VGA to fluctuate around a central point, moving the wiper of the Gaussian Interpolator back and forth on the R-2R ladder. Because the gain-control voltage is constantly moving across at least one of taps of the Gaussian Interpolator, the relationship between the rms signal strength of the VGA output and the VGA control voltage becomes independent of the VGA gain control ripple (see Figure 56). The signal being applied to the squaring cell is now lightly AM modulated. However, this does not change the peak-to-average ratio of the signal. 5V 5V 0.1µF VPOS 1kΩ VOUT VSET 3 1 7 Figure 56. Transfer Function and Linearity with Combined Ripple Reduction and Temperature Compensation Circuits, Frequency = 2.14 GHz, Single-Carrier W-CDMA, Test Model 1-64 Because of the reduced filter capacitor, the rms voltage appearing at the output of the error amplifier now contains significant peak-to-peak noise. While it is critical to feed this signal back to the VGA gain control input with the noise intact, the rms voltage going to the external measurement node can be filtered using a simple filter to yield a largely noise-free rms voltage. The circuit shown in Figure 57 also incorporates a temperature sensor that compensates temperature drift of the intercept. Because the temperature drift varies with frequency, the amount of compensation required must also be varied using R1 and R2. These compensation techniques are discussed in more detail in Application Note AN-653: Improving Temperature, Stability, and Linearity of High Dynamic Range RMS RF Power Detectors. 1nF 0.1µF AD8031 6 VOUT_COMP R1 AD83621 2 5 4 VREF VTGT 1µF COMM ACOM CLPF 440pF R2 5V 0.1µF 2 FREQUENCY (MHz) 900 1900 2200 R1 (kΩ) 1.02 1 1 R2 (kΩ) 25.5 82.5 19.1 1ADDITIONAL PINS OMITTED FOR CLARITY. 1 VTEMP TMP36F 5 02923-057 Figure 57. Temperature Compensation and Reduction of Transfer Function Ripple Rev. D | Page 23 of 32 02923-056 –2 ERROR (dB) AD8362 TEMPERATURE COMPENSATION AT VARIOUS WiMAX FREQUENCIES UP TO 3.8 GHz The AD8362 is ideally suited for measuring WiMAX type signals because crest factor changes in the modulation scheme have very little affect on the accuracy of the measurement. However, at higher frequencies, the AD8362 drifts more over temperature often making temperature compensation necessary. Temperature compensation is possible because the part-to-part variation over temperature is small, and temperature change only causes a shift in the AD8362’s intercept. Typically, users choose to compensate for temperature changes digitally. However, temperature compensation is possible using an analog temperature sensor. Because the drift of the output voltage is due mainly to intercept shift, the whole transfer function tends to drop with increasing temperature, while the slope remains quite stable. This makes the temperature drift independent of input level. Compensating the drift based on a particular input level (for example, −15 dBm), holds up well over the dynamic range. Figure 59 through Figure 63 show these results. The compensation is simple and relies on the TMP36 precision temperature sensor driving one side of the resistor divider as the AD8362 drives the other side. The output is at the junction of the two resistors (see Figure 58). At 25°C, TMP36 has an output voltage of 750 mV and a temperature coefficient of 10 mV/°C. As the temperature increases, the voltage from the AD8362 drops and the voltage from the TMP36 rises. R1 and R2 are chosen so the voltage at the center of the resistor divider remains steady over temperature. In practice, R2 is much larger than R1 so that the output voltage from the circuit is close to the voltage of the VOUT pin. The resistor ratio R2/R1 is determined by the temperature drift of the AD8362 at the frequency of interest. To calculate the values of R1 and R2, first calculate the drift at a particular input level, −15 dBm in this case. To do this, calculate the average drift over the temperature range from 25°C to 85°C. Using the following equation, the average drift in dB/°C is obtained. Table 5 shows the resultant values for R2 and R1 for frequencies ranging from 2350 MHz to 3650 MHz. Figure 59 through Figure 63 show the performance over temperature for the AD8362 with temperature compensation at frequencies across the WiMAX band. The compensation factor chosen optimizes temperature drift in the 25°C to 85°C range. This can be altered depending on the temperature requirements for the application. Table 5. Recommended Resistor Values for Temperature Compensation at Various Frequencies Average Drift @ −15 dBm (dB/°C) −0.0345 −0.0440 −0.0486 −0.0531 −0.0571 Average Drift @ −15 dBm (mV/°C) −1.7600 −2.2639 −2.5102 −2.7402 −2.9544 Freq. (MHz) 2350 2600 2800 3450 3650 Slope (mV/dB) 51 51.45 51.68 51.61 51.73 R1 (kΩ) 4.99 4.99 4.99 4.99 4.99 5V R2 (kΩ) 28 22.1 20 18.2 16.9 0.1µF 2.7nH 1nF 1nF INLO VTGT AD8362 INHI VOUT VSET CLPF VREF 0.1µF VOUT VTEMP R1 R2 1 2 4.7nH TMP36F 5 02923-058 Figure 58. AD8362 with Temperature Compensation Circuit dB/°C = dBError ΔTemperature (16) In this example, the drift of the AD8362 from 25°C to 85°C is −2.07 dB and the temperature delta is 60°C, which results in −0.0345 dB/°C drift. This temperature drift in dB/°C is converted to mV/°C through multiplication by the logarithmic slope (51 mV/dB at 2350 MHz). The result is −1.76 mV/°C. The following equation calculates the values of R1 and R2: 10 mV/°C R2 = R1 AD8362 Drift(mV/°C) (17) Rev. D | Page 24 of 32 AD8362 4.0 4.0 3.5 3.0 2.5 8 +85°C +25°C –40°C 6 4 3.5 3.0 2.5 8 +85°C +25°C –40°C 6 4 ERROR (dB) 2 0 –2 –4 VOUT (V) 2.0 1.5 1.0 0 –2 –4 –6 –8 20 2.0 1.5 1.0 0.5 0 –60 0.5 –6 –8 20 –50 –40 –30 –20 –10 0 10 0 –60 02923-059 ERROR (dB) 2 VOUT (V) –50 –40 –30 –20 –10 0 10 INPUT AMPLITUDE (dBm) INPUT AMPLITUDE (dBm) Figure 59. AD8362 VOUT and Error with Linear Temperature Compensation at 2350 MHz 4.0 3.5 3.0 2.5 8 +85°C +25°C –40°C 6 4 4.0 3.5 3.0 2.5 Figure 62. AD8362 VOUT and Error with Linear Temperature Compensation at 3450 MHz +125°C +105°C +85°C +25°C –40°C 8 6 4 2 0 –2 –4 –6 –8 20 ERROR (dB) 2.0 1.5 1.0 0.5 0 –60 0 –2 –4 –6 –8 20 2.0 1.5 1.0 0.5 0 –60 ERROR (dB) 02923-063 2 VOUT (V) VOUT (V) –50 –40 –30 –20 –10 0 10 02923-060 –50 –40 –30 –20 –10 0 10 INPUT AMPLITUDE (dBm) INPUT AMPLITUDE (dBm) Figure 60. AD8362 VOUT and Error with Linear Temperature Compensation at 2600 MHz 4.0 3.5 3.0 2.5 8 +85°C +25°C –40°C 6 4 Figure 63. AD8362 VOUT and Error with Linear Temperature Compensation at 3650 MHz, Temperature Compensation is Optimized for 85°C 2.0 1.5 1.0 0.5 0 –60 0 –2 –4 –6 –8 20 ERROR (dB) 2 VOUT (V) –50 –40 –30 –20 –10 0 10 INPUT AMPLITUDE (dBm) Figure 61. AD8362 VOUT and Error with Linear Temperature Compensation at 2800 MHz Rev. D | Page 25 of 32 02923-061 02923-062 AD8362 OPERATION IN CONTROLLER MODE The AD8362 provides a controller mode feature at the VOUT pin. Using VSET for the setpoint voltage, it is possible for the AD8362 to control subsystems such as power amplifiers (PAs), VGAs, or variable voltage attenuators (VVAs), which have output power that decreases monotonically with respect to their (increasing) gain control signal. CONTROLLED SYSTEM (OUTPUT POWER DECREASES AS VAPC INCREASES) POUT OUTPUT VAPC INPUT PIN OUTPUT CONTROL VOLTAGE 0.1V TO 4.9V VS ATTN 1 AD8362 1:4 Z-RATIO C8 1000pF C4 C6 100pF 1nF COMM CHPF DECL INHI INLO DECL PWDN COMM ACOM 16 VREF 15 VTGT 14 VPOS 13 VOUT 12 VSET 11 ACOM 10 CLPF 9 C3 (SEE TEXT) 2 3 4 C1 0.1µF C10 1000pF C2 1nF SETPOINT VOLTAGE INPUT 0V TO 3.5V 02923-064 To operate in controller mode, the link between VSET and VOUT is broken. A setpoint voltage is applied to the VSET input, while VOUT is connected to the gain control terminal of the VGA, and the AD8362 RF input is connected to the output of the VGA (generally using a directional coupler or power splitter and some additional attenuation). Based on the defined relationship between VOUT and the RF input signal when the device is in measurement mode, the AD8362 adjusts the voltage on VOUT (VOUT is now an error amplifier output) until the level at the RF input corresponds to the applied VSET. For example, in a closed loop system, if VSET is set to 3 V, VOUT increases or decreases until the input signal is equal to 0 dBm. This relationship follows directly from the measurement mode transfer function (see Figure 10, Figure 11, and Figure 12). Therefore, when the AD8362 operates in controller mode, there is no defined relationship between VSET and VOUT. VOUT settles to a value that results in balance between the input signal levels appearing at INHI/INLO and VSET. For this output power control loop to be stable, a groundreferenced capacitor must be connected to the CLPF pin. This capacitor integrates the internal error current that is present when the loop is not balanced. Increasing VSET, which corresponds to demanding a higher signal from the VGA, tends to decrease VOUT. The VGA or VVA therefore must have a negative sense. In other words, increasing the gain control voltage decreases gain. If this is not the case, an op amp, configured as an inverter with suitable level shifting, can be used to correct the sense of the VOUT signal. T1 ETC1.6-4-2-3 C5 100pF C7 1nF 5 6 7 8 Figure 64. Basic Connections for Controller Mode Operation Rev. D | Page 26 of 32 AD8362 RMS VOLTMETER WITH 90 dB DYNAMIC RANGE The 65 dB range of the AD8362 can be extended by adding a standalone VGA as a preamplifier whose gain control input is derived directly from VOUT. This extends the dynamic range by the gain control range of this second amplifier. When this VGA also provides a linear-in-dB (exponential) gain control function, the overall measurement remains linearly scaled in decibels. The VGA gain must decrease with an increase in its gain bias in the same way as the AD8362. Alternatively, an inverting op amp with suitable level shifting can be used. It is convenient to select a VGA needing only a single 5 V supply and capable of generating a fully balanced differential output. All of these conditions are met by the AD8330. Figure 66 shows the schematic. Also, note that the AD8131 is used to convert a single-ended input into the differential-ended input needed by the AD8330. The AD8131’s gain of 2 does create a dc offset on the output of the AD8362, but this is removed by connecting 0.5 V to the VMAG on AD8330. Using the inverse gain mode (MODE pin low) of the AD8330, its gain decreases on a slope of 30 mV/dB to a minimum value of 3 dB for a gain voltage (VDBS) of 1.5 V. VDBS is 40% of the output of the AD8362. Over the 3 V range from 0.5 V to 3.5 V, the gain of the AD8330 varies by (0.4 × 3 V)/(30 mV/dB), or 40 dB. Combined with the 65 dB gain span of the AD8362, this results in a 100 dB variation for a 3 V change in VOUT. Due to the noise generated from the AD8330, the dynamic range is limited to approximately 90 dB. This can only be achieved when a band-pass filter is used at the operating frequency between the AD8330 and AD8362. Figure 65 shows data results of the extended dynamic range at 70 MHz with error in VOUT. –103 –93 3.0 –83 –73 –63 INPUT (dBV) –53 –43 –33 –23 –13 –3 7 6 2.5 4 2.0 2 1.5 0 1.0 –2 0.5 –4 –80 –70 –60 –50 –40 –30 –20 INPUT (dBm) –10 0 10 Figure 65. Output and Conformance for the AD8330/AD8362 Extended Dynamic Range Circuit +5V GAIN OF 2 0.1µF 0.1µF 0.1µF 1 AD8362 COMM ACOM 16 10µF 0.1µF 0.1µF 0.01µF ENBL VPS1 OFST VPOS CNTR VPSO BAND-PASS @ 70MHz 2 CHPF VREF 15 3 DECL VTGT 14 AD8131 INPUT 49.9Ω 8 2 1 3 4 0.1µF INHI OPHI 4 INHI VPOS 13 VOUT AD8330 6 5 INLO 0.1µF MODE VDBS CMGN COMM OPLO 5 INLO VOUT 12 29.9Ω CMOP VMAG 0.1µF 6 DECL VSET 11 0.1µF –5V 0.01µF 7 PWDN ACOM 10 10µF 2kΩ +0.5V 8 COMM CLPF 9 Figure 66. RMS Voltmeter with 90 dB Dynamic Range Rev. D | Page 27 of 32 02923-066 2kΩ 02923-065 0 –90 –6 20 ERROR IN VOUT (dB) OUTPUT (V) AD8362 AD8362 EVALUATION BOARD The AD8362 evaluation board provides for a number of different operating modes and configurations, including many described in this data sheet. The measurement mode is set up by positioning SW2 as shown in Figure 67. The AD8362 can be operated in controller mode by applying the setpoint voltage to the VSET connector, and flipping SW2 to its alternate position. The internal voltage reference is used for the target voltage when SW1 is in the position shown in Figure 67. This voltage may optionally be reduced via a voltage divider implemented with R4 and R5, with LK1 in place, and SW1 switched to its alternate position. Alternatively, an external target voltage may be used with SW1 switched to its alternate position, LK1 removed, and the external target voltage applied to the VTGT connector. In measurement mode, the slope of the response at VOUT may be increased by using a voltage divider implemented with resistors in Position R17 and Position R9, and with SW2 switched to its alternate position. The AD8362 is powered up with SW3 in the position shown in Figure 67 and connector PWDN open. The part can be powered down by either connecting a logic high voltage to a connector, PWDN, with SW3 in the position, or by switching SW3 to its alternate position. R1 0Ω VPOS C1 0.1µF C2 100pF AGND R14 OPEN R15 0Ω 1 AD8362 COMM CHPF DECL INHI INLO DECL PWDN COMM ACOM 16 VREF 15 VTGT 14 VPOS 13 VOUT 12 VSET 11 ACOM 10 CLPF 9 C8 1000pF C10 1000pF RFIN C6 100pF R4 0Ω SW1 R5 10kΩ LK1 C7 1000pF 2 3 4 5 6 VREF T1 R6 0Ω R8 R17 OPEN 0Ω R9 10kΩ R10 0Ω C3 0.1µF R16 OPEN C5 100pF C4 1000pF SW3 PWDN R13 10kΩ VTGT R7 0Ω VOUT SW2 7 8 VSET C9 OPEN Figure 67. Evaluation Board Schematic Rev. D | Page 28 of 32 02923-067 AD8362 Figure 68. Component Side Metal of Evaluation Board Figure 69. Component Side Silkscreen of Evaluation Board Rev. D | Page 29 of 32 02923-069 02923-068 AD8362 Table 6. Bill of Materials Designator T1 C1 C2 C3, C9 C4, C7, C10 C5, C6 C8 DUT LK1 R1, R6, R7, R8, R10, R15 R4, R5 R9, R17 R13 R16 SW1 SW2 SW3 Description Part Number ETC 1.6-4-2-3 (M/A-COM) Default Value Supply filtering/decoupling capacitor Supply filtering/decoupling capacitor Output low-pass filter capacitor Input bias-point decoupling capacitors Input signal coupling capacitors Input high-pass filter capacitor AD8362 Use to reduce VTGT or to externally apply a voltage to VTGT Jumpers Use to reduce VTGT or to externally apply a voltage to VTGT Slope adjustment resistors (see the Altering the Slope section) Power-up terminating resistor Not installed Use to reduce VTGT or to externally apply a voltage to VTGT Measurement mode/controller mode selector Power-down/power-up or external power-down selector 0.1 μF 100 pF C3 = 0.1 μF, C9 = open 1000 pF 100 pF 1000 pF AD8362ARU LK1 = open 0Ω R4 = 0 Ω, R5 = 10 kΩ R9 = 10 kΩ, R17 = open R13 = 10 kΩ Open SW1 connects VREF to VTGT SW2 connects VSET to VOUT SW3 connects PWDN to R13 Rev. D | Page 30 of 32 AD8362 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 1 8 6.40 BSC PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX 0.20 0.09 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 70. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model AD8362ARU AD8362ARU-REEL AD8362ARU-REEL7 AD8362ARUZ 1 AD8362ARUZ-REEL71 AD8362-EVALZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead TSSOP, Tube 16-Lead TSSOP, 13" Tape and Reel 16-Lead TSSOP, 7" Tape and Reel 16-Lead TSSOP, Tube 16-Lead TSSOP, 7" Tape and Reel Evaluation Board Package Option RU-16 RU-16 RU-16 RU-16 RU-16 Z = RoHS Compliant Part. Rev. D | Page 31 of 32 AD8362 NOTES ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02923-0-6/07(D) Rev. D | Page 32 of 32