AD8567ACP

a FEATURES Single-Supply Operation: 4.5 V to 16 V Input Capability Beyond the Rails Rail-to-Rail Output Swing Continuous Output Current: 35 mA Peak Output Current: 250 mA Offset Voltage: 10 mV Slew Rate: 6 V/ s Unity Gain Stable with Large Capacitive Loads Supply Current: 700 A per Amplifier APPLICATIONS LCD Reference Drivers Portable Electronics Communications Equipment 16 V Rail-to-Rail Operational Amplifiers AD8565/AD8566/AD8567 PIN CONFIGURATIONS 5-Lead SC70 (KS Suffix) AD8565 OUT 1 V+ 2 +IN 3 4 –IN 5 V– OUT A –IN A +IN A V– 8-Lead MSOP (RM Suffix) 1 2 3 4 AD8566 8 7 6 5 V+ OUT B –IN B +IN B 14-Lead TSSOP (RU Suffix) OUT A 1 14 OUT D GENERAL DESCRIPTION The AD8565, AD8566, and AD8567 are low-cost single supply rail-to-rail input and output operational amplifiers optimized for LCD monitor applications. They are built on an advanced highvoltage CBCMOS process. The AD8565 contains a single amplifier, the AD8566 has two amplifiers, and the AD8567 has four amplifiers. These LCD op amps have high slew rates, 35 mA continuous output drive, 250 mA peak output drive, and high capacitive load drive capability. They have wide supply range and offset voltages below 10 mV. The AD8565, AD8566, and AD8567 are ideal for LCD grayscale reference buffer and VCOM applications. The AD8565, AD8566, and AD8567 are specified over the –40°C to +85°C temperature range. The AD8565 single is available in a 5-lead SC70 package. The AD8566 dual is available in an 8-lead MSOP package. The AD8567 quad is available in a 14-lead TSSOP package and a 16-lead lead frame Chip Scale Package. –IN A 2 13 –IN D +IN A 3 V+ 4 12 +IN D AD8567 11 V– +IN B 5 10 +IN C 9 –IN C –IN B 6 OUT B 7 8 OUT C 16-Lead CSP (CP Suffix) OUT A OUT D 14 NC 16 15 13 12 –IN A +IN A V+ +IN B 1 2 3 4 5 6 7 8 NC –IN D +IN D V– +IN C AD8567 TOP VIEW 11 10 9 –IN B OUT B OUT C NC = NO CONNECT R EV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 –IN C AD8565/AD8566/AD8567–SPECIFICATIONS Electrical Characteristics (4.5 V ≤ V ≤ 16 V, V S CM = VS /2, TA = 25 C, unless otherwise noted.) Min Typ 2 5 80 1 Max 10 600 800 80 130 VS + 0.5 Unit mV µV/°C nA nA nA nA V dB V/mV kΩ pF V V V V V mV mV mV mV mV mA mA V dB µA mA V/µs MHz MHz Degrees dB nV/√Hz nV/√Hz pA/√Hz Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Impedance Input Capacitance OUTPUT CHARACTERISTICS Output Voltage High Symbol VOS ∆VOS/∆T IB IOS CMRR AVO ZIN CIN VOH Conditions –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +85°C Common-Mode Input VCM = 0 to VS, –40°C ≤ TA ≤ +85°C RL = 10 kΩ, VO = 0.5 to (VS – 0.5 V) –0.5 54 3 95 10 400 1 VS – 0.005 15.95 4.38 5 42 95 35 250 Output Voltage Low VOL IL = 100 µA VS = 16 V, IL = 5 mA –40°C ≤ TA ≤ +85°C VS = 4.5 V, IL = 5 mA –40°C ≤ TA ≤ +85°C IL = 100 µA VS = 16 V, IL = 5 mA –40°C ≤ TA ≤ +85°C VS = 4.5 V, IL = 5 mA –40°C ≤ TA ≤ +85°C V S = 16 V 15.85 15.75 4.2 4.1 150 250 300 400 Continuous Output Current Peak Output Current POWER SUPPLY Supply Voltage Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product –3 dB Bandwidth Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density Specifications subject to change without notice. IOUT IPK VS PSRR ISY 4.5 VS = 4 V to 17 V, –40°C ≤ TA ≤ +85°C VO = VS/2, No Load –40°C ≤ TA ≤ +85°C RL = 10 kΩ, CL = 200 pF RL = 10 kΩ, CL = 10 pF RL = 10 kΩ, CL = 10 pF RL = 10 kΩ, CL = 10 pF 70 90 700 16 850 1 SR GBP BW Øo 4 6 5 6 65 75 26 25 0.8 en en in f = 1 kHz f = 10 kHz f = 10 kHz – 2– REV. A AD8565/AD8566/AD8567 ABSOLUTE MAXIMUM RATINGS * Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VS + 0.5 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Type 5-Lead SC70 (KS) 8-Lead MSOP (RM) 14-Lead TSSOP (RU) 16-Lead LFCSP (CP) JA 1 JC Unit °C/W °C/W °C/W °C/W 376 210 180 382 126 45 35 302 NOTES 1 θJA is specified for worst-case conditions, i.e., θJA is specified for device soldered onto a circuit board for surface mount packages. 2 DAP is soldered down to PCB. ORDERING GUIDE Model* AD8565AKS AD8566ARM AD8567ARU AD8567ACP * Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 5-Lead Plastic Surface-Mount 8-Lead MINI_SOIC 14-Lead Thin Shrink SO 16-Terminal Leadless Frame Chip Scale Package Option KS-5 RM-8 RU-14 CP-16 Branding Information ASA ATA Available in reels only. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8565/AD8566/AD8567 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. A –3– AD8565/AD8566/AD8567–Typical Performance Characteristics 0 VCM = VS/2 INPUT OFFSET VOLTAGE – mV 1000 4.5V VS TA = 25 C 16V 0.25 0.50 VS = 16V 0.75 VS = 4.5V 1.00 VOLTAGE NOISE DENSITY – nV Hz 100 10 1.25 1.50 40 25 TEMPERATURE – C 85 1 10 100 1k FREQUENCY – Hz 10k TPC 1. Input Offset Voltage vs. Temperature TPC 4. Voltage Noise Density vs. Frequency 10 4.5V VS TA = 25 C 16V SUPPLY CURRENT/AMPLIFIER – mA 1.0 VO = VS/2 AV = +1 TA = 25 C CURRENT NOISE DENSITY – pA Hz 0.8 0.6 1 0.4 0.2 0.1 10 100 1k FREQUENCY – Hz 10k 0 0 2 4 6 8 10 12 SUPPLY VOLTAGE – V 14 16 18 TPC 2. Current Noise Density vs. Frequency TPC 5. Supply Current/Amplifier vs. Supply Voltage 0.80 SUPPLY CURRENT/AMPLIFIER – mA VS = 16V RL = 10k CL = 100pF AV = +1 TA = 25 C TIME – 50mV/DIV VCM = VS/2 0.75 VS = 16V 0.70 0.65 0.60 VS = 4.5V 0.55 0.50 40 FREQUENCY – 1 s/DIV 25 TEMPERATURE – C 85 TPC 3. Small Signal Transient Response TPC 6. Supply Current/Amplifier vs. Temperature –4– REV. A AD8565/AD8566/AD8567 100 90 80 70 OVERSHOOT – % VS = 16V VIN = 100mV p-p RL = 10k AV = +1 TA = 25 C GAIN – dB 100 80 60 –OS VS = 16V RL = 10k CL = 40pF TA = 25 C 0 45 PHASE SHIFT – C 90 135 180 225 270 60 50 +OS 40 30 20 10 0 10 100 LOAD CAPACITANCE – pF 1k 40 20 0 1k 10k 100k 1M FREQUENCY – Hz 10M 100M TPC 7. Small Signal Overshoot vs. Load Capacitance TPC 10. Open-Loop Gain and Phase Shift vs. Frequency 18 16 OUTPUT VOLTAGE – mV 1k TA = 25 C 14 OUTPUT SWING – V p-p 100 VS = 4.5V VS = 16V 12 10 8 6 4 2 0 VS = 16V AV = +1 RL = 10k DISTORTION < 1% TA = 25 C 10 100 1k 10k 100k FREQUENCY – Hz 1M 10M 10 1 0.1 0.001 0.01 0.1 1 LOAD CURRENT – mA 10 100 TPC 8. Closed-Loop Output Swing vs. Frequency TPC 11. Output Voltage to Supply Rail vs. Load Current 150 60 50 4.5V VS 16V RL = 10k CL = 40pF TA = 25 C OUTPUT VOLTAGE – mV 135 120 105 90 75 60 45 30 15 0 ISINK = 5mA CLOSED-LOOP GAIN – dB 40 30 20 10 0 AVCL = –100 VS = 4.5V AVCL = –10 AVCL = +1 VS = 16V 10 100 1k 100k 10k FREQUENCY – Hz 1M 10M 40 25 TEMPERATURE – C 85 TPC 9. Closed-Loop Gain vs. Frequency TPC 12. Output Voltage Swing to Rail vs. Temperature REV. A –5– AD8565/AD8566/AD8567 150 ISOURCE = 5mA 135 120 160 140 VS = +16V TA = 25 C POWER SUPPLY REJECTION – dB OUTPUT VOLTAGE – mV VS = +4.5V 120 100 80 60 40 20 0 20 –PSRR +PSRR 105 90 75 60 45 30 15 0 40 25 TEMPERATURE – C 85 VS = +16V 40 100 1k 10k 100k FREQUENCY – Hz 1M 10M TPC 13. Output Voltage Swing to Rail vs. Temperature TPC 16. Power Supply Rejection Ratio vs. Frequency 500 450 400 TA = 25 C VS = 16V RL = 10k AV = +1 TA = 25 C IMPEDANCE – 300 250 200 150 100 50 0 100 1k 10k 100k FREQUENCY – Hz VS = 4.5V VS = 16V 1M 10M TIME – 40 s/DIV TPC 14. Close-Loop Output Impedance vs. Frequency VOLTAGE – 3V/DIV 350 TPC 17. No Phase Reversal 1.8k 140 120 100 VS = 16V TA = 25 C 1.6k 1.4k QUANTITY – Amplifiers VS = 16V TA = 25 C 1.2k 1.0k 800 600 400 200 CMRR – dB 80 60 40 20 0 10 100 1k 100k 10k FREQUENCY – Hz 1M 10M 0 10 8 6 0 2 4 4 2 INPUT OFFSET VOLTAGE – mV 6 8 10 TPC 15. Common-Mode Rejection Ratio vs. Frequency TPC 18. Input Offset Voltage Distribution –6– REV. A AD8565/AD8566/AD8567 5 4 7 6 INPUT OFFSET CURRENT – nA 3 BANDWIDTH – MHz 2 1 0 –1 –2 –3 1 –4 –5 0 –40 25 TEMPERATURE – C 85 0 VS = 16V VS = 4.5V 5 4 3 2 VS = 16V AV = +1 RL = x TA = 25 C 2 4 6 8 10 12 COMMON-MODE VOLTAGE – V 14 16 TPC 19. Input Offset Current vs. Temperature TPC 22. Frequency vs. Common-Mode Voltage (VS = 16 V) 0 6 VS = 5V AV = +1 RL = 10k TA = 25 C –50 5 INPUT BIAS CURRENT – nA –100 VS = 16V VS = 4.5V –150 BANDWIDTH – MHz 4 3 –200 2 –250 –300 1 –350 0 –40 25 TEMPERATURE – C 85 0 1 2 3 COMMON-MODE VOLTAGE – V 4 5 TPC 20. Input Bias Current vs. Temperature TPC 23. Frequency vs. Common-Mode Voltage (VS = 5.0 V) –20 –40 –60 CROSSTALK – dB –80 –100 –120 –140 –160 –180 50 4.5V 16V 100 1k FREQUENCY – Hz 10k 60k TPC 21. Channel A vs. Channel B Crosstalk REV. A –7– AD8565/AD8566/AD8567 APPLICATIONS Theory of Operation The AD856x family is designed to drive large capacitive loads in LCD applications. It has high output current drive, rail-to-rail input/output operation and is powered from a single 16 V supply. It is also intended for other applications where low distortion and high output current drive are needed. Figure 1 illustrates a simplified equivalent circuit for the AD856x. The rail-to-rail bipolar input stage is composed of two PNP differential pairs, Q4–Q5 and Q10–Q11, operating in series with diode protection networks, D1–D2. Diode network D1–D2 serves as protection against large transients for Q4 – Q5, to accommodate rail-to-rail input swing. D5–D6 protect Q10–Q11 against zenering. In normal operation, Q10–Q11 are off and their input stage is buffered from the operational amplifier inputs by Q6–D3 and Q8–D4. Operation of the input stage is best understood as a function of applied common-mode voltage: When the inputs of the AD856x are biased midway between the supplies, the differential signal path gain is controlled by resistive loads (Via R9, R10) Q4–Q5. As the input common-mode level is reduced toward the negative supply (VNEG or GND), the input transistor current sources, I1 and I2, are forced into saturation, thereby forcing the Q6–D3 and Q8–D4 networks into cutoff; However, Q4–Q5 remain active, providing input stage gain. Inversely, when common-mode input voltage is increased toward the positive supply, Q4–Q5 are driven into cutoff, Q3 is driven into saturation, and Q4 becomes active, providing bias to the Q10–Q11 differential pair. The point at which Q10–Q11 differential pair becomes active is approximately equal to (VPOS – 1 V). VPOS The benefit of this type of input stage is low bias current. The input bias current is the sum of base currents of Q4–Q5 and Q6–Q8 over the range from (VNEG + 1 V) to (VPOS – 1 V). Outside of this range, input bias current is dominated by the sum of base current of Q10–Q11 for input signals close to VNEG and of Q6–Q8 (Q10–Q11) for signal close to VPOS. From this type of design, the input bias current of AD856x not only exhibits different amplitude, but also exhibits different polarities. Figure 2 provides the characteristics of the input bias current versus common-mode voltage. It is important to keep in mind that the source impedances driving the AD856x inputs are balanced for optimum dc and ac performance. 1,000 800 VS = 16V TA = 25 C INPUT BIAS CURRENT – nA 600 400 200 0 –200 –400 –600 –800 –1,000 0 2 4 6 8 10 12 INPUT COMMON-MODE VOLTAGE – V 14 16 Figure 2. AD856x Input Bias Current vs. Common-Mode Voltage R1 Q3 Q4 BIAS LINE D1 R3 Q6 V+ C1 Q4 D3 R5 C2 D5 R6 D2 R4 Q8 Q5 D4 V– In order to achieve rail-to-rail output performance, the AD856x design uses a complementary common-source (or gmRL) output. This configuration allows output voltages to approach the power supply rails, particularly if the output transistors are allowed to enter the triode region on extremes of signal swing which are limited by VGS, the transistor sizes, and output load current. Also, this type of output stage exhibits voltage gain in an open-loop gain configuration. The amount of gain depends on the total load resistance at the output of the AD856x. Input Overvoltage Protection Q10 Q11 I1 D6 I2 FOLDED CASCADE As with any semiconductor device, whenever the input exceeds either supply voltages, attention needs to be paid to the input overvoltage characteristics. As an overvoltage occurs, the amplifier could be damaged, depending on the voltage level and the magnitude of the fault current. When the input voltage exceeds either supply by more than 0.6 V, internal pn junctions will allow current to flow from the input to the supplies. This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. If a condition exists using the AD856x where the input exceeds the supply more than 0.6 V, a series external resistor should be added. The size of the resistor can be calculated by using the maximum overvoltage divided by 5 mA. This resistance should be placed in series with either input exposed to an overvoltage. R9 R10 VNEG Figure 1. AD856x Equivalent Input Circuit –8– REV. A AD8565/AD8566/AD8567 Output Phase Reversal THD + N The AD856x family is immune to phase reversal. Although the device’s output will not change phase, large currents due to input overvoltage could damage the device. In applications where the possibility of an input voltage exceeding the supply voltage exists, overvoltage protection should be used as described in the previous section. Power Dissipation The AD856x family features low total harmonic distortion. Figure 4 shows a graph of THD + N versus frequency. The Total Harmonic Distortion plus Noise for the AD856x over the entire supply range is below 0.008%. When the device is powered from a 16 V supply, the THD + N stays below 0.003%. Figure 4 shows the AD8566 in a unity noninverting configuration. 10 The maximum allowable internal junction temperature of 150°C limits the AD856x family Maximum Power Dissipation. As the ambient temperature increases, the maximum power dissipated by the AD856x family must decrease linearly to maintain the maximum junction temperature. If this maximum junction temperature is exceeded momentarily, the part will still operate properly once the junction temperature is reduced below 150°C. If the maximum junction temperature is exceeded for an extended period of time, overheating could lead to permanent damage of the device. The maximum safe junction temperature, TJMAX, is 150°C. Using the following formula, we can obtain the maximum power that the AD856x family can safely dissipate as a function of temperature. PDISS = TJMAX – TA/θJA where: PDISS = AD856x power dissipation TJMAX = AD856x maximum allowable junction temp (150°C) TA = Ambient Temperature of the circuit θJA = AD856x package thermal resistance, junction-to-ambient The power dissipated by the device can be calculated as; PDISS = (VS – VOUT) where: VS = supply voltage VOUT = output voltage ILOAD = output load current Figure 3 shows the maximum power dissipation versus temperature. To achieve proper operation, use the previous equation to calculate PDISS for a specific package at any given temperature, or use the chart below. 1.25 14-LEAD SOIC 1 THD + N – % 0.1 VS = VS = 2.5V 8V 0.01 20 100 1k FREQUENCY – Hz 10k 30k Figure 4. THD + N vs. Frequency Graph Short Circuit Output Conditions The AD856x family does not have internal short circuit protection circuitry. As a precautionary measure, it is recommended not to short the output directly to the positive power supply or to ground. It is not recommended to operate the AD856x with more than 35 mA of continuous output current. The output current can be limited by placing a series resistor at the output of the amplifier whose value can be derive using the following equation: RX ≥ VS 35 mA ILOAD For a 5 V single supply operation, RX should have a minimum value of 143 Ω. LCD Panel Applications MAXIMUM POWER DISSIPATION – W 1.00 The AD856x amplifier is designed for LCD panel applications or applications where large capacitive load drive is required. It can instantaneously source/sink greater than 250 mA of current. At unity gain, it can drive 1 µF without compensation. This makes the AD856x ideal for LCD VCOM driver applications. To evaluate the performance of the AD856x family, a test circuit was developed to simulate the VCOM Driver application for an LCD panel. 0.75 14-LEAD TSSOP 8-LEAD MSOP 0.50 5-LEAD SOT-23 0.25 0 –35 –15 5 25 45 AMBIENT TEMPERATURE – C 65 85 Figure 3. Maximum Power Dissipation vs. Temperature for 5-, 8-, and 14-Lead Packages REV. A –9– AD8565/AD8566/AD8567 Figure 5 shows the test circuit. Series capacitors and resistors connected to the output of the op amp represent the load of the LCD panel. The 300 Ω and 3 kΩ feedback resistors are used to improve settling time. This test circuit simulates the worst-case scenario for a VCOM. It drives a represented load that is connected to a signal switched symmetrically around VCOM. Figure 6 displays a scope photo of the instantaneous output peak current capability of the AD856x family. 300 8V INPUT 0V TO 8V SQUARE WAVE WITH 15.6 s PULSEWIDTH 10 4V MEASURE CURRENT 10nF 10nF 10nF 10nF 10 –20 10 10 10 100 90 CH 2 = 100mA/DIV CH 1 = 5V/DIV 10 0% 3k TIME – 2 s/DIV Figure 6. Scope Photo of the VCOM Instantaneous Peak Current Figure 5. VCOM Test Circuit with Supply Voltage at 16 V – 10 – REV. A AD8565/AD8566/AD8567 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 5-Lead Plastic Surface-Mount (KS-5) 0.087 (2.20) 0.071 (1.80) 8-Lead MINI_SOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 0.053 (1.35) 0.045 (1.15) PIN 1 5 1 2 4 3 0.094 (2.40) 0.071 (1.80) 8 5 0.122 (3.10) 0.114 (2.90) 1 4 0.199 (5.05) 0.187 (4.75) 0.026 (0.65) BSC 0.039 (1.00) 0.031 (0.80) 0.004 (0.10) 0.000 (0.00) 0.043 (1.10) 0.031 (0.80) 0.012 (0.30) SEATING 0.006 (0.15) PLANE 0.007 (0.18) 0.004 (0.10) 0.016 (0.40) 0.004 (0.10) PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 33 27 0.012 (0.30) 0.004 (0.10) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.028 (0.71) 0.016 (0.41) 14-Lead Thin Shrink SO (RU-14) 0.201 (5.10) 0.193 (4.90) 14 8 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 7 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX SEATING PLANE 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8 0 0.028 (0.70) 0.020 (0.50) 16-Terminal Leadless Frame Chip Scale (CP-16) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 13 0.009 (0.24) 12 0.148 (3.75) BSC SQ 0.026 (0.65) BSC 0.030 (0.75) 0.024 (0.60) 0.020 (0.50) 9 8 5 0.157 (4.0) BSC SQ 16 1 PIN 1 INDICATOR TOP VIEW BOTTOM VIEW 4 0.073 (1.85) 0.067 (1.70) SQ 0.061 (1.55) 12 MAX 0.039 (1.00) MAX 0.033 (0.85) NOM SEATING PLANE 0.031 (0.80) MAX 0.026 (0.65) NOM 0.077 (1.95) BSC 0.014 (0.35) 0.008 (0.20) REF 0.011 (0.28) 0.009 (0.23) 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) CONTROLLING DIMENSIONS ARE IN MILLIMETERS REV. A – 11 – AD8565/AD8566/AD8567 Revision History Location Data Sheet changed from REV. 0 to REV. A. Page Edit to 16-Lead CSP and 5-Lead SC70 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edit to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 C01909–.8–10/01(A) PRINTED IN U.S.A. – 12 – REV. A