AD9049BR

a 9-Bit, 30 MSPS ADC AD9049 FUNCTIONAL BLOCK DIAGRAM FEATURES Low Power: 300 mW On-Chip T/H, Reference Single +5 V Power Supply Operation Selectable 5 V or 3 V Logic I/O Wide Dynamic Performance +5V AD9049 AINB APPLICATIONS Digital Communications Professional Video Medical Imaging Instrumentation REFERENCE CKTS T/H ADC AIN OBS PRODUCT DESCRIPTION GND +5V SUM AMP OLE The encode clock is TTL compatible and the digital outputs are CMOS; both can operate with 5 V/3 V logic, selected by the user. The two-step architecture used in the AD9049 is optimized to provide the best dynamic performance available while maintaining low power consumption. A 2.5 V reference is included onboard, or the user can provide an external reference voltage for gain control or matching of multiple devices. Fabricated on an advanced BiCMOS process, the AD9049 is packaged in space saving surface mount packages (SOIC, SSOP) and is specified over the industrial (–40°C to +85°C) temperature range. AIN (+3.3V ± 0.512V) 0.1µF TE 4 3 2, 8, 11, 20, 22 5 0.1µF 9 +5V 10 +5V DECODE LOGIC ADC TIMING ENCODE The AD9049 is a complete 9-bit monolithic sampling analogto-digital converter (ADC) with an onboard track-and-hold and reference. The unit is designed for low cost, high performance applications and requires only +5 V and an encode clock to achieve 30 MSPS sample rates with 9-bit resolution. DAC 9 BITS AD9049 (2) 74AC574 6 0.1µF 9 13 1, 7, 12, 21, 23 ENCODE Figure 1. Typical Connections REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD9049–SPECIFICATIONS ELECTRICAL CHARACTERISTICS Parameter (VD, VDD = +5 V; internal reference; ENCODE = 30 MSPS unless otherwise noted) Temp Test Level Min RESOLUTION DC ACCURACY Differential Nonlinearity 9 +25°C Full +25°C Full Full +25°C Full I V I V IV I V +25°C +25°C Full +25°C +25°C +25°C V I IV I V V BANDGAP REFERENCE Output Voltage Temperature Coefficient1 +25°C Full I V 2.4 SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Propagation Delay (tPD)2 +25°C +25°C +25°C +25°C Full I IV V V IV 30 +25°C +25°C V V +25°C +25°C V I +25°C +25°C Integral Nonlinearity No Missing Codes Gain Error Gain Tempco1 OBS ANALOG INPUT Input Voltage Range Input Offset Voltage Input Resistance Input Capacitance Analog Bandwidth DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time ENOBS fIN = 2.3 MHz fIN = 10.3 MHz Signal-to-Noise Ratio (SINAD)3 fIN = 2.3 MHz fIN = 10.3 MHz Signal-to-Noise Ratio (Without Harmonics) fIN = 2.3 MHz fIN = 10.3 MHz 2nd Harmonic Distortion fIN = 2.3 MHz fIN = 10.3 MHz 3rd Harmonic Distortion fIN = 2.3 MHz fIN = 10.3 MHz Two-Tone Intermodulation Distortion (IMD)4 Differential Phase Differential Gain AD9049BR/BRS Typ Max Bits 0.5 1.0 0.5 0.5 1.0 0.5 GUARANTEED ± 1.0 ± 7.5 ± 100 –10 –32 3.5 1.024 +7 +25 +51 6.5 OLE 5.0 5 100 2.5 ± 50 1.5 2.7 5 5 Units 2.6 LSB LSB LSB LSB % FS ppm/°C V p-p mV mV kΩ pF MHz V ppm/°C TE 3 15 MSPS MSPS ns ps, rms ns 10 10 ns ns 8.01 8.56 8.51 ENOBs ENOBs V I 50 53.3 53 dB dB +25°C +25°C V I 51 53.5 53.3 dB dB +25°C +25°C V I –69 –67 –60 dBc dBc +25°C +25°C V I –75 –66 –60 dBc dBc +25°C +25°C +25°C V V V 65 0.15 0.35 –2– dBc Degrees % REV. 0 AD9049 Parameter Temp Test Level ENCODE INPUT Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance Encode Pulse Width High (tEH) Encode Pulse Width Low (tEL ) Full Full Full Full +25°C +25°C +25°C IV IV IV IV V IV IV Full Full Full Full IV IV IV IV DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Voltage (3.0 VDD) Logic “0” Voltage (3.0 VDD) Output Coding OBS Min AD9049BR/BRS Typ Max 2.0 0.8 1 1 10 10 10 166 166 4.95 0.05 2.95 Offset Binary OLE POWER SUPPLY VD, VDD Supply Current5 Power Dissipation5 Power Supply Rejection Ratio (PSRR)6 Full Full IV IV +25°C I 40 60 300 0.05 Code Units V V µA µA pF ns ns V V V V 80 400 mA mW ± 10 mV/V TE NOTES 1“Gain Tempco” is for converter only; “Temperature Coefficient” is for bandgap reference only. 2Output propagation delay (t ) is measured from the 50% point of the rising edge of the encode command to the midpoint of the digital outputs with 10 pF PD maximum loads. 3RMS signal to rms noise with analog input signal 0.5 dB below full scale at specified frequency. 4Intermodulation measured relative to either tone with analog input frequencies of 9.5 MHz and 9.9 MHz at 7 dB below full scale. 5 Power dissipation is measured at 30 MSPS with AIN of 10.3 MHz and digital outputs loaded with 10 pF maximum. See Figure 4 for power dissipation at other conditions. 6 Measured as the ratio of the change in offset voltage for 5% change in +V D. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS* Test Level I – 100% Production Tested. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V ANALOG IN . . . . . . . . . . . . . . . . . . . . . –1.0 V to VD + 1.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD VREF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature AD9049BR/BRS . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ORDERING GUIDE Model Temperature Range Package Option* AD9049BR AD9049BRS – 40°C to +85°C – 40°C to +85°C R-28 RS-28 *R = Small Outline (SO); RS = Shrink Small Outline (SSOP). REV. 0 –3– AD9049 Table I. AD9049 Digital Coding (Single Ended Input AIN, AINB Bypassed to GND) Analog Input Voltage Level Digital Output MSB . . . LSB Digital Output 3.810 3.300 2.790 Positive Full Scale Midscale Negative Full Scale 111111111 011111111 000000000 PIN DESCRIPTIONS Pin No Name Function 1, 7, 12, 21, 23 2, 8, 11 3 4 5 6 9 10 13 GND VD VREFOUT VREFIN COMP REFBP AINB AIN ENCODE 14 15 16–19 20, 22 24–26 27 28 NC D8 (MSB) D7–D4 VDD D3–D1 D0 (LSB) NC Ground. Analog +5 V ± 5% power supply. Internal bandgap voltage reference (nominally +2.5 V). Input to reference amplifier. Voltage reference for ADC is connected here. Internal compensation pin, 0.1 µF bypass connected here to VD (+5 V). External connection for (0.1 µF) reference bypass capacitor. Complementary analog input pin (Analog input bar). Analog input pin. Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding) on rising edge of encode signal. Not internally connected. Most significant bit of ADC output. Digital output bits of ADC. Digital output power supply (only used by digital outputs). Digital output bits of ADC. Least significant bit of ADC output. Not internally connected. OBS OLE PIN CONNECTIONS 28 NC GND 1 VD 2 27 D0 (LSB) VREFOUT 3 26 D1 VREFIN 4 25 D2 COMP 5 24 D3 REFBP 6 GND 7 TE 23 GND AD9049 22 VDD TOP VIEW VD 8 (Not to Scale) 21 GND AINB 9 20 VDD AIN 10 19 D4 VD 11 18 D5 GND 12 17 D6 ENCODE 13 16 D7 15 D8 (MSB) NC 14 NC = NO CONNECT CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9049 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 AD9049 N N+1 N+2 N+3 N+4 N+5 AIN MIN tA ENCODE tEH tEL tPD DIGITAL OUTPUTS N–5 N–4 N–3 N–2 N–1 tA APERTURE DELAY tEH tEL tPD PULSE WIDTH HIGH 10ns PULSE WIDTH LOW 10ns OUTPUT PROP DELAY 5.0ns TYP MAX 2.7ns 166ns 166ns 8.2ns 15.0ns N Figure 2. Timing Diagram OBS VDD (Pins 20, 22) +3V to +5V VD 8k 8k AINB (Pin 9) AIN (Pin 10) 16k 16k Analog Input VD OLE INPUT BUFFER ENCODE (Pin 13) D0–D8 Output Stage VD VD VREFOUT (Pin 3) AV VREFIN (Pin 4) VREF Output VREFBF (Pin 6) Reference Circuit Figure 3. Equivalent Circuits REV. 0 –5– TE Encode Input AD9049–Typical Performance Curves 361 58 342 57 AIN = 10.3 MHz SIGNAL-TO-NOISE RATIO – dB (SINAD) 323 DISSIPATION – mW 304 OUTPUTS @ 5V 285 266 247 OUTPUTS @ 3V 228 209 55 54 53 52 51 50 190 49 171 48 –40 OBS 0 10 20 CLOCK RATE – MSPS 30 0 – 20 60 90 80 Figure 7. SNR vs. Temperature 0 ENCODE = 30 MSPS 74 HARMONIC DISTORTION 68 SIGNAL-TO-NOISE 56 ENCODE = 30 MSPS f1 IN = 9.5 MHz @ –7 dBFS f2 IN = 9.9 MHz @ –7 dBFS 2f1–f2 = –65.4 dBc 2f2–f1 = –65.0 dBc –10 –20 –30 TE –40 –50 dB 62 –60 –70 –80 50 –90 –100 44 –110 –120 38 10 0 100 2.5 5 7.5 10 FREQUENCY – MHz ANALOG INPUT FREQUENCY – MHz Figure 5. SNR/Distortion vs. Frequency 12.5 15 Figure 8. Two-Tone IMD 60 DIFF GAIN – % 0.50 58 AIN = 10.3 MHz 56 54 0.25 0.00 –0.25 –0.50 52 DIFF PHASE – Degrees SIGNAL-TO-NOISE RATIO – dB (SINAD) 40 OLE 80 1 20 TEMPERATURE – °C Figure 4. Power Dissipation vs. Clock Rate dB ENCODE = 30 MSPS AIN = 10.3 MHz 56 50 48 46 0 5 10 15 20 CLOCK RATE – MSPS 25 30 Figure 6. SNR vs. Clock Rate 1 2 3 4 5 6 1 2 3 4 5 6 0.50 0.25 0.00 –0.25 –0.50 Figure 9. Differential Gain/Differential Phase –6– REV. 0 AD9049 55.0 0 ENCODE = 30 MSPS ANALOG IN = 2.3 MHz SNR = 53.0 dB SNR (W/O HAR) = 53.3 dB 2ND HARMONIC = 69.3 dB 3RD HARMONIC = 72.9 dB –20 –30 –40 –50 dB ENCODE = 30 MSPS AIN = 2.3 MHz 54.5 SIGNAL-TO-NOISE – dB (SINAD) –10 –60 –70 –80 –90 –100 54.0 53.5 53.0 52.5 52.0 51.5 –110 51.0 25 –120 OBS 0 2.5 5 7.5 10 FREQUENCY – MHz 12.5 15 40 45 50 55 –40 –50 –60 –70 –80 –0.5 –1.5 –2.0 –2.5 –3.5 –110 –4.0 –120 –4.5 2.5 5 7.5 10 FREQUENCY – MHz 12.5 ENCODE = 30 MSPS TE –1.0 –100 0 75 0.0 –3.0 –90 70 0.5 ADC GAIN – dB –30 65 1.0 ENCODE = 30 MSPS ANALOG IN = 4.3 MHz SNR = 53.0 dB SNR (W/O HAR) = 53.3 dB 2ND HARMONIC = 69.0 dB 3RD HARMONIC = 72.6 dB –20 60 Figure 13. SNR vs. Clock Pulse Width OLE 0 –10 dB 35 DUTY CYCLE – % Figure 10. FFT Plot 30 MSPS, 2.3 MHz 15 1 10 1000 100 ANALOG INPUT FREQUENCY – MHz Figure 11. FFT Plot 30 MSPS, 4.3 MHz Figure 14. ADC Gain vs. AIN Frequency 15.0 0 ENCODE = 30 MSPS ANALOG IN = 10.3 MHz SNR = 52.7 dB SNR (W/O HAR) = 53.1 dB 2ND HARMONIC = 66.4 dB 3RD HARMONIC = 70.5 dB –10 –20 –30 14.0 13.0 [1] - 5V DATA RISING EDGE [2] - 5V DATA FALLING EDGE [3] - 3V DATA RISING EDGE [4] - 3V DATA FALLING EDGE [3] 12.0 –40 [1] 11.0 tPD – ns –50 dB 30 –60 –70 –80 [4] 10.0 [2] 9.0 8.0 –90 7.0 –100 6.0 –110 5.0 – 40 –120 0 2.5 5 7.5 10 FREQUENCY – MHz 12.5 15 0 20 40 60 80 TEMPERATURE – °C Figure 12. FFT Plot 30 MSPS, 10.3 MHz REV. 0 –20 Figure 15. tPD vs. Temperature 3 V/5 V –7– 100 AD9049 THEORY OF OPERATION 1kΩ Refer to the block diagram on the front page. +5V +5V 1kΩ The AD9049 employs a subranging architecture with digital error correction. This combination of design techniques insures true 9-bit accuracy at the digital outputs of the converter. VIN –0.5V to +0.5V 10 AD9049 AD8041 9 At the input, the analog signal is buffered by a high speed differential buffer and applied to a track-and-hold (T/H) that holds the analog value which is present when the unit is strobed with an ENCODE command. The conversion process begins on the rising edge of this pulse. The two stage architecture completes a coarse and then a fine conversion of the T/H output signal. 0.1µF 1kΩ 0.1µF Figure 16. Single Supply, Single Ended, DC Coupled AD9049 Error correction and decode logic correct and align data from the two conversions and present the result as a 9-bit parallel digital word. Output data are strobed on the rising edge of the ENCODE command. The subranging architecture results in five pipeline delays for the output data. Refer to the AD9049 Timing Diagram. OBS USING THE AD9049 3 V System +5V 1kΩ AD820 1kΩ +5V +5V 1kΩ 0.1µF VIN –0.5V to +0.5V OLE Analog Input AD9049 AD8011 9 –5V The digital input and outputs of the AD9049 can easily be configured to directly interface to 3 V logic systems. The encode input (Pin 13) is TTL compatible with a logic threshold of 1.5 V. This input is actually a CMOS stage (refer to Equivalent Encode Input Stage) with a TTL threshold, allowing operation with TTL, CMOS, and 3 V CMOS logic families. Using 3 V CMOS logic allows the user to drive the encode directly without the need to translate to +5 V. This saves the user power and board space. As with all high speed data converters, the clock signal must be clean and jitter free to prevent the degradation of dynamic performance. The AD9049 outputs can also directly interface to 3 V logic systems. The digital outputs are standard CMOS stages (refer to AD9049 Output Stage) with isolated supply pins (Pins 20, 22 VDD). By varying the voltage on the VDD pins, the digital output levels vary respectively. By connecting Pins 20 and 22 to the 3 V logic supply, the AD9049 will supply 3 V output levels. Care should be taken to filter and isolate the output supply of the AD9049 as noise could be coupled into the ADC, limiting performance. 10 0.1µF TE Figure 17. Single Ended, Capacitively Coupled AD9049 1kΩ +5V 1kΩ VIN –0.5V to +0.5V +5V 0.1µF T1-1T 10 AD9049 AD8011 50Ω –5V 9 Figure 18. Differentially Driven AD9049 Using Transformer Coupling. The AD830 provides a unique method of providing dc level shift for the analog input. Using the AD830 allows a great deal of flexibility for adjusting offset and gain. Figure 19 shows the AD830 configured to drive the AD9049. The offset is provided by the internal biasing of the AD9049 differential input (Pin 9). For more information regarding the AD830, see the AD830 data sheet. The analog input of the AD9049 is a differential input buffer (refer to AD9049 Equivalent Analog Input). The differential inputs are internally biased at +3.3 V, obviating the need for external biasing. Excellent performance is achieved whether the analog inputs are driven single-ended or differential (for best dynamic performance, impedances at AIN and AINB should match). VIN –0.5V to +0.5V 1 +5V +15V 2 3 AD830 7 10 AD9049 4 –5V 9 0.1µF Figure 16 shows typical connections for the analog inputs when using the AD9049 in a dc coupled system with single ended signals. All components are powered from a single +5 V supply. The AD820 is used to offset the ground referenced input signal to the level required by the AD9049. Figure 19. Level Shifting with the AD830 AC coupling the analog inputs of the AD9049 is easily accomplished. Figure 17 shows capacitive coupling of a single ended signal while Figure 18 shows transformer coupling differentially into the AD9049. –8– REV. 0 AD9049 Overdrive of the Analog Input Power Dissipation Special care was taken in the design of the analog input section of the AD9049 to prevent damage and corruption of data when the input is overdriven. The nominal input range is +2.788 V to 3.812 V (1.024 V p-p centered at 3.3 V). Out-of-range comparators detect when the analog input signal is out of this range and shut the T/H off. The digital outputs are locked at their maximum or minimum value (i.e., all “0” or all “1”). This precludes the digital outputs from changing to an invalid value when the analog input is out of range. The power dissipation specification in the parameter table is measured under the following conditions: encode is 30 MSPS, analog input is –1 dBFS at 10.3 MHz, the digital outputs are loaded with approximately 7 pF (10 pF maximum), and VDD is 5 V. These conditions intend to reflect actual usage of the device. As shown in Figure 4, the actual power dissipation varies based on these conditions. For instance, reducing the clock rate will reduce power as expected for CMOS type devices. Also the loading determines the power dissipated in the output stages. From an ac standpoint, the capacitive loading will be the key (refer to Equivalent Output Stage). When the analog input signal returns to the nominal range, the out-of-range comparators switch the T/H back to the active mode and the device recovers in approximately 10 ns. The analog input frequency and amplitude in conjunction with the clock rate determine the switching rate of the output data bits. Power dissipation increases as more data bits switch at faster rates. For instance, if the input is a dc signal that is out of range, no output bits will switch. This minimizes power in the output stages but is not realistic from a usage standpoint. OBS The input is protected to one volt outside the power supply rails. For nominal power (+5 V and ground), the analog input will not be damaged with signals from +6.0 V to –1.0 V. Timing The performance of the AD9049 is very insensitive to the duty cycle of the clock. Pulse width variations of as much as ± 10% will cause no degradation in performance, see Figure 13, SNR vs. Clock Pulse Width. OLE The dissipation in the output stages can be minimized by interfacing the outputs to 3 V logic (refer to USING THE AD9049, 3 V System). The lower output swings minimize consumption. Refer to Figure 4 for performance characteristics. The AD9049 provides latched data outputs, with five pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (refer to the AD9049 Timing Diagram). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9049; these transients can detract from the converter’s dynamic performance. Voltage Reference The minimum guaranteed conversion rate of the AD9049 is 3 MSPS. Below a nominal of 1.5 MSPS the internal T/H switches to a track function only. This precludes the T/H from drooping to the rail during the conversion process and minimizes saturation issues. At clock rates below 3 MSPS dynamic performance degrades. The AD9049 will operate in burst mode operation, but the user must flush the internal pipeline each time the clock stops. This requires 5 clock pulses each time the clock is restarted for the first valid data output, (refer to Figure 2 Timing Diagram). REV. 0 TE A stable and accurate +2.5 V voltage reference is built into the AD9049 (Pin 3, VREF Output). In normal operation the internal reference is used by strapping Pins 3 and 4 of the AD9049 together. The internal reference has 500 µA of extra drive current that can be used for other circuits. Some applications may require greater accuracy, improved temperature performance, or adjustment of the gain of the AD9049 which cannot be obtained by using the internal reference. For these applications, an external +2.5 V reference can be used to connect to Pin 4 of the AD9049. The VREFIN requires 5 µA of drive current. The input range can be adjusted by varying the reference voltage applied to the AD9049. No appreciable degradation in performance occurs when the reference is adjusted ± 5%. The full-scale range of the ADC tracks reference voltage changes linearly. –9– AD9049 OBS OLE Figure 20. Evaluation Board Top Layer Figure 22. Evaluation Board Bottom Layer TE Figure 21. Evaluation Board Ground Layer –10– REV. 0 AD9049 U3 74AC574R U1 AD9049R R5 1k R4 1k J2 R3 50 U2 AD9631Q 2 IN 6 OUT 3 IN 3 4 5 6 9 10 13 TP3 C9 0.1µF U6:B 74AC00R 6 C2 0.1µF J7 R1 50 3 OUT 4 VCC Y1 GND 2 SW41 +5V 12 13 11 U6:D 74AC00R R2 2k +5V J6 D8/MSB D7 D6 D5 D4 D3 D2 D1 D0 NC +5V +5V 15 16 17 18 19 24 25 26 27 8D 7D 6D 5D 4D 3D 2D 1D CK 11 9 8 7 6 5 4 3 2 +5V E1 +5V +5V CK U6:A 74AC00R 1 2 3 9 10 8 11 +5V C10 0.1µF C12 0.1µF C13 0.1µF C14 0.1µF C15 0.1µF –5.2V + –5.2V C20 0.1µF Figure 23. Evaluation Board Schematic REV. 0 12 13 14 15 16 17 18 19 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q OLE C7 0.1µF C8 0.1µF 1 8D 7D 6D 5D 4D 3D 2D 1D J5 C6 10µF 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OE U4 74AC574R TP2 C3 0.1µF J1 + J3 HDR20 20 22 U6:C 74AC00R C5 10µF 12 13 14 15 16 17 18 19 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q C1 0.1µF OBS 4 5 VREFOUT VREFIN COMP REFBP AINB AIN ENC 9 8 7 6 5 4 3 2 –11– OE 1 +5V TE C16 0.1µF C17 0.1µF C22 0.1µF C23 0.1µF C24 0.1µF AD9049 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C2104–6–1/96 28-Lead SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70) OBS 1 14 PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.4193 (10.65) 0.3937 (10.00) 15 0.2992 (7.60) 0.2914 (7.40) 29 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) x 45° 0.0098 (0.25) OLE 0.0500 (1.27) BSC 8° 0.0192 (0.49) 0° SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) TE 28-Lead SSOP (RS-28) 0.407 (10.34) 0.397 (10.08) 15 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 28 1 14 0.07 (1.79) 0.066 (1.67) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 0.015 (0.38) 0.010 (0.25) SEATING 0.009 (0.229) PLANE 0.005 (0.127) 8° 0° 0.03 (0.762) 0.022 (0.558) PRINTED IN U.S.A. 0.078 (1.98) PIN 1 0.068 (1.73) –12– REV. 0