AD9229BCPZ-50

Quad, 12-Bit, 50/65 MSPS, Serial, LVDS, 3 V A/D Converter AD9229 FEATURES Four ADCs in 1 package Serial LVDS digital output data rates to 780 Mbps (ANSI-644) Data and frame clock outputs SNR = 69.5 dB (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical) 400 MHz full power analog bandwidth Power dissipation 1,350 mW at 65 MSPS 985 mW at 50 MSPS 1 V p-p to 2 V p-p input voltage range 3.0 V supply operation Power-down mode Digital test pattern enable for timing alignments FUNCTIONAL BLOCK DIAGRAM PDWN DTP DRVDD DRGND AD9229 VIN+A VIN–A SHA PIPELINE ADC SHA PIPELINE ADC SHA PIPELINE ADC SHA PIPELINE ADC VIN+B VIN–B VIN+C VIN–C VIN+D VIN–D 12 12 12 12 SERIAL LVDS D+A SERIAL LVDS D+B SERIAL LVDS D+C SERIAL LVDS D+D D–A D–B D–C D–D VREF SENSE FCO+ 0.5V FCO– REFT REFB DATA RATE MULTIPLIER REF SELECT DCO+ AGND Digital beam-forming systems for ultrasound Wireless and wired broadband communications Communication test equipment LVDSBIAS CLK 04418-001 DCO– APPLICATIONS Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9229 is a quad, 12-bit, 65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at up to a 65 MSPS conversion rate and is optimized for outstanding dynamic performance in applications where a small package size is critical. 1. Four ADCs are contained in a small, space-saving package. 2. A data clock out (DCO) is provided, which operates up to 390 MHz and supports double-data rate operation (DDR). 3. The outputs of each ADC are serialized LVDS with data rates up to 780 Mbps (12 bits × 65 MSPS). 4. The AD9229 operates from a single 3.0 V power supply. 5. Packaged in a Pb-free, 48-lead LFCSP package. 6. The internal clock duty cycle stabilizer maintains performance over a wide range of input clock duty cycles. The ADC requires a single 3 V power supply and TTL-/CMOScompatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) trigger for signaling a new output byte are provided. Power-down is supported and typically consumes 3 mW when enabled. Fabricated with an advanced CMOS process, the AD9229 is available in a Pb-free, 48-lead LFCSP package. It is specified over the industrial temperature range of –40°C to +85°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD9229 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 11 Applications....................................................................................... 1 Terminology .................................................................................... 16 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 18 General Description ......................................................................... 1 Analog Input Considerations ................................................... 18 Revision History ............................................................................... 2 Clock Input Considerations...................................................... 19 Specifications..................................................................................... 3 Evaluation Board ............................................................................ 24 AC Specifications.......................................................................... 4 Power Supplies ............................................................................ 24 Digital Specifications ................................................................... 5 Input Signals................................................................................ 24 Switching Specifications .............................................................. 6 Output Signals ............................................................................ 24 Timing Diagram ............................................................................... 7 Default Operation and Jumper Selection Settings................. 25 Absolute Maximum Ratings............................................................ 8 Alternate Analog Input Drive Configuration......................... 25 Explanation of Test Levels ........................................................... 8 Outline Dimensions ....................................................................... 39 ESD Caution.................................................................................. 8 Ordering Guide .......................................................................... 39 Pin Configuration and Function Descriptions............................. 9 Equivalent Circuits ......................................................................... 10 REVISION HISTORY 9/05—Rev. 0 to Rev. A Change to Specifications.................................................................. 3 Changes to Differential Input Configurations Section.............. 19 Changes to Exposed Paddle Thermal Heat Slug Recommendations Section........................................................ 23 Changes to Evaluation Board Section.......................................... 24 Changes to Table 11........................................................................ 36 3/05—Revision 0: Initial Version Rev. A | Page 2 of 40 AD9229 SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 1. AD9229-50 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error 1 Gain Matching1 Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error1 Reference Voltage, VREF = 1 V REFERENCE Output Voltage Error, VREF = 1 V Load Regulation @ 1.0 mA, VREF = 1 V Output Voltage Error, VREF = 0.5 V Load Regulation @ 0.5 mA, VREF = 0.5 V Input Resistance ANALOG INPUTS Differential Input Voltage Range VREF = 1 V Differential Input Voltage Range VREF = 0.5 V Common Mode Voltage Input Capacitance 2 Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD DRVDD Power Dissipation 3 Power-Down Dissipation CROSSTALK 4 AD9229-65 Temperature Test Level Full Full Full Full Full 25°C Full 25°C Full VI VI VI VI VI V VI V VI Guaranteed ±5 ±5 ±0.3 ±0.2 ±0.3 ±0.3 ±0.6 ±0.6 Full Full Full V V V ±2 ±12 ±16 Full Full Full Full VI V VI V ±10 3 ±8 0.2 Full V 7 7 kΩ Full VI 2 2 V p-p Full VI 1 1 V p-p Full Full Full V V V 1.5 7 400 1.5 7 400 V pF MHz Full Full Full Full Full Full Full IV IV VI VI VI V V Min 12 2.7 2.7 Typ 3.0 3.0 300 28 985 3 –95 1 Max Min 12 Typ Guaranteed ±5 ±5 ±0.3 ±0.2 ±0.3 ±0.3 ±0.4 ±0.4 ±25 ±25 ±2.5 ±1.5 ±0.6 ±1 Max Unit Bits ±25 ±25 ±2.5 ±1.5 mV mV % FS % FS LSB LSB LSB LSB ±0.7 ±1 ±3 ±12 ±16 ±30 ±10 3 ±8 0.2 ±17 3.6 3.6 330 31 1083 2.7 2.7 3.0 3.0 420 29 1350 3 –95 ppm/°C ppm/°C ppm/°C ±30 ±17 3.6 3.6 455 33 1465 mV mV mV mV V V mA mA mW mW dB Gain error and gain temperature coefficients are based on the ADC only, with a fixed 1.0 V external reference and a 2 V p-p differential analog input. Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure. 3 Power dissipation measured with rated encode and 2.4 MHz analog input at –0.5 dBFS. 4 Typical specification over the first Nyquist zone. 2 Rev. A | Page 3 of 40 AD9229 AC SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 2. AD9229-50 Parameter SIGNAL-TO-NOISE RATIO (SNR) SIGNAL-TO-NOISE RATIO (SINAD) EFFECTIVE NUMBER OF BITS (ENOB) SPURIOUS-FREE DYNAMIC RANGE (SFDR) WORST HARMONIC (Second or Third) WORST OTHER (Excluding Second or Third) TWO-TONE INTERMODULATION DISTORTION (IMD) AIN1 and AIN2 = –7.0 dBFS fIN = 2.4 MHz fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN = 2.4 MHz Temperature Full 25°C Full Full 25°C Full 25°C Full Full 25°C Full Test Level IV V VI VI V V V VI VI V V fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN = 2.4 MHz 25°C Full Full 25°C Full V VI VI V V fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 10.3 MHz fIN = 25 MHz fIN = 30 MHz fIN = 70 MHz fIN1 = 15 MHz 25°C Full Full 25°C Full 25°C Full Full 25°C Full 25°C Full Full 25°C 25°C V VI VI V V V VI VI V V V VI VI V V fIN2 = 16 MHz fIN1 = 69 MHz fIN2 = 70 MHz 25°C V Rev. A | Page 4 of 40 Min 69.5 68.7 Typ 70.4 70.4 69.6 68.4 67.2 70.0 70.0 69.4 Max AD9229-65 Min 69.0 Typ 70.2 70.2 68.0 69.5 67.1 69.8 69.8 67.3 69.0 66.7 11.3 66.8 11.3 11.1 11.3 11.2 11.3 10.9 10.8 85 76 85 85 11.2 10.8 85 85 77 –85 –85 –76 –85 –77 –90 –90 –73 –88 –83 –73 –79.7 –85 –73 –68.5 –68.5 –78 –90 –90 –88 Unit dB dB dB dB dB dB dB dB dB dB Bits Bits Bits Bits Bits dBc 85 73 78 –85 –85 –85 Max –81.7 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc AD9229 DIGITAL SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 3. AD9229-50 Parameter CLOCK INPUT Logic Compliance High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC INPUTS (PDWN) Logic 1 Voltage Logic 0 Voltage High Level Input Current Low Level Input Current Input Capacitance DIGITAL OUTPUTS (D+, D–) Logic Compliance Differential Output Voltage Output Offset Voltage Output Coding Temperature Test Level Full Full Full Full 25°C IV IV VI VI V Full Full Full Full 25°C IV IV IV IV V Full Full Full VI VI VI Min Typ AD9229-65 Max TTL/CMOS 2.0 0.8 ±10 ±10 2.0 Max Unit 0.8 ±10 ±10 V V μA μA pF 0.5 0.5 2 0.8 ±10 ±10 V V μA μA pF 440 1.35 mV V 2.0 0.5 0.5 2 Rev. A | Page 5 of 40 Typ TTL/CMOS 2.0 0.5 0.5 2 LVDS 260 1.15 Min 1.25 Offset binary 0.8 ±10 ±10 440 1.35 0.5 0.5 2 LVDS 260 1.15 1.25 Offset binary AD9229 SWITCHING SPECIFICATIONS AVDD = 3.0 V, DRVDD = 3.0 V, maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless otherwise noted. Table 4. AD9229-50 AD9229-65 Temp Test Level Full Full Full VI IV VI 8 10 6.2 Full VI 8 10 Full Full VI V 3.3 6.5 250 Full V 250 250 ps Full V 6.5 6.5 ns Full V IV tFCO + (tSAMPLE/24) (tSAMPLE/24) ns Full tFCO + (tSAMPLE/24) (tSAMPLE/24) DCO-to-FCO Delay (tFRAME) Full IV Data-to-Data Skew (tDATA-MAX – tDATA-MIN) Wake-Up Time Pipeline Latency Full IV ±100 25°C Full V IV 4 10 4 10 ms CLK cycles 25°C 25°C V V 1.8