AD9234BCPZ-1000

12-Bit, 1 GSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter AD9234 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS BUFFER VIN+A VIN–A FD_A FD_B ADC CORE 12 DECIMATE BY 2 SIGNAL MONITOR 12 VIN+B VIN–B DECIMATE BY 2 ADC CORE JESD204B HIGH SPEED SERIALIZER + Tx OUTPUTS AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V) FAST DETECT 4 SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± BUFFER FAST DETECT V_1P0 CLK+ CLK– ÷2 ÷4 ÷8 AGND SYNCINB± JESD204B SUBCLASS 1 CONTROL CLOCK GENERATION AND ADJUST SPI CONTROL SYSREF± SIGNAL MONITOR AD9234 DRGND DGND SDIO SCLK CSB PDWN/ STBY 12244-001 JESD204B (Subclass 1) coded serial digital outputs 1.5 W total power per channel at 1 GSPS (default settings) SFDR 79 dBFS at 340 MHz (1 GSPS) 85 dBFS at 340 MHz (500 MSPS) SNR 63.4 dBFS at 340 MHz (AIN = −1.0 dBFS, 1 GSPS) 65.6 dBFS at 340 MHz (AIN = −1.0 dBFS, 500 MSPS) ENOB = 10.4 bits at 10 MHz (1 GSPS) DNL = ±0.16 LSB; INL = ±0.35 LSB (1 GSPS) Noise density −151 dBFS/Hz (1 GSPS) −150 dBFS/Hz (500 MSPS) 1.25 V, 2.5 V, and 3.3 V dc supply operation Low swing full-scale input 1.34 V p-p typical (1 GSPS) 1.63 V p-p typical (500 MSPS) No missing codes Internal ADC voltage reference Flexible termination impedance 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 2 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation Differential clock input Optional decimate by 2 DDC per channel Differential clock input Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Small signal dither Figure 1. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 7. Low power consumption analog core, 12-bit, 1.0 GSPS dual analog-to-digital converter (ADC) with 1.5 W per channel. Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm × 9 mm 64-lead LFCSP. Pin compatible with the AD9680 14-bit, 1 GSPS/500 MSPS dual ADC. Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE Point to point radio systems Digital predistortion observation path General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Digital oscilloscopes High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9234 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC Complex to Real Conversion ......................................... 36 Applications ....................................................................................... 1 Digital Outputs ............................................................................... 37 Functional Block Diagram .............................................................. 1 Introduction to the JESD204B Interface ................................. 37 Product Highlights ........................................................................... 1 JESD204B Overview .................................................................. 37 Revision History ............................................................................... 3 Functional Overview ................................................................. 38 General Description ......................................................................... 4 JESD204B Link Establishment ................................................. 39 Specifications..................................................................................... 5 Physical Layer (Driver) Outputs .............................................. 41 DC Specifications ......................................................................... 5 Configuring the JESD204B Link .............................................. 43 AC Specifications.......................................................................... 6 Deterministic Latency.................................................................... 46 Digital Specifications ................................................................... 8 Subclass 0 Operation.................................................................. 46 Switching Specifications .............................................................. 9 Subclass 1 Operation.................................................................. 46 Timing Specifications .................................................................. 9 Multichip Synchronization............................................................ 48 Absolute Maximum Ratings .......................................................... 11 Normal Mode .............................................................................. 48 Thermal Characteristics ............................................................ 11 Timestamp Mode ....................................................................... 48 ESD Caution ................................................................................ 11 SYSREF± Input ........................................................................... 50 Pin Configuration and Function Descriptions ........................... 12 SYSREF± Setup/Hold Window Monitor ................................. 52 Typical Performance Characteristics ........................................... 14 Latency ............................................................................................. 54 AD9234-1000 .............................................................................. 14 End to End Total Latency .......................................................... 54 AD9234-500 ................................................................................ 18 Example Latency Calculation ................................................... 54 Equivalent Circuits ......................................................................... 22 Test Modes ....................................................................................... 55 Theory of Operation ...................................................................... 24 ADC Test Modes ........................................................................ 55 ADC Architecture ...................................................................... 24 JESD204B Block Test Modes .................................................... 56 Analog Input Considerations.................................................... 24 Serial Port Interface ........................................................................ 58 Voltage Reference ....................................................................... 27 Configuration Using the SPI ..................................................... 58 Clock Input Considerations ...................................................... 28 Hardware Interface ..................................................................... 58 Clock Jitter Considerations ....................................................... 29 SPI Accessible Features .............................................................. 58 Power-Down/Standby Mode..................................................... 29 Memory Map .................................................................................. 59 Temperature Diode .................................................................... 29 Reading the Memory Map Register Table............................... 59 ADC Overrange and Fast Detect .................................................. 30 Memory Map Register Table ..................................................... 60 ADC Overrange .......................................................................... 30 Applications Information .............................................................. 71 Fast Threshold Detection (FD_A and FD_B) ........................ 30 Power Supply Recommendations............................................. 71 Signal Monitor ................................................................................ 31 Exposed Pad Thermal Heat Slug Recommendations ............ 71 Digital Downconverter (DDC) ..................................................... 34 AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) .............. 71 DDC General Description ........................................................ 34 Outline Dimensions ....................................................................... 72 Half-Band Filter .......................................................................... 35 Ordering Guide .......................................................................... 72 DDC Gain Stage ......................................................................... 36 Rev. B | Page 2 of 72 Data Sheet AD9234 REVISION HISTORY 1/2018—Rev. A to Rev. B Changes to Features Section .................................................................... 1 Added tACCESS Parameter, Table 5 ............................................................. 9 Change to Junction Temperature Range Parameter, Table 6 ..........11 Changes to Figure 38 and Figure 39 .............................................19 Added Deterministic Latency Section, Subclass 0 Operation Section, Subclass 1 Operation Section, Deterministic Latency Requirements Section, Setting Deterministic Latency Registers Section, and Figure 103; Renumbered Sequentially ........46 Added Figure 104 and Figure 105 .....................................................47 Changes to Multichip Synchronization Section ............................48 Added Normal Mode Section and Timestamp Mode Section .......48 Moved Figure 106...................................................................................48 Added Figure 107 ...................................................................................49 Added SYSREF± Input Section, SYSREF± Control Features Section, Figure 108, Figure 109, Figure 110, Figure 111 .............50 Added Figure 112 and Figure 113 .....................................................51 Changes to SYSREF± Setup/Hold Window Monitor Section ...52 Added Figure 114 ...................................................................................52 Added Figure 115 ...................................................................................53 Added Latency Section, End to End Total Latency Section, Table 15, Example Latency Calculation Section, Table 16, and Table 17; Renumbered Sequentially .........................................54 Changes to ADC Test Modes Section and Table 18 .....................55 Add Figure 116........................................................................................55 Changes to Transport Layer Sample Test Mode Section, Interface Test Mode Section, and Table 19 .....................................56 Moved Data Link Layer Test Modes Section ..................................56 Added Reg Addr (Hex) 0x122, Table 25.......................................62 Changes to Reg Addr (Hex) 0x56F, Table 25 ...............................67 Updated Outline Dimensions ........................................................72 Changes to Ordering Guide ...........................................................72 3/2015—Rev. 0 to Rev. A Added AD9234-500 ........................................................... Universal Changes to Features Section ............................................................ 1 Changes to Table 1 ............................................................................ 5 Changes to Table 2 ............................................................................ 6 Changes to Table 4 ............................................................................ 9 Changes to Table 6, Thermal Characteristics Section, and Table 7 ............................................................................................... 11 Change to Pin 58, Pin 59 Description Column, Table 8 ............ 15 Added AD9234-500 Section and Figure 29 to Figure 51 ........... 18 Changes to Figure 63 Caption and Figure 64 Caption, Analog Input Controls and SFDR Optimization Section, and Figure 66............... 25 Changes to Figure 70 and Figure 71 ............................................... 26 Changes to Voltage Reference Section............................................ 27 Changes to Figure 79 ...................................................................... 28 Changes to Figure 80 ...................................................................... 29 Changes to DDC General Description Section .......................... 34 Changes to Figure 91 ...................................................................... 38 Added Example 2: Full Bandwidth Mode at 500 MSPS Section... 44 Added Test Modes Section and Table 15 ..................................... 50 Added Table 16 and Table 17 ......................................................... 51 Added Table 18 and Table 19 ......................................................... 52 Changes to Table 22 ........................................................................ 55 Changes to Power Supply Recommendations Section and Figure 106 ......................................................................................... 65 Changes to Ordering Guide ........................................................... 66 8/2014—Revision 0: Initial Version Rev. B | Page 3 of 72 AD9234 Data Sheet GENERAL DESCRIPTION The AD9234 is a dual, 12-bit, 1 GSPS/500 MSPS ADC. The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block. The AD9234 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9234 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC. Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the acceptable lane rate of the receiving logic device and the sampling rate of the ADC. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins. The AD9234 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI. The AD9234 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent. Rev. B | Page 4 of 72 Data Sheet AD9234 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Voltage INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage Range Common-Mode Voltage (VCM) Differential Input Capacitance 1 Analog Input Full Power Bandwidth POWER SUPPLY AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD IAVDD1 IAVDD2 IAVDD3 IAVDD1_SR IDVDD 2 IDRVDD1 IDRVDD (L = 2 mode) ISPIVDD AD9234-500 Typ Max Min 12 Full Full Full Full Full Full Full Guaranteed 0 +0.20 0 +0.19 −13.8 −5.1 +3.6 −3.9 +1 +5.9 −0.3 +0.3 −0.8 +1.1 25°C 25°C ±2.6 ±36 ±6 ±36 ppm/°C ppm/°C Full 1.0 1.0 V 25°C 0.74 1.02 LSB rms Full 25°C 25°C 25°C 1.63 2.05 1.5 2 1.34 2.05 1.5 2 V p-p V pF GHz Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C Full −0.22 1.22 2.44 3.2 1.22 1.22 1.22 1.7 Rev. B | Page 5 of 72 1.25 2.50 3.3 1.25 1.25 1.25 1.8 430 380 65 15 140 190 140 5 1.28 2.56 3.4 1.28 1.28 1.28 3.4 480 430 75 18 152 246 6 Min 12 AD9234-1000 Typ Max Temperature Full Guaranteed 0 +0.20 0 +0.19 0 1 +4.8 −0.3 ±0.16 +0.3 −1.2 ±35 +1.4 −0.22 1.22 2.44 3.2 1.22 1.22 1.22 1.7 1.25 2.50 3.3 1.25 1.25 1.25 1.8 675 525 75 16 230 205 N/A 3 5 1.28 2.56 3.4 1.28 1.28 1.28 3.4 740 590 91 18 236 225 6 Unit Bits % FSR % FSR % FSR % FSR LSB LSB V V V V V V V mA mA mA mA mA mA mA mA AD9234 Parameter POWER CONSUMPTION Total Power Dissipation (Including Output Drivers)2 Total Power Dissipation (L = 2 Mode) Power-Down Dissipation Standby 4 Data Sheet Temperature Min AD9234-500 Typ Max Full 25°C Full Full 2.15 2.08 670 1.1 Min AD9234-1000 Typ Max 2.5 3.0 N/A3 750 1.25 3.3 Unit W W mW W All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used. Default mode. No DDCs used. L = 4, M = 2, F = 1. N/A = not applicable. At the maximum sample rate, it is not applicable to use L = 2 mode on the JESD204B output interface because this exceeds the maximum lane rate of 12.5 Gbps. L = 2 mode is supported when the equation ((M × N΄ × (10/8) × fOUT)/L) results in a line rate that is ≤12.5 Gbps. fOUT is the output sample rate and is denoted by fS/DCM, where DCM = decimation ratio. 4 Can be controlled by the SPI. 1 2 3 AC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 2. Parameter 1 ANALOG INPUT FULL SCALE NOISE DENSITY 2 SIGNAL-TO-NOISE RATIO (SNR) 3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 737 MHz fIN = 985 MHz fIN = 1410 MHz SNR AND DISTORTION RATIO (SINAD)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 737 MHz fIN = 985 MHz fIN = 1410 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 737 MHz fIN = 985 MHz fIN = 1410 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 737 MHz fIN = 985 MHz fIN = 1410 MHz Temperature Full Full 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C Rev. B | Page 6 of 72 AD9234-500 Min Typ Max 1.63 −150 65.1 65.0 10.5 77 65.9 65.8 65.6 65.3 64.2 63.6 62.2 65.8 65.7 65.5 65.2 63.7 63.1 61.2 10.7 10.6 10.6 10.5 10.3 10.2 9.9 84 85 85 87 75 75 71 AD9234-1000 Min Typ Max 1.34 −151 61.6 61.2 9.9 70 Unit V p-p dBFS/Hz 64.2 63.9 63.4 63.1 61.6 60.7 58.8 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 64.1 63.8 63.3 63.0 61.5 60.6 58.7 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 10.4 10.3 10.2 10.2 9.9 9.8 9.5 Bits Bits Bits Bits Bits Bits Bits 89 80 79 80 81 79 78 dBFS dBFS dBFS dBFS dBFS dBFS dBFS Data Sheet AD9234 Parameter 1 WORST HARMONIC, SECOND OR THIRD3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 737 MHz fIN = 985 MHz fIN = 1410 MHz WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 737 MHz fIN = 985 MHz fIN = 1410 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7 dBFS fIN1 = 187 MHz, fIN2 = 190 MHz fIN1 = 338 MHz, fIN2 = 341 MHz CROSSTALK 4 FULL POWER BANDWIDTH 5 Temperature AD9234-500 Min Typ Max 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C −84 −85 −85 −87 −75 −75 −71 −82 −77 AD9234-1000 Min Typ Max −89 −80 −79 −80 −82 −79 −78 −96 −95 −94 −93 −88 −89 −86 −89 −85 −83 −82 −81 −85 −80 −90 −86 95 2 −81 −78 95 2 −70 −76 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Noise density is measured at a low analog input frequency (30 MHz). 3 See Table 9 for recommended settings for the buffer current setting optimized for SFDR. 4 Crosstalk is measured at 170 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel. 5 Measured with circuit shown in Figure 64. 1 2 Rev. B | Page 7 of 72 Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB GHz AD9234 Data Sheet DIGITAL SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted. Table 3. Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance SYSTEM REFERENCE INPUTS (SYSREF+, SYSREF−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance LOGIC OUTPUT (SDIO) Logic Compliance Logic 1 Voltage (IOH = 800 µA) Logic 0 Voltage (IOL = 50 µA) SYNC INPUTS (SYNCINB+, SYNCINB−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC OUTPUTS (FD_A, FD_B) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3) Logic Compliance Differential Output Voltage Output Common-Mode Voltage (VCM) AC-Coupled Short-Circuit Current (IDshort) Differential Return Loss (RLDIFF) 1 Common-Mode Return Loss (RLCM)1 Differential Termination Impedance 1 Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Min Typ LVDS/LVPECL 1200 0.85 35 600 Max Unit 1800 mV p-p V kΩ pF 2.5 LVDS/LVPECL 1200 0.85 35 400 0.6 1800 2.0 2.5 mV p-p V kΩ pF CMOS 0.8 × SPIVDD 0 0.5 30 V V kΩ CMOS 0.8 × SPIVDD 0 400 0.6 0.5 LVDS/LVPECL/CMOS 1200 1800 0.85 2.0 35 2.5 V V mV p-p V kΩ pF CMOS 0.8 × SPIVDD 0 0.5 V V kΩ 30 Full Full 360 770 mV p-p 25°C 25°C 25°C 25°C Full 0 −100 8 6 80 1.8 +100 V mA dB dB Ω Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate. Rev. B | Page 8 of 72 CML 100 120 Data Sheet AD9234 SWITCHING SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted. Table 4. Parameter CLOCK Clock Rate (at CLK+/CLK− Pins) Maximum Sample Rate 1 Minimum Sample Rate 2 Clock Pulse Width High Clock Pulse Width Low OUTPUT PARAMETERS Unit Interval (UI) 3 Rise Time (tR) (20% to 80% into 100 Ω Load) Fall Time (tF) (20% to 80% into 100 Ω Load) PLL Lock Time Data Rate per Channel (NRZ) 4 LATENCY 5 Pipeline Latency Fast Detect Latency Wake-Up Time 6 Standby Power-Down APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tj) Out-of-Range Recovery Time AD9234-500 Typ Max Temperature Min Full Full Full Full Full 0.3 500 300 1000 1000 Full 25°C 25°C 25°C 25°C 80 24 24 3.125 4 200 32 32 2 5 Full Full 55 25°C 25°C 1 Full Full Full 530 55 1 AD9234-1000 Min Typ Max Unit 0.3 1000 300 500 500 GHz MSPS MSPS ps ps 80 24 24 12.5 3.125 4 100 32 32 2 10 12.5 ps ps ps ms Gbps 28 Clock cycles Clock cycles 4 ms ms 55 28 1 4 530 55 1 ps fs rms Clock Cycles The maximum sample rate is the clock rate after the divider. The minimum sample rate operates at 300 MSPS with L = 2 or L = 1. 3 Baud rate = 1/UI. A subset of this range can be supported. 4 Default L = 4. This number can be changed based on the sample rate and decimation ratio. 5 No DDCs used. L = 4, M = 2, F = 1. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode. 1 2 TIMING SPECIFICATIONS Table 5. Parameter CLK+ to SYSREF+ TIMING REQUIREMENTS tSU_SR tH_SR SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tACCESS tEN_SDIO tDIS_SDIO Test Conditions/Comments See Figure 2 Device clock to SYSREF+ setup time Device clock to SYSREF+ hold time See Figure 3 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Maximum time delay between falling edge of SCLK and output data valid for a read operation Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 3) Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 3) Rev. B | Page 9 of 72 Min Typ Max Unit 117 −96 ps ps 6 ns ns ns ns ns ns ns ns 2 2 40 2 2 10 10 10 10 ns 10 ns AD9234 Data Sheet Timing Diagrams CLK– CLK+ tSU_SR tH_SR 12244-003 SYSREF– SYSREF+ Figure 2. SYSREF± Setup and Hold Timing tHIGH tDS tS tCLK tDH tACCESS tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 12244-004 SCLK DON’T CARE Figure 3. Serial Port Interface Timing Diagram APERTURE DELAY ANALOG INPUT SIGNAL SAMPLE N N – 54 N+1 N – 55 N – 53 N – 52 N–1 N – 51 CLK– CLK+ CLK– CLK+ SERDOUT0– A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 LSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 LSB SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SAMPLE N – 55 ENCODED INTO 1 8-BIT/10-BIT SYMBOL SAMPLE N – 54 ENCODED INTO 1 8-BIT/10-BIT SYMBOL SAMPLE N – 53 ENCODED INTO 1 8-BIT/10-BIT SYMBOL Figure 4. Data Output Timing (Full Bandwidth Mode; L = 4; M = 2; F = 1) Rev. B | Page 10 of 72 12244-002 SERDOUT3+ Data Sheet AD9234 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical AVDD1 to AGND AVDD1_SR to AGND AVDD2 to AGND AVDD3 to AGND DVDD to DGND DRVDD to DRGND SPIVDD to AGND AGND to DRGND VIN±x to AGND SCLK, SDIO, CSB to AGND PDWN/STBY to AGND Operating Temperature Range Junction Temperature Range Storage Temperature Range (Ambient) Rating 1.32 V 1.32 V 2.75 V 3.63 V 1.32 V 1.32 V 3.63 V −0.3 V to +0.3 V 3.2 V −0.3 V to SPIVDD + 0.3 V −0.3 V to SPIVDD + 0.3 V −40°C to +85°C −40°C to +125°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Typical θJA, θJB, and θJC are specified vs. the number of printed circuit board (PCB) layers in different airflow velocities (in m/sec). Airflow increases heat dissipation effectively reducing θJA and θJB. In addition, metal in direct contact with the package leads and exposed pad from metal traces, through holes, ground, and power planes, reduces the θJA. Thermal performance for actual applications requires careful inspection of the conditions in an application. The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in Table 6. Table 7. Thermal Resistance Values PCB Type JEDEC 2s2p Board Airflow Velocity (m/sec) 0.0 1.0 2.5 θJA 17.81, 2 15.61, 2 15.01, 2 ΨJB 6.31, 3 5.91, 3 5.71, 3 θJC_TOP 4.71, 5 N/A4 N/A4 θJC_BOT 1.21, 5 Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per JEDEC JESD51-8 (still air). 4 N/A = not applicable. 5 Per MIL-STD 883, Method 1012.1. 1 2 ESD CAUTION Rev. B | Page 11 of 72 Unit °C/W °C/W °C/W AD9234 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD1 AVDD2 AVDD2 AVDD1 AGND SYSREF– SYSREF+ AVDD1_SR AGND AVDD1 CLK– CLK+ AVDD1 AVDD2 AVDD2 AVDD1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9234 TOP VIEW (Not to Scale) AVDD1 AVDD1 AVDD2 AVDD3 VIN–B VIN+B AVDD3 AVDD2 AVDD2 AVDD2 SPIVDD CSB SCLK SDIO DVDD DGND NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE GROUND REFENCE FOR AVDDx. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 12244-005 FD_A DRGND DRVDD SYNCINB– SYNCINB+ SERDOUT0– SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ DRVDD DRGND FD_B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD1 AVDD1 AVDD2 AVDD3 VIN–A VIN+A AVDD3 AVDD2 AVDD2 AVDD2 AVDD2 V_1P0 SPIVDD PDWN/STBY DVDD DGND Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. Power Supplies 0 Mnemonic Type Description EPAD Ground 1, 2, 47, 48, 49, 52, 55, 61, 64 3, 8, 9, 10, 11, 39, 40, 41, 46, 50, 51, 62, 63 4, 7, 42, 45 13, 38 15, 34 16, 33 18, 31 19, 30 56, 60 57 Analog 5, 6 12 AVDD1 AVDD2 Supply Supply Exposed Pad. The exposed thermal pad on the bottom of the package provides the ground reference for AVDDx. This exposed pad must be connected to ground for proper operation. Analog Power Supply (1.25 V Nominal). Analog Power Supply (2.5 V Nominal). AVDD3 SPIVDD DVDD DGND DRGND DRVDD AGND1 AVDD1_SR 1 Supply Supply Supply Ground Ground Supply Ground Supply Analog Power Supply (3.3 V Nominal). Digital Power Supply for SPI (1.8 V to 3.3 V). Digital Power Supply (1.25 V Nominal). Ground Reference for DVDD. Ground Reference for DRVDD. Digital Driver Power Supply (1.25 V Nominal). Ground Reference for SYSREF±. Analog Power Supply for SYSREF± (1.25 V Nominal). VIN−A, VIN+A V_1P0 Input Input/DNC VIN+B, VIN−B CLK+, CLK− Input Input ADC A Analog Input Complement/True. 1.0 V Reference Voltage Input/Do Not Connect. This pin is configurable through the SPI as a no connect or an input. Do not connect this pin if using the internal reference. This pin requires a 1.0 V reference voltage input if using an external voltage reference source. ADC B Analog Input True/Complement. Clock Input True/Complement. FD_A, FD_B Output Fast Detect Outputs for Channel A and Channel B. 43, 44 53, 54 CMOS Outputs 17, 32 Rev. B | Page 12 of 72 Data Sheet Pin No. Digital Inputs 20, 21 58, 59 Data Outputs 22, 23 24, 25 26, 27 28, 29 Device Under Test (DUT) Controls 14 35 36 37 1 AD9234 Mnemonic Type Description SYNCINB−, SYNCINB+ SYSREF+, SYSREF− Input Input Active Low JESD204B LVDS Sync Input Complement/True. Active High JESD204B LVDS System Reference Input True/Complement. SERDOUT0−, SERDOUT0+ SERDOUT1−, SERDOUT1+ SERDOUT2−, SERDOUT2+ SERDOUT3−, SERDOUT3+ Output Output Output Output Lane 0 Output Data Complement/True. Lane 1 Output Data Complement/True. Lane 2 Output Data Complement/True. Lane 3 Output Data Complement/True. PDWN/STBY Input SDIO SCLK CSB Input/output Input Input Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as powerdown or standby. SPI Serial Data Input/Output. SPI Serial Clock. SPI Chip Select (Active Low). To ensure proper ADC operation, connect AVDD1_SR and AGND separately from the AVDD1 and EPAD connection. For more information, refer to the Applications Information section. Rev. B | Page 13 of 72 AD9234 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AD9234-1000 AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.34 V p-p full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted. 0 0 AIN = –1dBFS SNR = 64.2dBFS ENOB = 10.4BITS SFDR = 88dBFS BUFFER CURRENT = 2.5× –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –40 –60 –80 0 100 200 300 400 500 FREQUENCY (MHz) –120 12244-100 –120 0 300 400 500 Figure 9. Single-Tone FFT with fIN = 450.3 MHz 0 0 AIN = –1dBFS SNR = 63.9dBFS ENOB = 10.3 BITS SFDR = 80dBFS BUFFER CURRENT = 2.5× AIN = –1dBFS SNR = 61.6dBFS ENOB = 9.9 BITS SFDR = 81dBFS BUFFER CURRENT = 6.5× –20 AMPLITUDE (dBFS) –20 –40 –60 –80 –40 –60 –80 –100 –100 0 100 200 300 400 500 FREQUENCY (MHz) –120 12244-101 –120 0 100 200 300 400 500 FREQUENCY (MHz) 12244-300 AMPLITUDE (dBFS) 200 FREQUENCY (MHz) Figure 6. Single-Tone FFT with Input Frequency (fIN) = 10.3 MHz Figure 10. Single-Tone FFT with fIN = 737.3 MHz Figure 7. Single-Tone FFT with fIN = 170.3 MHz 0 0 AIN = –1dBFS SNR = 63.4dBFS ENOB = 10.2 BITS SFDR = 79dBFS BUFFER CURRENT = 3.0× AIN = –1dBFS SNR = 60.7dBFS ENOB = 9.8 BITS SFDR = 79dBFS BUFFER CURRENT = 6.5× –20 AMPLITUDE (dBFS) –20 –40 –60 –80 –100 –40 –60 –80 –100 –120 0 100 200 300 400 FREQUENCY (MHz) 500 12244-102 AMPLITUDE (dBFS) 100 12244-103 –100 Figure 8. Single-Tone FFT with fIN = 340.3 MHz –120 0 100 200 300 400 FREQUENCY (MHz) Figure 11. Single-Tone FFT with fIN = 985.3 MHz Rev. B | Page 14 of 72 500 12244-301 AMPLITUDE (dBFS) –20 AIN = –1dBFS SNR = 63.1dBFS ENOB = 10.2 BITS SFDR = 80dBFS BUFFER CURRENT = 4.5× Data Sheet AD9234 0 90 AIN = –1dBFS SNR = 59.7dBFS ENOB = 9.6 BITS SFDR = 80dBFS BUFFER CURRENT = 7.0× SFDR (dBFS) –40 SNR/SFDR (dBFS) –60 –80 80 70 SNR (dBFS) –100 0 100 200 300 400 500 FREQUENCY (MHz) 60 10.3 12244-302 –120 128.3 180.3 242.3 309.3 361.3 420.3 480.3 INPUT FREQUENCY (MHz) Figure 12. Single-Tone FFT with fIN = 1213.3 MHz Figure 15. SNR/SFDR vs. Input Frequency (fIN); fIN < 500 MHz ; Buffer Current = 3.5× (Uses Circuit Shown in Figure 63) 90 0 AIN = –1dBFS SNR = 58.8dBFS ENOB = 9.5 BITS SFDR = 78dBFS BUFFER CURRENT = 7.5× –20 80 –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) 85.3 12244-306 AMPLITUDE (dBFS) –20 –60 –80 SFDR (dBFS) 70 SNR (dBFS) 60 0 100 200 300 400 500 FREQUENCY (MHz) 50 453.3 629.3 737.3 837.3 937.3 1077.3 1177.3 1277.3 1377.3 1477.3 12244-303 –120 INPUT FREQUENCY (MHz) Figure 16. SNR/SFDR vs. Input Frequency; 450 MHz < fIN < 1500 MHz; Buffer Current = 7.5× (Uses Circuit Shown in Figure 64) Figure 13. Single-Tone FFT with fIN = 1413.3 MHz 80 90 SFDR (dBFS) SFDR (dBFS) SNR/SFDR (dBFS) 80 70 70 60 SNR (dBFS) 60 700 750 800 850 900 950 1000 1050 SAMPLE RATE (MHz) Figure 14. SNR/SFDR vs. Sample Rate (fS), fIN = 170.3 MHz ; Buffer Current = 3.0× 1100 50 1523.3 1587.3 1623.3 1687.3 1723.3 1787.3 1823.3 1887.3 1923.3 1987.3 INPUT FREQUENCY (MHz) 12244-308 SNR (dBFS) 12244-304 SNR/SFDR (dBFS) 12244-307 –100 Figure 17. SNR/SFDR vs. Input Frequency; 1500 MHz < fIN < 2000 MHz; Buffer Current = 8.5× (Uses Circuit Shown in Figure 64) Rev. B | Page 15 of 72 AD9234 Data Sheet 0 0 AIN1 AND AIN2 = –7dBFS SFDR = 81dBFS IMD2 = 81dBFS IMD3 = 83dBFS BUFFER CURRENT = 4.5× SFDR (dBc) –20 SFDR/IMD3 (dBc AND dBFS) –40 –60 –80 –100 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 0 100 200 300 400 500 FREQUENCY (MHz) IMD3 (dBFS) –120 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 12244-205 –120 INPUT AMPLITUDE (dBFS) Figure 18. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz Figure 21. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 338 MHz and fIN2 = 341 MHz 120 AIN1 AND AIN2 = –7dBFS SFDR = 78dBFS IMD2 = 78dBFS IMD3 = 85dBFS BUFFER CURRENT = 4.5× –15 –30 SFDR (dBFS) 100 SNR/SFDR (dBc AND dBFS) 0 AMPLITUDE (dBFS) –40 12244-208 AMPLITUDE (dBFS) –20 –45 –60 –75 –90 –105 80 SNR (dBFS) 60 40 SFDR (dBc) 20 SNR (dBc) 0 –120 0 100 200 300 400 500 FREQUENCY (MHz) –40 –97 12244-206 –150 –84 –74 –64 –54 –44 –34 –24 –14 –4 INPUT AMPLITUDE (dBFS) Figure 19. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz 12244-209 –20 –135 Figure 22. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz; Buffer Current = 2.0× 0 90 SFDR (dBc) SFDR SNR/SFDR (dBFS) –40 IMD3 (dBc) –60 –80 80 70 SFDR (dBFS) SNR IMD3 (dBFS) –120 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 INPUT AMPLITUDE (dBFS) Figure 20. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz 60 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 TEMPERATURE (°C) Figure 23. SNR/SFDR vs. Temperature, fIN = 170.3 MHz Rev. B | Page 16 of 72 85 12244-400 –100 12244-207 SFDR/IMD3 (dBc AND dBFS) –20 Data Sheet AD9234 3.10 0.4 3.05 POWER DISSIPATION (W) 0.6 0 –0.2 –0.4 3.00 2.95 2.90 2.85 2.80 –0.6 0 500 1000 1500 2000 2500 3000 3500 4000 OUTPUT CODE 2.75 –45 –35 –25 –15 –5 12244-401 –0.8 5 15 25 35 45 55 65 75 85 TEMPERATURE (°C) Figure 24. INL, fIN = 10.3 MHz 12244-404 INL (LSB) 0.2 Figure 27. Power Dissipation vs. Temperature 0.3 3.5 3.4 0.2 POWER DISSIPATION (W) 3.3 DNL (LSB) 0.1 0 –0.1 3.2 3.1 3.0 2.9 2.8 2.7 –0.2 500 1000 1500 2000 2500 3000 3500 4000 OUTPUT CODE 2.5 700 12244-402 0 1.02 LSB rms 3000000 2000000 1500000 1000000 500000 N N+1 N+2 OUTPUT CODE N+3 12244-403 NUMBER OF HITS 2500000 N–1 820 860 900 940 980 1020 1060 1110 Figure 28. Power Dissipation vs. Sample Rate (fS) 3500000 N–2 780 SAMPLE RATE (MHz) Figure 25. DNL, fIN = 10 MHz 0 N–3 740 Figure 26. Input Referred Noise Histogram Rev. B | Page 17 of 72 12244-405 2.6 –0.3 AD9234 Data Sheet AD9234-500 AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.63 V p-p full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted. 0 0 AIN = –1dFBS SNR = 65.9dBFS ENOB = 10.7BITS SFDR = 85dBFS BUFFER CURRENT = 2.5× AIN = –1dFBS SNR = 65.3dBFS ENOB = 10.5BITS SFDR = 86dBFS BUFFER CURRENT = 4.5× –20 AMPLITUDE (dBFS) –40 –60 –80 –40 –60 –80 0 50 100 150 FREQUENCY (MHz) 200 250 –120 12244-030 –120 0 100 150 200 250 FREQUENCY (MHz) Figure 32. Single-Tone FFT with fIN = 450.3 MHz Figure 29. Single-Tone FFT with Input Frequency (fIN) = 10.3 MHz 0 0 AIN = –1dFBS SNR = 65.9dBFS ENOB = 10.6BITS SFDR = 85dBFS BUFFER CURRENT = 2.5× AIN = –1dFBS SNR = 64.2dBFS ENOB = 10.3BITS SFDR = 75dBFS BUFFER CURRENT = 4.5x –20 AMPLITUDE (dBFS) –20 –40 –60 –80 –40 –60 –80 –100 –100 250 12244-509 AMPLITUDE (dBFS) 50 250 0 50 100 150 200 250 FREQUENCY (MHz) 12244-506 –120 –120 0 50 100 150 200 FREQUENCY (MHz) Figure 33. Single-Tone FFT with fIN = 737.3 MHz Figure 30. Single-Tone FFT with fIN = 170.3 MHz 0 0 AIN = –1dFBS SNR = 65.5dBFS ENOB = 10.5BITS SFDR = 86dBFS BUFFER CURRENT = 4.5× AIN = –1dFBS SNR = 63.6dBFS ENOB = 10.2BITS SFDR = 75dBFS BUFFER CURRENT = 5.5× –20 AMPLITUDE (dBFS) –20 –40 –60 –80 –40 –60 –80 –100 –100 –120 –120 0 50 100 150 200 FREQUENCY (MHz) 250 12244-507 AMPLITUDE (dBFS) 12244-508 –100 –100 12244-510 AMPLITUDE (dBFS) –20 Figure 31. Single-Tone FFT with fIN = 340.3 MHz 0 50 100 150 200 FREQUENCY (MHz) Figure 34. Single-Tone FFT with fIN = 985.3 MHz Rev. B | Page 18 of 72 Data Sheet AD9234 90 0 AIN = –1dFBS SNR = 62.9dBFS ENOB = 10.0BITS SFDR = 72dBFS BUFFER CURRENT = 8.5× –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) –20 –60 –80 80 2.5× SNR 2.5× SFDR 4.5× SNR 4.5× SFDR 70 12244-515 480.3 450.3 420.3 390.3 360.3 340.7 330.3 301.3 270.3 240.3 210.3 60 180.3 250 170.3 200 150.3 150 95.3 100 FREQUENCY (MHz) 125.3 50 65.3 0 10.3 –120 12244-511 –100 FREQUENCY (MHz) Figure 38. SNR/SFDR vs. Input Frequency; fIN < 500 MHz; Buffer Current = 2.5× and 4.5× (Uses Circuit Shown in Figure 63 Figure 35. Single-Tone FFT with fIN = 1213.3 MHz 90 0 –20 –40 SNF/SFDR (dBFS) AMPLITUDE (dBFS) 6.5× SNR 6.5× SFDR 8.5× SNR 8.5× SFDR AIN = –1dFBS SNR = 62.2dBFS ENOB = 9.9BITS SFDR = 71dBFS BUFFER CURRENT = 8.5× –60 –80 80 70 FREQUENCY (MHz) Figure 36. Single-Tone FFT with fIN = 1413.3 MHz 12244-516 1510.3 1410.3 1310.3 1205.3 1110.3 1010.3 985.3 60 810.3 250 765.3 200 610.3 150 515.3 100 FREQUENCY (MHz) 510.3 50 480.3 0 450.3 –120 12244-512 –100 Figure 39. SNR/SFDR vs. Input Frequency; 450 MHz < fIN < 1500 MHz; Buffer Current = 6.5× and 8.5× (Uses Circuit Shown in Figure 64) 90 72 70 SFDR (dBFS) SFDR (dBFS) SNR/SFDR (dBFS) 80 70 66 64 62 SNR (dBFS) 60 58 SNRFS (dBFS) 60 300 320 340 360 380 400 420 440 460 480 500 520 540 FREQUENCY (MHz) Figure 37. SNR/SFDR vs. Sample Rate (fS), fIN = 170.3 MHz; Buffer Current = 3.0× 54 1510.3 1600.3 1710.3 1810.3 FREQUENCY (MHz) 1910.3 1950.3 12244-517 56 12244-513 SNRFS/SFDR (dBFS) 68 Figure 40. SNR/SFDR vs. Input Frequency; 1500 MHz < fIN < 2000 MHz; Buffer Current = 8.5× (Uses Circuit Shown in Figure 64) Rev. B | Page 19 of 72 AD9234 Data Sheet 0 0 AIN1 AND AIN2 = –7dBFS SFDR = 90dBFS IMD2 = 99dBFS IMD3 = 90dBFS BUFFER CURRENT = 2.0× –40 –60 –80 –40 IMD3 (dBc) –60 –80 SFDR (dBFS) 0 100 50 250 200 150 FREQUENCY (MHz) –120 –90 12244-518 –120 Figure 41. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz IMD3 (dBFS) –80 –70 –60 –50 –40 AMPLITUDE –30 –20 –10 12244-521 –100 –100 Figure 44. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 338 MHz and fIN2 = 341 MHz 0 120 AIN1 AND AIN2 = –7dBFS SFDR = 86dBFS IMD2 = 86dBFS IMD3 = 76dBFS BUFFER CURRENT = 4.5× SFDR (dBFS) 100 SNR/SFDR (dBc AND dBFS) –20 AMPLITUDE (dBFS) SFDR (dBc) –20 SFDR/IMD3 (dBc AND dBFS) AMPLITUDE (dBFS) –20 –40 –60 –80 80 SNR (dBFS) 60 SFDR (dBc) 40 20 0 –100 50 100 150 250 200 FREQUENCY (MHz) –40 –90 –70 –60 –50 –40 –30 –20 –10 0 85 AMPLITUDE (dBFS) Figure 42. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz Figure 45. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz; Buffer Current = 2.0× 0 100 SFDR (dBc) –20 SFDR (dBFS) SNR/SFDR (dBFS) 90 –40 IMD3 (dBc) –60 –80 SFDR (dBFS) 80 70 SNRFS (dBFS) –100 –120 –90 IMD3 (dBFS) –80 –70 –60 –50 –40 AMPLITUDE (dBFS) –30 –20 –10 12244-520 SFDR/IMD3 (dBc AND dBFS) –80 12244-522 0 SNR (dBc) 12244-523 –120 12244-519 –20 Figure 43. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz 60 –45 –25 –15 –5 15 25 45 65 TEMPERATURE (°C) Figure 46. SNR/SFDR vs. Temperature, fIN = 170.3 MHz Rev. B | Page 20 of 72 Data Sheet AD9234 0.4 2.14 0.3 2.13 0.2 2.12 2.11 DUT POWER INL (LSB) 0.1 0 –0.1 2.10 2.09 2.08 –0.2 2.07 –0.3 2.06 –0.4 1000 1500 2000 2500 3000 3500 4000 OUTPUT CODE 2.04 –45 –25 –15 –5 15 25 TEMPERATURE (°C) 45 65 85 12244-527 500 550 12244-528 0 12244-524 2.05 –0.5 Figure 50. Power Dissipation vs. Temperature Figure 47. INL, fIN = 10.3 MHz 0.15 2.20 2.15 0.10 POWER DISSIPATION (W) 2.10 DNL (LSB) 0.05 0 –0.05 L.M.F = 4.2.1 2.05 2.00 1.95 L.M.F = 2.2.2 1.90 1.85 1.80 –0.10 –0.15 0 500 1000 1500 2000 2500 3000 3500 4000 OUTPUT CODE 12244-525 1.75 Figure 48. DNL, fIN = 10 MHz 1,800,000 1,600,000 1,400,000 1,200,000 1,000,000 800,000 600,000 400,000 12244-526 200,000 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 NUMBER OF HITS 350 400 450 500 SAMPLE RATE (MHz) Figure 51. Power Dissipation vs. Sample Rate (fS) 2,000,000 0 1.70 300 OUTPUT CODE Figure 49. Input Referred Noise Histogram Rev. B | Page 21 of 72 AD9234 Data Sheet EQUIVALENT CIRCUITS AVDD3 AVDD3 VIN+x AVDD3 200Ω EMPHASIS/SWING CONTROL (SPI) VCM BUFFER 200Ω DRVDD DATA+ AVDD3 AVDD3 SERDOUTx+ x = 0, 1, 2, 3 3pF SERDOUTx– x = 0, 1, 2, 3 DRGND Figure 52. Analog Inputs Figure 55. Digital Outputs DVDD AVDD1 25Ω SYNCINB+ 1kΩ DGND AVDD1 20kΩ LEVEL TRANSLATOR 25Ω CLK– DRVDD DATA– 12244-011 AIN CONTROL (SPI) CLK+ DRGND OUTPUT DRIVER VIN–x 20kΩ 20kΩ VCM = 0.85V 12244-012 DVDD 20kΩ SYNCINB– VCM = 0.85V VCM 1kΩ 12244-015 67Ω 28Ω 10pF 200Ω 400Ω SYNCINB± PIN CONTROL (SPI) DGND Figure 53. Clock Inputs Figure 56. SYNCINB± Inputs AVDD1_SR SYSREF+ 1kΩ SPIVDD 20kΩ LEVEL TRANSLATOR AVDD1_SR ESD PROTECTED VCM = 0.85V 20kΩ SCLK SPIVDD 1kΩ 30kΩ 1kΩ ESD PROTECTED 12244-016 12244-013 SYSREF– 12244-014 67Ω 200Ω 28Ω 3pF Figure 57. SCLK Input Figure 54. SYSREF± Inputs Rev. B | Page 22 of 72 Data Sheet AD9234 SPIVDD ESD PROTECTED 30kΩ 1kΩ CSB 30kΩ 1kΩ PDWN/ STBY ESD PROTECTED 12244-017 ESD PROTECTED Figure 58. CSB Input PDWN CONTROL (SPI) Figure 61. PDWN/STBY Input AVDD2 SPIVDD ESD PROTECTED SDO ESD PROTECTED SPIVDD 1kΩ SDIO 12244-020 ESD PROTECTED SPIVDD SDI V_1P0 ESD PROTECTED 12244-018 ESD PROTECTED V_1P0 PIN CONTROL (SPI) Figure 59. SDIO Input Figure 62. V_1P0 Input SPIVDD ESD PROTECTED FD_A/FD_B FD JESD LMFC JESD SYNC~ TEMPERATURE DIODE (FD_A ONLY) FD_x PIN CONTROL (SPI) 12244-019 ESD PROTECTED Figure 60. FD_A/FD_B Outputs Rev. B | Page 23 of 72 12244-021 30kΩ AD9234 Data Sheet THEORY OF OPERATION The AD9234 has two analog input channels and four JESD204B output lane pairs. The ADC is designed to sample wide bandwidth analog signals of up to 2 GHz. The AD9234 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD9234 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. The Subclass 1 JESD204B-based high speed serialized output data rate can be configured in one-lane (L = 1), two-lane (L = 2), and four-lane (L = 4) configurations, depending on the sample rate and the decimation ratio. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins. ADC ARCHITECTURE The architecture of the AD9234 consists of an input buffered pipelined ADC. The input buffer is designed to provide a termination impedance to the analog input signal. This termination impedance can be changed using the SPI to meet the termination needs of the driver/amplifier. The default termination value is set to 400 Ω. The equivalent circuit diagram of the analog input termination is shown in Figure 52. The input buffer is optimized for high linearity, low noise, and low power. The input buffer provides a linear high input impedance (for ease of drive) and reduces kickback from the ADC. The buffer is optimized for high linearity, low noise, and low power. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample; at the same time, the remaining stages operate with the preceding samples. Sampling occurs on the rising edge of the clock. ANALOG INPUT CONSIDERATIONS The analog input to the AD9234 is a differential buffer. The internal common-mode voltage of the buffer is 2.05 V. The clock signal alternately switches the input circuit between sample mode and hold mode. When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor, in series with each input, helps reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, thus, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a differential capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input, which limits unwanted broadband noise. For more information, refer to the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “TransformerCoupled Front-End for Wideband A/D Converters” (Volume 39, April 2005). In general, the precise values depend on the application. For best dynamic performance, the source impedances driving VIN+x and VIN−x must be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates a differential reference that defines the span of the ADC core. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9234, the available span is 1.34 V p-p differential for AD9234-1000 and 1.63 V p-p differential for AD9234-500. Differential Input Configurations There are several ways to drive the AD9234, either actively or passively. However, optimum performance is achieved by driving the analog input differentially. For applications where SNR and SFDR are key parameters, differential transformer coupling is the recommended input configuration (see Figure 63 and Figure 64) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9234. For low to midrange frequencies, a double balun or double transformer network (see Figure 63) is recommended for optimum performance of the AD9234. For higher frequencies in the second and third Nyquist zones, it is better to remove some of the front-end passive components to ensure wideband operation (see Figure 64). Rev. B | Page 24 of 72 Data Sheet AD9234 10Ω 10Ω 0.1µF 25Ω 4pF ADC 2pF 0.1µF 25Ω 10Ω 10Ω 0.1µF 12244-022 ETC1-11-13/ MABA007159 1:1Z 4pF Figure 63. Differential Transformer-Coupled Configuration for Frequencies up to 500 MHz 25Ω 25Ω MARKI BAL-0006 OR BAL-0006SMG 25Ω 0.1µF ADC 0.1µF 12244-023 25Ω 0.1µF Figure 64. Differential Transformer-Coupled Configuration for Frequencies > 500 MHz Input Common Mode The analog inputs of the AD9234 are internally biased to the common mode as shown in Figure 65. The common-mode buffer has a limited range in that the performance suffers greatly if the common-mode voltage drops by more than 100 mV. Therefore, in dc-coupled applications, set the common-mode voltage to 2.05 V, ±100 mV to ensure proper ADC operation. Using Register 0x018, the buffer currents on each channel can be scaled to optimize the SFDR over various input frequencies and bandwidths of interest. As the input buffer currents are set, the amount of current required by the AVDD3 supply changes. This relationship is shown in Figure 66. For a complete list of buffer current settings, see Table 25. 300 AD9234-1000 AD9234-500 Analog Input Controls and SFDR Optimization 250 IAVDD3 (mA) The AD9234 offers flexible controls for the analog inputs, such as input termination and buffer current. All of the available controls are shown in Figure 65. AVDD3 AVDD3 200 150 VIN+x 3pF 50 VCM BUFFER 1.5× 2.5× 3.5× 4.5× 5.5× 6.5× 7.5× BUFFER CONTROL 1 SETTING 200Ω 67Ω 28Ω 10pF 200Ω 400Ω Figure 66. AVDD3 Power (IAVDD3) vs. Buffer Current Setting AVDD3 AVDD3 VIN–x AIN CONTROL (SPI) REGISTERS (0x008, 0x015, 0x016, 0x018) 12244-027 3pF Figure 65. Analog Input Controls Rev. B | Page 25 of 72 8.5× 12244-341 200Ω 67Ω 200Ω 28Ω 100 AVDD3 AD9234 Data Sheet 80 75 8.5× 70 7.5× 65 SFDR (dBFS) Figure 67, Figure 68, and Figure 69 show how the SFDR for AD9234-1000 can be optimized using the buffer current setting in Register 0x018 for different Nyquist zones. Figure 70, Figure 71, and Figure 72 show how the SFDR for AD9234-500 can be optimized using the buffer current setting in Register 0x018 for different Nyquist zones. At frequencies greater than 1 GHz, it is better to run the ADC at input amplitudes less than −1 dBFS (−3 dBFS, for example). This greatly improves the linearity of the converted signal without sacrificing SNR performance. 6.5× 60 5.5× 55 50 45 40 90 30 1523.3 1587.3 1623.3 1687.3 1723.3 1787.3 1823.3 1887.3 1923.3 1987.3 4.5× INPUT FREQUENCY (MHz) Figure 69. Buffer Current Sweeps, AD9234-1000; SFDR vs. Input Frequency (IBUFF); 1500 MHz < fIN < 2000 MHz 75 3.5× 1.5× 70 95 2.5× 90 60 85 55 80 50 10.3 85.3 128.3 180.3 242.3 309.3 361.3 420.3 480.3 INPUT FREQUENCY (MHz) SFDR (dBFS) 65 12244-342 SFDR (dBFS) 80 12244-344 35 85 Figure 67. Buffer Current Sweeps, AD9234-1000; SFDR vs. Input Frequency (IBUFF); fIN < 500 MHz 4.5× 3.5× 75 2.5× 2.0× 70 65 60 90 1.5× 55 12244-529 480.3 450.3 420.3 390.3 360.3 340.7 330.3 301.3 270.3 240.3 210.3 180.3 170.3 150.3 95.3 125.3 65.3 7.5× FREQUENCY (MHz) 75 Figure 70. Buffer Current Sweeps, AD9234-500; SFDR vs. Input Frequency (IBUFF); fIN < 500 MHz 70 6.5× 90 5.5× 60 85 80 50 453.3 629.3 737.3 837.3 937.3 1077.3 1177.3 1277.3 1377.3 1477.3 75 FREQUENCY (MHz) Figure 71. Buffer Current Sweeps, AD9234-500; SFDR vs. Input Frequency (IBUFF); 500 MHz < fIN < 1500 MHz Rev. B | Page 26 of 72 12244-530 1410.3 1310.3 1205.3 1110.3 50 1010.3 4.5× 985.3 55 810.3 5.5× 765.3 60 610.3 6.5× 1510.3 7.5× 65 515.3 Figure 68. Buffer Current Sweeps, AD9234-1000; SFDR vs. Input Frequency (IBUFF); 500 MHz < fIN < 1500 MHz 8.5× 70 510.3 INPUT FREQUENCY (MHz) SFDR (dBFS) 55 480.3 4.5× 450.3 65 12244-343 SFDR (dBFS) 50 8.5× 80 10.3 85 Data Sheet AD9234 72 VIN+A/ VIN+B 70 8.5× VIN–A/ VIN–B 68 7.5× INTERNAL V_1P0 GENERATOR 64 ADC CORE FULL-SCALE VOLTAGE ADJUST 62 V_1P0 ADJUST SPI REGISTER (0x024) 6.5× V_1P0 58 V_1P0 PIN CONTROL SPI REGISTER (0x024) 56 1600.3 1710.3 1810.3 FREQUENCY (MHz) 1910.3 Figure 73. Internal Reference Configuration and Controls 1950.3 Figure 72. Buffer Current Sweeps, AD9234-500; SFDR vs. Input Frequency (IBUFF); 1500 MHz < fIN < 2000 MHz Table 9 shows the recommended buffer current and full-scale voltage settings for the different analog input frequency ranges. Table 9. SFDR Optimization for Analog Input Frequencies Input Frequency 1 GHz Input Buffer Current Control Setting, Register 0x018 2.5× or 3.0× 4.5× or 6.5× 6.5× or higher The SPI Register 0x024 enables the user to either use this internal 1.0 V reference, or to provide an external 1.0 V reference. When using an external voltage reference, provide a 1.0 V reference. The use of an external reference may be necessary, in some applications, to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 74 shows the typical drift characteristics of the internal 1.0 V reference. 1.0010 1.0009 1.0008 1.0007 V_1P0 VOLTAGE (V) Absolute Maximum Input Swing The absolute maximum input swing allowed at the inputs of the AD9234 is 4.3 V p-p differential. Signals operating near or at this level can cause permanent damage to the ADC. VOLTAGE REFERENCE 1.0006 1.0005 1.0004 1.0003 1.0002 1.0001 A stable and accurate 1.0 V voltage reference is built into the AD9234. This internal 1.0 V reference is used to set the fullscale input range of the ADC. For more information on adjusting the input swing, see Table 25. Figure 73 shows the block diagram of the internal 1.0 V reference controls. 1.0000 0.9999 0.9998 –50 0 25 TEMPERATURE (°C) 90 Figure 74. Typical V_1P0 Drift The external reference must be a stable 1.0 V reference. The ADR130 is a good option for providing the 1.0 V reference. Figure 75 shows how the ADR130 can be used to provide the external 1.0 V reference to the AD9234. The grayed out areas show unused blocks within the AD9234 while using the ADR130 to provide the external reference. INTERNAL V_1P0 GENERATOR ADR130 INPUT 1 NC 2 GND SET 5 3 VIN 0.1µF V_1P0 ADJUST NC 6 VOUT 4 V_1P0 0.1µF V_1P0 ADJUST Figure 75. External Reference Using ADR130 Rev. B | Page 27 of 72 12244-032 52 1510.3 12244-531 54 12244-031 60 12244-106 SFDR (dBFS) 66 AD9234 Data Sheet CLOCK INPUT CONSIDERATIONS Input Clock Divider For optimum performance, drive the AD9234 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or clock drivers. These pins are biased internally and require no additional biasing. The AD9234 contains an input clock divider with the ability to divide the Nyquist input clock by 1, 2, 4, and 8. The divider ratios can be selected using Register 0x10B. This is shown in Figure 79. Figure 76 shows a preferred method for clocking the AD9234. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. 0.1µF CLK+ 100Ω 50Ω CLK+ ADC CLK– 0.1µF CLK– ÷2 ÷4 Figure 76. Transformer-Coupled Differential Clock ÷8 Another option is to ac couple a differential CML or LVDS signal to the sample clock input pins, as shown in Figure 77 and Figure 78. REG 0x10B Figure 79. Clock Divider Circuit 3.3V 71Ω 10pF 33Ω 33Ω Z0 = 50Ω The AD9234 clock divider can be synchronized using the external SYSREF± input. A valid SYSREF± causes the clock divider to reset to a programmable state. This feature is enabled by setting Bit 7 of Register 0x10D. This synchronization feature allows multiple devices to have their clock dividers aligned to guarantee simultaneous input sampling. See the Deterministic Latency section for more information 0.1µF ADC Z0 = 50Ω 0.1µF 12244-036 CLK+ CLK– Figure 77. Differential CML Sample Clock CLK+ LVDS DRIVER 100Ω CLK– CLOCK INPUT 50Ω1 The input clock divider inside the AD9234 provides phase delay in increments of ½ the input clock cycle. Register 0x10C can be programmed to enable this delay independently for each channel. Changing this register does not affect the stability of the JESD204B link. CLK+ 50Ω1 ADC CLK– 0.1µF 150Ω RESISTORS ARE OPTIONAL. 12244-037 0.1µF Input Clock Divider ½ Period Delay Adjust 0.1µF 0.1µF CLOCK INPUT 12244-038 1:1Z 12244-035 CLOCK INPUT The maximum frequency at the CLK± inputs is 4 GHz. This is the limit of the divider. In applications where the clock input is a multiple of the sample clock, care must be taken to program the appropriate divider ratio into the clock divider before applying the clock signal. This ensures that the current transients during device startup are controlled. Figure 78. Differential LVDS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. In applications where the clock duty cycle cannot be guaranteed to be 50%, a higher multiple frequency clock can be supplied to the device. The AD9234 can be clocked at 2 GHz with the internal clock divider set to 2. The output of the divider offers a 50% duty cycle, high slew rate (fast edge) clock signal to the internal ADC. See the Memory Map section for more details on using this feature. Clock Fine Delay Adjust The AD9234 sampling edge instant can be adjusted by writing to Register 0x117 and Register 0x118. Setting Bit 0 of Register 0x117 enables the feature, and Register 0x118, Bits[7:0] set the value of the delay. This value can be programmed individually for each channel. The clock delay can be adjusted from −151.7 ps to +150 ps in ~1.7 ps increments. The clock delay adjust takes effect immediately when it is enabled via SPI writes. Enabling the clock fine delay adjust in Register 0x117 causes a datapath reset. However, the contents of Register 0x118 can be changed without affecting the stability of the JESD204B link. Rev. B | Page 28 of 72 Data Sheet AD9234 CLOCK JITTER CONSIDERATIONS POWER-DOWN/STANDBY MODE High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by The AD9234 has a PDWN/STBY pin that can be used to configure the device in power-down or standby mode. The default operation is the PDWN function. The PDWN/STBY pin is a logic high pin. When in power-down mode, the JESD204B link is disrupted. The power-down option can also be set via Register 0x03F and Register 0x040. SNR = 20 × log 10 (2 × π × fA × tJ) In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 80). In standby mode, the JESD204B link is not disrupted and transmits zeroes for all converter samples. This can be changed using Register 0x571, Bit 7 to select /K/ characters. TEMPERATURE DIODE 130 12.5fS 25fS 50fS 100fS 200fS 400fS 800fS SNR (dB) 100 90 The AD9234 contains a diode-based temperature sensor for measuring the temperature of the die. This diode can output a voltage and serve as a coarse temperature sensor to monitor the internal die temperature. 80 70 60 50 30 10 100 1000 10000 ANALOG INPUT FREQUENCY (MHz) 12244-039 40 Figure 80. Ideal SNR vs. Analog Input Frequency and Jitter Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9234. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. If the clock is generated from another type of source (by gating, dividing, or other methods), retime the clock by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs. The temperature diode voltage can be output to the FD_A pin using the SPI. Use Register 0x028, Bit 0 to enable or disable the diode. Register 0x028 is a local register. Channel A must be selected in the device index register (Register 0x008) to enable the temperature diode readout. Configure the FD_A pin to output the diode voltage by programming Register 0x040[2:0]. See Table 25 for more information. The voltage response of the temperature diode (SPIVDD = 1.8 V) is shown in Figure 81. 0.90 0.85 0.80 0.75 0.70 0.65 0.60 –55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 115 125 TEMPERATURE (°C) Figure 81. Diode Voltage vs. Temperature Rev. B | Page 29 of 72 12244-353 110 DIODE VOLTAGE (V) 120 AD9234 Data Sheet ADC OVERRANGE AND FAST DETECT The operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in Figure 82. In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overrange bit in the JESD204B outputs provides information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, the latency of this function is of major concern. Highly pipelined converters can have significant latency. The AD9234 contains fast detect circuitry for individual channels to monitor the threshold and assert the FD_A and FD_B pins. The FD indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located at Register 0x247 and Register 0x248. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of 28 clock cycles (maximum). The approximate upper threshold magnitude is defined by Upper Threshold Magnitude (dBFS) = 20 log (Threshold Magnitude/213) The FD indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold registers, located at Register 0x249 and Register 0x24A. The fast detect lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to the ADC pipeline latency, but is accurate in terms of converter resolution. The lower threshold magnitude is defined by ADC OVERRANGE The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange indicator can be embedded within the JESD204B link as a control bit (when CSB > 0). The latency of this overrange indicator matches the sample latency. The AD9234 also records any overrange condition in any of the four virtual converters. For more information on the virtual converters, refer to Figure 87. The overrange status of each virtual converter is registered as a sticky bit in Register 0x563. The contents of Register 0x563 can be cleared using Register 0x562, by toggling the bits corresponding to the virtual converter to set and reset position. Lower Threshold Magnitude (dBFS) = 20 log (Threshold Magnitude/213) For example, to set an upper threshold of −6 dBFS, write 0xFFF to Register 0x247 and Register 0x248. To set a lower threshold of −10 dBFS, write 0xA1D to Register 0x249 and Register 0x24A. FAST THRESHOLD DETECTION (FD_A AND FD_B) The dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, located at Register 0x24B and Register 0x24C. See the Memory Map section (Register 0x040, and Register 0x245 to Register 0x24C in Table 25) for more details. The FD bit (enabled via the control bits in Register 0x559 and Register 0x55A) is immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. The FD bit is only cleared when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time. This feature provides hysteresis and prevents the FD bit from excessively toggling. UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LOWER THRESHOLD DWELL TIME FD_A OR FD_B Figure 82. Threshold Settings for FD_A and FD_B Signals Rev. B | Page 30 of 72 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 12244-040 MIDSCALE LOWER THRESHOLD Data Sheet AD9234 SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the peak magnitude of the digitized signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the magnitude storage register is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. The results of the signal monitor block can be obtained either by reading back the internal values from the SPI port or by embedding the signal monitoring information into the JESD204B interface as special control bits. A global, 24-bit programmable period controls the duration of the measurement. Figure 83 shows the simplified block diagram of the signal monitor block. When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register, which can be read through the memory map or output through the SPORT over the JESD204B interface. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. In addition, the magnitude of the first input sample is updated in the magnitude storage register, and the comparison and update procedure, as explained previously, continues. FROM MEMORY MAP SIGNAL MONITOR PERIOD REGISTER (SMPR) 0x271, 0x272, 0x273 DOWN COUNTER IS COUNT = 1? LOAD FROM INPUT MAGNITUDE STORAGE REGISTER LOAD LOAD SIGNAL MONITOR HOLDING REGISTER SPORT Over JESD204B TO SPORT OVER JESD204B AND MEMORY MAP 12244-406 CLEAR COMPARE A>B Figure 83. Signal Monitor Block The peak detector captures the largest signal within the observation period. The detector only observes the magnitude of the signal. The resolution of the peak detector is a 13-bit value and the observation period is 24 bits and represents converter output samples. The peak magnitude can be derived by using the following equation: Peak Magnitude (dBFS) = 20 log (Peak Detector Value/213) The magnitude of the input port signal is monitored over a programmable time period, which is determined by the signal monitor period register (SMPR). The peak detector function is enabled by setting Bit 1 of Register 0x270 in the signal monitor control register. The 24-bit SMPR must be programmed before activating this mode. After enabling this mode, the value in the SMPR is loaded into a monitor period timer, which decrements at the decimated clock rate. The magnitude of the input signal is compared with the The signal monitor data can also be serialized and sent over the JESD204B interface as control bits. These control bits must be deserialized from the samples to reconstruct the statistical data. This function is enabled by setting Bit 1 and Bit 0 of Register 0x279 and Bit 1 of Register 0x27A. Figure 84 shows two different example configurations for the signal monitor control bit locations inside the JESD204B samples. There are a maximum of three control bits that can be inserted into the JESD204B samples; however, only one control bit is required for the signal monitor. Control bits are inserted from MSB to LSB. If only one control bit is to be inserted (CS = 1), then only the most significant control bit is used (see Example Configuration 1 and Example Configuration 2 in Figure 84). To select the SPORT over JESD204B option, program Register 0x559, Register 0x55A, and Register 0x58F. See Table 25 for more information on setting these bits. Figure 85 shows the 25-bit frame data that encapsulates the peak detector value. The frame data is transmitted MSB first with five 5-bit subframes. Each subframe contains a start bit that can be used by a receiver to validate the deserialized data. Figure 86 shows the SPORT over JESD204B signal monitor data with a monitor period timer set to 80 samples. Rev. B | Page 31 of 72 AD9234 Data Sheet 16-BIT JESD204B SAMPLE SIZE (N' = 16) EXAMPLE CONFIGURATION 1 (N' = 16, N = 15, CS = 1) 1-BIT CONTROL BIT (CS = 1) 15-BIT CONVERTER RESOLUTION (N = 15) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S[14] X S[13] X S[12] X S[11] X S[10] X S[9] X S[8] X S[7] X S[6] X S[5] X S[4] X S[3] X S[2] X S[1] X S[0] X CTRL [BIT 2] X SERIALIZED SIGNAL MONITOR FRAME DATA 16-BIT JESD204B SAMPLE SIZE (N' = 16) 15 S[13] X 14 S[12] X 13 S[11] X 12 S[10] X 11 10 9 S[8] X S[9] X 8 7 S[6] X S[7] X 6 S[5] X 5 S[4] X 4 S[3] X S[2] X 3 S[1] X 2 1 0 S[0] X CTRL [BIT 2] X TAIL X SERIALIZED SIGNAL MONITOR FRAME DATA Figure 84. Signal Monitor Control Bit Locations 5-BIT SUB-FRAMES 5-BIT IDLE SUB-FRAME (OPTIONAL) 25-BIT FRAME IDLE 1 IDLE 1 IDLE 1 IDLE 1 IDLE 1 5-BIT IDENTIFIER START 0 SUB-FRAME ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 5-BIT DATA MSB SUB-FRAME START 0 P[12] P[11] P[10] P[9] 5-BIT DATA SUB-FRAME START 0 P[8] P[7] P[6] P5] 5-BIT DATA SUB-FRAME START 0 P[4] P[3] P[2] P1] 5-BIT DATA LSB SUB-FRAME START 0 P[0] 0 0 0 P[] = PEAK MAGNITUDE VALUE Figure 85. SPORT over JESD204B Signal Monitor Frame Data Rev. B | Page 32 of 72 12244-408 EXAMPLE CONFIGURATION 2 (N' = 16, N = 14, CS = 1) 12244-407 1 CONTROL 1 TAIL BIT BIT (CS = 1) 14-BIT CONVERTER RESOLUTION (N = 14) Data Sheet AD9234 SMPR = 80 SAMPLES (0x271 = 0x50; 0x272 = 0x00; 0x273 = 0x00) 80 SAMPLE PERIOD PAYLOAD #3 25-BIT FRAME (N) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD PAYLOAD #3 25-BIT FRAME (N + 1) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE Figure 86. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples Rev. B | Page 33 of 72 12244-409 PAYLOAD #3 25-BIT FRAME (N + 2) AD9234 Data Sheet DIGITAL DOWNCONVERTER (DDC) Each DDC block contains a decimate by 2 digital processing block, as shown in Figure 87. The AD9234 includes two digital downconverters (DDC 0 and DDC 1) that provide filtering and reduce the output data rate. This digital processing section includes a half-band decimating filter, a gain stage, and a complex to real conversion stage. Each of these processing blocks has control lines that allow it to be independently enabled and disabled to provide the desired processing function. The digital downconverter can be configured to output either real data or complex output data. When DDCs have different decimation ratios, the chip decimation ratio (Register 0x201) must be set to the lowest decimation ratio of all the DDC blocks. In this scenario, samples of higher decimation ratio DDCs are repeated to match the chip decimation ratio sample rate. Whenever the NCO frequency is set or changed, the DDC soft reset must be issued. If the DDC soft reset is not issued, the output may potentially show amplitude variations. The DDCs output a 16-bit stream. To enable this operation, the converter number of bits N is set to a default value of 16, even though the analog core only outputs 12 bits. DDC GENERAL DESCRIPTION The two DDC blocks are used to extract a portion of the full digital spectrum captured by the ADC(s). They are intended for IF sampling or oversampled baseband radios requiring wide bandwidth input signals. DDC 0 REAL/I ADC A SAMPLING AT fS REAL/I I HB1 FIR DCM = 2 REAL/Q Q REAL/I CONVERTER 0 Q CONVERTER 1 I/Q CROSSBAR MUX OUTPUT INTERFACE REAL/I REAL/Q ADC B SAMPLING AT fS I HB1 FIR DCM = 2 REAL/Q Q REAL/I CONVERTER 2 Q CONVERTER 3 Figure 87. DDC Detailed Block Diagram Rev. B | Page 34 of 72 12244-161 DDC 1 Data Sheet AD9234 HALF-BAND FILTER Table 10. Half-Band Filter Coefficients The AD9234 offers one half-band filter per DDC to enable digital signal processing of the ADC converted data. HB1 Coefficient Number C1, C55 C2, C54 C3, C53 C4, C52 C5, C51 C6, C50 C7, C49 C8, C48 C9, C47 C10, C46 C11, C45 C12, C44 C13, C43 C14, C42 C15, C41 C16, C40 C17, C39 C18, C38 C19, C37 C20, C36 C21, C35 C22, C34 C23, C33 C24, C32 C25, C31 C26, C30 C27, C29 C28 The decimate by 2, half-band (HB), low-pass FIR filter uses a 55-tap, symmetrical, fixed coefficient filter implementation, optimized for low power consumption. The HB filter is enabled when the DDC is selected. Table 10 and Figure 88 show the coefficients and response of the HB1 filter. 0 –40 –60 –80 –100 –120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 NORMALIZED FREQUENCY (× π RAD/SAMPLE) Figure 88. HB1 Filter Response 12244-048 MAGNITUDE (dB) –20 Rev. B | Page 35 of 72 Normalized Coefficient −0.000023 0 0.000097 0 −0.000288 0 0.000696 0 −0.0014725 0 0.002827 0 −0.005039 0 0.008491 0 −0.013717 0 0.021591 0 −0.033833 0 0.054806 0 −0.100557 0 0.316421 0.500000 Decimal Coefficient (21-Bit) −24 0 102 0 −302 0 730 0 −1544 0 2964 0 −5284 0 8903 0 −14,383 0 22640 0 −35476 0 57468 0 −105442 0 331,792 524,288 AD9234 Data Sheet DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION Each DDC contains an independently controlled gain stage. The gain is selectable as either 0 dB or 6 dB. When mixing a real input signal down to baseband, it is recommended that the user enable the 6 dB of gain to recenter the dynamic range of the signal within the full scale of the output bits. Each DDC contains an independently controlled complex to real conversion block. The complex to real conversion block reuses the last filter (HB1 FIR) in the filtering stage, along with an fS/4 complex mixer, to upconvert the signal. After upconverting the signal, the Q portion of the complex mixer is no longer needed and is dropped. When mixing a complex input signal down to baseband, the mixer has already recentered the dynamic range of the signal within the full scale of the output bits and no additional gain is necessary. However, the optional 6 dB gain can be used to compensate for low signal strengths. The downsample by 2 portion of the HB1 FIR filter is bypassed when using the complex to real conversion stage (see Figure 89). Figure 89 shows a simplified block diagram of the complex to real conversion. GAIN STAGE HB1 FIR COMPLEX TO REAL ENABLE LOW-PASS FILTER I 2 0dB OR 6dB I 0 I/REAL 1 COMPLEX TO REAL CONVERSION 0dB OR 6dB I cos(wt) + REAL 90° fS/4 0° – sin(wt) LOW-PASS FILTER 2 Q 0dB OR 6dB Q Q 12244-049 Q 0dB OR 6dB HB1 FIR Figure 89. Complex to Real Conversion Block Rev. B | Page 36 of 72 Data Sheet AD9234 DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE • The AD9234 digital outputs are designed to the JEDEC standard JESD204B, serial interface for data converters. JESD204B is a protocol to link the AD9234 to a digital processing device over a serial interface with lane rates of up to 10 Gbps. The benefits of the JESD204B interface over LVDS include a reduction in required board area for data interface routing, and an ability to enable smaller packages for converter and logic devices. • • • JESD204B OVERVIEW The JESD204B data transmit block assembles the parallel data from the ADC into frames and uses 8B/10B encoding as well as optional scrambling to form serial output data. Lane synchronization is supported through the use of special control characters during the initial establishment of the link. Additional control characters are embedded in the data stream to maintain synchronization thereafter. A JESD204B receiver is required to complete the serial link. For additional details on the JESD204B interface, users are encouraged to refer to the JESD204B standard. The AD9234 JESD204B data transmit block maps up to two physical ADCs or up to eight virtual converters (when DDCs are enabled) over a link. A link can be configured to use one, two, or four JESD204B lanes. The JESD204B specification refers to a number of parameters to define the link, and these parameters must match between the JESD204B transmitter (the AD9234 output) and the JESD204B receiver (the logic device input). The JESD204B link is described according to the following parameters: • • • • • • L = number of lanes/converter device (lanes/link) (AD9234 value = 1, 2, or 4) M = number of converters/converter device (virtual converters/link) (AD9234 value = 1, 2, 4, or 8) F = octets/frame (AD9234 value = 1, 2, 4, 8, or 16) N΄ = number of bits per sample (JESD204B word size) (AD9234 value = 8 or 16) N = converter resolution (AD9234 value = 7 to 16) CS = number of control bits/sample (AD9234 value = 0, 1, 2, or 3) K = number of frames per multiframe (AD9234 value = 4, 8, 12, 16, 20, 24, 28, or 32 ) S = samples transmitted/single converter/frame cycle (AD9234 value = set automatically based on L, M, F, and N΄) HD = high density mode (AD9234 = set automatically based on L, M, F, and N΄) CF = number of control words/frame clock cycle/converter device (AD9234 value = 0) Figure 90 shows a simplified block diagram of the AD9234 JESD204B link. By default, the AD9234 is configured to use two converters and four lanes. Converter A data is output to SERDOUT0± and/or SERDOUT1±, and Converter B is output to SERDOUT2± and/or SERDOUT3±. The AD9234 allows other configurations such as combining the outputs of both converters onto a single lane, or changing the mapping of the A and B digital output paths. These modes are set up via a quick configuration register in the SPI register map, along with additional customizable options. By default in the AD9234, the 12-bit converter word from each converter is broken into two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits can be configured as zeros or a pseudorandom number (PN) sequence. The tail bits can also be replaced with control bits indicating overrange, SYSREF±, signal monitor, or fast detect output. The two resulting octets can be scrambled. Scrambling is optional; however, it is recommended to avoid spectral peaks when transmitting similar digital data patterns. The scrambler uses a self-synchronizing, polynomial-based algorithm defined by the equation 1 + x14 + x15. The descrambler in the receiver is a self-synchronizing version of the scrambler polynomial. The two octets are then encoded with an 8B/10B encoder. The 8B/10B encoder works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. Figure 91 shows how the 12-bit data is taken from the ADC, the tail bits are added, the two octets are scrambled, and how the octets are encoded into two 10-bit symbols. Figure 91 illustrates the default data format. Rev. B | Page 37 of 72 AD9234 Data Sheet CONVERTER 0 CONVERTER A INPUT ADC A MUX/ FORMAT (SPI REG 0x561, REG 0x564) CONVERTER B INPUT JESD204B LINK CONTROL (L.M.F) (SPI REG 0x570) LANE MUX AND MAPPING (SPI REG 0x5B0, REG 0x5B2, REG 0x5B3, REG 0x5B5, REG 0x5B6) ADC B SERDOUT0–, SERDOUT0+ SERDOUT1–, SERDOUT1+ SERDOUT2–, SERDOUT2+ SERDOUT3–, SERDOUT3+ 12244-050 CONVERTER 1 SYSREF± SYNCINB± Figure 90. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x00) JESD204B INTERFACE TEST PATTERN (REG 0x573, REG 0x551 TO REG 0x558) JESD204B LONG TRANSPORT TEST PATTERN REG 0x571[5] SERIALIZER MSB A13 A12 A11 A10 A9 A8 A6 LSB A7 A5 A4 A3 A2 A1 A0 C2 T MSB S7 S6 S5 S4 S3 S2 S1 LSB S0 S7 S6 S5 S4 S3 S2 S1 S0 8-BIT/10-BIT ENCODER a b a b c d e f g h i j SERDOUT0± SERDOUT1± i j a b SYMBOL0 i j SYMBOL1 a b c d e f g h i j 12244-151 TAIL BITS 0x571[6] SCRAMBLER 1 + x14 + x15 (OPTIONAL) OCTET 1 JESD204B SAMPLE CONSTRUCTION MSB A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 LSB A0 OCTET 1 OCTET 0 FRAME CONSTRUCTION OCTET 0 ADC TEST PATTERNS (RE0x550, REG 0x551 TO REG 0x558) ADC JESD204B DATA LINK LAYER TEST PATTERNS REG 0x574[2:0] C2 CONTROL BITS C1 C0 Figure 91. ADC Output Datapath Showing Data Framing TRANSPORT LAYER SAMPLE CONSTRUCTION FRAME CONSTRUCTION SCRAMBLER ALIGNMENT CHARACTER GENERATION 8-BIT/10-BIT ENCODER PHYSICAL LAYER CROSSBAR MUX SERIALIZER Tx OUTPUT 12244-052 PROCESSED SAMPLES FROM ADC DATA LINK LAYER SYSREF± SYNCINB± Figure 92. Data Flow FUNCTIONAL OVERVIEW Data Link Layer The block diagram in Figure 92 shows the flow of data through the JESD204B hardware from the sample input to the physical output. The processing can be divided into layers that are derived from the open-source initiative (OSI) model widely used to describe the abstraction layers of communications systems. These layers are the transport layer, data link layer, and physical layer (serializer and output driver). The data link layer is responsible for the low level functions of passing data across the link. These include optionally scrambling the data, inserting control characters for multichip synchronization/lane alignment/monitoring, and encoding 8-bit octets into 10-bit symbols. The data link layer is also responsible for sending the initial lane alignment sequence (ILAS), which contains the link configuration data used by the receiver to verify the settings in the transport layer. Transport Layer The transport layer handles packing the data (consisting of samples and optional control bits) into JESD204B frames that are mapped to 8-bit octets. These octets are sent to the data link layer. The transport layer mapping is controlled by rules derived from the link parameters. Tail bits are added to fill gaps where required. The following equation can be used to determine the Physical Layer The physical layer consists of the high speed circuitry clocked at the serial clock rate. In this layer, parallel data is converted into one, two, or four lanes of high speed differential serial data. number of tail bits within a sample (JESD204B word): T = N΄ – N – CS Rev. B | Page 38 of 72 Data Sheet AD9234 JESD204B LINK ESTABLISHMENT Initial Lane Alignment Sequence (ILAS) The AD9234 JESD204B transmitter (Tx) interface operates in Subclass 1 as defined in the JEDEC Standard JESD204B (July 2011 specification). The link establishment process is divided into the following steps: code group synchronization and SYNCINB±, initial lane alignment sequence, and user data and error correction. The ILAS phase follows the CGS phase and begins on the next LMFC boundary. The ILAS consists of four multiframes, with an /R/ character marking the beginning and an /A/ character marking the end. The ILAS begins by sending an /R/ character followed by 0 to 255 ramp data for one multiframe. On the second multiframe, the link configuration data is sent, starting with the third character. The second character is a /Q/ character to confirm that the link configuration data follows. All undefined data slots are filled with ramp data. The ILAS sequence is never scrambled. Code Group Synchronization (CGS) and SYNCINB± The CGS is the process by which the JESD204B receiver finds the boundaries between the 10-bit symbols in the stream of data. During the CGS phase, the JESD204B transmit block transmits /K28.5/ characters. The receiver must locate /K28.5/ characters in its input data stream using clock and data recovery (CDR) techniques. The receiver issues a synchronization request by asserting the SYNCINB± pin of the AD9234 low. The JESD204B Tx then begins sending /K/ characters. After the receiver has synchronized, it waits for the correct reception of at least four consecutive /K/ symbols. It then deasserts SYNCINB±. The AD9234 then transmits an ILAS on the following local multiframe clock (LMFC) boundary. The ILAS sequence construction is shown in Figure 93. The four multiframes include the following: • • • For more information on the code group synchronization phase, refer to the JEDEC Standard JESD204B, July 2011, Section 5.3.3.1. • Multiframe 1. Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 2. Begins with an /R/ character followed by a /Q/ (/K28.4/) character, followed by link configuration parameters over 14 configuration octets (see Table 11) and ends with an /A/ character. Many of the parameter values are of the value – 1 notation. Multiframe 3. Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 4. Begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). The SYNCINB± pin operation can also be controlled by the SPI. The SYNCINB± signal is a differential dc-coupled LVDS mode signal by default, but it can also be driven single-ended. For more information on configuring the SYNCINB± pin operation, refer to Register 0x572. K K R D D A R Q C C D D A R D D A R D D A D START OF ILAS START OF USER DATA START OF LINK CONFIGURATION DATA Figure 93. Initial Lane Alignment Sequence Rev. B | Page 39 of 72 12244-053 END OF MULTIFRAME AD9234 Data Sheet User Data and Error Detection 8B/10B Encoder After the initial lane alignment sequence is complete, the user data is sent. Normally, within a frame, all characters are considered user data. However, to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /F/ or /A/ alignment characters when the data meets certain conditions. These conditions are different for unscrambled and scrambled data. The scrambling operation is enabled by default, but it can be disabled using the SPI. The 8B/10B encoder converts 8-bit octets into 10-bit symbols and inserts control characters into the stream when needed. The control characters used in JESD204B are shown in Table 11. The 8B/10B encoding ensures that the signal is dc balanced by using the same number of ones and zeros across multiple symbols. For scrambled data, any 0xFC character at the end of a frame is replaced by an /F/, and any 0x7C character at the end of a multiframe is replaced with an /A/. The JESD204B receiver (Rx) checks for /F/ and /A/ characters in the received data stream and verifies that they only occur in the expected locations. If an unexpected /F/ or /A/ character is found, the receiver handles the situation by using dynamic realignment or asserting the SYNCINB± signal for more than four frames to initiate a resynchronization. For unscrambled data, if the final character of two subsequent frames is equal, the second character is replaced with an /F/ if it is at the end of a frame, and an /A/ if it is at the end of a multiframe. The 8B/10B interface has options that can be controlled via the SPI. These operations include bypass and invert. These options are intended to be troubleshooting tools for the verification of the digital front end (DFE). Refer to the Memory Map section, Register 0x572[2:1] for information on configuring the 8B/10B encoder. Insertion of alignment characters can be modified using SPI. The frame alignment character insertion (FACI) is enabled by default. More information on the link controls is available in the Memory Map section, Register 0x571. Table 11. AD9234 Control Characters Used in JESD204B Abbreviation /R/ /A/ /Q/ /K/ /F/ 1 Control Symbol /K28.0/ /K28.3/ /K28.4/ /K28.5/ /K28.7/ 8-Bit Value 000 11100 011 11100 100 11100 101 11100 111 11100 10-Bit Value, RD 1 = −1 001111 0100 001111 0011 001111 0010 001111 1010 001111 1000 RD means running disparity. Rev. B | Page 40 of 72 10-Bit Value, RD1 = +1 110000 1011 110000 1100 110000 1101 110000 0101 110000 0111 Description Start of multiframe Lane alignment Start of link configuration data Group synchronization Frame alignment Data Sheet AD9234 PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls The AD9234 physical layer consists of drivers that are defined in the JEDEC Standard JESD204B, July 2011. The differential digital outputs are powered up by default. The drivers use a dynamic 100 Ω internal termination to reduce unwanted reflections. Place a 100 Ω differential termination resistor at each receiver, which results in a nominal 300 mV p-p swing at the receiver (see Figure 94). It is recommended to use ac coupling to connect the AD9234 SERDES outputs to the receiver. DRVDD 100Ω DIFFERENTIAL 0.1µF TRACE PAIR SERDOUTx+ 100Ω RECEIVER SERDOUTx– 12244-054 0.1µF OUTPUT SWING = 300mV p-p Figure 95 to Figure 100 show examples of the digital output data eye, time interval error (TIE) jitter histogram, and bathtub curve for one AD9234 lane running at 10 Gbps and 6 Gbps, respectively. The format of the output data is twos complement by default. To change the output data format, see the Memory Map section (Register 0x561 in Table 25). De-Emphasis De-emphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the JESD204B specification. Use the de-emphasis feature only when the receiver is unable to recover the clock due to excessive insertion loss. Under normal conditions, it is disabled to conserve power. Additionally, enabling and setting too high a de-emphasis value on a short link may cause the receiver eye diagram to fail. Use the de-emphasis setting with caution because it may increase electromagnetic interference (EMI). See the Memory Map section (Register 0x5C1 to Register 0x5C5 in Table 25) for more details. Phase-Locked Loop Figure 94. AC-Coupled Digital Output Termination Example If there is no far-end receiver termination, or if there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. The PLL is used to generate the serializer clock, which will operate at the JESD204B lane rate. The JESD204B lane rate Register 0x056E[4:3] must be set to correspond with the lane rate. 400 400 300 300 200 Tx EYE MASK –100 100 0 –100 –200 –200 –300 –300 –400 –80 –60 –40 –20 0 TIME (ps) 20 40 60 80 12244-500 –400 –100 Tx EYE MASK –150 –100 –50 0 TIME (ps) Figure 95. Digital Outputs Data Eye, External 100 Ω Terminations at 10 Gbps 50 100 150 12244-503 0 VOLTAGE (mV) VOLTAGE (mV) 200 100 Figure 96. Digital Outputs Data Eye, External 100 Ω Terminations at 6 Gbps Rev. B | Page 41 of 72 AD9234 Data Sheet 8000 12000 10000 6000 8000 4000 HITS HITS 7000 6000 4000 3000 4000 2000 –2 0 2 4 6 TIME (ps) 1–2 1–2 1–4 1–4 1–6 1–6 BER 1 1–10 1–12 1–12 1–14 1–14 1–16 –0.5 1–16 –0.5 –0.3 –0.2 –0.1 0 UI 0.1 0.2 0.3 0.4 0.5 Figure 98. Digital Outputs Bathtub Curve, External 100 Ω Terminations at 10 Gbps 1 0 2 3 4 1–8 1–10 –0.4 –1 Figure 99. Digital Outputs Histogram, External 100 Ω Terminations at 6 Gbps 1 1–8 –2 TIME (ps) 12244-502 BER Figure 97. Digital Outputs Histogram, External 100 Ω Terminations at 10 Gbps –3 –0.4 –0.3 –0.2 –0.1 0 UI 0.1 0.2 0.3 0.4 0.5 12244-505 –4 0 –4 12244-501 0 12244-504 1000 2000 Figure 100. Digital Outputs Bathtub Curve, External 100 Ω Terminations at 6 Gbps Rev. B | Page 42 of 72 Data Sheet AD9234 CONFIGURING THE JESD204B LINK The AD9234 has one JESD204B link. The device offers an easy way to set up the JESD204B link through the quick configuration register (Register 0x570). The serial outputs (SERDOUT0± to SERDOUT3±) are considered part of one JESD204B link. The basic parameters that determine the link setup are 1. 2. 3. 4. 5. 6. • • • If the lane line rate calculated is less than 6.25 Gbps, select the low line rate option. This is done by programming a value of 0x10 to Register 0x56E. Number of lanes per link (L) Number of converters per link (M) Number of octets per frame (F) The maximum lane rate allowed by the JESD204B specification is 12.5 Gbps. The lane line rate is related to the JESD204B parameters using the following equation: 10 M × N '×   × fOUT  8  Lane Line Rate = L Power down the link. Select quick configuration options. Configure detailed options. Set output lane mapping (optional). Set additional driver configuration options (optional). Power up the link. Table 12 and Table 13 show the JESD204B output configurations supported for both N΄ = 16 and N΄ = 8 for a given number of virtual converters. Care must be taken to ensure that the serial line rate for a given configuration is within the supported range of 3.125 Gbps to 12.5 Gbps. where fOUT = fADC_CLOCK/decimation ratio. The following steps can be used to configure the output: Table 12. JESD204B Output Configurations for N΄ = 16 No. of Virtual Converters Supported (Same Value as M) 1 2 4 JESD204B Quick Configuration (0x570) 0x01 0x40 0x41 0x80 0x81 0x0A 0x49 0x88 0x89 0x13 0x52 0x91 JESD204B Transport Layer Settings 2 JESD204B Serial Line Rate 1 20 × fOUT 10 × fOUT 10 × fOUT 5 × fOUT 5 × fOUT 40 × fOUT 20 × fOUT 10 × fOUT 10 × fOUT 80 × fOUT 40 × fOUT 20 × fOUT L 1 2 2 4 4 1 2 4 4 1 2 4 M 1 1 1 1 1 2 2 2 2 4 4 4 F 2 1 2 1 2 4 2 1 2 8 4 2 S 1 1 2 2 4 1 1 1 2 1 1 1 HD 0 1 0 1 0 0 0 1 0 0 0 0 N 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 8 to 16 N΄ 16 16 16 16 16 16 16 16 16 16 16 16 CS 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 0 to 3 K3 Only valid K values that are divisible by 4 are supported fOUT = output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be ≥3.125 Gbps and ≤12.5 Gbps; when the serial line rate is ≤12.5 Gbps and ≥6.25 Gbps, the low line rate mode must be disabled (set Bit 4 to 0x0 in 0x56E). When the serial line rate is 1? (0x10B) YES NO SYSREF± ENABLED IN CONTROL BITS? (0x559, 0x55A, 0x58F) YES SYSREF± INSERTED IN JESD204B CONTROL BITS NO RAMP TEST MODE ENABLED? (0x550) NORMAL MODE YES SYSREF± RESETS RAMP TEST MODE GENERATOR BACK TO START NO YES ALIGN PHASE OF ALL INTERNAL CLOCKS (INCLUDING LMFC) TO SYSREF± SEND INVALID 8-BIT/10-BIT CHARACTERS (ALL 0s) SYNC~ ASSERTED NO SEND K28.5 CHARACTERS NORMAL JESD204B INITIALIZATION NO NO SIGNAL MONITOR ALIGNMENT ENABLED? (0x26F) YES YES ALIGN SIGNAL MONITOR COUNTERS DDC NCO ALIGNMENT ENABLED? (0x300) YES ALIGN DDC NCO PHASE ACCUMULATOR NO Figure 107. SYSREF± Capture Scenarios and Multichip Synchronization Rev. B | Page 49 of 72 BACK TO START 12244-112 JESD204B LMFC ALIGNMENT REQUIRED? AD9234 Data Sheet SETUP REQUIREMENT 117ps CLK± SYSREF± SYSREF± Control Features SYSREF± and the input clock (CLK±) are part of a source synchronous timing interface that requires setup and hold timing requirements of 117 ps and −96 ps, relative to the input clock (see Figure 108). The AD9234 has several features to meet these requirements. First, the SYSREF± sample event can be defined as either a synchronous low to high transition or synchronous high to low transition. Second, the AD9234 allows the SYSREF± signal to be sampled using either the rising edge or falling edge of the input clock. Figure 108, Figure 109, Figure 110, and Figure 111 show all four possible combinations. 12244-706 KEEP OUT WINDOW SETUP REQUIREMENT 117ps HOLD REQUIREMENT –96ps CLK± 12244-707 The input clock divider, DDCs, signal monitor block, and JESD204B link are all synchronized using the SYSREF± input when in normal synchronization mode (Register 0x1FF, Bits[1:0] = 0). The SYSREF± input can also time stamp an ADC sample to provide a mechanism for synchronizing multiple AD9234 devices in a system. For the highest level of timing accuracy, SYSREF± must meet the setup and hold requirements relative to the CLK± input. There are several features in the AD9234 to ensure these requirements are met (see the SYSREF± Control Features section). SYSREF± SAMPLE POINT Figure 108. SYSREF± Setup and Hold Time Requirements; SYSREF± Low to High Transition Using the Rising Edge Clock (Default) LMFC = ADC Clock/S × K where: S is the JESD204B parameter for number of samples per converter. K is JESD204B parameter for number of frames per multiframe. HOLD REQUIREMENT –96ps SYSREF± SAMPLE POINT SYSREF± Figure 109. SYSREF± Low to High Transition Using Falling Edge Clock Capture (Register 0x120, Bit 4 = 0 and Register 0x120, Bit 3 = 1) SETUP REQUIREMENT 117ps HOLD REQUIREMENT –96ps CLK± SYSREF± SAMPLE POINT 12244-708 The SYSREF± input signal is used as a high accuracy system reference for deterministic latency and multichip synchronization. The AD9234 accepts a single shot or periodic input signal. The SYSREF± mode select bits (Register 0x120, Bits[2:1]) select the input signal type and also arm the SYSREF± state machine when set. If in single (or N) shot mode (Register 0x120, Bits[2:1] = 2), the SYSREF± mode select bit self clears after detecting the appropriate SYSREF± transition. The pulse width must have a minimum width of two CLK± periods. If the clock divider (Register 0x10B, Bits[2:0]) is set to a value other than divide by 1, then multiply this minimum pulse width requirement by the divide ratio (for example, if set to divide by 8, the minimum pulse width is 16 CLK± cycles). When using a continuous SYSREF± signal (Register 0x120, Bits[2:1] = 1), the period of the SYSREF± signal must be an integer multiple of the LMFC. Derive the LMFC using the following formula: register (Register 0x120, Bits[2:1]) to 10, which is labeled as N shot mode. The AD9234 can ignore N SYSREF± events, which can handle periodic SYSREF± signals that require time to settle after startup. Ignoring SYSREF± until the clocks in the system settle avoids an inaccurate SYSREF± trigger. Figure 112 shows an example of the SYSREF± ignore feature when ignoring three SYSREF± events. SYSREF± Figure 110. SYSREF± High to Low Transition Using Rising Edge Clock Capture (Register 0x120, Bit 4 = 1 and Register 0x120, Bit 3 = 0) SETUP REQUIREMENT 117ps HOLD REQUIREMENT –96ps CLK± SYSREF± SAMPLE POINT SYSREF± Figure 111. SYSREF± High to Low Transition Using Falling Edge Clock Capture (Register 0x120, Bit 4 = 1 and Register 0x120, Bit 3 = 1) The third SYSREF± related feature available is the ability to ignore a programmable number (up to 16) of SYSREF± events. The SYSREF± ignore feature is enabled by setting the SYSREF± mode Rev. B | Page 50 of 72 12244-709 SYSREF± INPUT Data Sheet AD9234 SYSREF± SAMPLE PART 1 SYSREF± SAMPLE PART 2 SYSREF± SAMPLE PART 3 SYSREF± SAMPLE PART 4 SYSREF± SAMPLE PART 5 CLK± 12244-079 SYSREF± SAMPLE THE FOURTH SYSREF± IGNORE FIRST THREE SYSREF±s Figure 112. SYSREF± Ignore Example; SYSREF± Ignore Count Bits (Register 0x121, Bits[3:0]) = 3 SYSREF± SKEW SYSREF± SKEW SYSREF± SKEW SYSREF± SKEW WINDOW WINDOW WINDOW WINDOW = ±3 = ±2 = ±1 =0 12244-080 CLK± SYSREF± Figure 113. SYSREF± Skew Window When in continuous SYSREF± mode (Register 0x120, Bits[2:1] = 1), the AD9234 monitors the placement of the SYSREF± leading edge compared to the internal LMFC. If the SYSREF± edge is captured with a clock edge other than the one that is aligned with LMFC, the AD9234 initiates a resynchronization of the link. Because the input clock rates for the AD9234 can range up to 4 GHz, the AD9234 provides another SYSREF± related feature that makes it possible to accommodate periodic SYSREF± signals where cycle accurate capture is not feasible or is not required. For these scenarios, the AD9234 has a programmable SYSREF± skew window that allows the internal dividers to remain undisturbed, unless SYSREF± occurs outside the skew window. The resolution of the SYSREF± skew window is set in sample clock cycles. If the SYSREF± negative skew window is 1 and the positive skew window is 1, the total skew window is ±1 sample clock cycles, meaning that, as long as SYSREF± is captured within ±1 sample clock cycle of the clock that is aligned with the LMFC, the link continues to operate normally. If the SYSREF± has jitter, which can cause a misalignment between SYSREF± and the LMFC, the system continues to run without a resynchronization, while still allowing the device to monitor for larger errors not caused by jitter. For the AD9234, the positive and negative skew window is controlled by the SYSREF± window negative bits (Register 0x122, Bits[3:2]) and the SYSREF± window positive bits (Register 0x0122, Bits[1:0]). Figure 113 shows the location of the skew window settings relative to Phase 0 of the internal dividers. Negative skew is defined as occurring before the internal dividers reach Phase 0 and positive skew is defined after the internal dividers reach Phase 0. Rev. B | Page 51 of 72 AD9234 Data Sheet SYSREF± SETUP/HOLD WINDOW MONITOR To ensure a valid SYSREF± signal capture, the AD9234 has a SYSREF± setup and hold window monitor. This feature allows the system designer to determine the location of the SYSREF± signals relative to the CLK± signals by reading back the amount of setup and hold margin on the interface through the memory map. Figure 114 and Figure 115 show the setup and hold status values for different phases of SYSREF±. The setup detector returns the status of the SYSREF± signal before the CLK± edge, and the hold detector returns the status of the SYSREF signal after the CLK± edge. Register 0x128 stores the status of SYSREF± and lets the user know if the SYSREF± signal is captured by the ADC. Table 14 describes the contents of Register 0x128 and how to interpret them. 0xF 0xE 0xD 0xC 0xB 0xA 0x9 REG 0x128[3:0] 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 CLK± INPUT VALID SYSREF± INPUT FLIP-FLOP HOLD (MIN) FLIP-FLOP HOLD (MIN) Figure 114. SYSREF± Setup Detector Rev. B | Page 52 of 72 12244-113 FLIP-FLOP SETUP (MIN) Data Sheet AD9234 REG 0x128[7:4] 0xF 0xE 0xD 0xC 0xB 0xA 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 CLK± INPUT SYSREF± INPUT FLIP-FLOP SETUP (MIN) FLIP-FLOP HOLD (MIN) FLIP-FLOP HOLD (MIN) 12244-114 VALID Figure 115. SYSREF± Hold Detector Table 14. SYSREF± Setup/Hold Monitor, Register 0x128 Register 0x128,Bits[7:4], Hold Status 0x0 0x0 to 0x8 0x8 0x8 0x9 to 0xF 0x0 Register 0x128, Bits[3:0], Setup Status 0x0 to 0x7 0x8 0x9 to 0xF 0x0 0x0 0x0 Description Possible setup error. The smaller this number, the smaller the setup margin. No setup or hold error (best hold margin). No setup or hold error (best setup and hold margin). No setup or hold error (best setup margin). Possible hold error. The larger this number, the smaller the hold margin. Possible setup or hold error. Rev. B | Page 53 of 72 AD9234 Data Sheet LATENCY END TO END TOTAL LATENCY Table 15. Latency Through the ADC and DSP Blocks Total latency in the AD9234 is dependent on the various digital signal processing (DSP) and JESD204B configuration modes. Latency is fixed at 26 encode clocks through the ADC itself; however, the latency through the DSP and JESD204B blocks can vary greatly depending on the configuration. Therefore, total latency must be calculated based on the DSP options selected and the JESD204B configuration. Latency (Number of Encode Clocks), ADC + DSP Total 29 78 ADC Application Mode Full Bandwidth DDC (HB1), no mixer, complex outputs EXAMPLE LATENCY CALCULATION For a configuration where the ADC application mode is full bandwidth, the decimation ratio = 2, L = 4, M = 2, F = 1, and S = 1 (JESD204B mode): Table 15 shows the combined latency through the ADC and DSP blocks (including data formatting) for the different application modes supported by the AD9234. Table 16 shows the latency through the JESD204B block for each JESD204B configuration and the various decimation modes supported for those modes. For Table 15 and Table 16, latency is in units of the number of encode clocks. Latency through the JESD204B clock can also be affected by the decimation ratio in some JESD204B configurations. Table 17 shows the latency for these modes for each of the possible decimation ratios. Latency = 29 + 30 = 59 Encode Clocks Table 16. Latency Through JESD204B Block—Full Bandwidth Modes JESD204B Quick Configuration (Register 0x570) 0x01 0x40 0x41 0x80 0x81 0x0A 0x49 0x88 0x89 Decimation Ratio 1 1 1 1 1 1 1 1 1 L 1 2 2 4 4 1 2 4 4 JESD204B Transport Layer Settings M F S HD N N΄ 1 2 1 0 8 to 16 16 1 1 1 1 8 to 16 16 1 2 2 0 8 to 16 16 1 1 2 1 8 to 16 16 1 2 4 0 8 to 16 16 2 4 1 0 8 to 16 16 2 2 1 0 8 to 16 16 2 1 1 1 8 to 16 16 2 2 2 0 8 to 16 16 Latency (Encode Clock) 13 28 28 53 53 7 13 28 28 JESD204B Transport Layer Settings M F S HD N 2 1 1 1 8 to 16 2 2 2 0 8 to 16 4 8 1 0 8 to 16 4 4 1 0 8 to 16 4 2 1 0 8 to 16 8 16 1 0 8 to 16 8 8 1 0 8 to 16 8 4 1 0 8 to 16 Latency (Encode CLK) 30 30 4 7 13 2 4 7 Table 17. Latency Through JESD204B Block with Decimation JESD204B Quick Configuration (Register 0x570) 0x88 0x89 0x13 1 0x521 0x911 0x1C1 0x5B1 0x9A1 1 Decimation Ratio 2 2 2, 4, 8, 16 2, 4, 8, 16 2, 4, 8, 16 4, 8, 16 4, 8, 16 4, 8, 16 L 4 4 1 2 4 1 2 4 For these modes, changing decimation does not affect latency. Rev. B | Page 54 of 72 N΄ 16 16 16 16 16 16 16 16 Data Sheet AD9234 TEST MODES These tests can be performed with or without an analog signal (if present, the analog signal is ignored); however, they do require an encode clock. ADC TEST MODES The AD9234 has various test options that aid in system level implementation. The AD9234 has ADC test modes that are available in Register 0x550. These test modes are described in Table 18. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks, and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x550. JESD204B INTERFACE TEST PATTERN (REG 0x573, REG 0x551 TO REG 0x558) JESD204B LONG TRANSPORT TEST PATTERN REG 0x571[5] JESD204B DATA LINK LAYER TEST PATTERNS REG 0x574[2:0] SERIALIZER MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 A5 A4 A3 A2 A1 A0 C2 T MSB S7 S6 S5 S4 S3 S2 S1 LSB S0 S7 S6 S5 S4 S3 S2 S1 S0 8-BIT/10-BIT ENCODER a b c d e f g h i j a b SERDOUT0± SERDOUT1± i j a b SYMBOL0 i j SYMBOL1 a b c d e f g h i j 12244-051 TAIL BITS 0x571[6] SCRAMBLER 1 + x14 + x15 (OPTIONAL) OCTET 1 JESD204B SAMPLE CONSTRUCTION MSB A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 LSB A0 OCTET 1 OCTET 0 FRAME CONSTRUCTION OCTET 0 ADC TEST PATTERNS (REG 0x550, REG 0x551 TO REG 0x558) ADC If the application mode is set to select a DDC mode of operation, the test modes must be enabled for each DDC enabled. The test patterns can be enabled via Bit 2 and Bit 0 of Register 0x327 and Register 0x347 depending on which DDCs are selected. The I data uses the test patterns selected for Channel A, and the Q data uses the test patterns selected for Channel B. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. C2 CONTROL BITS C1 C0 Figure 116. ADC Output Datapath Showing Data Framing Table 18. ADC Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 Pattern Name Off (default) Midscale short Positive full-scale short Negative full-scale short Checkerboard PN sequence long PN sequence short One-/zero-word toggle User input Expression Not applicable 0000 0000 0000 01 1111 1111 1111 10 0000 0000 0000 10 1010 1010 1010 x23 + x18 + 1 x9 + x5 + 1 11 1111 1111 1111 Register 0x551 to Register 0x558 1111 Ramp Output (x) % 214 Default/ Seed Value Not applicable Not applicable Not applicable Not applicable Not applicable 0x3AFF 0x0092 Not applicable Not applicable Not applicable Rev. B | Page 55 of 72 Sample (N, N + 1, N + 2, …) Not applicable Not applicable Not applicable Not applicable 0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555 0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6 0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697 0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000 User Pattern 1, Bits[15:2], User Pattern 2, Bits[15:2], User Pattern 3, Bits[15:2], User Pattern 4, Bits[15:2], User Pattern 1, Bits[15:2] … for repeat mode. User Pattern 1, Bits[15:2], User Pattern 2, Bits[15:2], User Pattern 3, Bits[15:2], User Pattern 4, Bits[15:2], 0x0000 … for single mode. (x) % 214, (x +1) % 214, (x +2) % 214, (x +3) % 214 AD9234 Data Sheet JESD204B BLOCK TEST MODES Interface Test Modes In addition to the ADC pipeline test modes, the AD9234 also has flexible test modes in the JESD204B block. These test modes are listed in Register 0x573 and Register 0x574. These test patterns can be injected at various points along the output datapath. These test injection points are shown in Figure 116. Table 19 describes the various test modes available in the JESD204B block. For the AD9234, a transition from test modes (Register 0x573 ≠ 0x00) to normal mode (Register 0x573 = 0x00) requires an SPI soft reset, which is done by writing 0x81 to Register 0x000 (self cleared). The interface test modes are described in Register 0x573, Bits[3:0]. These test modes are also explained in Table 19. The interface tests can be injected at various points along the data. See Figure 91 for more information on the test injection points. Register 0x573, Bits[5:4] show where these tests are injected. Transport Layer Sample Test Mode Data Link Layer Test Modes The transport layer samples are implemented in the AD9234 as defined by Section 5.1.6.3 in the JEDEC JESD204B specification. These tests are shown in Register 0x571, Bit 5. The test pattern is equivalent to the raw samples from the ADC. The data link layer test modes are implemented in the AD9234, defined by Section 5.3.3.8.2 in the JEDEC JESD204B specification. These tests are shown in Register 0x574, Bits[2:0]. Test patterns inserted at this point are useful for verifying the functionality of the data link layer. When the data link layer test modes are enabled, disable SYNCINB± by writing 0xC0 to Register 0x572. Table 20, Table 21, and Table 22 show examples of some of the test modes when injected at the JESD204B sample input, PHY 10-bit input, and scrambler 8-bit input. UPx in the Table 20, Table 21, and Table 22 represent the user pattern control bits from the memory map. Table 19. JESD204B Interface Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1110 1111 Pattern Name Off (default) Alternating checker board 1/0 word toggle 31-bit PN sequence 23-bit PN sequence 15-bit PN sequence 9-bit PN sequence 7-bit PN sequence Ramp output Continuous/repeat user test Single user test Expression Not applicable 0x5555, 0xAAAA, 0x5555, … 0x0000, 0xFFFF, 0x0000, … x31 + x28 + 1 x23 + x18 + 1 x15 + x14 + 1 x9 + x5 + 1 x7 + x6 + 1 (x) % 216 Register 0x551 to Register 0x558 Register 0x551 to Register 0x558 Default Not applicable Not applicable Not applicable 0x0003AFFF 0x003AFF 0x03AF 0x092 0x07 Ramp size depends on test injection point User Pattern 1 to User Pattern 4, then repeat User Pattern 1 to User Pattern 4, then zeros Table 20. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x573, Bits[5:4] = 0) Frame No. 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 Converter No. 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Sample No. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Alternating Checkerboard 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 1/0 Word Toggle 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF Rev. B | Page 56 of 72 Ramp (x) % 216 (x) % 216 (x) % 216 (x) % 216 (x +1) % 216 (x +1) % 216 (x +1) % 216 (x +1) % 216 (x +2) % 216 (x +2) % 216 (x +2) % 216 (x +2) % 216 (x +3) % 216 (x +3) % 216 (x +3) % 216 (x +3) % 216 PN9 0x496F 0x496F 0x496F 0x496F 0xC9A9 0xC9A9 0xC9A9 0xC9A9 0x980C 0x980C 0x980C 0x980C 0x651A 0x651A 0x651A 0x651A PN23 0xFF5C 0xFF5C 0xFF5C 0xFF5C 0x0029 0x0029 0x0029 0x0029 0xB80A 0xB80A 0xB80A 0xB80A 0x3D72 0x3D72 0x3D72 0x3D72 User Repeat UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] User Single UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] Data Sheet Frame No. 4 4 4 4 AD9234 Converter No. 0 0 1 1 Sample No. 0 1 0 1 Alternating Checkerboard 0x5555 0x5555 0x5555 0x5555 1/0 Word Toggle 0x0000 0x0000 0x0000 0x0000 Ramp (x +4) % 216 (x +4) % 216 (x +4) % 216 (x +4) % 216 PN9 0x5FD1 0x5FD1 0x5FD1 0x5FD1 PN23 0x9B26 0x9B26 0x9B26 0x9B26 User Repeat UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] User Single 0x0000 0x0000 0x0000 0x0000 Table 21. Physical Layer 10-Bit Input (Register 0x573, Bits[5:4] = 1) 10-Bit Symbol No. 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 1/0 Word Toggle 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF Ramp (x) % 210 (x + 1) % 210 (x + 2) % 210 (x + 3) % 210 (x + 4) % 210 (x + 5) % 210 (x + 6) % 210 (x + 7) % 210 (x + 8) % 210 (x + 9) % 210 (x + 10) % 210 (x + 11) % 210 PN9 0x125 0x2FC 0x26A 0x198 0x031 0x251 0x297 0x3D1 0x18E 0x2CB 0x0F1 0x3DD Ramp (x) % 28 (x + 1) % 28 (x + 2) % 28 (x + 3) % 28 (x + 4) % 28 (x + 5) % 28 (x + 6) % 28 (x + 7) % 28 (x + 8) % 28 (x + 9) % 28 (x + 10) % 28 (x + 11) % 28 PN9 0x49 0x6F 0xC9 0xA9 0x98 0x0C 0x65 0x1A 0x5F 0xD1 0x63 0xAC PN23 0x3FD 0x1C0 0x00A 0x1B8 0x028 0x3D7 0x0A6 0x326 0x10F 0x3FD 0x31E 0x008 User Repeat UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] User Single UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0x000 Table 22. Scrambler 8-Bit Input (Register 0x573, Bits[5:4] = 0) 8-Bit Octet No. 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 1/0 Word Toggle 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF Rev. B | Page 57 of 72 PN23 0xFF 0x5C 0x00 0x29 0xB8 0x0A 0x3D 0x72 0x9B 0x26 0x43 0xFF User Repeat UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] User Single UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 AD9234 Data Sheet SERIAL PORT INTERFACE The AD9234 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see the Serial Control Interface Standard (Rev. 1.0). write command is issued, allowing the SDIO pin to change direction from an input to an output. CONFIGURATION USING THE SPI Data can be sent in MSB first mode or in LSB first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the Serial Control Interface Standard (Rev. 1.0). Three pins define the SPI of the AD9234 ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 23). The SCLK pin synchronizes the read and write data presented from/to the ADC. The SDIO (serial data input/output) pin is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 23. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial clock. The serial shift clock input that synchronizes serial interface, reads, and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 3 and Table 5. Other modes involving the CSB pin are available. The CSB pin can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB pin can stall high between bytes to allow additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change direction from an input to an output at the appropriate point in the serial frame. HARDWARE INTERFACE The pins described in Table 23 comprise the physical interface between the user programming device and the serial port of the AD9234. The SCLK pin and the CSB pin function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. Do not activate the SPI port during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9234 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SPI ACCESSIBLE FEATURES Table 24 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the Serial Control Interface Standard (Rev. 1.0). The AD9234 device-specific features are described in the Memory Map section. Table 24. Features Accessible Using the SPI Feature Name Mode Clock DDC Test Input/Output Output Mode SERDES Output Setup Description Allows the user to set either power-down mode or standby mode. Allows the user to access the clock divider via the SPI. Allows the user to set up decimation filters for different applications. Allows the user to set test modes to have known data on output bits. Allows the user to set up outputs. Allows the user to vary SERDES settings such as swing and emphasis. Rev. B | Page 58 of 72 Data Sheet AD9234 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Logic Levels Each row in the memory map register table has eight bit locations. The memory map is divided into four sections: the Analog Devices SPI registers (Register 0x000 to Register 0x00D), the ADC function registers (Register 0x015 to Register 0x27A), The DDC function registers (Register 0x300 to Register 0x347), and the digital outputs and test modes registers (Register 0x550 to Register 0x5C5). An explanation of logic level terminology follows: Table 25 (see the Memory Map section) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x561, the output mode register, has a hexadecimal default value of 0x01. This means that Bit 0 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see the Table 25. Open and Reserved Locations All address and bit locations that are not included in Table 25 are not currently supported for this device. Write unused bits of a valid address location with 0s unless the default value is set otherwise. Writing to these locations is required only when part of an address location is unassigned (for example, Address 0x561). If the entire address location is open (for example, Address 0x013), do not write to this address location. Default Values After the AD9234 is reset, critical registers are loaded with default values. The default values for the registers are given in Table 25. • • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” X denotes a don’t care bit. Channel-Specific Registers Some channel setup functions, such as the input termination (Register 0x016), can be programmed to a different value for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 25 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x008. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A or Channel B to read one of the two registers. If both bits are set during an SPI read cycle, the device returns the value for Channel A. Registers and bits designated as global in Table 25 affect the entire device and the channel features for which independent settings are not allowed between channels. The settings in Register 0x005 do not affect the global registers and bits. SPI Soft Reset After issuing a soft reset by programming 0x81 to Register 0x000, the AD9234 requires 5 ms to recover. When programming the AD9234 for application setup, ensure that an adequate delay is programmed into the firmware after asserting the soft reset and before starting the device setup. Rev. B | Page 59 of 72 AD9234 Data Sheet MEMORY MAP REGISTER TABLE All address locations that are not included in Table 25 are not currently supported for this device and must not be written. Table 25. Memory Map Registers Reg Addr Register Bit 7 (Hex) Name (MSB) Bit 6 Analog Devices SPI Registers Soft reset LSB first 0x000 INTERFACE_ 0 = MSB CONFIG_A (self 1 = LSB clearing) Single 0x001 INTERFACE_ 0 CONFIG_B instruction Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Address ascension 0 0 0 0 0 0 Soft reset LSB first (self 0 = MSB clearing) 1 = LSB Datapath 0 0 soft reset (self clearing) 00 = normal operation 0 10 = standby 11 = power-down 011 = high speed ADC Address ascension Default 0x00 0x00 0x002 DEVICE_ CONFIG (local) 0 0 0 0 0x003 CHIP_TYPE 0 0 0 0 0x004 CHIP_ID (low byte) CHIP_ID (high byte) CHIP_GRADE 1 1 0 0 1 1 1 0 0xCE 0 0 0 0 0 0 0 0 0x00 X X X X 0x005 0x006 0x008 0x00A 0x00B 0x00C Device index Scratch pad SPI revision Vendor ID (low byte) 0x00D Vendor ID (high byte) ADC Function Registers 0x015 Analog Input (local) 0x016 Input termination (local) 0x018 Input buffer current control (local) 0x024 V_1P0 control 1010 = 1000 MSPS 0101 = 500 MSPS 0x00 0x03 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 Channel B 0 0 1 Channel A 0 1 0 0xAX for AD92341000 0x5X for AD9234500 0x03 0x00 0x01 0x56 0 0 0 0 0 1 0 0 0x04 0 0 0 0 0 0 0 Input disable 0 = normal operation 1 = input disabled 0x00 0011 = AD9234-1000 0001 = AD9234-500 Analog input differential termination 0000 = 400 Ω 0001 = 200 Ω 0010 = 100 Ω 0110 = 50 Ω 0 0000 = 1.0× buffer current 0001 = 1.5× buffer current 0010 = 2.0× buffer current 0011 = 2.5× buffer current 0100 = 3.0× buffer current 0101 = 3.5× buffer current … 1111 = 8.5× buffer current 0 0 0 0 0 0 0 0 0 0 1.0 V reference select 0 = internal 1 = external Rev. B | Page 60 of 72 Notes 0x03 for AD92341000; 0x01 for AD9234500 0x30 for AD92341000; 0x20 for AD9234500 0x00 Read only Read only Read only Read only Read only Read only Data Sheet Reg Addr (Hex) 0x028 AD9234 Register Name Temperature diode (local) Bit 7 (MSB) 0 0x03F PDWN/ STBY pin control (local) 0x040 Chip pin control 0x10B Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 0= 0 PDWN/ STBY enabled 1= disabled PDWN/STBY function 00 = power down 01 = standby 10 = disabled 0 0 0 0 0 Clock divider 0 0 0 0 0x10C Clock divider phase (local) 0 0 0 0 0x10D Clock divider and SYSREF control 0 0 0 0x117 Clock delay control Clock divider auto phase adjust 0= disabled 1= enabled 0 0 0 0 0x118 Clock fine delay (local) 0x11C Clock status 0 Bit 6 0 Bit 0 (LSB) Diode selection 0 = no diode selected 1= temperature diode selected 0 Fast Detect A (FD_A) 000 = Fast Detect A output 001 = JESD204B LMFC output 010 = JESD204B internal SYNC~ output 011 = temperature diode 111 = disabled 000 = divide by 1 0 001 = divide by 2 011 = divide by 4 111 = divide by 8 Independently controls Channel A and Channel B clock divider phase offset 0000 = 0 input clock cycles delayed 0001 = ½ input clock cycles delayed 0010 = 1 input clock cycles delayed 0011 = 1½ input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2½ input clock cycles delayed … 1111 = 7½ input clock cycles delayed Clock divider positive Clock divider negative skew window skew window 00 = no positive skew 00 = no negative skew 01 = 1 device clock of 01 = 1 device clock of positive skew negative skew 10 = 2 device clocks of 10 = 2 device clocks of positive skew negative skew 11 = 3 device clocks of 11 = 3 device clocks of positive skew negative skew Clock fine 0 0 0 delay adjust enable 0 = disabled 1 = enabled Fast Detect B (FD_B) 000 = Fast Detect B output 001 = JESD204B LMFC output 010 = JESD204B internal SYNC~ output 111 = disabled Clock fine delay adjust[7:0], twos complement coded control to adjust the fine sample clock skew in ~1.7 ps steps ≤ −88 = −151.7 ps skew −87 = −150 ps skew … 0 = 0 ps skew … ≥ +87 = +150 ps skew 0 = no input 0 0 0 0 0 0 clock detected 1 = input clock detected Rev. B | Page 61 of 72 Default 0x00 Notes Used in conjunction with Reg. 0x040 0x00 Used in conjunction with Reg. 0x040 0x3F 0x00 0x00 0x00 Clock divider must be >1 0x00 Enabling the clock fine delay adjust causes a datapath reset Used in conjunction with Reg. 0x0117 0x00 Read only AD9234 Reg Addr (Hex) 0x120 Data Sheet Register Name SYSREF± Control 1 Bit 7 (MSB) 0 0x121 SYSREF± Control 2 0 0x122 SYSREF± Control 3 0x123 SYSREF± timestamp delay control 0x128 SYSREF± Status 1 SYSREF± and clock divider status 0x129 0x12A 0x1FF SYSREF± counter Chip sync mode 0 0 0 Bit 6 SYSREF± flag reset 0= normal operation 1 = flags held in reset 0 Bit 4 SYSREF± transition select 0 = low to high 1 = high to low 0 0 Bit 3 CLK± edge select 0 = rising 1 = falling Bit 2 Bit 1 SYSREF± mode select 00 = disabled 01 = continuous 10 = N shot Bit 0 (LSB) 0 SYSREF± N-shot ignore counter select 0000 = next SYSREF± Only 0001 = ignore the first SYSREF± transitions 0010 = ignore the first two SYSREF± transitions … 1111 = ignore the first 16 SYSREF± transitions Positive skew window Negative skew window (measured in sample (measured in sample clocks); number of clock clocks); number of clock cycles before the sample cycles before the clock by which captured sample clock by which SYSREF± transitions are captured SYSREF± ignored transitions are ignored 00 = no positive 00 = no negative skew – SYSREF± must be skew – SYSREF± must captured accurately be captured accurately 01 = 1 sample clock of 01 = 1 sample clock of positive skew negative skew 10 = 2 sample clocks of 10 = 2 sample clocks of positive skew negative skew 11 = 3 sample clocks of 11 = 3 sample clocks of positive skew negative skew SYSREF± timestamp delay, Bits[6:0] 0 0x00 = no delay 0x01 = 1 clock delay … 0x7F = 127 clocks delay SYSREF± hold status, Register 0x128[7:4], SYSREF± setup status, Register 0x128[3:0], refer to Table 14 refer to Table 14 Clock divider phase when SYSREF± was captured 0 0 0 0000 = in-phase 0001 = SYSREF± is ½ cycle delayed from clock 0010 = SYSREF± is 1 cycle delayed from clock 0011 = 1½ input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2½ input clock cycles delayed … 1111 = 7½ input clock cycles delayed SYSREF± counter, Bits[7:0] increments when a SYSREF± signal is captured 0 0 0x200 Chip application mode 0 0 0x201 Chip 0 decimation ratio Customer offset 0 0x228 Bit 5 0 0 0 Default 0x00 Notes 0x00 Mode select, Reg. 0x120, Bits[2:1], must be N shot 0x00 0x00 Read only Read only Read only Synchronization mode 00 = normal 01 = timestamp Chip operating mode 00 = full bandwidth mode 01 = DDC 0 on 10 = DDC 0 and DDC 1 0x00 Chip decimation ratio select 000 = full sample rate (decimate = 1) 001 = decimate by 2 Offset adjust in LSBs from +127 to −128 (twos complement format) 0x00 0 Chip Q ignore 0= normal (I/Q) 1= ignore (I– only) 0 0 0 0 0 0 0 0 0 Rev. B | Page 62 of 72 0x00 0x00 Ignored when Reg. 0x01FF = 0x00 Data Sheet Reg Addr (Hex) 0x245 0x247 0x248 0x249 0x24A 0x24B 0x24C 0x26F Register Name Fast detect (FD) control (local) FD upper threshold LSB (local) FD upper threshold MSB (local) FD lower threshold LSB (local) FD lower threshold MSB (local) FD dwell time LSB (local) FD dwell time MSB (local) Signal ,onitor synchronizatio n control AD9234 Bit 7 (MSB) 0 0 Bit 6 0 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 Force Force FD_A/ FD_B value of FD_A/ pins; FD_B pins 0 = normal if force function; 1 = force to pins is true, this value value is output on FD pins Fast detect upper threshold, Bits[7:0] 0 Bit 1 0 Bit 0 (LSB) Enable fast detect output 0 Fast detect upper threshold, Bits[12:8] 0 0x00 0x00 Fast detect lower threshold, Bits[12:8] 0x00 Fast detect dwell time, Bits[7:0] 0x00 Fast detect dwell time, Bits[15:8] 0x00 0 0 0 0 0 0 0 0 0 0 0 0 Synchronization mode 00 = disabled 01 = continuous 11 = one shot Signal monitor control (local) 0x271 Signal Monitor Period Register 0 (local) Signal monitor period, Bits[7:0] 0x80 0x272 Signal Monitor Period Register 1 (local) Signal monitor period, Bits[15:8] 0x00 0x273 Signal Monitor Period Register 2 (local) Signal monitor period, Bits[23:16] 0x00 0x274 Signal monitor result control (local) 0x01 0x275 Signal Monitor Result Register 0 (local) Signal Monitor Result Register 1 (local) Result Result 0 0 0 selection update 0 = reserved 1 = update 1 = peak results (self detector clear) Signal monitor result, Bits[7:0] When Register 0x0274[0] = 1, result bits [19:7] = peak detector absolute value [12:0]; result bits [6:0] = 0 0x276 0 0 Signal monitor result, Bits[15:8] Rev. B | Page 63 of 72 Peak detector 0= disabled 1= enabled 0x00 0x270 0 Notes 0x00 Fast detect lower threshold, Bits[7:0] 0 Default 0x00 0 Refer to the Signal Monitor section 0x00 Read only Read only In decimate d output clock cycles In decimate d output clock cycles In decimate d output clock cycles Updated based on Reg. 0x274[4] Updated based on Reg. 0x274[4] AD9234 Reg Addr (Hex) 0x277 0x278 0x279 0x27A Data Sheet Register Bit 7 Name (MSB) Signal Monitor 0 Result Register 1 (local) Signal monitor period counter result (local) Signal monitor SPORT over JESD204B control (local) SPORT over JESD204B input selection (local) Bit 6 0 Bit 5 0 Bit 4 0 0x315 0x320 0x321 0x327 DDC 0 frequency LSB DDC0 frequency MSB DDC 0 phase LSB DDC 0 phase MSB DDC 0 output test mode selection Bit 2 Bit 1 Bit 0 (LSB) Signal monitor result, Bits[19:16] Period count result, Bits[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Complex to real enable 0= disabled 1= enabled 0 DDC Function Registers (See the Digital Downconverter (DDC) Section) DDC NCO 0x300 DDC synch 0 0 0 control soft reset 0 = normal operation 1 = reset IF (intermediate Gain 0x310 DDC 0 control Mixer frequency) mode select select 00 = variable IF mode 0 = 0 dB 0 = real (mixers and NCO gain mixer enabled) 1 = 6 dB 1= 01 = 0 Hz IF mode gain complex (mixer bypassed, NCO mixer disabled) 10 = fADC/4 Hz IF mode (fADC/4 downmixing mode) 11 = test mode (mixer inputs forced to +FS, NCO enabled) 0x311 DDC 0 input 0 0 0 0 selection 0x314 Bit 3 X X X X X X 0 0 0 Read only 00 = reserved 11 = enable Peak detector 0= disabled 1= enabled Rev. B | Page 64 of 72 0x00 0 0x00 Synchronization mode (triggered by SYSREF±) 00 = disabled 01 = continuous 11 = 1-shot Decimation rate select (complex to real disabled) 11 = decimate by 2 (complex to real enabled) 11 = decimate by 1 0x00 I input select Q input 0 0 = Ch A select 1 = Ch B 0 = Ch A 1 = Ch B DDC 0 NCO frequency value, Bits[7:0], twos complement DDC 0 NCO frequency value, Bits[11:8], X twos complement DDC 0 NCO phase value, Bits[7:0], twos complement DDC 0 NCO phase value, Bits[11:8], X twos complement I output test Q output 0 0 0 mode test mode enable enable 0 = disabled 0= 1 = enabled disabled from Ch A 1= enabled from Ch B 0 Default Read only 0x00 0x00 0x00 0x00 0x00 0x00 Notes Updated based on Reg. 0x274[4] Updated based on Reg. 0x274[4] Data Sheet Reg Addr (Hex) 0x330 AD9234 Register Name DDC 1 control Bit 7 (MSB) Mixer select 0 = real mixer 1= complex mixer Bit 6 Gain select 0 = 0 dB gain 1 = 6 dB gain 0x331 DDC 1 input selection 0 0 0x334 DDC 1 frequency LSB DDC 1 frequency MSB DDC 1 phase LSB DDC 1 phase MSB DDC 1 output test mode selection 0x335 0x340 0x341 0x347 X X Bit 5 Bit 4 IF (intermediate frequency) mode 00 = variable IF mode (mixers and NCO enabled) 01 = 0 Hz IF mode (mixer bypassed, NCO disabled) 10 = fADC/4 Hz IF mode (fADC/4 downmixing mode) 11 = test mode (mixer inputs forced to +FS, NCO enabled) 0 0 X Bit 2 0 Bit 1 Bit 0 (LSB) Decimation rate select (complex to real disabled) 11 = decimate by 2 (complex to real enabled) 11 = decimate by 1 I input select Q input 0 0 = Ch A select 1 = Ch B 0 = Ch A 1 = Ch B DDC 1 NCO frequency value, Bits[7:0], twos complement DDC 1 NCO frequency value, Bits[11:8], X twos complement DDC 1 NCO phase value, Bits[7:0], twos complement DDC 1 NCO phase value, Bits[11:8], X twos complement I output test Q output 0 0 0 mode test mode enable enable 0 = disabled 0= 1 = enabled disabled from Ch A 1= enabled from Ch B X X X 0 0 0 0 Reset PN long gen 0 = long PN enable 1 = long PN reset Reset PN short gen 0 = short PN enable 1 = short PN reset Digital Outputs and Test Modes User 0x550 ADC test modes pattern (local) selection 0= continuous repeat 1 = single pattern Bit 3 Complex to real enable 0= disabled 1= enabled 0 Test mode selection 0000 = off, normal operation 0001 = midscale short 0010 = positive full scale 0011 = negative full scale 0100 = alternating checker board 0101 = PN sequence, long 0110 = PN sequence, short 0111 = 1/0 word toggle 1000 = the user pattern test mode (used with Register 0x550, Bit 7 and user pattern (1, 2, 3, 4) registers), 1111 = ramp output 0 0 0 Default 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x551 User Pattern 1 LSB 0 0 0 0 0 0x552 User Pattern 1 MSB 0 0 0 0 0 0 0 0 0x00 0x553 User Pattern 2 LSB 0 0 0 0 0 0 0 0 0x00 Rev. B | Page 65 of 72 Notes 0x00 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 AD9234 Reg Addr (Hex) 0x554 Data Sheet Register Name User Pattern 2 MSB Bit 7 (MSB) 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 (LSB) 0 Default 0x00 0x555 User Pattern 3 LSB 0 0 0 0 0 0 0 0 0x00 0x556 User Pattern 3 MSB 0 0 0 0 0 0 0 0 0x00 0x557 User Pattern 4 LSB 0 0 0 0 0 0 0 0 0x00 0x558 User Pattern 4 MSB 0 0 0 0 0 0 0 0 0x00 0x559 Output Mode Control 1 0 0 0x55A Output Mode Control 2 0 Converter control Bit 1 selection 000 = tie low (1’b0) 001 = overrange bit 010 = signal monitor bit 011 = fast detect (FD) bit 101 = SYSREF± Only used when CS (Register 0x58F) = 2 or 3 0 0 0 0 0x561 Output mode 0 0 0 0 0 0x562 Virtual Output overrange (OR) Converter 7 clear OR 0 = OR bit enabled 1 = OR bit cleared Output OR Virtual status Converter 7 OR 0 = no OR 1 = OR occurred Virtual Converter 6 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 6 OR 0 = no OR 1 = OR occurred Virtual Converter 5 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 5 OR 0 = no OR 1 = OR occurred Virtual Converter 4 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 3 OR 0 = OR bit enabled 1 = OR bit cleared Virtual Converter 4 OR 0 = no OR 1 = OR occurred Virtual Converter 3 OR 0 = no OR 1 = OR occurred Converter control Bit 0 selection 000 = tie low (1’b0) 001 = overrange bit 010 = signal monitor bit 011 = fast detect (FD) bit 101 = SYSREF± Only used when CS (Register 0x58F) = 3 Converter control Bit 2 selection 000 = tie low (1’b0) 001 = overrange bit 010 = signal monitor bit 011 = fast detect (FD) bit 101 = SYSREF Used when CS (Register 0x58F) = 1, 2, or 3 Data format select Sample 00 = offset binary invert 01 = twos complement 0 = normal 1 = sample invert Virtual ConVirtual Con- Virtual verter r 0 OR verter 2 OR Con0 = OR bit verter 1 0 = OR bit enabled OR enabled 0 = OR bit 1 = OR bit 1 = OR bit cleared enabled cleared 1 = OR bit cleared Virtual ConVirtual Con- Virtual verter 0 OR verter 2 OR Con0 = no OR verter 1 0 = no OR 1 = OR OR 1 = OR 0 = no OR occurred occurred 1 = OR occurred 0x563 Rev. B | Page 66 of 72 Notes Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 Used with Reg. 0x550 and Reg. 0x573 0x00 0x01 0x01 0x00 0x00 Read only Data Sheet Reg Addr (Hex) 0x564 AD9234 Register Name Output channel select Bit 7 (MSB) 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 0x56E JESD204B lane rate control 0 0 0 0 0 0 0x56F JESD204B PLL lock status 0 = serial lane rate ≥ 6.25 Gbps and ≤12.5 Gbps 1 = serial lane rate must be ≥ 3.125 Gbps and ≤ 6.25 Gbps 0 0x570 JESD204B quick configuration 0x571 JESD204B Link Mode Control 1 0x572 JESD204B Link Mode Control 2 0x573 JESD204B Link Mode Control 3 0x574 JESD204B Link Mode Control 4 0x578 JESD204B LMFC offset PLL lock 0 = not locked 1= locked 0 0 0 0 0 Bit 0 (LSB) Converter channel swap 0 = normal channel ordering 1 = channel swap enabled 0 0 JESD204B quick configuration L = number of lanes = 2Register 0x570, Bits[7:6] M = number of converters = 2Register 0x570, Bits[5:3] F = number of octets/frame = 2 Register 0x570, Bits[2:0] Link control FACI ILAS sequence mode Lane Tail bit (t) Long Standby 0 = active 0= 00 = ILAS disabled transport synchronPN mode 1 = power enabled 01 = ILAS enabled layer test ization 0= 0 = all down 0 = disable 11 = ILAS always on test 1 = 0= converter disable disabled mode FACI uses disable outputs 0 1 = /K28.7/ 1= enable 1 = CGS 1 = enable T = N΄ − N enable (/K28.5/) FACI uses − CS /K28.3/ and /K28.7/ 8B/10B bit 0 8B/10B SYNCINB± 0 SYNCINB± pin control SYNCinvert bypass pin type INB± pin 00 = normal 0 = normal 0 = normal 0= 10 = ignore SYNCINB± invert 1 = bypass 1 = invert 0 = active differential (force CGS) the a…j 1 = cmos 11 = ignore SYNCINB± low symbols 1 = active (force ILAS/user data) high JESD204B test mode patterns Test injection point CHKSUM mode 0000 = normal operation (test mode disabled) 00 = N΄ sample input 00 = sum of all 8-bit 0001 = alternating checker board 01 = 10-bit data at link config registers 0010 = 1/0 word toggle 8B/10B output (for 01 = sum of 0011 = 31-bit PN sequence—X31 + X28 + 1 PHY testing) individual link config 10 = 8-bit data at fields 0100 = 23-bit PN sequence—X23 + X18 + 1 scrambler input 10 = checksum set to 0101 = 15-bit PN sequence—X15 + X14 + 1 zero 0110 = 9-bit PN sequence—X9 + X5 + 1 0111 = 7-bit PN sequence—X7 + X6 + 1 1000 = ramp output 1110 = continuous/repeat user test 1111 = single user test ILAS delay Link layer test mode 0 0000 = transmit ILAS on first LMFC after 000 = normal operation (link layer test SYNCINB± deasserted mode disabled) 0001 = transmit ILAS on second LMFC after 001 = continuous sequence of /D21.5/ SYNCINB± deasserted characters … 100 = modified RPAT test sequence 1111 = transmit ILAS on 16th LMFC after 101 = JSPAT test sequence 110 = JTSPAT test sequence SYNCINB± deasserted 0 0 0 LMFC phase offset value, Bits[4:0] Rev. B | Page 67 of 72 Default 0x00 Notes 0x00 for AD92341000; 0x10 for AD9234500 0x00 0x88 0x14 0x00 0x00 0x00 0x00 Read only Refer to Table 12 and Table 13 AD9234 Reg Addr (Hex) 0x580 0x581 0x583 0x584 0x585 0x586 0x58B Register Name JESD204B DID config JESD204B BID config JESD204B LID Config 1 JESD204B LID Config 2 JESD204B LID Config 3 JESD204B LID Config 4 JESD204B parameters SCR/L 0x58C JESD204B F config 0x58D JESD204B K config 0x58E JESD204B M config 0x58F JESD204B CS/N config 0x0590 JESD204B N’ config 0x591 JESD204B S config JESD204B HD and CF configuration 0x592 0x5A0 0x5A1 0x5A2 0x5A3 JESD204B CHKSUM 0 JESD204B CHKSUM 1 JESD204B CHKSUM 2 JESD204B CHKSUM 3 Data Sheet Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 JESD204B Tx DID value, Bits[7:0] 0 0 0 0 0 0 0 Lane 0 LID value, Bits[4:0] 0x00 0 0 0 Lane 1 LID value, Bits[4:0] 0x01 0 0 0 Lane 2 LID value, Bits[4:0] 0x01 0 0 0 Lane 3 LID value, Bits[4:0] 0x03 JESD204B scramblin g (SCR) 0= disabled 1= enabled 0 0 0 Bit 1 Bit 0 (LSB) JESD204B Tx BID value, Bits[7:0] 0 0 JESD204B lanes (L) 00 = 1 lane 01 = 2 lanes 11 = 4 lanes Read only, see Register 0x570 Number of octets per frame, F = Register 0x58C, Bits[7:0] + 1 0 0 Number of frames per multiframe, K = Register 0x58D, Bits[4:0] + 1 Only values where (F × K) mod 4 = 0 are supported 0 Number of converters per link, Bits[7:0] 0x00 = link connected to one virtual converter (M = 1) 0x01 = link connected to two virtual converters (M = 2) 0x03 = link connected to four virtual converters (M = 4) 0x07 = link connected to eight virtual converters (M = 8) ADC converter resolution (N) 0 0x06 = 7-bit resolution 0x07 = 8-bit resolution 0x08 = 9-bit resolution 0x09 = 10-bit resolution 0x0A = 11-bit resolution 0x0B = 12-bit resolution 0x0C = 13-bit resolution 0x0D = 14-bit resolution 0x0E = 15-bit resolution 0x0F = 16-bit resolution Number of control bits (CS) per sample 00 = no control bits (CS = 0) 01 = 1 control bit (CS = 1); Control Bit 2 only 10 = 2 control bits (CS = 2); Control Bit 2 and Control Bit 1 only 11 = 3 control bits (CS = 3); all control bits (2, 1, 0) Subclass support (Subclass version) 000 = Subclass 0 (no deterministic latency) 001 = Subclass 1 0 0 1 HD value 0= disabled 1= enabled 0 0 ADC number of bits per sample (N’) 0x7 = 8 bits 0xF = 16 bits Samples per converter frame cycle (S) S value = Register 0x591[4:0] +1 Control words per frame clock cycle per link (CF) CF value = Register 0x592, Bits[4:0] Default 0x00 Notes 0x00 0x8X 0x88 0x1F Read only, see Reg. 0x570 See Reg. 0x570 Read only 0x0F 0x2F 0x80 Read only Read only CHKSUM value for SERDOUT0±, Bits[7:0] 0x81 Read only CHKSUM value for SERDOUT1±, Bits[7:0] 0x82 Read only CHKSUM value for SERDOUT2±, Bits[7:0] 0x82 Read only CHKSUM value for SERDOUT3±, Bits[7:0] 0x84 Read only Rev. B | Page 68 of 72 Data Sheet Reg Addr (Hex) 0x5B0 AD9234 Register Name JESD204B lane power-down Bit 7 (MSB) 1 0x5B2 JESD204B lane SERDOUT0± assign 0x5B3 Bit 5 1 X Bit 6 SERDOUT3± 0 = on 1 = off X Bit 3 1 X Bit 4 SERDOUT2± 0 = on 1 = off X JESD204B lane SERDOUT1± assign X X X X 0 0x5B5 JESD204B lane SERDOUT2± assign X X X X 0 0x5B6 JESD204B lane SERDOUT3± assign X X X X 0 0x5BF JESD serializer drive adjust 0 0 0 0 0x5C1 De-emphasis select 0 0 SERDOUT2± 0 = disable 1 = enable 0x5C2 De-emphasis setting for SERDOUT0± 0 SERDOUT3± 0= disable 1= enable 0 0 0 0x5C3 De-emphasis setting for SERDOUT1± 0 0 0 0 Bit 2 Bit 1 Bit 0 (LSB) SERDOUT0± SERD1 0 = on OUT1± 1 = off 0 = on 1 = off SERDOUT0± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 SERDOUT1± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 SERDOUT2± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 SERDOUT3± lane assignment 000 = Logical Lane 0 001 = Logical Lane 1 010 = Logical Lane 2 011 = Logical Lane 3 Swing voltage 0000 = 237.5 mV 0001 = 250 mV 0010 = 262.5 mV 0011 = 275 mV 0100 = 287.5 mV 0101 = 300 mV (default) 0110 = 312.5 mV 0111 = 325 mV 1000 = 337.5 mV 1001 = 350 mV 1010 = 362.5 mV 1011 = 375 mV 1100 = 387.5 mV 1101 = 400 mV 1110 = 412.5 mV 1111 = 425 mV SERDOUT0± SERD0 0 = disable OUT1± 1 = enable 0 = disable 1 = enable 0 0 SERDOUT0± de-emphasis settings: 0000 = 0 dB 0001 = 0.3 dB 0010 = 0.8 dB 0011 = 1.4 dB 0100 = 2.2 dB 0101 = 3.0 dB 0110 = 4.0 dB 0111 = 5.0 dB SERDOUT1± de-emphasis settings: 0000 = 0 dB 0001 = 0.3 dB 0010 = 0.8 dB 0011 = 1.4 dB 0100 = 2.2 dB 0101 = 3.0 dB 0110 = 4.0 dB 0111 = 5.0 dB Rev. B | Page 69 of 72 Default 0xAA 0x00 0x11 0x22 0x33 0x05 0x00 0x00 0x00 Notes AD9234 Reg Addr (Hex) 0x5C4 0x5C5 Data Sheet Register Name De-emphasis setting for SERDOUT2± Bit 7 (MSB) 0 Bit 6 0 Bit 5 0 Bit 4 0 De-emphasis setting for SERDOUT3± 0 0 0 0 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) SERDOUT2± de-emphasis settings: 0000 = 0 dB 0001 = 0.3 dB 0010 = 0.8 dB 0011 = 1.4 dB 0100 = 2.2 dB 0101 = 3.0 dB 0110 = 4.0 dB 0111 = 5.0 dB SERDOUT3± de-emphasis settings: 0000 = 0 dB 0001 = 0.3 dB 0010 = 0.8 dB 0011 = 1.4 dB 0100 = 2.2 dB 0101 = 3.0 dB 0110 = 4.0 dB 0111 = 5.0 dB Rev. B | Page 70 of 72 Default 0x00 0x00 Notes Data Sheet AD9234 APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS The AD9234 must be powered by the following seven supplies: AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, and SPIVDD = 1.8 V. For applications requiring an optimal high power efficiency and low noise performance, it is recommended that the ADP2164 and ADP2370 switching regulators be used to convert the 3.3 V, 5.0 V, or 12 V input rails to an intermediate rail (1.8 V and 3.8 V). These intermediate rails are then postregulated by very low noise, low dropout (LDO) regulators (ADP1741, ADM7172, and ADP125). Figure 117 shows the recommended power supply scheme for AD9234. ADP1741 1.8V AVDD1 1.25V AVDD1_SR 1.25V ADP1741 DVDD 1.25V DRVDD 1.25V 3.6V ADP125 AVDD3 3.3V 3.3V ADM7172 OR ADP1741 AVDD2 2.5V It is required that the exposed pad on the underside of the ADC be connected to ground to achieve the best electrical and thermal performance of the AD9234. Connect an exposed continuous copper plane on the PCB to the AD9234 exposed pad, Pin 0. The copper plane must have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias must be solder filled or plugged. The number of vias and the fill determine the resultant θJA measured on the board, which is shown in Table 7. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 118 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). 12244-063 SPIVDD (1.8V OR 3.3V) EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS Figure 117. High Efficiency, Low Noise Power Solution for the AD9234 12244-064 It is not necessary to split all of these power domains in all cases. The recommended solution shown in Figure 117 provides the lowest noise, highest efficiency power delivery system for the AD9234. If only one 1.25 V supply is available, route to AVDD1 first and then tap it off and isolate it with a ferrite bead or a filter choke, preceded by decoupling capacitors for AVDD1_SR, SPIVDD, DVDD, and DRVDD, in that order. The user can employ several different decoupling capacitors to cover both high and low frequencies. These must be located close to the point of entry at the PCB level and close to the devices, with minimal trace lengths. Figure 118. Recommended PCB Layout of Exposed Pad for the AD9234 AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) can be used to provide a separate power supply node to the SYSREF± circuits of AD9234. If running in Subclass 1, the AD9234 can support periodic one shot or gapped signals. To minimize the coupling of this supply into the AVDD1 supply node, adequate supply bypassing is needed. Rev. B | Page 71 of 72 AD9234 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 9.10 9.00 SQ 8.90 0.30 0.25 0.18 PIN 1 INDICATOR 49 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 64 1 48 0.50 BSC 7.70 7.60 SQ 7.50 EXPOSED PAD 33 0.80 0.75 0.70 SIDE VIEW PKG-004396 SEATING PLANE 0.45 0.40 0.35 16 32 17 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.20 MIN 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WMMD 04-10-2017-A TOP VIEW Figure 119. 64-Lead Lead Frame Chip Scale Package [LFCSP] 9 mm × 9 mm Body and 0.75 Package Height (CP-64-15) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9234BCPZ-500 AD9234BCPZRL7-500 AD9234BCPZ-1000 AD9234BCPZRL7-1000 AD9234-500EBZ AD9234-1000EBZ AD9234-LF500EBZ AD9234-LF1000EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP] 64-Lead Lead Frame Chip Scale Package [LFCSP] 64-Lead Lead Frame Chip Scale Package [LFCSP] 64-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board for AD9234-500 (Optimized for Full Analog Input Frequency Range) Evaluation Board for AD9234-1000 (Optimized for Full Analog Input Frequency Range) Evaluation Board for AD9234-500 with 1 GHz Bandwidth Evaluation Board for AD9234-1000 with 1 GHz Bandwidth Z = RoHS Compliant Part. ©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12244-0-1/18(B) Rev. B | Page 72 of 72 Package Option CP-64-15 CP-64-15 CP-64-15 CP-64-15