AD9238BCPZ-65EB

12-Bit, 20 MSPS/40 MSPS/65 MSPS Dual A/D Converter AD9238 FEATURES Integrated dual 12-bit ADC Single 3 V supply operation (2.7 V to 3.6 V) SNR = 70 dB (to Nyquist, AD9238-65) SFDR = 80.5 dBc (to Nyquist, AD9238-65) Low power: 300 mW/channel at 65 MSPS Differential input with 500 MHz, 3 dB bandwidth Exceptional crosstalk immunity > 85 dB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty cycle stabilizer Output datamux option FUNCTIONAL BLOCK DIAGRAM AVDD AGND OTR_A VIN+_A SHA VIN–_A ADC 12 OUTPUT MUX/ BUFFERS 12 D11_A TO D0_A OEB_A REFT_A REFB_A VREF SENSE AGND 0.5V MODE CONTROL REFT_B CLOCK DUTY CYCLE STABILIZER MUX_SELECT CLK_A CLK_B DCS SHARED_REF PWDN_A PWDN_B DFS APPLICATIONS Ultrasound equipment Direct conversion or IF sampling receivers WB-CDMA, CDMA2000, WiMAX Battery-powered instruments Hand-held scopemeters Low cost, digital oscilloscopes REFB_B VIN+_B SHA VIN–_B ADC OTR_B 12 OUTPUT 12 MUX/ BUFFERS D11_B TO D0_B OEB_B 02640-001 AD9238 DRVDD DRGND Figure 1. GENERAL DESCRIPTION The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS analog-to-digital converter (ADC). It features dual high performance sample-and-hold amplifiers (SHAs) and an integrated voltage reference. The AD9238 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy and to guarantee no missing codes over the full operating temperature range at up to 65 MSPS data rates. The wide bandwidth, differential SHA allows for a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for various applications, including multiplexed systems that switch fullscale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate. Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available and can compensate for wide variations in the clock duty cycle, allowing the converter to maintain excellent performance. The digital output data is presented in either straight binar y or twos complement format. Out-of-range signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fabricated on an advanced CMOS process, the AD9238 is available in a Pb-free, space saving, 64-lead LQFP or LFCSP and is specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. Pin-compatible with the AD9248, 14-bit 20MSPS/ 40 MSPS/65 MSPS ADC. 2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS allow flexibility between power, cost, and performance to suit an application. 3. Low power consumption: • AD9238-65: 65 MSPS = 600 mW • AD9238-40: 40 MSPS = 330 mW • AD9238-20: 20 MSPS = 180 mW 4. Typical channel isolation of 85 dB @ fIN = 10 MHz. 5. The clock duty cycle stabilizer (AD9238-20/AD9238-40/ AD9238-65) maintains performance over a wide range of clock duty cycles. 6. Multiplexed data output option enables single-port operation from either Data Port A or Data Port B. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 ©2005 Analog Devices, Inc. All rights reserved. AD9238 TABLE OF CONTENTS Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 6 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels ........................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Terminology .................................................................................... 10 Typical Performance Characteristics ........................................... 11 Equivalent Circuits ......................................................................... 15 Theory of Operation ...................................................................... 16 Analog Input ............................................................................... 16 Clock Input and Considerations .............................................. 17 Power Dissipation and Standby Mode..................................... 18 Digital Outputs ........................................................................... 18 Timing.......................................................................................... 18 Data Format ................................................................................ 19 Voltage Reference....................................................................... 19 AD9238 LQFP Evaluation Board ................................................. 21 Clock Circuitry ........................................................................... 21 Analog Inputs ............................................................................. 21 Reference Circuitry .................................................................... 21 Digital Control logic .................................................................. 21 Outputs ........................................................................................ 21 LQFP Evaluation Board Bill of Materials (BOM).................. 23 LQFP Evaluation Board Schematics ........................................ 24 LQFP PCB Layers....................................................................... 28 Dual ADC LFCSP PCB.................................................................. 34 Power Connector........................................................................ 34 Analog Inputs ............................................................................. 34 Optional Operational Amplifier .............................................. 34 Clock ............................................................................................ 34 Voltage Reference ....................................................................... 34 Data Outputs............................................................................... 34 LFCSP Evaluation Board Bill of Materials (BOM) ................ 35 LFCSP PCB Schematics............................................................. 36 LFCSP PCB Layers ..................................................................... 39 Thermal Considerations............................................................ 44 Outline Dimensions ....................................................................... 45 Ordering Guide .......................................................................... 46 REVISION HISTORY 4/05—Rev. A to Rev. B Changes to Format and Layout........................................ Universal Added LFCSP ..................................................................... Universal Changes to Features and Applications...........................................1 Changes to General Description and Product Highlights ..........1 Changes to Figure 1..........................................................................1 Changes to Table 1............................................................................3 Changes to Table 2............................................................................5 Added Digital Specifications...........................................................6 Moved Switching Specifications to.................................................6 Changes to Pin Function Descriptions..........................................8 Changes to Terminology Section .................................................10 Changes to Figure 29......................................................................15 Changes to Clock Input and Considerations Section................17 Changes to Figure 33......................................................................18 Changes to Data Format Section..................................................19 Added AD9238 LQFP Evaluation Board Section ......................21 Added Dual ADC LFCSP PCB Section.......................................34 Added Thermal Considerations Section.....................................44 Updated Outline Dimensions.......................................................45 Changes to Ordering Guide ..........................................................46 Rev. B | Page 2 of 48 AD9238 9/03—Rev. 0 to Rev. A Changes to DC Specifications ........................................................ 2 Changes to Switching Specifications ............................................. 3 Changes to AC Specifications......................................................... 4 Changes to Figure 1.......................................................................... 4 Changes to Ordering Guide............................................................ 5 Changes to TPCs 2, 3, and 6 ........................................................... 8 Changes to Clock Input and Considerations Section................ 13 Added Text to Data Format Section ............................................ 15 Changes to Figure 9........................................................................ 16 Added Evaluation Board Diagrams Section ............................... 17 Update Outline Dimensions ......................................................... 24 2/03—Revision 0: Initial Version Rev. B | Page 3 of 48 AD9238 SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Guaranteed Offset Error Gain Error1 Differential Nonlinearity (DNL)2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA INPUT REFERRED NOISE Input Span = 1 V Input Span = 2.0 V ANALOG INPUT Input Span = 1.0 V Input Span = 2.0 V Input Capacitance3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD2 IDRVDD2 PSRR POWER CONSUMPTION DC Input4 Sine Wave Input2 Standby Power5 MATCHING CHARACTERISTICS Offset Error Gain Error 1 2 3 Temp Full Full Full Full Full 25°C Full 25°C Full Full Full Full Full Full 25°C 25°C Full Full Full Full Test Level VI VI VI IV V I V I V V VI V V V V V IV IV V V AD9238BST/BCP-20 Min Typ Max 12 12 ±0.30 ±0.30 ±0.35 ±0.35 ±0.45 ±0.40 ±4 ±12 ±5 0.8 ±2.5 0.1 0.54 0.27 1 2 7 7 ±35 ±1.2 ±2.2 ±0.9 ±1.4 AD9238BST/BCP-40 Min Typ Max 12 12 ±0.50 ±0.50 ±0.35 ±0.35 ±0.60 ±0.50 ±4 ±12 ±5 0.8 ±2.5 0.1 0.54 0.27 1 2 7 7 ±35 ±1.1 ±2.4 ±0.8 ±1.4 AD9238BST/BCP-65 Min Typ Max 12 12 ±0.50 ±0.50 ±0.35 ±0.35 ±0.70 ±0.55 ±6 ±12 ±5 0.8 ±2.5 0.1 0.54 0.27 1 2 7 7 ±35 ±1.1 ±2.5 ±1.0 ±1.75 Unit Bits Bits % FSR % FSR LSB LSB LSB LSB µV/°C ppm/°C mV mV mV mV LSBrms LSBrms V p-p V p-p pF kΩ Full Full Full Full Full Full Full Full 25°C 25°C IV IV V V V V VI V V V 2.7 2.25 3.0 3.0 60 4 ±0.01 180 190 2.0 ±0.1 ±0.05 3.6 3.6 2.7 2.25 3.0 3.0 110 10 ±0.01 330 360 2.0 ±0.1 ±0.05 3.6 3.6 2.7 2.25 3.0 3.0 200 14 ±0.01 600 640 2.0 ±0.1 ±0.05 3.6 3.6 V V mA mA % FSR mW mW mW % FSR % FSR 212 397 698 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference). Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 28 for the equivalent analog input structure. 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND). Rev. B | Page 4 of 48 AD9238 AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 2. Parameter SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz EFFECTIVE NUMBER OF BITS (ENOB) fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz WORST HARMONIC (SECOND or THIRD) fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 35 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz CROSSTALK Temp 25°C Full 25°C Full 25°C Full 25°C 25°C Test Level V V IV V IV V IV V AD9238BST/BCP-20 Min Typ Max 70.4 70.2 70.4 69.7 AD9238BST/BCP-40 Min Typ Max 70.4 AD9238BST/BCP-65 Min Typ Max 70.3 Unit dB dB dB dB dB dB dB dB 69.7 70.1 70.3 68.7 69.3 70.0 67.6 68.7 68.3 25°C Full 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full 25°C Full 25°C 25°C Full Full Full 25°C Full 25°C Full 25°C Full 25°C 25°C Full V V IV V IV V IV V V V IV V IV V IV V V V V V V I V I V I V V 69.3 70.2 70.1 70.2 69.4 70.2 70.1 69.9 70.1 68.1 68.9 69.1 66.6 11.4 67.9 11.5 11.4 11.5 11.3 67.9 11.5 dB dB dB dB dB dB dB dB Bits Bits Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB 11.3 11.4 11.4 11.1 11.2 11.3 10.9 11.1 −84.0 11.1 −85.0 −80.0 86.0 84.0 86.0 76.7 86.0 86.0 76.1 85.0 86.0 72.5 80.0 80.5 75.0 −85.0 −85.0 −85.0 Rev. B | Page 5 of 48 AD9238 DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless other wise noted. Table 3. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS1 High Level Output Voltage Low Level Output Voltage 1 Temp Full Full Full Full Full Full Full Test Level IV IV IV IV IV IV IV AD9238BST/BCP-20 Min Typ Max 2.0 −10 −10 2 DRVDD − 0.05 0.05 0.8 +10 +10 AD9238BST/BCP-40 Min Typ Max 2.0 −10 −10 2 DRVDD − 0.05 0.05 0.8 +10 +10 AD9238BST/BCP-65 Min Typ Max 2.0 −10 −10 2 DRVDD − 0.05 0.05 0.8 +10 +10 Unit V V µA µA pF V V Output voltage levels measured with capacitive load only on each output. SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless other wise noted. Table 4. Parameter SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate CLK Period CLK Pulse-Width High1 CLK Pulse-Width Low1 DATA OUTPUT PARAMETER Output Delay2 (tPD) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (tJ) Wake-Up Time3 OUT-OF-RANGE RECOVERY TIME 1 2 Temp Full Full Full Full Full Full Full Full Full Full Full Test Level VI V V V V VI V V V V V AD9238BST/BCP-20 Min Typ Max 20 1 50.0 15.0 15.0 2 3.5 7 1.0 0.5 2.5 2 6 AD9238BST/BCP-40 Min Typ Max 40 1 25.0 8.8 8.8 2 3.5 7 1.0 0.5 2.5 2 6 AD9238BST/BCP-65 Min Typ Max 65 1 15.4 6.2 6.2 2 3.5 7 1.0 0.5 2.5 2 6 Unit MSPS MSPS ns ns ns ns Cycles ns pS rms ms Cycles The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 23). Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. N N–1 ANALOG INPUT N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 CLOCK DATA OUT N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N tPD = MIN 2.0ns, MAX 6.0ns Figure 2. Timing Diagram Rev. B | Page 6 of 48 02640-002 AD9238 ABSOLUTE MAXIMUM RATINGS1 Table 5. Parameter Pin Name ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF OEB, DFS VINA, VINB VREF SENSE REFB, REFT PDWN ENVIRONMENTAL2 Operating Temperature Junction Temperature Lead Temperature (10 sec) Storage Temperature 1 With Respect To AGND DRGND DRGND DRVDD DRGND AGND AGND AGND AGND AGND AGND Rating Min −0.3 −0.3 −0.3 −3.9 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −0.3 −45 Max +3.9 +3.9 +0.3 +3.9 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +85 150 300 +150 Unit V V V V V V V V V V V °C °C °C °C −65 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances: 64-lead LQFP, θJA = 54°C/W; 64-lead LFCSP, θJA = 26.4°C/W with heat slug soldered to ground plane. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. EXPLANATION OF TEST LEVELS I II III IV V VI 100% production tested. 100% production tested at 25°C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 7 of 48 AD9238 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SHARED_REF MUX_SELECT D11_A (MSB) PDWN_A OEB_A DRGND D10_A DRVDD D7_A OTR_A CLK_A AVDD D9_A D8_A 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AGND 1 VIN+_A 2 VIN–_A 3 AGND 4 AVDD 5 REFT_A 6 REFB_A 7 VREF 8 SENSE 9 REFB_B 10 REFT_B 11 AVDD 12 AGND 13 VIN–_B 14 VIN+_B 15 AGND 16 D6_A D5_A 48 D4_A 47 D3_A 46 D2_A 45 D1_A 44 D0_A (LSB) 43 DNC 42 DNC 41 DRVDD 40 DRGND 39 OTR_B 38 D11_B (MSB) 37 D10_B 36 D9_B 35 D8_B 34 D7_B 33 D6_B PIN 1 IDENTIFIER AD9238 64-LEAD LQFP TOP VIEW (Not to Scale) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 OEB_B D1_B D2_B D3_B D4_B PDWN_B D0_B (LSB) CLK_B DRGND DRVDD AVDD D5_B DCS DFS DNC DNC DNC = DO NOT CONNECT Figure 3. 64-Lead LQFP and LFCSP Pin Configuration Rev. B | Page 8 of 48 02640-003 AD9238 Table 6. Pin Function Descriptions (64-Lead LQFP and 64-Lead LFCSP) Pin No. 1, 4, 13, 16 2 3 5, 12, 17, 64 6 7 8 9 10 11 14 15 18 19 20 21 Mnemonic AGND VIN+_A VIN–_A AVDD REFT_A REFB_A VREF SENSE REFB_B REFT_B VIN−_B VIN+_B CLK_B DCS DFS PDWN_B Description Analog Ground. Analog Input Pin (+) for Channel A. Analog Input Pin (−) for Channel A. Analog Power Supply. Differential Reference (+) for Channel A. Differential Reference (−) for Channel A. Voltage Reference Input/Output. Reference Mode Selection. Differential Reference (−) for Channel B. Differential Reference (+) for Channel B. Analog Input Pin (−) for Channel B. Analog Input Pin (+) for Channel B. Clock Input Pin for Channel B. Enable Duty Cycle Stabilizer (DCS) Mode (Tie High to Enable). Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement). Power-Down Function Selection for Channel B: Logic 0 enables Channel B. Logic 1 powers down Channel B. (Outputs static, not High-Z.) Output Enable Bit for Channel B: Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z. Do Not Connect Pins. Should be left floating. Channel B Data Output Bits. Digital Output Ground. Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor. Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF. Out-of-Range Indicator for Channel B. Channel A Data Output Bits. Out-of-Range Indicator for Channel A. Output Enable Bit for Channel A: Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z. Power-Down Function Selection for Channel A: Logic 0 enables Channel A. Logic 1 powers down Channel A. (Outputs static, not High-Z.) Data Multiplexed Mode. (See Data Format section for how to enable; high setting disables output data multiplexed mode). Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode). Clock Input Pin for Channel A. 22 OEB_B 23, 24, 42, 43 25 to 27, 30 to 38 28, 40, 53 29, 41, 52 39 44 to 51, 54 to 57 58 59 DNC D0_B (LSB) to D11_B (MSB) DRGND DRVDD OTR_B D0_A (LSB) to D11_A (MSB) OTR_A OEB_A 60 PDWN_A 61 62 63 MUX_SELECT SHARED_REF CLK_A Rev. B | Page 9 of 48 AD9238 TERMINOLOGY Aperture Delay SHA performance measured from the rising edge of the clock input to when the input signal is held for conversion. Aperture Jitter The variation in aperture delay for successive samples, which is manifested as noise on the input to the ADC. Integral Nonlinearity (INL) Deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4,096 codes must be present over all operating ranges. Offset Error The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN−. Offset error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value 1½ LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Temperature Drift The temperature drift for zero error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX. Power Supply Rejection The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Total Harmonic Distortion (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal, expressed as a percentage or in decibels relative to the peak carrier signal (dBc). Signal-to-Noise and Distortion (SINAD) Ratio The ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in dB. Effective Number of Bits (ENOB) Using the following formula ENOB = (SINAD − 1.76)/6.02 ENOB for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Signal-to-Noise Ratio (SNR) The ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in dB. Spurious-Free Dynamic Range (SFDR) The difference in dB between the rms amplitude of the input signal and the peak spurious signal, which may or may not be a harmonic. Nyquist Sampling When the frequency components of the analog input are below the Nyquist frequency (fCLOCK/2), this is often referred to as Nyquist sampling. IF Sampling Due to the effects of aliasing, an ADC is not limited to Nyquist sampling. Higher sampled frequencies are aliased down into the first Nyquist zone (DC − fCLOCK/2) on the output of the ADC. The bandwidth of the sampled signal should not overlap Nyquist zones and alias onto itself. Nyquist sampling performance is limited by the bandwidth of the input SHA and clock jitter (jitter adds more noise at higher input frequencies). Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Crosstalk Coupling onto one channel being driven by a (−0.5 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Measurement includes all spurs resulting from both direct coupling and mixing components. Rev. B | Page 10 of 48 AD9238 TYPICAL PERFORMANCE CHARACTERISTICS AVDD, DRVDD = 3.0 V, T = 25°C, AIN differential drive, full scale = 2 V, unless other wise noted. 0 100 95 –20 90 85 SFDR MAGNITUDE (dBFS) SFDR/SNR (dBc) –40 80 75 SNR 70 65 60 –60 SECOND HARMONIC –80 CROSSTALK –100 02640-004 THIRD HARMONIC 55 50 40 45 50 55 60 65 ADC SAMPLE RATE (MSPS) –120 0 5 10 15 20 25 30 FREQUENCY (MHz) Figure 4. Single-Tone FFT of Channel A Digitizing fIN = 12.5 MHz While Channel B Is Digitizing fIN = 10 MHz 0 Figure 7. AD9238-65 Single-Tone SNR/SFDR vs. FS with fIN = 32.5 MHz 100 95 –20 90 85 SFDR SNR SFDR/SNR (dBc) –40 80 75 SNR SNR 70 65 60 –60 SECOND HARMONIC CROSSTALK dB –80 –100 02640-005 55 50 20 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) 25 30 ADC SAMPLE RATE (MSPS) 35 40 Figure 5. Single-Tone FFT of Channel A Digitizing fIN = 70 MHz While Channel B Is Digitizing fIN = 76 MHz 0 Figure 8. AD9238-40 Single-Tone SNR/SFDR vs. FS with fIN = 20 MHz 100 95 –20 90 SFDR 85 SFDR/SNR (dBc) –40 CROSSTALK –60 SECOND HARMONIC dB 80 75 SNR 70 65 60 –80 –100 02640-006 55 50 0 5 10 ADC SAMPLE RATE (MSPS) 15 20 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) Figure 6. Single-Tone FFT of Channel A Digitizing fIN = 120 MHz While Channel B is Digitizing fIN = 126 MHz Figure 9. AD9238-20 Single-Tone SNR/SFDR vs. FS with fIN = 10 MHz Rev. B | Page 11 of 48 02640-009 02640-008 02640-007 AD9238 100 95 90 SFDR SNR 90 SFDR/SNR (dBc) SFDR/SNR (dBc) 80 85 SNR SFDR 80 70 SNR 60 75 50 02640-010 70 40 –35 65 0 20 40 60 80 100 120 140 INPUT FREQUENCY (MHz) –30 –25 –20 –15 –10 –5 0 INPUT AMPLITUDE (dBFS) Figure 10. AD9238-65 Single-Tone SNR/SFDR vs. AIN with fIN = 32.5 MHz Figure 13. AD9238-65 Single-Tone SNR/SFDR vs. fIN 100 95 90 90 SNR SFDR SFDR/SNR (dBc) 70 SFDR/SNR (dBc) 80 SNR SFDR 85 80 60 SNR 75 SNR 50 02640-011 70 02640-014 40 –35 65 0 20 40 60 80 100 120 140 INPUT FREQUENCY (MHz) –30 –25 –20 –15 –10 –5 0 INPUT AMPLITUDE (dBFS) Figure 11. AD9238-40 Single-Tone SNR/SFDR vs. AIN with fIN = 20 MHz Figure 14. AD9238-40 Single-Tone SNR/SFDR vs. fIN 100 95 90 SNR SFDR 90 SFDR SNR SFDR/SNR (dBc) 70 SNR SFDR/SNR (dBc) 80 85 80 60 75 SNR 50 02640-012 70 02640-015 40 –35 65 0 20 40 60 80 100 120 140 INPUT FREQUENCY (MHz) –30 –25 –20 –15 –10 –5 0 INPUT AMPLITUDE (dBFS) Figure 12. AD9238-20 Single-Tone SNR/SFDR vs. AIN with fIN = 10 MHz Figure 15. AD9238-20 Single-Tone SNR/SFDR vs. fIN Rev. B | Page 12 of 48 02640-013 SNR AD9238 0 100 SNR SFDR –20 95 90 MAGNITUDE (dBFS) –40 SFDR/SNR (dBFS) 85 80 75 70 –60 –80 SNR 02640-019 –100 02640-016 65 60 –24 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) –21 –18 –15 –12 –9 –6 INPUT AMPLITUDE (dBFS) Figure 16. Dual-Tone FFT with fIN1 = 45 MHz and fIN2 = 46 MHz Figure 19. Dual-Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz 0 100 95 90 SNR SFDR –20 MAGNITUDE (dBFS) SFDR/SNR (dBFS) –40 85 80 75 SNR 70 –60 –80 –100 02640-017 02640-020 65 60 –24 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) –21 –18 –15 –12 –9 –6 INPUT AMPLITUDE (dBFS) Figure 17. Dual-Tone FFT with fIN1 = 70 MHz and fIN2 = 71 MHz Figure 20. Dual-Tone SNR/SFDR vs. AIN with fIN1 = 70 MHz and fIN2 = 71 MHz 0 100 95 90 –20 MAGNITUDE (dBFS) SNR SFDR SFDR/SNR (dBFS) –40 85 80 75 SNR 70 –60 –80 –100 02640-018 02640-021 65 60 –24 –120 0 5 10 15 20 25 30 FREQUENCY (MHz) –21 –18 –15 –12 –9 –6 INPUT AMPLITUDE (dBFS) Figure 18. Dual-Tone FFT with fIN1 = 200 MHz and fIN2 = 201 MHz Figure 21. Dual-Tone SNR/SFDR vs. AIN with fIN1 = 200 MHz and fIN2 = 201 MHz Rev. B | Page 13 of 48 AD9238 74 12.0 600 –65 72 SINAD (dBc) AVDD POWER (mW) 500 400 –40 300 11.5 SINAD –20 70 200 02640-022 –20 02640-025 SINAD –40 68 0 20 40 CLOCK FREQUENCY SINAD –65 11.0 60 100 0 10 20 30 40 50 60 SAMPLE RATE (MSPS) Figure 22. SINAD vs. FS with Nyquist Input Figure 25. Analog Power Consumption vs. FS 95 DCS ON (SFDR) 90 85 DCS OFF (SFDR) 1.0 0.8 0.6 0.4 INL (LSB) 02640-023 SINAD/SFDR (dBc) 80 DCS ON (SINAD) 75 70 65 DCS OFF (SINAD) 60 55 50 30 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 1500 2000 CODE 2500 3000 3500 4000 02640-026 35 40 45 50 55 60 65 DUTY CYCLE (%) Figure 23. SINAD/SFDR vs. Clock Duty Cycle Figure 26. AD9238-65 Typical INL 84 82 80 SFDR 1.0 0.8 0.6 0.4 SINAD/SFDR (dB) 78 76 74 72 DNL (LSB) SINAD 02640-024 0.2 0 –0.2 –0.4 70 68 66 –50 –0.6 –0.8 –1.0 0 500 1000 1500 2000 CODE 2500 3000 3500 4000 02640-027 0 50 100 TEMPERATURE (°C) Figure 24. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz Figure 27. AD9238-65 Typical DNL Rev. B | Page 14 of 48 AD9238 EQUIVALENT CIRCUITS AVDD AVDD VIN+_A, VIN–_A, VIN+_B, VIN–_B CLK_A, CLK_B DCS, DFS, MUX_SELECT, SHARED_REF 02640-064 02640-062 Figure 28. Equivalent Analog Input Circuit DRVDD Figure 30. Equivalent Digital Input Circuit Figure 29. Equivalent Digital Output Circuit 02640-063 Rev. B | Page 15 of 48 AD9238 THEORY OF OPERATION The AD9238 consists of two high performance ADCs that are based on the AD9235 converter core. The dual ADC paths are independent, except for a shared internal band gap reference source, VREF. Each of the ADC paths consists of a proprietar y front end SHA followed by a pipelined switched-capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4-bit first stage, followed by eight 1.5-bit stages, and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined through the digital correction logic block into a final 12-bit result. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the respective clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC and a residual multiplier to drive the next stage of the pipeline. The residual multiplier uses the flash ADC output to control a switched-capacitor digital-to-analog converter (DAC) of the same resolution. The DAC output is subtracted from the stage’s input signal and the residual is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called a multiplying DAC (MDAC). One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be configured as ac- or dc-coupled in differential or single-ended modes. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. In IF undersampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. H T 5pF VIN+ CPAR T T 5pF VIN– CPAR T 02640-065 H Figure 31. Switched-Capacitor Input An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as: REFT = ½(AVDD + VREF) REFB = ½ (AVDD + VREF) Span = 2 × (REFT − REFB) = 2 × VREF The equations above show that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9238 set to the largest input span of 2 V p-p. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode. The SHA may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as: VCMMIN = VREF/2 VCMMAX = (AVDD + VREF)/2 ANALOG INPUT The analog input to the AD9238 is a differential, switchedcapacitor, SHA that has been designed for optimum performance while processing a differential input signal. The SHA input accepts inputs over a wide common-mode range. An input common-mode voltage of midsupply is recommended to maintain optimal performance. The SHA input is a differential, switched-capacitor circuit. In Figure 31, the clock signal alternatively switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. Also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependant on the application. Rev. B | Page 16 of 48 AD9238 The minimum common-mode input level allows the AD9238 to accommodate ground-referenced inputs. Although optimum performance is achieved with a differential input, a singleended source may be driven into VIN+ or VIN−. In this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal may be applied to VIN+, while a 1 V reference is applied to VIN−. The AD9238 then accepts an input signal var ying between 2 V and 0 V. In the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies and in the lower speed grade models (AD9238-40 and AD9238-20). CLOCK INPUT AND CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9238 provides separate clock inputs for each channel. The optimum performance is achieved with the clocks operated at the same frequency and phase. Clocking the channels asynchronously may degrade performance significantly. In some applications, it is desirable to skew the clock timing of adjacent channels. The AD9238’s separate clock inputs allow for clock timing skew (typically ±1 ns) between the channels without significant performance degradation. The AD9238 contains two clock duty cycle stabilizers, one for each converter, that retime the nonsampling edge, providing an internal clock with a nominal 50% duty cycle. When proper track-and-hold times for the converter are required to maintain high performance, maintaining a 50% duty cycle clock is particularly important in high speed applications. It may be difficult to maintain a tightly controlled duty cycle on the input clock on the PCB (see Figure 23). DCS can be enabled by tying the DCS pin high. The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 2 µs to 3 µs to allow the DLL to acquire and settle to the new rate. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated as ⎡ 1 SNR = 20 × log ⎢ ⎢ 2 × π × f INPUT × t j ⎣ Differential Input Configurations As previously detailed, optimum performance is achieved while driving the AD9238 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9238. This is especially true in IF under-sampling applications where frequencies in the 70 MHz to 200 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration, as shown in Figure 32. AVDD VINA 2V p-p 49.9Ω 10pF 50Ω VINB 10pF 1kΩ 0.1µF 1kΩ AGND 50Ω AD9238 ( ) ⎤ ⎥ ⎥ ⎦ 02640-032 Figure 32. Differential Transformer Coupling The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. In the equation, the rms aperture jitter, tJ, represents the rootsum square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. For optimal performance, especially in cases where aperture jitter may affect the dynamic range of the AD9238, it is important to minimize input clock jitter. The clock input circuitr y should use stable references; for example, use analog power and ground planes to generate the valid high and low digital levels for the AD9238 clock input. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, cr ystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source Single-Ended Input Configuration A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance. Rev. B | Page 17 of 48 AD9238 (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. discharged 0.1 µF and 10 µF decoupling capacitors on REFT and REFB. A single channel can be powered down for moderate power savings. The powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain powered on. Because the buffer and voltage reference remain powered on, the wake-up time is reduced to several clock cycles. POWER DISSIPATION AND STANDBY MODE The power dissipated by the AD9238 is proportional to its sampling rates. The digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by IDRVDD = VDRVDD × CLOAD × fCLOCK × N where N is the number of bits changing, and CLOAD is the average load on the digital pins that changed. The analog circuitr y is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates that increases with clock frequency. Either channel of the AD9238 can be placed into standby mode independently by asserting the PDWN_A or PDWN_B pins. It is recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which results in a typical power consumption of 1 mW for the ADC. Note that if DCS is enabled, it is mandator y to disable the clock of an independently powered-down channel. Other wise, significant distortion results on the active channel. If the clock inputs remain active while in total standby mode, typical power dissipation of 12 mW results. The minimum standby power is achieved when both channels are placed into full power-down mode (PDWN_A = PDWN_B = HI). Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and to the duration of the power-down. Typically, it takes approximately 5 ms to restore full operation with fully A–1 A0 A1 A2 DIGITAL OUTPUTS The AD9238 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. The data format can be selected for either offset binary or twos complement. See the Data Format section for more information. TIMING The AD9238 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram. The internal duty cycle stabilizer can be enabled on the AD9238 using the DCS pin. This provides a stable 50% duty cycle to internal circuits. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9238. These transients can detract from the converter’s dynamic performance. The lowest typical conversion rate of the AD9238 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance may degrade. A8 A7 A4 A5 A6 ANALOG INPUT ADC A A3 B–1 B0 B1 B2 B8 B3 B4 B5 B7 B6 ANALOG INPUT ADC B CLK_A = CLK_B = MUX_SELECT B–8 A–7 B–7 A–6 B–6 A–5 B–5 A–4 B–4 A–3 B–3 A–2 B–2 A–1 B–1 A0 B0 A1 D0_A TO D11_A 02640-066 tPD tPD Figure 33. Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT Rev. B | Page 18 of 48 AD9238 DATA FORMAT The AD9238 data output format can be configured for either twos complement or offset binar y. This is controlled by the data format select pin (DFS). Connecting DFS to AGND produces offset binar y output data. Conversely, connecting DFS to AVDD formats the output data as twos complement. The output data from the dual ADCs can be multiplexed onto a single 12-bit output bus. The multiplexing is accomplished by toggling the MUX_SELECT bit, which directs channel data to the same or opposite channel data port. When MUX_SELECT is logic high, the Channel A data is directed to the Channel A output bus, and the Channel B data is directed to the Channel B output bus. When MUX_SELECT is logic low, the channel data is reversed, that is the Channel A data is directed to the Channel B output bus, and the Channel B data is directed to the Channel A output bus. By toggling the MUX_SELECT bit, multiplexed data is available on either of the output data ports. If the ADCs run with synchronized timing, this same clock can be applied to the MUX_SELECT pin. Any skew between CLK_A, CLK_B, and MUX_SELECT can degrade ac performance. It is recommended to keep the clock skew