AD9245BCP-80EB

14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter AD9245 FEATURES Single 3 V supply operation (2.7 V to 3.6 V) SNR = 72.7 dBc to Nyquist SFDR = 83.0 dBc to Nyquist Low power 366 mW at 80 MSPS 300 mW at 65 MSPS 165 mW at 40 MSPS 90 mW at 20 MSPS Differential input with 500 MHz bandwidth On-chip reference and sample-and-hold DNL = ±0.5 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary or twos complement data format Clock duty-cycle stabilizer FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD AD9245 VIN+ SHA VIN– 4 REFT REFB CORRECTION LOGIC 14 OUTPUT BUFFERS D13 (MSB) VREF D0 (LSB) SENSE REF SELECT 0.5V CLOCK DUTY CYCLE STABILIZER MODE SELECT 03583-001 MDAC1 8-STAGE 1 1/2-BIT PIPELINE 16 A/D 3 A/D OTR APPLICATIONS Medical imaging equipment IF sampling in communications receivers WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA Battery-powered instruments Hand-held scopemeters Spectrum analyzers Power-sensitive military applications AGND CLK PDWN MODE DGND Figure 1. GENERAL DESCRIPTION The AD9245 is a monolithic, single 3 V supply, 14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital converter (ADC) featuring a high performance sample-andhold amplifier (SHA) and voltage reference. The AD9245 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy and guarantee no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and common modes, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available analog-to-digital converters, the AD9245 is suitable for applications in communications, imaging, and medical ultrasound. A single-ended clock input is used to control all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in straight binary or twos complement formats. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9245 is available in a 32-lead LFCSP and is specified over the industrial temperature range (–40°C to +85°C). PRODUCT HIGHLIGHTS 1. The AD9245 operates from a single 3 V power supply and features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families. 2. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz and can be configured for single-ended or differential operation. 3. The AD9245 is pin-compatible with the AD9215, AD9235, and AD9236. This allows a simplified migration from 10 bits to 14 bits and 20 MSPS to 80 MSPS. 4. The clock DCS maintains overall ADC performance over a wide range of clock pulse widths. 5. The OTR output bit indicates when the signal is beyond the selected input range. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. AD9245 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 7 Switching Specifications .............................................................. 8 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution.................................................................................. 9 Terminology .................................................................................... 10 Pin Configuration and Function Descriptions........................... 11 Equivalent Circuits ......................................................................... 12 Typical Performance Characteristics ........................................... 13 Theory of Operation ...................................................................... 18 Analog Input and Reference Overview ................................... 18 Clock Input Considerations...................................................... 19 Jitter Considerations .................................................................. 20 Power Dissipation and Standby Mode .................................... 20 Digital Outputs ........................................................................... 20 Timing ......................................................................................... 21 Voltage Reference ....................................................................... 21 Internal Reference Connection ................................................ 21 External Reference Operation .................................................. 22 Operational Mode Selection ..................................................... 22 Evaluation Board ........................................................................ 22 Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 29 REVISION HISTORY 1/06—Rev. C to Rev. D Changes to Differential Input Configurations Section and Figure 40 .......................................................................................... 19 Changes to Internal Reference Connection Section .................. 21 Changes to Figure 49...................................................................... 23 Changes to Figure 50...................................................................... 24 Changes to Table 12........................................................................ 28 Updated Outline Dimensions ....................................................... 29 Changes to Ordering Guide .......................................................... 29 8/05—Rev. B to Rev. C Updated Format..................................................................Universal Changes to Features, Applications, General Description, and Product Highlights ........................................................................... 1 Added Table 1; Renumbered Sequentially .................................... 3 Changes to Table 2............................................................................ 4 Added Table 3; Renumbered Sequentially .................................... 5 Changes to Table 4............................................................................ 6 Changes to Table 5............................................................................ 7 Changes to Table 6............................................................................ 8 Deleted Explanation of Test Levels Table ...................................... 8 Added Figure 26 to Figure 31; Renumbered Sequentially ........ 16 Added Figure 32 to Figure 37; Renumbered Sequentially ........ 17 Changes to Figure 39...................................................................... 18 Changes to Clock Input Consideration Section......................... 19 Changes to Figure 44...................................................................... 20 Changes to Table 10 ....................................................................... 21 Changes to Figure 51...................................................................... 25 Changes to Table 12 ....................................................................... 28 Changes to Ordering Guide .......................................................... 29 Updated Outline Dimensions....................................................... 29 10/03—Rev. A to Rev. B Changes to Figure 33...................................................................... 17 5/03—Rev. 0 to Rev. A Changes to Figure 30...................................................................... 15 Changes to Figure 37...................................................................... 19 Changes to Figure 38...................................................................... 20 Changes to Figure 39...................................................................... 21 Changes to Table 10 ....................................................................... 24 Changes to the Ordering Guide ................................................... 25 Rev. D | Page 2 of 32 AD9245 SPECIFICATIONS DC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Guaranteed Offset Error Gain Error 1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT1 Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA INPUT REFERRED NOISE VREF = 0.5 V VREF = 1.0 V ANALOG INPUT Input Span, VREF = 0.5 V Input Span, VREF = 1.0 V Input Capacitance 3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD2 IDRVDD2 PSRR POWER CONSUMPTION DC Input 4 Sine Wave Input2 Standby Power 5 1 2 Min 14 14 AD9245BCP-20 Typ Max Min 14 14 AD9245BCP-40 Typ Max Min 14 14 AD9245BCP-65 Typ Max Unit Bits Bits % FSR % FSR LSB LSB ppm/°C ppm/°C ±0.30 ±0.30 ±0.50 ±1.20 ±2 ±12 ±5 0.8 ±2.5 0.1 2.28 1.08 1 2 7 7 ±1.60 ±3.25 ±1.00 ±3.10 ±0.50 ±0.50 ±0.50 ±1.40 ±2 ±12 ±1.75 ±3.25 ±1.00 ±3.40 ±0.50 ±0.50 ±0.50 ±1.60 ±3 ±12 ±1.75 ±6.90 ±1.00 ±5.55 ±35 ±5 0.8 ±2.5 0.1 2.28 1.08 1 2 7 7 ±35 ±5 0.8 ±2.5 0.1 2.28 1.08 1 2 7 7 ±35 mV mV mV mV LSB rms LSB rms V p-p V p-p pF kΩ 2.7 2.25 3.0 3.0 30 2 ±0.01 90 95 1.0 3.6 3.6 2.7 2.25 3.0 3.0 55 5 ±0.01 165 180 1.0 3.6 3.6 2.7 2.25 3.0 3.0 100 7 ±0.01 300 320 1.0 3.6 3.6 V V mA mA % FSR mW mW mW 120 220 375 Gain errors and gain temperature coefficients are based on the ADC only (with a fixed 1.0 V external reference). Measured at maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Measured with dc input at maximum clock rate. 5 Standby power is measured with a dc input, the CLK pin inactive (that is, set to AVDD or AGND). Rev. D | Page 3 of 32 AD9245 AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted. Table 2. AD9245BCP-80 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error 1 Gain Error Gain Error1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 TEMPERATURE DRIFT Offset Error1 Gain Error Gain Error1 INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA Output Voltage Error (0.5 V Mode) Load Regulation @ 0.5 mA INPUT REFERRED NOISE VREF = 0.5 V VREF = 1.0 V ANALOG INPUT Input Span, VREF = 0.5 V Input Span, VREF = 1.0 V Input Capacitance 3 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD2 IDRVDD2 PSRR POWER CONSUMPTION Low Frequency Input 4 Standby Power 5 1 2 Min 14 Typ Max Unit Bits Guaranteed ±0.30 ±0.28 ±0.70 ±0.5 ±1.4 ±10 ±12 ±17 ±3 ±2 ±6 ±1 1.86 1.17 1 2 7 7 ±1.2 ±4.16 ±1.0 ±5.15 % FSR % FSR % FSR LSB LSB ppm/°C ppm/°C ppm/°C ±34 mV mV mV mV LSB rms LSB rms V p-p V p-p pF kΩ 2.7 2.25 3.0 2.5 122 9 ±0.01 366 1.0 3.6 3.6 138 V V mA mA % FSR mW mW With a 1.0 V internal reference. Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 4 for the equivalent analog input structure. 4 Measured at ac specification conditions without output drivers. 5 Standby power is measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND). Rev. D | Page 4 of 32 AD9245 AC SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, DCS off, unless otherwise noted. Table 3. Parameter SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD) fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz EFFECTIVE NUMBER OF BITS (ENOB) fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz WORST HARMONIC (SECOND OR THIRD) fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fINPUT = 2.4 MHz fINPUT = 9.7 MHz fINPUT = 19.6 MHz fINPUT = 32.5 MHz fINPUT = 100 MHz AD9245BCP-20 Min Typ Max 73.5 73.3 70.5 70.8 73.4 73.2 70.0 69.5 11.9 11.8 11.7 –89 –80 –89 –80 –83 92.0 89.0 80.0 84.0 92.0 89.0 74.0 85.0 83.0 80.5 92.0 –74 AD9245BCP-40 Min Typ Max 73.5 73.4 70.3 71.3 73.4 73.2 68.4 69.1 72.6 67.9 72.7 70.2 73.0 AD9245BCP-65 Min Typ Max 73.1 Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc 70.6 69.4 80.0 Rev. D | Page 5 of 32 AD9245 AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, AIN = –0.5 dBFS, DCS off, unless otherwise noted. Table 4. Parameter SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 40 MHz fIN = 70 MHz fIN = 100 MHz Min 71.1 70.5 AD9245BCP-80 Typ Max 73.3 72.7 71.7 70.2 73.2 72.5 71.2 69.6 11.9 11.8 11.5 11.3 −92.8 –87.6 −81.6 –79.0 76.5 75.7 92.8 87.6 81.6 79.0 –76.5 –75.7 Unit dB dB dB dB dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc 70.7 69.9 11.5 11.3 Rev. D | Page 6 of 32 AD9245 DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, 1.0 V internal reference, unless otherwise noted. Table 5. Parameter LOGIC INPUTS (CLK, PDWN) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance DIGITAL OUTPUT BITS (D0 to D13, OTR) 2 DRVDD = 3.3 V High Level Output Voltage (IOH = 50 μA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOH = 1.6 mA) Low Level Output Voltage (IOH = 50 μA) DRVDD = 2.5 V High Level Output Voltage (IOH = 50 μA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOH = 1.6 mA) Low Level Output Voltage (IOH = 50 μA) 1 2 AD9245BCP-20/AD9245BCP-40/AD9245BCP-65/AD9245BCP-80 1 Min Typ Max 2.0 –10 –10 2 0.8 +10 +10 Unit V V μA μA pF 3.29 3.25 0.2 0.05 2.49 2.45 0.2 0.05 V V V V V V V V AD9245BCP-80 performance measured with 1.0 V external reference. Output voltage levels measured with 5 pF load on each output. Rev. D | Page 7 of 32 AD9245 SWITCHING SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted. Table 6. Parameter CLOCK INPUT PARAMETERS Maximum Conversion Rate Minimum Conversion Rate CLK Period CLK Pulse Width High 1 CLK Pulse Width Low1 DATA OUTPUT PARAMETERS Output Delay 2 (tPD) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty Jitter (tJ) Wake-Up Time 3 OUT-OF-RANGE RECOVERY TIME 1 AD9245BCP-20 Min Typ Max 20 1 50.0 15.0 15.0 3.5 7 1.0 0.5 3.0 1 AD9245BCP-40 Min Typ Max 40 1 25.0 8.8 8.8 3.5 7 1.0 0.5 3.0 1 AD9245BCP-65 Min Typ Max 65 1 15.4 6.2 6.2 3.5 7 1.0 0.5 3.0 2 AD9245BCP-80 Min Typ Max 80 1 12.5 4.6 4.6 4.2 7 1.0 0.3 7.0 2 Unit MSPS MSPS ns ns ns ns Cycles ns ps rms ms Cycles For the AD9245BCP-65 and AD9245BCP-80 models only, with duty cycle stabilizer enabled. DCS function not applicable for AD9245BCP-20 and AD9245BCP-40 models. 2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB. N N–1 ANALOG INPUT N+1 N+2 N+8 N+3 N+4 N+5 N+6 N+7 tA CLK DATA OUT tPD = 6.0ns MAX 2.0ns MIN Figure 2. Timing Diagram Rev. D | Page 8 of 32 03583-002 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N AD9245 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter With Respect to ELECTRICAL AVDD AGND DRVDD DGND AGND DGND AVDD DRVDD D0 to D13 DGND CLK, MODE AGND VIN+, VIN– AGND VREF AGND SENSE AGND REFT, REFB AGND PDWN AGND ENVIRONMENTAL Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Min –0.3 –0.3 –0.3 –3.9 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –65 –40 Max +3.9 +3.9 +0.3 +3.9 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +125 +85 300 150 Unit V V V V V V V V V V V °C °C °C °C THERMAL RESISTANCE θJA is specified for the worst-case conditions on a 4-layer board in still air, in accordance with EIA/JESD51-1. Table 8. Thermal Resistance Package Type 32-Lead LFCSP θJA 32.5 θJC 32.71 Unit °C/W Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 9 of 32 AD9245 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay (tA) The delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter, tJ) The sample-to-sample variation in aperture delay. Integral Nonlinearity (INL) The deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16,384 codes must be present over all operating ranges. Offset Error The major carry transition should occur for an analog value ½ LSB below VIN+ = VIN–. Offset error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value ½ LSB above negative full scale. The last transition should occur at an analog value 1½ LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Temperature Drift The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value at TMIN or TMAX. Power Supply Rejection Ratio The change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Total Harmonic Distortion (THD) 1 The ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. Signal-to-Noise and Distortion (SINAD)1 The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: ENOB = (SINAD − 1.76 ) 6.02 Signal-to-Noise Ratio (SNR)1 The ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. Spurious-Free Dynamic Range (SFDR)1 The difference in dB between the rms input signal amplitude and the peak spurious signal. The peak spurious component may or may not be a harmonic. Two-Tone SFDR1 The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. Clock Pulse Width and Duty Cycle Pulse width high is the minimum amount of time that the clock pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse should be left in the Logic 0 state. At a given clock rate, these specifications define an acceptable clock duty cycle. Minimum Conversion Rate The clock rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The clock rate at which parametric testing is performed. Output Propagation Delay (tPD) The delay between the clock rising edge and the time when all bits are within valid logic levels. Out-of-Range Recovery Time The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. 1 AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. D | Page 10 of 32 AD9245 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 31 AGND 28 AGND 32 AVDD 27 AVDD 25 REFB 24 VREF 23 SENSE 22 MODE 21 OTR 20 D13 (MSB) 19 D12 18 D11 17 D10 DNC 1 CLK 2 DNC 3 PDWN 4 (LSB) D0 5 D1 6 D2 7 D3 8 AD9245 CSP TOP VIEW (Not to Scale) D5 10 D6 11 D7 12 D8 13 D9 14 DGND 15 26 REFT 29 VIN+ 30 VIN– DRVDD 16 D4 9 Figure 3. LFCSP Pin Configuration Table 9. Pin Function Descriptions Pin No. 1, 3 2 4 5 to 14, 17 to 20 15 16 21 22 23 24 25 26 27, 32 28, 31 29 30 Mnemonic DNC CLK PDWN D0 (LSB) to D13 (MSB) DGND DRVDD OTR MODE SENSE VREF REFB REFT AVDD AGND VIN+ VIN– Description Do Not Connect Clock Input Pin Power-Down Function Select Data Output Bits Digital Output Ground Digital Output Driver Supply Out-of-Range Indicator Data Format Select and DCS Mode Selection (See Table 11) Reference Mode Selection (See Table 10) Voltage Reference Input/Output Differential Reference (–) Differential Reference (+) Analog Power Supply Analog Ground Analog Input Pin (+) Analog Input Pin (–) Rev. D | Page 11 of 32 03583-022 AD9245 EQUIVALENT CIRCUITS AVDD DRVDD VIN+, VIN– 03583-003 D13-D0, OTR 03583-005 Figure 4. Equivalent Analog Input Circuit Figure 6. Equivalent Digital Output Circuit AVDD AVDD MODE 03583-004 CLK, PDWN 03583-006 20kΩ Figure 5. Equivalent MODE Input Circuit Figure 7. Equivalent Digital Input Circuit Rev. D | Page 12 of 32 AD9245 TYPICAL PERFORMANCE CHARACTERISTICS DUT = AD9245-80, AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, DCS disabled, TA = 25°C, 2 V p-p differential input, AIN = −0.5 dBFS, VREF = 1.0 V external, unless otherwise noted. 0 –10 –20 –30 AMPLITUDE (dBFS) AIN = –0.5dBFS SNR = 73.2dBc ENOB = 11.8 BITS SFDR = 92.8dBc 100 SFDR (dBFS) 90 SFDR (dBc) SNR/SFDR (dBc AND dBFS) –40 –50 –60 –70 –80 –90 –100 03583-032 80 SNR (dBFS) 70 SFDR = 90dBc REFERENCE LINE 60 SNR (dBc) 50 03583-033 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 40 –30 –25 –20 –15 –10 INPUT AMPLITUDE (dBFS) –5 0 Figure 8. Single Tone 8K FFT @ 2.5 MHz 0 –10 –20 –30 AMPLITUDE (dBFS) Figure 11. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz 100 SFDR (dBFS) AIN = –0.5dBFS SNR = 72.7dBc ENOB = 11.8 BITS SFDR = 87.6dBc 90 SFDR (dBc) SNR/SFDR (dBc AND dBFS) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 03583-023 80 SNR (dBFS) 70 SFDR = 90dBc REFERENCE LINE 60 SNR (dBc) 50 03583-034 40 40 –30 –25 –20 –15 –10 INPUT AMPLITUDE (dBFS) –5 0 Figure 9. Single Tone 8K FFT @ 39 MHz 0 –10 –20 –30 AMPLITUDE (dBFS) Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz 100 SFDR (DIFF) 90 SFDR (SE) SNR (DIFF) AIN = –0.5dBFS SNR = 71.7dBc ENOB = 11.5 BITS SFDR = 81.6dBc –40 SNR/SFDR (dBc) –50 –60 –70 –80 –90 –100 03583-024 80 70 SNR (SE) 60 03583-025 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 50 0 20 40 60 SAMPLE RATE (MSPS) 80 40 100 Figure 10. Single Tone 8K FFT @ 70 MHz Figure 13. SNR/SFDR vs. Sample Rate @ 40 MHz Rev. D | Page 13 of 32 AD9245 0 –10 –20 –30 AIN = –6.5dBFS SNR = 73.4dBFS SFDR = 86.0dBFS 100 SFDR (dBFS) 90 SFDR (dBc) SNR/SFDR (dBc AND dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 03583-029 80 70 SNR (dBFS) 60 SFDR = 90dBc REFERENCE LINE SNR (dBc) 50 03583-031 40 40 –30 –27 –24 –21 –18 –15 –12 INPUT AMPLITUDE (dBFS) –9 –6 Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 MHz 0 –10 –20 –30 AIN = –6.5dBFS SNR = 72.7dBFS SFDR = 78.8dBFS Figure 17. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz 100 SFDR (dBFS) 90 SFDR (dBc) SNR/SFDR (dBc AND dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 –120 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 03583-030 80 70 SNR (dBFS) 60 SFDR = 90dBc REFERENCE LINE SNR (dBc) 50 03583-027 40 40 –30 –27 –24 –21 –18 –15 INPUT AMPLITUDE (dBFS) –12 –9 –6 Figure 15. Two-Tone 8K FFT @ 69 MHz and 70 MHz 1.5 Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz 1.0 0.8 1.0 0.6 0.4 0.5 DNL (LSB) 03583-026 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 2048 4096 6144 03583-028 INL (LSB) 0 –0.5 –1.0 –1.5 0 2048 4096 6144 8192 CODE 10240 12288 14336 16384 8192 10240 12288 14336 16384 CODE Figure 16. Typical INL Figure 19. Typical DNL Rev. D | Page 14 of 32 AD9245 75 74 73 72 –40°C +25°C 100 95 90 +85°C 70 69 68 67 03583-036 SFDR (dBc) SNR (dBc) 71 85 –40°C 80 +85°C 75 +25°C 66 65 0 25 50 75 INPUT FREQUENCY (MHz) 100 125 70 0 25 50 75 INPUT FREQUENCY (MHz) 100 125 Figure 20. SNR vs. Input Frequency 90 88 86 AMPLITUDE (dBFS) 0 Figure 23. SFDR vs. Input Frequency SFDR (DCS ON) –10 –20 –30 84 SNR/SFDR (dBc) 82 80 78 76 74 72 70 30 SFDR (DCS OFF) –40 –50 –60 –70 –80 –90 SNR (DCS OFF) 03583-037 –100 –110 –120 0 9.6 19.2 FREQUENCY (MHz) 28.8 03583-060 SNR (DCS ON) 35 40 45 50 55 DUTY CYCLE (%) 60 65 70 38.4 Figure 21. SNR/SFDR vs. Clock Duty Cycle 0 –10 –20 –30 Figure 24. Two 32K FFT CDMA-2000 Carriers @ FIN = 46.08 MHz; Sample Rate = 61.44 MSPS 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 03583-059 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 9.6 19.2 FREQUENCY (MHz) 28.8 03583-061 –110 –120 0 9.6 19.2 FREQUENCY (MHz) 28.8 38.4 38.4 Figure 22. 32K FFT WCDMA Carrier @ FIN = 96 MHz; Sample Rate = 76.8 MSPS Figure 25. Two 32K FFT WCDMA Carriers @ FIN = 76.8 MHz; Sample Rate = 61.44 MSPS Rev. D | Page 15 of 32 03583-038 AD9245 0 AIN = –0.5dBFS SNR = 72.7dBc ENOB = 11.7 BITS SFDR = 81.3dBc 0 AIN = –0.5dBFS SNR = 73.4dBc ENOB = 11.9 BITS SFDR = 88.3dBc –20 –20 AMPLITUDE (dBFS) –40 AMPLITUDE (dBFS) 03583-062 –40 –60 –60 –80 –80 –100 –100 03583-065 –120 0 5 10 15 20 FREQUENCY (MHz) 25 30 –120 0 2 4 6 8 10 12 14 FREQUENCY (MHz) 16 18 20 Figure 26. AD9245-65 Single Tone 16K FFT @ 35 MHz 2.0 1.5 1.0 Figure 29. AD9245-40 Single Tone 16K FFT @ 19.7 MHz 1.0 0.8 0.6 0.4 0.5 0 –0.5 –1.0 DNL (LSB) 03583-063 INL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 2048 4096 6144 03583-066 –1.5 –2.0 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE 8192 10240 12288 14336 16384 CODE Figure 27. AD9245-65 Typical INL 2.0 1.5 1.0 0.5 1.0 0.8 0.6 0.4 Figure 30. AD9245-65 Typical DNL INL (LSB) 0 –0.5 –1.0 03583-064 DNL (LSB) 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 2048 4096 6144 03583-067 –1.5 –2.0 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE 8192 10240 12288 14336 16384 CODE Figure 28. AD9245-40 Typical INL Figure 31. AD9245-40 Typical DNL Rev. D | Page 16 of 32 AD9245 2.0 1.5 1.0 0.4 1.0 0.8 0.6 0.5 0 –0.5 –1.0 DNL (LSB) INL (LSB) 0.2 0 –0.2 –0.4 –0.6 –1.5 –2.0 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE –0.8 –1.0 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE Figure 32. AD9245-20 Typical INL 0 AIN = –0.5dBFS SNR = 73.4dBc ENOB = 11.9 BITS SFDR = 95.0dBc 0 Figure 35. AD9245-20 Typical DNL –20 –20 AIN = –0.5dBFS SNR = 73.3dBc ENOB = 11.9 BITS SFDR = 92.6dBc AMPLITUDE (dBFS) –40 AMPLITUDE (dBFS) –40 –60 –60 –80 –80 –100 03583-069 –100 03583-072 –120 0 1 2 3 4 5 6 FREQUENCY (MHz) 7 8 9 10 –120 0 1 2 3 4 5 6 FREQUENCY (MHz) 7 8 9 10 Figure 33. AD9245-20 Single Tone 16K FFT @ 5 MHz 75 –0.5dBFS 70 Figure 36. AD9245-20 Single Tone 16K FFT @ 9.7 MHz 10004707 7996189 –6dBFS 7281624 HITS SINAD (dBc) 65 60 3167101 55 03583-070 1755666 –20dBFS 50 1 10 INPUT FREQUENCY (MHz) 253625 N–3 N–2 N–1 N CODE N+1 N+2 547498 N+3 100 Figure 34. AD9245-20 SINAD vs. Input Frequency Figure 37. AD9245-20 Grounded-Input Histogram Rev. D | Page 17 of 32 03583-073 03583-071 AD9245 THEORY OF OPERATION The AD9245 architecture consists of a front-end sample-andhold amplifier (SHA) followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections consisting of a 4-bit first stage followed by eight 1.5-bit stages, and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be ac-coupled or dc-coupled in differential or single-ended modes. The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. Referring to Figure 39, the clock signal alternately switches the SHA between sample mode and hold mode. When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. In addition, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent upon the application. In IF undersampling applications, any shunt capacitors should be reduced or removed. In combination with the driving source impedance, they would limit the input bandwidth. H T 5pF VIN+ CPAR T T 5pF VIN– CPAR T 03583-012 H ANALOG INPUT AND REFERENCE OVERVIEW The analog input to the AD9245 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA input can support a wide common-mode range (VCM) and maintain excellent performance, as shown in Figure 38. An input common-mode voltage of midsupply minimizes signaldependent errors and provides optimum performance. 100 95 90 85 SFDR (2.5MHz) Figure 39. Switched-Capacitor SHA Input For best dynamic performance, the source impedances driving VIN+ and VIN– should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal differential reference buffer creates positive and negative reference voltages, REFT and REFB, that define the span of the ADC core. The output common mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as: REFT = ½ (AVDD + VREF) REFB = ½ (AVDD − VREF) Span = 2 × (REFT − REFB) = 2 × VREF The previous equations show that the REFT and REFB voltages are symmetrical about the midsupply voltage, and, by definition, the input span is twice the value of the VREF voltage. The internal voltage reference can be pin strapped to fixed values of 0.5 V or 1.0 V, or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9245 set to the largest input span of 2 V p-p. The relative SNR degradation is 3 dB when changing from 2 V p-p mode to 1 V p-p mode. SNR/SFDR (dBc) SFDR (39MHz) 80 75 70 65 60 55 50 0.5 03583-039 SNR (2.5MHz) SNR (39MHz) 1.0 1.5 2.0 COMMON-MODE LEVEL (V) 2.5 3.0 Figure 38. AD9245-80 SNR/SFDR vs. Common-Mode Level Rev. D | Page 18 of 32 AD9245 The SHA can be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as VCM MIN VREF = 2 33Ω 2V p-p 49.9Ω 20pF 33Ω AVDD VIN+ AD9245 VIN– AGND VCM MAX = ( AVDD + VREF ) 2 0.1μF 1kΩ 1kΩ 03583-014 The minimum common-mode input level allows the AD9245 to accommodate ground referenced inputs. Although optimum performance is achieved with a differential input, a single-ended source can be applied to VIN+ or VIN–. In this configuration, one input accepts the signal, while the opposite input is set to midscale by connecting it to an appropriate reference. For example, a 2 V p-p signal can be applied to VIN+ while a 1 V reference is applied to VIN–. The AD9245 then accepts an input signal varying between 2 V and 0 V. In the single-ended configuration, distortion performance can degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies. Figure 41. Differential Transformer-Coupled Configuration The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. Single-Ended Input Configuration A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large input common-mode swing (see Figure 13). However, if the source impedances on each input are matched, there should be little effect on SNR performance. Figure 42 details a typical single-ended input configuration. Differential Input Configurations As previously detailed, optimum performance is achieved while driving the AD9245 in a differential input configuration. For baseband applications, the AD8351 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8351 is easily set to AVDD/2, and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 1.2kΩ 0.1μF 2V p-p 50Ω 25Ω 0.1μF 1kΩ 1kΩ 0.1μF 1kΩ 2V p-p 49.9Ω 0.33μF 1kΩ 1kΩ + 33Ω 20pF 33Ω AVDD VIN+ AD9245 VIN– 03583-015 33Ω 20pF AVDD VIN+ 10μF 0.1μF 1kΩ AGND AD8351 AD9245 VIN– AGND 0.1μF 33Ω 25Ω 03583-013 Figure 42. Single-Ended Input Configuration CLOCK INPUT CONSIDERATIONS Typical high speed ADCs use both clock edges to generate a variety of internal timing signals, and as a result can be sensitive to clock duty cycle. Commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9245-80 and AD9245-65 contain a clock duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9245. As shown in Figure 21, noise and distortion performance is nearly flat for a 30% to 70% duty cycle with the DCS on. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow the DLL to acquire and lock to the new rate. Figure 40. Differential Input Configuration Using the AD8351 At input frequencies in the second Nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the AD9245. This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The value of the shunt capacitor is dependent on the input frequency and source impedance and should be reduced or removed. An example is shown in Figure 41. Rev. D | Page 19 of 32 AD9245 JITTER CONSIDERATIONS High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fINPUT) due only to aperture jitter (tJ) can be calculated with the following equation: SNR = −20log10[2π fINPUT × tj] In the equation, the rms aperture jitter represents the rootmean square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter (see Figure 43). The clock input should be treated as an analog signal in cases where aperture jitter can affect the dynamic range of the AD9245. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. 75 0.2ps 70 MEASURED SNR 0.5ps which is determined by the sample rate and the characteristics of the analog input signal. 450 400 AD9245-80 350 TOTAL POWER (mW) 300 250 200 AD9245-40 150 AD9245-65 50 0 10 20 30 40 50 SAMPLE RATE (MSPS) 60 70 80 Figure 44. AD9245 Power vs. Sample Rate @ 2.5 MHz Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 44 was taken with the same operating conditions as those reported in the Typical Performance Characteristics section, and with a 5 pF load on each output driver. By asserting the PDWN pin high, the AD9245 is placed in standby mode. In this state, the ADC typically dissipates 1 mW if the CLK and analog inputs are static. During standby, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9245 to its normal operational mode. Low power dissipation in standby mode is achieved by shutting down the reference, reference buffer, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering standby mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF and 10 μF decoupling capacitors on REFT and REFB, it takes approximately 1 second to fully discharge the reference buffer decoupling capacitors and 7 ms to restore full operation. 65 SNR (dBc) 60 1.0ps 1.5ps 2.0ps 2.5ps 3.0ps 03583-041 55 50 45 40 1 10 100 INPUT FREQUENCY (MHz) 1000 Figure 43. SNR vs. Input Frequency and Jitter POWER DISSIPATION AND STANDBY MODE As shown in Figure 44, the power dissipated by the AD9245 is proportional to its sample rate. The digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be calculated as I DRVDD = VDRVDD × C LOAD × f CLK × N DIGITAL OUTPUTS The AD9245 output drivers can be configured to interface with 2.5 V or 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies, which can affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts can require external buffers or latches. where N is the number of output bits, 14 in the case of the AD9245. This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency, fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, Rev. D | Page 20 of 32 03583-074 100 AD9245-20 AD9245 As detailed in Table 11, the data format can be selected for either offset binary or twos complement. TIMING The AD9245 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram. The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9245. These transients can degrade the converter’s dynamic performance. The lowest typical conversion rate of the AD9245 is 1 MSPS. At clock rates below 1 MSPS, dynamic performance can degrade. In all reference configurations, REFT and REFB drive the A/D conversion core and establish its input span. The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. VIN+ VIN– REFT ADC CORE 0.1μF 0.1μF REFB VREF 10μF + 0.1μF SELECT LOGIC SENSE 0.5V 0.1μF + 10μF VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD9245. The input range can be adjusted by varying the reference voltage applied to the AD9245 using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in Table 10 and described in the following sections. If the ADC is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage). AD9245 Figure 45. Internal Reference Configuration If the internal reference of the AD9245 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 46 depicts how the internal reference voltage is affected by loading. A 2 mA load is the maximum recommended load. 0.05 INTERNAL REFERENCE CONNECTION A comparator within the AD9245 detects the potential at the SENSE pin and configures the reference into one of four possible states, which are summarized in Table 10. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 45), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected as shown in Figure 47, the switch is again set to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as 0 –0.05 ERROR (%) 0.5V ERROR (%) –0.10 1.0V ERROR (%) –0.15 –0.20 03583-019 R2 ⎞ VREF = 0.5 × ⎛1 + ⎜ ⎟ ⎝ R1 ⎠ –0.25 0 0.5 1.0 1.5 LOAD (mA) 2.0 2.5 03583-017 3.0 Figure 46. VREF Accuracy vs. Load Table 10. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF 0.2 V to VREF AGND to 0.2 V Resulting VREF (V) N/A 0.5 R2 ⎞ (See Figure 47) 0.5 × ⎛ 1 + ⎜ ⎟ R1 ⎠ ⎝ Resulting Differential Span (V p-p) 2 × External Reference 1.0 2 × VREF 2.0 1.0 Rev. D | Page 21 of 32 AD9245 OPERATIONAL MODE SELECTION VIN+ VIN– REFT ADC CORE 0.1μF 0.1μF REFB VREF + 10μF 0.1μF R2 SENSE SELECT LOGIC 0.1μF + 10μF As discussed earlier, the AD9245 can output data in either offset binary or twos complement format. There is also a provision for enabling or disabling the clock DCS. The MODE pin is a multilevel input that controls the data format and DCS state. The input threshold values and corresponding mode selections are outlined in Table 11. Table 11. Mode Selection MODE Voltage AVDD 2/3 AVDD 1/3 AVDD AGND (Default) Data Format Twos Complement Twos Complement Offset Binary Offset Binary Duty Cycle Stabilizer Disabled Enabled Enabled Disabled R1 0.5V AD9245 03583-018 Figure 47. Programmable Reference Configuration EVALUATION BOARD The AD9245 evaluation board provides the support circuitry required to operate the ADC in its various modes and configurations. Complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level. It is critical that signal sources with very low phase noise (