AD9246

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter AD9246 FEATURES 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.4 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Clock duty cycle stabilizer Data output clock Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD AD9246 VIN+ VIN– SHA MDAC1 4 REFT REFB CORRECTION LOGIC 15 OUTPUT BUFFERS VREF SENSE REF SELECT DCO D13 (MSB) D0 (LSB) 0.5V CLOCK DUTY CYCLE STABILIZER MODE SELECT SCLK/DFS SDIO/DCS CSB 05491-001 8-STAGE 1 1/2-BIT PIPELINE 8 A/D 3 A/D OR AGND CLK+ CLK– PDWN DRGND APPLICATIONS Ultrasound equipment IF sampling in communications receivers IS-95, CDMA-One, IMT-2000 Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes Figure 1. GENERAL DESCRIPTION The AD9246 is a monolithic, single 1.8 V supply, 14-bit, 80 MSPS/ 105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and on-chip voltage reference. The product uses a multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9246 is suitable for applications in communications, imaging, and medical ultrasound. A differential clock input controls all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. The digital output data is presented in offset binary, Gray code, or twos complement formats. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. The AD9246 is available in a 48-lead LFCSP_VQ and is specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. The AD9246 operates from a single 1.8 V power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented SHA input maintains excellent performance for input frequencies up to 225 MHz. The clock DCS maintains overall ADC performance over a wide range of clock pulse widths. A standard serial port interface supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the clock DCS, power-down, and voltage reference mode. The AD9246 is pin-compatible with the AD9233, allowing a simple migration from 12 bits to 14 bits. 2. 3. 4. 5. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD9246 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Diagram ........................................................................... 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Equivalent Circuits ......................................................................... 10 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 15 Analog Input Considerations.................................................... 15 Voltage Reference ....................................................................... 17 Clock Input Considerations ...................................................... 18 Jitter Considerations .................................................................. 20 Power Dissipation and Standby Mode..................................... 20 Digital Outputs ........................................................................... 21 Timing ......................................................................................... 22 Serial Port Interface (SPI).............................................................. 23 Configuration Using the SPI..................................................... 23 Hardware Interface..................................................................... 23 Configuration Without the SPI ................................................ 23 Memory Map .................................................................................. 24 Reading the Memory Map Register Table............................... 24 Memory Map Register Table..................................................... 25 Layout Considerations................................................................... 27 Power and Ground Recommendations ................................... 27 CML ............................................................................................. 27 RBIAS........................................................................................... 27 Reference Decoupling................................................................ 27 Evaluation Board ............................................................................ 28 Power Supplies ............................................................................ 28 Input Signals................................................................................ 28 Output Signals ............................................................................ 28 Default Operation and Jumper Selection Settings................. 29 Alternative Clock Configurations............................................ 29 Alternative Analog Input Drive Configuration...................... 29 Schematics................................................................................... 31 Evaluation Board Layouts ......................................................... 36 Bill of Materials........................................................................... 39 Outline Dimensions ....................................................................... 42 Ordering Guide .......................................................................... 42 Rev. A | Page 2 of 44 AD9246 REVISION HISTORY 8/06—Rev. 0 to Rev. A Added 80 MSPS .................................................................. Universal Changes to Features ..........................................................................1 Deleted Figures 19, 20, 22, 23 ........................................................11 Deleted Figures 24, 25, 27 to 29.....................................................12 Deleted Figures 31, 34.....................................................................13 Deleted Figures 37, 38, 40, 41 ........................................................14 Deleted Figure 46 ............................................................................15 Deleted Figure 52 ............................................................................16 Changes to Figure 41 ......................................................................17 Changes to Figure 46 ......................................................................19 Inserted Figure 54 ...........................................................................21 Added Data Clock Output (DCO) Section .................................22 Changes to Table 15 ........................................................................25 Changes to Table 16 ........................................................................39 Changes to the Ordering Guide ....................................................42 4/06—Revision 0: Initial Version Rev. A | Page 3 of 44 AD9246 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL)1 TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 2 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD1 IDRVDD1 (DRVDD = 1.8 V) IDRVDD1 (DRVDD = 3.3 V) POWER CONSUMPTION DC Input Sine Wave Input1 (DRVDD = 1.8 V) Sine Wave Input1 (DRVDD = 3.3 V) Standby Power 3 Power-Down Power 1 2 Temp Full Full Full Full Full 25°C Full 25°C Full Full Full Full 25°C Full Full Full AD9246BCPZ-80 Min Typ Max 14 Guaranteed ±0.3 ±0.5 ±0.6 ±4.7 ±1.0 ±0.4 ±5.0 ±1.5 ±15 ±95 ±5 7 1.3 2 8 6 ±20 AD9246BCPZ-105 Min Typ Max 14 Guaranteed ±0.3 ±0.8 ±0.6 ±5.0 ±1.0 ±0.4 ±5.0 ±1.3 ±15 ±95 ±5 7 1.3 2 8 6 ±35 AD9246BCPZ-125 Min Typ Max 14 Guaranteed ±0.3 ±0.8 ±0.6 ±4.2 ±1.0 ±0.4 ±5.0 ±1.5 ±15 ±95 ±5 7 1.3 2 8 6 ±35 Unit Bits % FSR % FSR LSB LSB LSB LSB ppm/°C ppm/°C mV mV LSB rms V p-p pF kΩ Full Full Full Full Full Full Full Full Full Full 1.7 1.7 1.8 2.5 138 7 12 248 261 288 40 1.8 1.9 3.6 155 1.7 1.7 1.8 2.5 178 9 16 320 337 373 40 1.8 1.9 3.6 194 1.7 1.7 1.8 2.5 220 11 19 395 415 458 40 1.8 1.9 3.6 236 V V mA mA mA mW mW mW mW mW 279 350 425 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure. 3 Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND). Rev. A | Page 4 of 44 AD9246 AC SPECIFICATIONS AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference;AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE-RATIO (SNR) fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz WORST OTHER HARMONIC OR SPUR fIN = 2.4 MHz fIN = 70 MHz fIN = 100 MHz fIN = 170 MHz T WO-TONE SFDR fIN = 29 MHz (−7 dBFS), 32 MHz (−7 dBFS) fIN = 169 MHz (−7 dBFS), 172 MHz (−7 dBFS) ANALOG INPUT BANDWIDTH 1 Temp 25°C 25°C Full 25°C 25°C AD9246BCPZ-80 Min Typ Max 71.9 71.9 70.8 71.6 70.9 AD9246BCPZ-105 Min Typ Max 71.9 71.9 69.5 71.6 70.9 AD9246BCPZ-125 Min Typ Max 71.9 71.7 69.5 71.6 70.8 Unit dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 71.1 71.5 70.4 70.6 69.9 11.7 11.6 11.6 11.5 −90 −85 −76 71.1 70.8 68.5 70.6 69.9 11.7 11.6 11.6 11.5 −90 −85 −73 71.1 70.6 68.5 70.6 69.8 11.7 11.6 11.6 11.5 −90 −85 −73 −85 −83 90 85 73 85 83 −90 −90 −80 dBc dBc dBc dBc dBc Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc MHz −85 −83.5 90 85 76 85 83.5 −90 −90 −85 −85 −83.5 90 85 73 85 83.5 −90 −90 −90 −90 87 83 650 −80 −90 −90 85 84 650 −90 −90 87 83 650 See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Rev. A | Page 5 of 44 AD9246 DIGITAL SPECIFICATIONS AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance Input Capacitance LOGIC INPUTS (SCLK/DFS, OEB, PWDN) High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance Input Capacitance LOGIC INPUTS (CSB) High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance Input Capacitance LOGIC INPUTS (SDIO/DCS) High Level Input Voltage (VIH) Low Level Input Voltage (VIL) High Level Input Current (IIH) Low Level Input Current (IIL) Input Resistance Input Capacitance DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage (VOH, IOH = 50 μA) High Level Output Voltage (VOH , IOH = 0.5 mA) Low Level Output Voltage (VOL, IOL = 1.6 mA) Low Level Output Voltage (VOL, IOL = 50 μA) DRVDD = 1.8 V High Level Output Voltage (VOH, IOH = 50 μA) High Level Output Voltage (VOH, IOH = 0.5 mA) Low Level Output Voltage (VOL, IOL = 1.6 mA) Low Level Output Voltage (VOL, IOL = 50 μA) Temp Min AD9246BCPZ-80/105/125 Typ Max CMOS/LVDS/LVPECL 1.2 6 AVDD + 1.6 AVDD 3.6 0.8 +10 +10 10 12 4 3.6 0.8 −75 +10 30 2 1.2 0 −10 +40 26 2 1.2 0 −10 +40 26 5 DRVDD + 0.3 0.8 +10 +130 3.6 0.8 +10 +135 Unit Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 0.2 AVDD − 0.3 1.1 1.2 0 −10 −10 8 V V p-p V V V V μA μA kΩ pF V V μA μA kΩ pF V V μA μA kΩ pF V V μA μA kΩ pF 1.2 0 −50 −10 Full Full Full Full Full Full Full Full 3.29 3.25 0.2 0.05 1.79 1.75 0.2 0.05 V V V V V V V V Rev. A | Page 6 of 44 AD9246 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted. Table 4. Parameter 1 CLOCK INPUT PARAMETERS Conversion Rate, DCS Enabled Conversion Rate, DCS Disabled CLK Period CLK Pulse Width High, DCS Enabled CLK Pulse Width High, DCS Disabled DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) 2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time 3 OUT-OF-RANGE RECOVERY TIME SERIAL PORT INTERFACE 4 SCLK Period (tCLK) SCLK Pulse Width High Time (tHI) SCLK Pulse Width Low Time (tLO) SDIO to SCLK Setup Time (tDS) SDIO to SCLK Hold Time (tDH) CSB to SCLK Setup Time (tS) CSB to SCLK Hold Time (tH) 1 2 3 Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full AD9246BCPZ-80 Min Typ Max 20 10 12.5 3.75 5.63 3.1 4.9 5.9 80 80 6.25 6.25 3.9 4.4 5.7 6.8 12 0.8 0.1 350 2 8.75 6.88 4.8 AD9246BCPZ-105 Min Typ Max 20 10 9.5 2.85 4.28 3.1 3.4 4.4 105 105 4.75 4.75 3.9 4.4 4.3 5.3 12 0.8 0.1 350 2 6.65 5.23 4.8 AD9246BCPZ-125 Min Typ Max 20 10 8 2.4 3.6 3.1 2.6 3.7 125 125 4 4 3.9 4.4 3.5 4.5 12 0.8 0.1 350 3 5.6 4.4 4.8 Unit MSPS MSPS ns ns ns ns ns ns ns cycles ns ps rms μs Cycles ns ns ns ns ns ns ns 40 16 16 5 2 5 2 40 16 16 5 2 5 2 40 16 16 5 2 5 2 See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB. 4 See Figure 57 and the Serial Port Interface (SPI) section. TIMING DIAGRAM N+1 N N+2 N+3 N+4 tA tCLK N+8 N+5 N+6 N+7 CLK+ CLK– tPD DATA N – 13 N – 12 N – 11 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 tS DCO Figure 2. Timing Diagram Rev. A | Page 7 of 44 05491-002 tH tDCO tCLK AD9246 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DGND AGND to DGND AVDD to DRVDD D0 through D13 to DGND DCO to DGND OR to DGND CLK+ to AGND CLK− to AGND VIN+ to AGND VIN− to AGND VREF to AGND SENSE to AGND REFT to AGND REFB to AGND SDIO/DCS to DGND PDWN to AGND CSB to AGND SCLK/DFS to AGND OEB to AGND ENVIRONMENTAL Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 Sec) Junction Temperature Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +0.3 V −3.9 V to +2.0 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V –65°C to +125°C –40°C to +85°C +300°C +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The exposed paddle must be soldered to the ground plane for the LFCSP_VQ package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 6. Thermal Resistance Package Type 48-lead LFCSP_VQ (CP-48-3) θJA 26.4 θJC 2.4 Unit °C/W Typical θJA and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation effectively reducing θJA. In addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes, reduces the θJA. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 8 of 44 AD9246 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 DRVDD DRGND D1 D0 (LSB) DCO OEB AVDD AGND AVDD CLK– CLK+ AGND D2 D3 1 2 PIN 1 INDICATOR D4 3 D5 4 D6 5 D7 6 DRGND 7 DRVDD 8 D8 9 D9 10 D10 11 D11 12 AD9246 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 PDWN RBIAS CML AVDD AGND VIN– VIN+ AGND REFT REFB VREF SENSE D12 D13 (MSB) OR DRGND DRVDD SDIO/DCS SCLK/DFS CSB AGND AVDD AGND AVDD 13 14 15 16 17 18 19 20 21 22 23 24 Figure 3. Pin Configuration Table 7. Pin Function Description Pin No. 0, 21, 23, 29, 32, 37, 41 45, 46, 1 to 6, 9 to 14 7, 16, 47 8, 17, 48 15 18 19 20 22, 24, 33, 40, 42 25 26 27 28 30 31 34 35 36 38 39 43 44 Mnemonic AGND D0 (LSB) to D13 (MSB) DRGND DRVDD OR SDIO/DCS SCLK/DFS CSB AVDD SENSE VREF REFB REFT VIN+ VIN– CML RBIAS PDWN CLK+ CLK– OEB DCO Description Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.) Data Output Bits. Digital Output Ground. Digital Output Driver Supply (1.8 V to 3.3 V). Out-of-Range Indicator. Serial Port Interface (SPI)® Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Pin Mode). See Table 10. Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). Serial Port Interface Chip Select (Active Low). See Table 10. Analog Power Supply. Reference Mode Selection. See Table 9. Voltage Reference Input/Output. Differential Reference (−). Differential Reference (+). Analog Input Pin (+). Analog Input Pin (−). Common-Mode Level Bias Output. External Bias Resistor Connection. A 10 kΩ resistor must be connected between this pin and analog ground (AGND). Power-Down Function Select. Clock Input (+). Clock Input (−). Output Enable (Active Low). Data Clock Output. Rev. A | Page 9 of 44 05491-003 AD9246 EQUIVALENT CIRCUITS VIN SCLK/DFS OEB PDWN 1kΩ 30kΩ Figure 4. Equivalent Analog Input Circuit AVDD 05491-004 Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit AVDD 1.2V CLK+ 10kΩ 10kΩ CLK– 26kΩ CSB 1kΩ 05491-005 Figure 5. Equivalent Clock Input Circuit DRVDD Figure 9. Equivalent CSB Input Circuit SENSE 1kΩ 1kΩ SDIO/DCS 05491-011 05491-006 Figure 6. Equivalent SDIO/DCS Input Circuit DRVDD Figure 10. Equivalent Sense Circuit AVDD VREF 6kΩ 05491-012 DRGND 05491-007 Figure 7. Equivalent Digital Output Circuit Figure 11. Equivalent VREF Circuit Rev. A | Page 10 of 44 05491-010 05491-008 AD9246 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input; AIN = −1.0 dBFS; 64k sample; TA = 25°C, unless otherwise noted. All figures show typical performance for all speed grades. 0 –20 –40 –60 –80 –100 –120 –140 125MSPS 2.3MHz @ –1dBFS SNR = 71.9dB (72.9dBFS) ENOB = 11.7 BITS SFDR = 90dBc 0 –20 –40 –60 –80 –100 –120 –140 125MSPS 100.3MHz @ –1dBFS SNR = 71.6dBc (72.6dBFS) ENOB = 11.5 BITS SFDR = 85dBc AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 Figure 12. AD9246-125 Single-Tone FFT with fIN = 2.3 MHz 0 –20 –40 –60 –80 –100 –120 –140 125MSPS 30.3MHz @ –1dBFS SNR = 71.9dBc (72.9dBFS) ENOB = 11.6 BITS SFDR = 88.8dBc AMPLITUDE (dBFS) Figure 15. AD9246-125 Single-Tone FFT with fIN = 100.3 MHz 0 –20 –40 –60 –80 –100 –120 –140 125MSPS 140.3MHz @ –1dBFS SNR = 71dB (72dBFS) ENOB = 11.4 BITS SFDR = 85dBc AMPLITUDE (dBFS) 05491-014 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 Figure 13. AD9246-125 Single-Tone FFT with fIN = 30.3 MHz 0 –20 –40 –60 –80 –100 –120 –140 125MSPS 70.3MHz @ –1dBFS SNR = 71.7dB (72.7dBFS) ENOB = 11.5 BITS SFDR = 85dBc AMPLITUDE (dBFS) Figure 16. AD9246-125 Single-Tone FFT with fIN = 140.3 MHz 0 –20 –40 –60 –80 –100 –120 –140 125MSPS 170.3MHz @ –1dBFS SNR = 70.8dB (71.8dBFS) ENOB = 11.4 BITS SFDR = 83.4dBc AMPLITUDE (dBFS) 05491-015 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 Figure 14. AD9246-125 Single-Tone FFT with fIN = 70.3 MHz Figure 17. AD9246-125 Single-Tone FFT with fIN = 170.3 MHz Rev. A | Page 11 of 44 05491-018 05491-017 05491-016 05491-013 AD9246 0 –20 –40 –60 –80 –100 –120 –140 70 SNR/SFDR (dBc) 125MSPS 225.3MHz @ –1dBFS SNR = 70.3dB (71.3dBFS) ENOB = 11.3 BITS SFDR = 80.4dBc 95 SFDR = +25°C 90 SFDR = –40°C AMPLITUDE (dBFS) 85 80 SNR = +85°C 75 SFDR = +85°C SNR = +25°C SNR = –40°C 05491-019 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 0 50 100 150 200 250 INPUT FREQUENCY (MHz) Figure 18. AD9246-125 Single-Tone FFT with fIN = 225.3 MHz 0 –20 –40 Figure 21. AD9246 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 2 V p-p Full Scale 95 SFDR = +85°C 90 125MSPS 300.3MHz @ –1dBFS SNR = 69.3dB (70.3dBFS) ENOB = 11 BITS SFDR = 77.5dBc SNR/SFDR (dBc) AMPLITUDE (dBFS) 85 SFDR = –40°C 80 SFDR = +25°C –60 –80 –100 –120 –140 75 SNR = +85°C 70 SNR = +25°C SNR = –40°C 05491-020 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 0 50 100 150 200 250 INPUT FREQUENCY (MHz) Figure 19. AD9246-125 Single-Tone FFT with fIN = 300.3 MHz 120 SFDR (dBFS) 100 Figure 22. AD9246 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 1 V p-p Full Scale 0 GAIN/OFFSET ERROR (%FSR) SNR/SFDR (dBc and dBFS) –0.25 OFFSET ERROR 80 SNR (dBFS) 60 –0.50 40 SFDR (dBc) 85dB REFERENCE LINE GAIN ERROR –0.75 20 SNR (dBc) 05491-040 –80 –70 –60 –50 –40 –30 –20 –10 0 –20 0 20 40 60 80 INPUT AMPLITUDE (dBFS) TEMPERATURE (°C) Figure 20. AD9246 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 2.4 MHz Figure 23. AD9246 Gain and Offset vs. Temperature Rev. A | Page 12 of 44 05491-035 0 –90 –1.00 –40 05491-023 65 05491-022 65 AD9246 0 –20 –40 –60 –80 –100 –120 –140 125MSPS 29.1MHz @ –7dBFS 32.1MHz @ –7dBFS SFDR = 85dBc (92dBFS) SFDR/IMD3 (dBc and dBFS) 0 –20 SFDR (dBc) AMPLITUDE (dBFS) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 IMD3 (dBFS) 05491-025 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 –78 –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) Figure 24. AD9246-125 Two-Tone FFT with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz 0 –20 –40 –60 –80 –100 –120 –140 Figure 27. AD9246 Two-Tone SFDR/IMD vs. Input Amplitude (AIN) with FIN1 = 29.1 MHz, FIN2 = 32.1 MHz 0 125MSPS 169.1MHz @ –7dBFS 172.1MHz @ –7dBFS SFDR = 84dBc (91dBFS) SFDR/IMD3 (dBc and dBFS) –20 SFDR (dBFS) AMPLITUDE (dBFS) –40 IMD3 (dBFS) –60 –80 SFDR (dBc) –100 IMD3 (dBc) 05491-026 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 –78 –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) Figure 25. AD9246-125 Two-Tone FFT with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz 0 Figure 28. AD9246 Two-Tone SFDR/IMD vs. Input Amplitude (AIN) with FIN1 = 169.1 MHz, FIN2 = 172.11 MHz 0 NPR = 62.9dBc NOTCH @ 18.5MHz NOTCH WIDTH = 3MHz –20 –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –40 –60 –60 –80 –80 –100 –100 0 15.625 31.250 FREQUENCY (MHz) 46.875 62.500 FREQUENCY (MHz) Figure 26. AD9246-125 Two 64k WCDMA Carriers with fIN = 215.04 MHz, fS = 122.88 MSPS Figure 29. AD9246 Noise Power Ratio (NPR) Rev. A | Page 13 of 44 05491-089 0 15.36 30.72 46.08 61.44 05491-085 –120 –120 05491-029 –120 –90 05491-028 –120 –90 AD9246 100 10 1.3 LSB rms 95 SFDR 8 NUMBER OF HITS (1M) SNR/SFDR (dBc) 90 6 85 4 80 75 2 SNR 05491-030 5 25 45 65 85 105 125 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 CLOCK FREQUENCY (MSPS) OUTPUT CODE Figure 30. AD9246 Single-Tone SNR/SFDR vs. Clock Frequency (fS) with fIN = 2.4 MHz 2.0 100 1.5 95 90 SNR/SFDR (dBc) Figure 33. AD9246 Grounded Input Histogram SFDR DCS ON 1.0 INL ERROR (LSB) 0.5 0 –0.5 –1.0 85 80 SFDR DCS OFF SNR DCS ON 75 70 –1.5 65 60 20 SNR DCS OFF 0 2048 4096 6144 8192 10240 12288 14336 16384 05491-024 05491-021 –2.0 40 DUTY CYCLE (%) 60 80 05491-027 OUTPUT CODE Figure 34. AD9246 INL with fIN = 10.3 MHz 0.5 Figure 31. AD9246 SNR/SFDR vs. Duty Cycle with fIN = 10.3 MHz 90 SFDR 85 0.4 0.3 DNL ERROR (LSB) 0.2 0.1 0 –0.1 –0.2 –0.3 SNR/SFDR (dBc) 80 75 SNR 70 0.5 –0.4 05491-031 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 –0.5 0 2048 4096 6144 8192 10240 12288 14336 16384 INPUT COMMON-MODE VOLTAGE (V) OUTPUT CODE Figure 32. AD9246 SNR/SFDR vs. Input Common Mode (VCM) with fIN = 30 MHz Figure 35. AD9246 DNL with fIN = 10.3 MHz Rev. A | Page 14 of 44 05491-084 70 0 AD9246 THEORY OF OPERATION The AD9246 architecture consists of a front-end sample-andhold amplifier (SHA) followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipeline architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power down, the output buffers go into a high impedance state. For more information, see Application Notes AN-742, Frequency Domain Response of Switched-Capacitor ADCs; and AN-827, A Resonant Approach to Interfacing Amplifiers to SwitchedCapacitor ADCs, and the Analog Dialogue article, “TransformerCoupled Front-End for Wideband A/D Converters.” S CH S CS VIN+ CPIN, PAR VIN– CPIN, PAR CH S H CS S Figure 36. Switched Capacitor SHA Input ANALOG INPUT CONSIDERATIONS The analog input to the AD9246 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. The clock signal alternately switches the SHA between sample mode and hold mode (see Figure 36). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a lowpass filter at the ADC input; therefore, the precise values are dependent on the application. In IF undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, these capacitors would limit the input bandwidth. For best dynamic performance, the source impedances driving VIN+ and VIN− should match such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal differential reference buffer creates two reference voltages used to define the input span of the ADC core. The span of the ADC core is set by the buffer to be 2 × VREF. The reference voltages are not available to the user. Two bypass points, REFT and REFB, are brought out for decoupling to reduce the noise contributed by the internal reference buffer. It is recommended that REFT be decoupled to REFB by a 0.1 μF capacitor, as described in the Layout Considerations section. Input Common Mode The analog inputs of the AD9246 are not internally dc-biased. In ac-coupled applications, the user must provide this bias externally. Setting the device such that VCM = 0.55 × AVDD is recommended for optimum performance; however, the device functions over a wider range with reasonable performance (see Figure 32). An on-board, common-mode voltage reference is included in the design and is available from the CML pin. Optimum performance is achieved when the common-mode voltage of the analog input is set by the CML pin voltage (typically 0.55 × AVDD). The CML pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Layout Considerations section. Rev. A | Page 15 of 44 05491-037 AD9246 DIFFERENTIAL INPUT CONFIGURATIONS Optimum performance is achieved by driving the AD9246 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9246 (see Figure 37), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 1V p-p 49.9Ω 499Ω R 499Ω VIN+ C R 499Ω AVDD At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9246. For applications where SNR is a key parameter, transformer coupling is the recommended input. For applications where SFDR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 40). As an alternative to using a transformer-coupled input at frequencies in the second Nyquist zone, the AD8352 differential driver can be used (see Figure 41). In any configuration, the value of the shunt capacitor, C, is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 8 displays recommended values to set the RC network. However, these values are dependent on the input signal and should only be used as a starting guide. Table 8. RC Network Recommended Values Frequency Range (MHz) 0 to 70 70 to 200 200 to 300 >300 R Series (Ω) 33 33 15 15 C Differential (pF) 15 5 5 Open AD8138 0.1µF 523Ω AD9246 05491-038 VIN– CML Figure 37. Differential Input Configuration Using the AD8138 For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 38). The CML voltage can be connected to the center tap of the secondary winding of the transformer to bias the analog input. The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can cause core saturation, which leads to distortion. R VIN+ C R Single-Ended Input Configuration Although not recommended, it is possible to operate the AD9246 in a single-ended input configuration, as long as the input voltage swing is within the AVDD supply. Single-ended operation can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 39 details a typical single-ended input configuration. 2V p-p 49.9Ω AD9246 VIN– CML 0.1µF Figure 38. Differential Transformer-Coupled Configuration 05491-039 10µF AVDD 1kΩ R VIN+ 1V p-p 49.9Ω 0.1µF 1kΩ C R AVDD 1kΩ 10µF 0.1µF 1kΩ AD9246 VIN– 05491-042 Figure 39. Single-Ended Input Configuration Rev. A | Page 16 of 44 AD9246 0.1µF 2V p-p 25Ω PA S S P 0.1µF 25Ω 0.1µF R C 0.1µF R VIN+ AD9246 VIN– CML 05491-080 Figure 40. Differential Double Balun Input Configuration VCC 0.1µF 0.1µF ANALOG INPUT 0Ω 16 1 2 200Ω CD RD RG 3 4 ANALOG INPUT 0.1µF 5 0Ω 14 0.1µF 05491-081 8, 13 11 0.1µF R VIN+ C R AD8352 10 0.1µF 200Ω AD9246 VIN– CML 0.1µF Figure 41. Differential Input Configuration Using the AD8352 Table 9. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF 0.2 V to VREF AGND to 0.2 V Resulting VREF (V) N/A 0.5 Resulting Differential Span (V p-p) 2 × External Reference 1.0 2 × VREF 2.0 R2 ⎞ 0.5 × ⎛1 + ⎟ (see Figure 43) ⎜ ⎝ R1 ⎠ 1.0 VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9246. The input range is adjustable by varying the reference voltage applied to the AD9246, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the following sections. The Reference Decoupling section describes the best practices and requirements for PCB layout of the reference. If a resistor divider is connected external to the chip as shown in Figure 43, the switch sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as R2 ⎞ VREF = 0.5 ⎛1 + ⎜ ⎟ R1 ⎠ ⎝ If the SENSE pin is connected to AVDD, the reference amplifier is disabled, and an external reference voltage can be applied to the VREF pin (see the External Reference Operation section). The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. Internal Reference Connection A comparator within the AD9246 detects the potential at the SENSE pin and configures the reference into four possible states, as summarized in Table 9. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 42), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier input to the SENSE pin, completing the loop and providing a 0.5 V reference output. Rev. A | Page 17 of 44 AD9246 VIN+ VIN– – ADC CORE External Reference Operation REFT – 0.1µF REFB The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 45 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes. 10 VREF 0.1µF 0.1µF SELECT LOGIC REFERENCE VOLTAGE ERROR (mV) 8 VREF = 1V SENSE 0.5V 05491-043 6 VREF = 0.5V AD9246 Figure 42. Internal Reference Configuration 4 2 VIN+ VIN– – REFT –20 0 20 40 60 80 TEMPERATURE (°C) 0.1µF Figure 45. Typical VREF Drift VREF 0.1µF 0.1µF R2 SENSE SELECT LOGIC REFB R1 0.5V 05491-044 When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal resistor divider loads the external reference with an equivalent 6 kΩ load (see Figure 11). In addition, an internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1 V. AD9246 Figure 43. Programmable Reference Configuration CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9246 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ pin and the CLK− pin via a transformer or capacitors. These pins are biased internally (see Figure 5) and require no external bias. If the internal reference of the AD9246 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 44 depicts how the internal reference voltage is affected by loading. 0 VREF = 0.5V Clock Input Options The AD9246 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal used, the jitter of the clock source is of the most concern (see the Jitter Considerations section). Figure 46 shows one preferred method for clocking the AD9246. A low jitter clock source is converted from singleended to a differential signal using an RF transformer. The back-to-back Schottky diodes across the transformer secondary limit clock excursions into the AD9246 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9246, while preserving the fast rise and fall times of the signal, which are critical to a low jitter performance. REFERENCE VOLTAGE ERROR (%) –0.25 VREF = 1V –0.50 –0.75 –1.00 0 0.5 1.0 LOAD CURRENT (mA) 1.5 2.0 Figure 44. VREF Accuracy vs. Load 05491-033 –1.25 Rev. A | Page 18 of 44 05491-036 ADC CORE – 0 –40 AD9246 0.1µF CLOCK INPUT 50Ω MIN-CIRCUITS ADT1–1WT, 1:1Z 0.1µF XFMR 100Ω 0.1µF 0.1µF SCHOTTKY DIODES: HSMS2812 VCC 0.1µF CLOCK INPUT 1kΩ 1kΩ AD951x CMOS DRIVER OPTIONAL 0.1µF 100Ω CLK+ CLK+ ADC AD9246 05491-048 50Ω1 ADC AD9246 CLK– 0.1µF 05491-051 CLK– 39kΩ Figure 46. Transformer Coupled Differential Clock 150Ω RESISTOR IS OPTIONAL Figure 49. Single-Ended 1.8 V CMOS Sample Clock If a low jitter clock source is not available, another option is to ac-couple a differential PECL signal to the sample clock input pins, as shown in Figure 47. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515 family of clock drivers offers excellent jitter performance. VCC CLOCK INPUT 0.1µF 50Ω1 1kΩ 1kΩ 0.1µF AD951x CMOS DRIVER OPTIONAL 0.1µF 100Ω CLK+ ADC AD9246 05491-052 CLK– 0.1µF CLK AD951x 0.1µF PECL DRIVER CLK 50Ω1 150Ω CLOCK INPUT 0.1µF CLK+ 100Ω 0.1µF 240Ω 05491-049 150Ω RESISTOR IS OPTIONAL ADC AD9246 CLK– Figure 50. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9246 contains a duty cycle stabilizer (DCS) that retimes the nonsampling, or falling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9246. Noise and distortion performance are nearly flat for a wide range of duty cycles when the DCS is on, as shown in Figure 31. Jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can change dynamically. This requires a wait time of 1.5 μs to 5 μs after a dynamic clock frequency increase (or decrease) before the DCS loop is relocked to the input signal. During the time period the loop is not locked, the DCS loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. In such an application, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. CLOCK INPUT 50Ω1 240Ω RESISTORS ARE OPTIONAL Figure 47. Differential PECL Sample Clock A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 48. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers offers excellent jitter performance. 0.1µF CLOCK INPUT CLK AD951x 0.1µF LVDS DRIVER CLK 50Ω1 50Ω1 0.1µF CLK+ 100Ω 0.1µF ADC AD9246 CLK– 05491-050 CLOCK INPUT 150Ω RESISTORS ARE OPTIONAL Figure 48. Differential LVDS Sample Clock In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, directly drive CLK+ from a CMOS gate, while bypassing the CLK− pin to ground using a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 49). CLK+ may be directly driven from a CMOS gate. This input is designed to withstand input voltages up to 3.6 V, making the selection of the drive logic voltage very flexible. When driving CLK+ with a 1.8 V CMOS signal, biasing the CLK− pin with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 49) is required. The 39 kΩ resistor is not required when driving CLK+ with a 3.3 V CMOS signal (see Figure 50). Rev. A | Page 19 of 44 AD9246 The DCS can be enabled or disabled by setting the SDIO/DCS pin when operating in the external pin mode (see Table 10), or via the SPI, as described in Table 13. Table 10. Mode Selection (External Pin Mode) Voltage at Pin AGND AVDD SCLK/DFS Binary (default) Twos complement SDIO/DCS DCS disabled DCS enabled (default) POWER DISSIPATION AND STANDBY MODE As shown in Figure 52 and Figure 53, the power dissipated by the AD9246 is proportional to its sample rate. The digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be calculated as: I DRVDD = VDRVDD × CLOAD × fCLK ×N 2 JITTER CONSIDERATIONS High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fIN) due to jitter (tJ) is calculated as follows: SNR = −20 log (2π × fIN × tJ) In the equation, the rms aperture jitter represents the root mean square of all jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 51. 75 70 65 MEASURED PERFORMANCE 0.20ps 0.05ps where N is the number of output bits, 14 in the case of the AD9246. This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency, fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 52 and Figure 53 was taken under the same operating conditions as the data for the Typical Performance Characteristics section, with a 5 pF load on each output driver. 475 250 SNR (dBc) 60 0.5ps 55 50 45 40 1.0ps 1.50ps 2.00ps 2.50ps 3.00ps 05491-083 450 IAVDD 200 150 400 TOTAL POWER 375 100 1 10 100 1000 INPUT FREQUENCY (MHz) 350 IDRVDD 0 25 50 75 100 50 Figure 51. SNR vs. Input Frequency and Jitter 120 TOTAL POWER 100 80 60 40 330 310 290 270 250 Refer to Application Notes AN-501, Aperture Uncertainty and ADC System Performance, and AN-756, Sampled Systems and the Effects of Clock Phase Noise and Jitter, for more in-depth information about jitter performance as it relates to ADCs. IDRVDD 20 05491-068 0 25 50 75 100 0 CLOCK FREQUENCY (MSPS) Figure 53. AD9246-105 Power and Current vs. Clock Frequency fIN = 30 MHz Rev. A | Page 20 of 44 CURRENT (mA) POWER (mW) Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9246. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. The power supplies should also not be shared with analog input circuits, such as buffers, to avoid the clock modulating onto the input signal or vice versa. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. CLOCK FREQUENCY (MSPS) Figure 52. AD9246-125 Power and Current vs. Clock Frequency fIN = 30 MHz 410 390 370 140 350 200 180 IAVDD 160 05491-034 325 0 125 CURRENT (mA) 425 POWER (mW) AD9246 290 IAVDD 275 120 150 As detailed in the Interfacing to High Speed ADCs via SPI User Manual, the data format can be selected for either offset binary, twos complement, or Gray code when using the SPI control. Out-of-Range (OR) Condition 260 TOTAL POWER 245 60 90 CURRENT (mA) POWER (mW) 230 IDRVDD 0 20 40 CLOCK FREQUENCY (MSPS) 60 An out-of-range condition exists when the analog input voltage is beyond the input range of the ADC. OR is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. Thus, OR has the same pipeline latency as the digital data. OR DATA OUTPUTS 1 11 1111 1111 1111 0 11 1111 1111 1111 0 11 1111 1111 1110 +FS – 1 LSB OR 30 05491-091 215 0 80 –FS + 1/2 LSB 0 0 1 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 –FS –FS – 1/2 LSB +FS +FS – 1/2 LSB 05491-088 Figure 54. AD9246-80 Power and Current vs. Clock Frequency fIN = 30 MHz Power-Down Mode By asserting the PDWN pin high, the AD9246 is placed in power-down mode. In this state, the ADC typically dissipates 1.8 mW. During power-down, the output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9246 to its normal operational mode. This pin is both 1.8 V and 3.3 V tolerant. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and then must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in power-down mode; and shorter power-down cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF decoupling capacitors on REFT and REFB, it takes approximately 0.25 ms to fully discharge the reference buffer decoupling capacitors and 0.35 ms to restore full operation. Figure 55. OR Relation to Input Voltage and Output Data OR is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range, as shown in Figure 55. OR remains high until the analog input returns to within the input range, and another conversion is completed. By logically AND’ing the OR bit with the MSB and its complement, overrange high or underrange low conditions can be detected. Table 11 is a truth table for the overrange/ underrange circuit in Figure 56, which uses NAND gates. MSB OR MSB UNDER = 1 05491-087 OVER = 1 Figure 56. Overrange/Underrange Logic Table 11. Overrange/Underrange Truth Table OR 0 0 1 1 MSB 0 1 0 1 Analog Input Is: Within range Within range Underrange Overrange Standby Mode When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required (see the Memory Map section). DIGITAL OUTPUTS The AD9246 output drivers can be configured to interface with 1.8 V to 3.3 V logic families by matching DRVDD to the digital supply of the interfaced logic. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fan-outs may require external buffers or latches. The output data format can be selected for either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 10). Digital Output Enable Function (OEB) The AD9246 has three-state ability. If the OEB pin is low, the output data drivers are enabled. If the OEB pin is high, the output data drivers are placed in a high impedance state. This is not intended for rapid access to the data bus. Note that OEB is referenced to the digital supplies (DRVDD) and should not exceed that supply voltage. Rev. A | Page 21 of 44 AD9246 TIMING The lowest typical conversion rate of the AD9246 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. The AD9246 provides latched data outputs with a pipeline delay of 12 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9246. These transients can degrade the dynamic performance of the converter. Table 12. Output Data Format Input (V) VIN+ – VIN– VIN+ – VIN– VIN+ – VIN– VIN+ – VIN– VIN+ – VIN– Condition (V) < –VREF – 0.5 LSB = –VREF =0 = +VREF – 1.0 LSB > +VREF – 0.5 LSB Binary Output Mode 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1111 Twos Complement Mode 10 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111 Gray Code Mode (SPI accessible) 11 0000 0000 0000 11 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0000 10 0000 0000 0000 OR 1 0 0 0 1 Data Clock Output (DCO) The AD9246 provides a data clock output (DCO) intended for capturing the data in an external register. The data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. See Figure 2 for a graphical timing description. Rev. A | Page 22 of 44 AD9246 SERIAL PORT INTERFACE (SPI) The AD9246 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that are further divided into fields, as documented in the Memory Map section. For detailed operational information, see the Interfacing to High Speed ADCs via SPI User Manual. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip as well as read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or in LSB-first mode. MSB first is the default on power up and can be changed via the configuration register. For more information, see the Interfacing to High Speed ADCs via SPI User Manual. Table 14. SPI Timing Diagram Specifications Name tDS tDH tCLK tS tH tHI tLO Description Setup time between data and rising edge of SCLK Hold time between data and rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state CONFIGURATION USING THE SPI As summarized in Table 13, three pins define the SPI of this ADC. The SCLK/DFS pin synchronizes the read and write data presented to the ADC. The SDIO/DCS dual purpose pin allows data to be sent and read from the internal ADC memory map registers. The CSB pin is an active low control that enables or disables the read and write cycles. Table 13. Serial Port Interface Pins Pin Name SCLK/DFS SDIO/DCS Function SCLK (serial clock) is the serial shift clock in. SCLK synchronizes serial interface reads and writes. SDIO (serial data input/output) is a dual purpose pin. The typical role for this pin is an input and output, depending on the instruction being sent and the relative position in the timing frame. CSB (chip select bar) is an active low control that gates the read and write cycles. HARDWARE INTERFACE The pins described in Table 13 comprise the physical interface between the user’s programming device and the serial port of the AD9246. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either PROM or PIC microcontrollers. This provides the user with the ability to use an alternate method to program the ADC. One method is described in detail in the Application Note AN-812, Microcontroller-based Serial Port Interface Boot Circuit. When the SPI interface is not used, some pins serve a dual function. When strapped to AVDD or ground during device power-on, the pins are associated with a specific function. CSB The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. Figure 57 and Table 14 provide examples of the serial timing and its definitions. Other modes involving the CSB are available. The CSB can be held low indefinitely to permanently enable the device (this is called streaming). The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and the length is determined by the W0 bit and the W1 bit. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output. CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS and SCLK/DFS pins serve as stand-alone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the output data format and duty cycle stabilizer (see Table 10). In this mode, the CSB chip select should be connected to AVDD, which disables the serial port interface. For more information, see the Interfacing to High Speed ADCs via SPI User Manual. Rev. A | Page 23 of 44 AD9246 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight address locations. The memory map is roughly divided into three sections: the chip configuration registers map (Address 0x00 to Address 0x02), the device index and transfer registers map (Address 0xFF), and the ADC functions map (Address 0x08 to Address 0x18). Table 15 displays the register address number in hexadecimal in the first column. The last column displays the default value for each hexadecimal address. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Hexadecimal Address 0x14, output_phase, has a hexadecimal default value of 0x00. This means Bit 3 = 0, Bit 2 = 0, Bit 1 = 1, and Bit 0 = 1 or 0011 in binary. This setting is the default output clock or DCO phase adjust option. The default value adjusts the DCO phase 90° relative to the nominal DCO edge and 180° relative to the data edge. For more information on this function, consult the Interfacing to High Speed ADCs via SPI User Manual. Default Values Coming out of reset, critical registers are loaded with default values. The default values for the registers are shown in Table 15. Logic Levels An explanation of two registers follows: • • “Bit is set” is synonymous with “Bit is set to Logic 1” or “Writing Logic 1 for the bit.” “Clear a bit” is synonymous with “Bit is set to Logic 0” or “Writing Logic 0 for the bit.” SPI-Accessible Features A list of features accessible via the SPI and a brief description of what the user can do with these features follow. These features are described in detail in the Interfacing to High Speed ADCs via SPI User Manual. • • • • • • • Modes: Set either power-down or standby mode. Clock: Access the DCS via the SPI. Offset: Digitally adjust the converter offset. Test I/O: Set test modes to have known data on output bits. Output Mode: Set up outputs; vary the strength of the output drivers. Output Phase: Set the output clock polarity. VREF: Set the reference voltage. Open Locations Locations marked as open are currently not supported for this device. When required, these locations should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x14). If the entire address location is open (Address 0x13), then the address location does not need to be written. tDS tS CSB tHI tDH tLO tCLK tH SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 57. Serial Port Interface Timing Diagram Rev. A | Page 24 of 44 05491-056 AD9246 MEMORY MAP REGISTER TABLE Table 15. Memory Map Register Addr. Bit 7 (Hex) Parameter Name (MSB) Chip Configuration Registers 00 chip_port_config 0 Bit 6 LSB first 0 = Off (Default) 1 = On Bit 5 Soft reset 0 = Off (Default) 1 = On Bit 4 1 Bit 3 1 Bit 2 Soft reset 0 = Off (Default) 1 = On Bit 1 LSB first 0 = Off (Default) 1 = On Bit 0 (LSB) 0 Default Value (Hex) 0x18 Default Notes/ Comments The nibbles should be mirrored. See the Interfacing to High Speed ADCs via SPI User Manual. Default is unique chip ID, different for each device. Child ID used to differentiate speed grades. 01 chip_id 8-bit Chip ID Bits 7:0 (AD9246 = 0x00), (default) Open Open Open Open Child ID 0 = 125 MSPS, 1 = 105 MSPS Open Open Open Open Read only Read only 02 chip_grade Device Index and Transfer Registers FF device_update Open Open Open Open Open Open SW transfer 0x00 Synchronously transfers data from the master shift register to the slave. Determines various generic modes of chip operation. See the Power Global ADC Functions 08 modes Open Open PDWN 0—full (Default) 1—standby Open Open Internal power-down mode 000—normal (power-up, Default) 001—full power-down 010—standby 011—normal (power-up) Note: External PDWN pin overrides this setting. 0x00 Dissipation and Standby Mode section and the SPIAccessible Features section. 0x01 See the Clock Duty Cycle section and the 09 clock Open Open Open Open Open Open Open Duty cycle stabilizer 0—disabled 1— enabled (Default) SPI-Accessible Features section. Rev. A | Page 25 of 44 AD9246 Addr. Bit 7 (Hex) Parameter Name (MSB) Flexible ADC Functions 10 offset Bit 0 (LSB) Default Value (Hex) 0x00 Default Notes/ Comments Adjustable for offset inherent in the converter. See the SPI- Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0D test_io Digital Offset Adjust 011111 011110 011101 … 000010 000001 000000 111111 111110 111101 ... 100001 100000 PN9 PN23 0= 0= normal normal (Default) (Default) 1 = reset 1 = reset Offset in LSBs +31 +30 +29 +2 +1 0 (Default) 1 −2 −3 −31 −32 Global Output Test Options 000—off (Default) 001—midscale short 010—+FS short 011—−FS short 100—checker board output 101—PN 23 sequence 110—PN 9 111—one/zero word toggle Data Format Select Output 00—offset binary Data (default) Invert 01—twos 1= complement invert 10—Gray Code Open Open Open Accessible Features section. 0x00 See the Interfacing to High Speed ADCs via SPI User Manual. 14 output_mode Output Driver Configuration 00 for DRVDD = 2.5 V to 3.3 V (Default) 10 for DRVDD = 1.8 V Open Output Clock Polarity 1 = inverted 0 = normal (Default) Internal Reference Resistor Divider 00—VREF = 1.25 V 01—VREF = 1.5 V 10—VREF = 1.75 V 11—VREF = 2.00 V (Default) Open 16 output_phase Open Output Disable 1— disabled 0— enabled 1 Open Open 0x00 Configures the outputs and the format of the data. Open 0x00 See the SPIAccessible Features section. See the SPIAccessible Features section. 18 VREF Open Open Open Open Open Open 0xC0 1 External output enable (OEB) pin must be high. Rev. A | Page 26 of 44 AD9246 LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS When connecting power to the AD9246, it is recommended that two separate supplies be used: one for analog (AVDD, 1.8 V nominal) and one for digital (DRVDD, 1.8 V to 3.3 V nominal). If only a single 1.8 V supply is available, it is routed to AVDD first, then tapped off and isolated with a ferrite bead or filter choke with decoupling capacitors proceeding connection to DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace length. A single PC board ground plane is sufficient when using the AD9246. With proper decoupling and smart partitioning of analog, digital, and clock sections of the PC board, optimum performance is easily achieved. SILKSCREEN PARTITION PIN 1 INDICATOR Figure 58. Typical PCB Layout CML The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 38. RBIAS The AD9246 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. Exposed Paddle Thermal Heat Slug Recommendations It is required that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9246. An exposed, continuous copper plane on the PCB should mate to the AD9246 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the two during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and PCB. See Figure 58 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see Application Note AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package. REFERENCE DECOUPLING The VREF pin should be externally decoupled to ground with a low ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic low ESR capacitor. In all reference configurations, REFT and REFB are bypass points provided for reducing the noise contributed by the internal reference buffer. It is recommended that an external 0.1 μF ceramic capacitor be placed across REFT/REFB. While placement of this 0.1 μF capacitor is not required, the SNR performance degrades by approximately 0.1 dB without it. All reference decoupling capacitors should be placed as close to the ADC as possible with minimal trace lengths. Rev. A | Page 27 of 44 05491-057 AD9246 EVALUATION BOARD The AD9246 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a double balun configuration (default) or through the AD8352 differential driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the AD8352 drive circuitry. Each input configuration can be selected by proper connection of various components (see Figure 60 to Figure 70). Figure 59 shows the typical bench characterization setup used to evaluate the ac performance of the AD9246. It is critical that the signal sources used for the analog input and clock have very low phase noise (