14-Bit, 20 MSPS/40 MSPS/65 MSPS
Dual A/D Converter
AD9248
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
AGND
OTR_A
VIN+_A
14
SHA
14
ADC
OUTPUT
MUX/
BUFFERS
VIN–_A
REFT_A
CLOCK
DUTY CYCLE
STABILIZER
VREF
GENERAL DESCRIPTION
The AD9248 is a dual, 3 V, 14-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and hold amplifiers (SHAs) and an
integrated voltage reference. The AD9248 uses a multistage
differential pipelined architecture with output error correction
logic to provide 14-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch fullscale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.
CLK_A
CLK_B
DCS
SENSE
AGND
SHARED_REF
0.5V
MODE
CONTROL
PWDN_A
PWDN_B
DFS
REFB_B
OTR_B
VIN+_B
Ultrasound equipment
Direct conversion or IF sampling receivers
WB-CDMA, CDMA2000, WiMAX
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
OEB_A
MUX_SELECT
REFB_A
REFT_B
APPLICATIONS
D13_A TO D0_A
SHA
ADC
14
VIN–_B
OUTPUT 14
MUX/
BUFFERS
D13_B TO D0_B
OEB_B
AD9248
DRVDD DRGND
04446-001
Integrated dual 14-bit ADC
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 71.6 dB (to Nyquist, AD9248-65)
SFDR = 80.5 dBc (to Nyquist, AD9248-65)
Low power: 300 mW/channel at 65 MSPS
Differential input with 500 MHz, 3 dB bandwidth
Exceptional crosstalk immunity > 85 dB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Output datamux option
Figure 1.
Fabricated on an advanced CMOS process, the AD9248 is
available in a Pb-free, space saving, 64-lead LQFP or LFCSP and
is specified over the industrial temperature range (−40°C to
+85°C).
PRODUCT HIGHLIGHTS
1. Pin-compatible with the AD9238, 12-bit 20 MSPS/
40 MSPS/65 MSPS ADC.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
allow flexibility between power, cost, and performance to suit
an application.
3. Low power consumption: AD9248-65: 65 MSPS = 600 mW,
AD9248-40: 40 MSPS = 330 mW, and AD9248-20: 20 MSPS =
180 mW.
4. Typical channel isolation of 85 dB @ fIN = 10 MHz.
5. The clock duty cycle stabilizer (AD9248-20/AD9248-40/
AD9248-65) maintains performance over a wide range of
clock duty cycles.
6. Multiplexed data output option enables single-port operation
from either Data Port A or Data Port B.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
AD9248
TABLE OF CONTENTS
Specifications..................................................................................... 3
Clock Circuitry ........................................................................... 22
DC Specifications ......................................................................... 3
Analog Inputs ............................................................................. 22
AC Specifications.......................................................................... 5
Reference Circuitry .................................................................... 22
Digital Specifications ................................................................... 6
Digital Control Logic ................................................................. 22
Switching Specifications .............................................................. 7
Outputs ........................................................................................ 22
Absolute Maximum Ratings ............................................................ 8
LQFP Evaluation Board Bill of Materials (BOM) .................. 24
Explanation of Test Levels ........................................................... 8
LQFP Evaluation Board Schematics ........................................ 25
ESD Caution .................................................................................. 8
LQFP PCB Layers ....................................................................... 29
Pin Configurations and Function Descriptions ........................... 9
Dual ADC LFCSP PCB .................................................................. 35
Terminology .................................................................................... 11
Power Connector........................................................................ 35
Typical Performance Characteristics ........................................... 12
Analog Inputs ............................................................................. 35
Equivalent Circuits ......................................................................... 16
Optional Operational Amplifier .............................................. 35
Theory of Operation ...................................................................... 17
Clock ............................................................................................ 35
Analog Input ............................................................................... 17
Voltage Reference ....................................................................... 35
Clock Input and Considerations .............................................. 18
Data Outputs ............................................................................... 35
Power Dissipation and Standby Mode ..................................... 19
LFCSP Evaluation Board Bill of Materials (BOM) ................ 36
Digital Outputs ........................................................................... 19
LFCSP PCB Schematics ............................................................. 37
Timing.......................................................................................... 19
LFCSP PCB Layers ..................................................................... 40
Data Format ................................................................................ 20
Thermal Considerations............................................................ 45
Voltage Reference ....................................................................... 20
Outline Dimensions ....................................................................... 46
AD9248 LQFP Evaluation Board ................................................. 22
Ordering Guide .......................................................................... 47
REVISION HISTORY
11/10—Rev. A to Rev. B
Changes to Absolute Maximum Ratings Section ......................... 8
Changes to Figure 3 .......................................................................... 9
Add Figure 4; Renumbered Sequentially ....................................... 9
Changes to Theory of Operation Section and Analog Input
Section .............................................................................................. 17
Deleted Note 1 from Dual ADC LFCSP PCB Section ............... 35
Updated Outline Dimensions ....................................................... 46
3/05—Rev. 0 to Rev. A
Added LFCSP ...................................................................... Universal
Changes to Features.......................................................................... 1
Changes to Applications .................................................................. 1
Changes to General Description .................................................... 1
Changes to Product Highlights....................................................... 1
Changes to Table 6 .......................................................................... 10
Changes to Terminology ............................................................... 11
Changes to Figure 22...................................................................... 15
Changes to Clock Input and Considerations Section ................ 18
Changes to Timing Section ........................................................... 19
Changes to Figure 33...................................................................... 19
Changes to Data Format Section .................................................. 20
Changes to Table 10 ....................................................................... 24
Changes to Figure 39...................................................................... 25
Changes to Table 13 ....................................................................... 36
Updated Outline Dimensions ....................................................... 46
Changes to Ordering Guide .......................................................... 47
1/05—Revision 0: Initial Version
Rev. B | Page 2 of 48
AD9248
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error 1
Differential Nonlinearity (DNL) 2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error1
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
Input Span = 1 V
Input Span = 2.0 V
ANALOG INPUT
Input Span = 1.0 V
Input Span = 2.0 V
Input Capacitance 3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2
PSRR
POWER CONSUMPTION
DC Input 4
Sine Wave Input2
Standby Power 5
Temp
Full
Test
Level
VI
AD9248BST/BCP-20
Min Typ
Max
14
AD9248BST/BCP-40
Min Typ
Max
14
AD9248BST/BCP-65
Min Typ
Max
14
Full
25°C
Full
Full
25°C
Full
25°C
VI
I
IV
V
IV
V
IV
14
14
14
Full
Full
V
V
±2
±12
Full
Full
Full
Full
VI
V
V
V
±5
0.8
±2.5
0.1
25°C
25°C
V
V
2.1
1.05
2.1
1.05
2.1
1.05
LSB rms
LSB rms
Full
Full
Full
Full
IV
IV
V
V
1
2
7
7
1
2
7
7
1
2
7
7
V p-p
V p-p
pF
kΩ
Full
Full
IV
IV
Full
Full
Full
V
V
V
60
5
±0.01
Full
Full
Full
V
VI
V
180
190
2.0
±0.2
±0.25
±0.65
±0.6
±2.7
±2.3
2.7
2.25
3.0
3.0
±1.3
±2.2
±0.2
±0.3
±0.65
±0.6
±2.7
±2.3
±1.0
±4.5
±1.3
±2.4
±0.2
±0.5
±0.7
±0.65
±2.8
±2.4
±1.0
±4.5
±2
±12
±35
3.6
3.6
±5
0.8
±2.5
0.1
2.7
2.25
3.0
3.0
Rev. B | Page 3 of 48
330
360
2.0
±1.0
±4.5
±3
±12
±35
3.6
3.6
110
11
±0.01
217
±1.3
±2.5
±5
0.8
±2.5
0.1
2.7
2.25
3.0
3.0
600
640
2.0
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
±35
3.6
3.6
200
16
±0.01
400
Unit
Bits
mV
mV
mV
mV
V
V
mA
mA
% FSR
700
mW
mW
mW
AD9248
Parameter
MATCHING CHARACTERISTICS
Offset Error
(Nonshared Reference Mode)
Offset Error
(Shared Reference Mode)
Gain Error
(Nonshared Reference Mode)
Gain Error
(Shared Reference Mode)
Temp
Test
Level
AD9248BST/BCP-20
Min Typ
Max
AD9248BST/BCP-40
Min Typ
Max
AD9248BST/BCP-65
Min Typ
Max
25°C
I
±0.19
±1.56
±0.19
±1.56
±0.25
±1.74
% FSR
25°C
I
±0.19
±1.56
±0.19
±1.56
±0.25
±1.74
% FSR
25°C
I
±0.07
±1.43
±0.07
±1.43
±0.07
±1.47
% FSR
25°C
I
±0.01
±0.06
±0.01
±0.06
±0.01
±0.10
% FSR
1
Unit
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 29 for the equivalent analog input structure.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
2
3
Rev. B | Page 4 of 48
AD9248
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V external reference,
TMIN to TMAX, DCS Enabled, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
fINPUT = 100 MHz
SIGNAL-TO-NOISE AND DISTORTION
RATIO (SINAD)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
fINPUT = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
fINPUT = 100 MHz
WORST HARMONIC (SECOND or THIRD)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
Temp
Test
Level
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
V
IV
V
IV
V
IV
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
V
IV
V
IV
V
IV
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
V
IV
V
IV
V
IV
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
V
IV
V
I
V
I
V
I
AD9248BST/BCP-20
Min Typ
Max
73.1
72.4
73.4
73.7
72.9
73.1
AD9248BST/BCP-40
Min Typ
Max
72.8
73.1
73.4
72.3
72.7
72.9
AD9248BST/BCP-65
Min Typ
Max
72.3
71.2
70
72.2
70.9
73.0
73.2
72.0
72.2
69.5
72.0
72.8
73.0
71.0
72.1
72.3
71.7
70.0
69.5
11.7
11.5
11.8
11.8
11.7
11.7
69.0
11.7
11.8
11.8
11.5
11.7
11.7
11.6
11.3
11.3
77.5
76.1
86.0
87.5
83.0
84.0
Rev. B | Page 5 of 48
11.2
77.5
85.0
86.0
76.0
83.0
84.0
72.8
73.1
71.5
71.6
69.0
72.5
72.7
70.9
71.0
68.5
11.8
11.8
11.5
11.5
11.2
77.5
84.0
86.0
73.0
80.0
80.5
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
AD9248
Parameter
WORST OTHER SPUR
(NONSECOND or THIRD)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
fINPUT = 100 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 35 MHz
CROSSTALK
Temp
Test
Level
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
I
V
I
V
I
V
I
V
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
V
IV
V
I
V
I
V
I
V
AD9248BST/BCP-20
Min Typ
Max
83.3
83.1
88.0
89.0
87.0
88.0
AD9248BST/BCP-40
Min Typ
Max
83.5
88.0
89.0
82.6
88.0
88.5
AD9248BST/BCP-65
Min Typ
Max
81.0
79.8
79.0
77.5
86.0
87.5
83.0
76.1
81.0
77.5
85.0
86.0
76.0
83.0
84.0
77.5
85.5
86.0
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
85.5
86.0
75.0
84.0
86.0
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
84.0
73.0
−85.0
−85.0
Unit
80.0
80.5
−85.0
DIGITAL SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 3.
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS 1
High Level Output Voltage
Temp
Test
Level
AD9248BST/BCP-20
Min
Typ Max
Min
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
2.0
2.0
Full
IV
Low Level Output Voltage
Full
IV
1
0.8
+10
+10
−10
−10
AD9248BST-40
Typ Max
AD9248BST-65
Typ Max
2.0
0.8
+10
+10
−10
−10
2
Min
−10
−10
2
DRVDD −
0.05
2
DRVDD −
0.05
0.05
Output voltage levels measured with capacitive load only on each output.
Rev. B | Page 6 of 48
0.8
+10
+10
V
V
μA
μA
pF
V
DRVDD −
0.05
0.05
Unit
0.05
V
AD9248
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4.
Parameter
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse-Width High 1
CLK Pulse-Width Low1
DATA OUTPUT PARAMETER
Output Delay 2 (tPD)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (tJ)
Wake-Up Time 3
OUT-OF-RANGE RECOVERY TIME
2
3
AD9248BST/BCP-20
Min
Typ
Max
AD9248BST/BCP-40
Min
Typ
Max
AD9248BST/BCP-65
Min
Typ
Max
Full
Full
Full
Full
Full
VI
V
V
V
V
20
40
65
Full
Full
Full
Full
Full
Full
VI
V
V
V
V
V
1
1
50.0
15.0
15.0
2
6
MSPS
MSPS
ns
ns
ns
1
25.0
8.8
8.8
3.5
7
1.0
0.5
2.5
2
Unit
15.4
6.2
6.2
2
3.5
7
1.0
0.5
2.5
2
6
2
3.5
7
1.0
0.5
2.5
2
6
ns
Cycles
ns
ps rms
ms
Cycles
The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24).
Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output.
Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
N
N+1
N+8
N+2
N+3
N–1
ANALOG
INPUT
N+7
N+4
N+5
N+6
CLOCK
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
tPD = MIN 2.0ns,
MAX 6.0ns
Figure 2. Timing Diagram
Rev. B | Page 7 of 48
04446-002
1
Temp
Test
Level
AD9248
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are limiting values to be applied
individually, and beyond which the serviceability of the circuit
may be impaired. Functional operability is not necessarily implied.
Exposure to absolute maximum rating conditions for an extended
period may affect device reliability.
EXPLANATION OF TEST LEVELS
I
II
III
IV
Table 5.
Parameter
ELECTRICAL
AVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
Digital Outputs to DRGND
OEB, DFS, CLK, DCS, MUX_SELECT,
SHARED_REF to AGND
VINA, VINB to AGND
VREF to AGND
SENSE to AGND
REFB, REFT to AGND
PDWN to AGND
ENVIRONMENTAL1
Operating Temperature
Junction Temperature
Lead Temperature (10 sec)
Storage Temperature
1
Rating
V
VI
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
100% production tested.
100% production tested at 25°C and sample tested at
specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
Parameter is a typical value only.
100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range;
100% production tested at temperature extremes for
military devices.
ESD CAUTION
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +85°C
150°C
300°C
−65°C to +150°C
Typical thermal impedances: 64-lead LQFP, θJA = 54°C/W; 64-lead LFCSP, θJA
= 26.4°C/W with heat slug soldered to ground plane. These measurements
were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
Rev. B | Page 8 of 48
AD9248
64 63 62 61 60 59 58
D7_A
D8_A
D9_A
DRVDD
DRGND
D10_A
D11_A
D12_A
D13_A (MSB)
OTR_A
OEB_A
PDWN_A
MUX_SELECT
SHARED_REF
CLK_A
AVDD
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
57 56 55 54 53 52 51 50 49
AGND 1
48 D6_A
PIN 1
VIN+_A 2
47 D5_A
VIN–_A 3
46 D4_A
AGND 4
45 D3_A
AVDD 5
44 D2_A
REFT_A 6
43 D1_A
AD9248
REFB_A 7
42 D0_A (LSB)
64-LEAD LQFP
TOP VIEW
(Not to Scale)
VREF 8
SENSE 9
41 DRVDD
40 DRGND
REFB_B 10
39 OTR_B
REFT_B 11
38 D13_B (MSB)
AVDD 12
37 D12_B
AGND 13
36 D11_B
VIN–_B 14
35 D10_B
VIN+_B 15
34 D9_B
AGND 16
33 D8_B
04446-003
D7_B
D6_B
D5_B
DRVDD
DRGND
D4_B
D3_B
D2_B
D1_B
D0_B (LSB)
OEB_B
PDWN_B
DFS
DCS
AVDD
CLK_B
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
CLK_A
SHARED_REF
MUX_SELECT
PDWN_A
OEB_A
OTR_A
D13_A (MSB)
D12_A
D11_A
D10_A
DRGND
DRVDD
D9_A
D8_A
D7_A
Figure 3. 64-Lead LQFP Pin Configuration
PIN 1
INDICATOR
AD9248
64-LEAD LFCSP
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D6_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A (LSB)
DRVDD
DRGND
OTR_B
D13_B (MSB)
D12_B
D11_B
D10_B
D9_B
D8_B
NOTES
1. THERE IS AN EXPOSED PAD THAT MUST CONNECT TO AGND.
Figure 4. 64-Lead LFCSP Pin Configuration
Rev. B | Page 9 of 48
04446-103
AVDD
CLK_B
DCS
DFS
PDWN_B
OEB_B
D0_B (LSB)
D1_B
D2_B
D3_B
D4_B
DRGND
DRVDD
D5_B
D6_B
D7_B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND 1
VIN+_A 2
VIN–_A 3
AGND 4
AVDD 5
REFT_A 6
REFB_A 7
VREF 8
SENSE 9
REFB_B 10
REFT_B 11
AVDD 12
AGND 13
VIN–_B 14
VIN+_B 15
AGND 16
AD9248
Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions
Pin No.
1, 4, 13, 16
2
3
5, 12, 17, 64
6
7
8
9
10
11
14
15
18
19
20
21
Mnemonic
AGND
VIN+_A
VIN−_A
AVDD
REFT_A
REFB_A
VREF
SENSE
REFB_B
REFT_B
VIN−_B
VIN+_B
CLK_B
DCS
DFS
PDWN_B
22
OEB_B
23 to 27,
30 to 38
28, 40, 53
29, 41, 52
D0_B (LSB) to
D13_B (MSB)
DRGND
DRVDD
39
42 to 51,
54 to 57
58
59
OTR_B
D0_A (LSB) to
D13_A (MSB)
OTR_A
OEB_A
60
PDWN_A
61
MUX_SELECT
62
63
SHARED_REF
CLK_A
EP
Description
Analog Ground.
Analog Input Pin (+) for Channel A.
Analog Input Pin (−) for Channel A.
Analog Power Supply.
Differential Reference (+) for Channel A.
Differential Reference (−) for Channel A.
Voltage Reference Input/Output.
Reference Mode Selection.
Differential Reference (−) for Channel B.
Differential Reference (+) for Channel B.
Analog Input Pin (−) for Channel B.
Analog Input Pin (+) for Channel B.
Clock Input Pin for Channel B.
Enable Duty Cycle Stabilizer (DCS) Mode.
Data Output Format Select Pin (Low for Offset Binary, High for Twos Complement).
Power-Down Function Selection for Channel B.
Logic 0 enables Channel B. Logic 1 powers down Channel B (outputs static, not High-Z).
Output Enable Pin for Channel B.
Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z.
Channel B Data Output Bits.
Digital Output Ground.
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor.
Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF capacitor.
Out-of-Range Indicator for Channel B.
Channel A Data Output Bits.
Out-of-Range Indicator for Channel A.
Output Enable Pin for Channel A.
Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z.
Power-Down Function Selection for Channel A.
Logic 0 enables Channel A. Logic 1 powers down Channel A (outputs static, not High-Z).
Data Multiplexed Mode.
(See Data Format section for how to enable; high setting disables output data multiplexed mode.)
Shared Reference Control Pin (Low for Independent Reference Mode, High for Shared Reference Mode).
Clock Input Pin for Channel A.
For the 64-Lead LFCSP only, there is an exposed pad that must connect to AGND.
Rev. B | Page 10 of 48
AD9248
TERMINOLOGY
Aperture Delay
SHA performance measured from the rising edge of the clock
input to when the input signal is held for conversion.
Aperture Jitter
The variation in aperture delay for successive samples, which is
manifested as noise on the input to the ADC.
Integral Nonlinearity (INL)
Deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1½ LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX.
Power Supply Rejection
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal, expressed as a
percentage or in decibels relative to the peak carrier signal (dBc).
Signal-to-Noise and Distortion (SINAD) Ratio
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed dB.
Effective Number of Bits (ENOB)
Using the following formula
ENOB = (SINAD − 1.76)/6.02
ENOB for a device for sine wave inputs at a given input
frequency can be calculated directly from its measured SINAD.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in dB.
Spurious-Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2), this is often referred to as
Nyquist sampling.
IF Sampling
Due to the effects of aliasing, an ADC is not limited to Nyquist
sampling. Higher sampled frequencies are aliased down into the
first Nyquist zone (DC − fCLOCK/2) on the output of the ADC.
The bandwidth of the sampled signal should not overlap
Nyquist zones and alias onto itself. Nyquist sampling
performance is limited by the bandwidth of the input SHA and
clock jitter (jitter adds more noise at higher input frequencies).
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
Crosstalk
Coupling onto one channel being driven by a (−0.5 dBFS) signal
when the adjacent interfering channel is driven by a full-scale
signal. Measurement includes all spurs resulting from both
direct coupling and mixing components.
Rev. B | Page 11 of 48
AD9248
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD, DRVDD = 3.0 V, T = 25°C, AIN differential drive, full scale = 2 V, unless otherwise noted.
0
100
SNR = 72.6dB
SINAD = 71.9dB
H2 = –81.5dBc
H3 = –86.8dBc
SFDR = 81.5dB
95
90
SFDR
85
–40
SFDR/SNR (dBc)
–60
THIRD
HARMONIC
–80
80
75
SECOND
HARMONIC
CROSSTALK
SNR
70
65
60
04446-060
–100
–120
0
5
10
15
20
25
04446-007
MAGNITUDE (dBFS)
–20
55
50
30
40
45
50
FREQUENCY (MHz)
Figure 5. Single-Tone FFT of Channel A Digitizing fIN = 12.5 MHz
While Channel B Is Digitizing fIN = 10 MHz
60
65
Figure 8. AD9248-65 Single-Tone SFDR/SNR vs. FS with fIN = 32.5 MHz
0
100
SNR = 70.5dB
SINAD = 69.4dB
H2 = –92.3dBc
H3 = –80.1dBc
SFDR = 80.1dBc
–20
95
90
SFDR
SNR
85
–40
SFDR/SNR (dBc)
MAGNITUDE (dBFS)
55
ADC SAMPLE RATE (MSPS)
–60
SECOND
HARMONIC
THIRD HARMONIC
–80
80
75
SNR
70
65
CROSSTALK
04446-061
–120
0
5
10
15
20
25
55
50
20
30
25
30
40
35
FREQUENCY (MHz)
ADC SAMPLE RATE (MSPS)
Figure 6. Single-Tone FFT of Channel A Digitizing fIN = 70 MHz
While Channel B Is Digitizing fIN = 76 MHz
Figure 9. AD9248-40 Single-Tone SFDR/SNR vs. FS with fIN = 20 MHz
100
0
SNR = 68.1dB
SINAD = 68.0dB
H2 = –83.4dBc
H3 = –83.1dBc
SFDR = 75.1dBc
–20
95
90
SFDR
SFDR/SNR (dBc)
85
–40
–60
SECOND HARMONIC
CROSSTALK
80
75
SNR
70
–80
65
–120
0
5
10
15
20
25
04446-009
60
–100
55
04446-062
MAGNITUDE (dBFS)
04446-008
60
–100
50
0
30
5
10
15
20
ADC SAMPLE RATE (MSPS)
FREQUENCY (MHz)
Figure 7. Single-Tone FFT of Channel A Digitizing fIN = 120 MHz
While Channel B Is Digitizing fIN = 126 MHz
Figure 10. AD9248-20 Single-Tone SFDR/SNR vs. FS with fIN = 10 MHz
Rev. B | Page 12 of 48
AD9248
100
95
90
90
80
SFDR/SNR (dBc)
SFDR/SNR (dBc)
SFDR
SNR
70
SNR
60
85
SNR
SFDR
80
75
SNR
–30
–25
–20
–15
–10
–5
04446-013
40
–35
70
04446-010
50
65
0
0
20
INPUT AMPLITUDE (dBFS)
40
60
80
100
120
140
INPUT FREQUENCY (MHz)
Figure 11. AD9248-65 Single-Tone SFDR/SNR vs. AIN with fIN = 32.5 MHz
Figure 14. AD9248-65 Single-Tone SFDR/SNR vs. fIN
100
95
90
90
80
SNR
SFDR
SFDR/SNR (dBc)
SFDR/SNR (dBc)
SNR
SFDR
70
SNR
60
85
80
75
SNR
04446-011
40
–35
–30
–25
–20
–15
–10
–5
04446-014
70
50
65
0
0
20
40
80
100
120
140
Figure 15. AD9248-40 Single-Tone SFDR/SNR vs. fIN
Figure 12. AD9248-40 Single-Tone SFDR/SNR vs. AIN with fIN = 20 MHz
95
100
90
90
SNR
SFDR
SFDR
SNR
80
SFDR/SNR (dBc)
SFDR/SNR (dBc)
60
INPUT FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
70
SNR
60
85
80
75
SNR
04446-012
40
–35
–30
–25
–20
–15
–10
–5
04446-015
70
50
65
0
0
20
40
60
80
100
120
INPUT AMPLITUDE (dBFS)
INPUT FREQUENCY (MHz)
Figure 13. AD9248-20 Single-Tone SFDR/SNR vs. AIN with fIN = 10 MHz
Figure 16. AD9248-20 Single-Tone SFDR/SNR vs. fIN
Rev. B | Page 13 of 48
140
AD9248
100
0
SNR
SFDR
95
–20
SFDR/SNR (dBFS)
MAGNITUDE (dBFS)
90
–40
–60
IMD = –85dBc
–80
85
80
75
SNR
70
–100
–120
0
5
10
15
20
25
60
–24
30
04446-019
04446-063
65
–21
FREQUENCY (MHz)
–18
–15
–12
–9
–6
INPUT AMPLITUDE (dBFS)
Figure 17. Dual-Tone FFT with fIN1 = 39 MHz and fIN2 = 40 MHz
Figure 20. Dual-Tone SFDR/SNR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz
0
100
SNR
SFDR
95
–20
SFDR/SNR (dBFS)
MAGNITUDE (dBFS)
90
–40
IMD =
–83dBc
–60
–80
85
80
75
SNR
70
–100
–120
0
5
10
15
20
25
60
–24
30
04446-020
04446-064
65
–21
FREQUENCY (MHz)
Figure 18. Dual-Tone FFT with fIN1 = 70 MHz and fIN2 = 71 MHz
–15
–12
–9
–6
Figure 21. Dual-Tone SFDR/SNR vs. AIN with fIN1 = 70 MHz and fIN2 = 71 MHz
0
100
95
–20
90
SFDR/SNR (dBFS)
–40
–60
–80
SNR
SFDR
85
80
75
SNR
70
–100
–120
0
5
10
15
20
25
30
65
60
–24
04446-021
04446-018
MAGNITUDE (dBFS)
–18
INPUT AMPLITUDE (dBFS)
–21
–18
–15
–12
–9
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 19. Dual-Tone FFT with fIN1 = 200 MHz and fIN2 = 201 MHz
Figure 22. Dual-Tone SFDR/SNR vs.
AIN with fIN1 = 200 MHz and fIN2 = 201 MHz
Rev. B | Page 14 of 48
–6
AD9248
74
12.0
–65
600
SINAD –65
11.5
SINAD –40
ENOB
SINAD (dBc)
72
70
AVDD POWER (mW)
SINAD –20
500
400
–40
300
68
11.0
0
20
40
–20
04446-025
04446-022
200
100
0
10
20
60
30
40
50
60
SAMPLE RATE (MSPS)
CLOCK FREQUENCY (MHz)
Figure 26. Analog Power Consumption vs. FS
Figure 23. SINAD vs. FS with Nyquist Input
95
2.5
DCS ON (SFDR)
2.0
90
1.5
85
1.0
80
75
INL (LSB)
DCS ON (SINAD)
70
0
–0.5
65
–1.0
DCS OFF (SINAD)
60
04446-023
50
30
35
40
45
50
55
60
–2.0
–2.5
65
0
2000
4000
6000
8000
10000 12000 14000
DUTY CYCLE (%)
CODE
Figure 24. SINAD/SFDR vs. Clock Duty Cycle
Figure 27. AD9248-65 Typical INL
84
16000
1.0
SFDR
82
0.8
0.6
80
0.4
DNL (LSB)
78
76
74
72
SINAD
0.2
0
–0.2
–0.4
70
–0.6
04446-024
68
66
–50
04446-026
–1.5
55
SINAD/SFDR (dB)
0.5
0
50
100
04446-027
SINAD/SFDR (dBc)
DCS OFF (SFDR)
–0.8
–1.0
0
2000
4000
6000
8000
10000 12000 14000
TEMPERATURE (°C)
CODE
Figure 25. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz
Figure 28. AD9248-65 Typical DNL
Rev. B | Page 15 of 48
16000
AD9248
EQUIVALENT CIRCUITS
AVDD
AVDD
04446-028
04446-030
CLK_A, CLK_B
DCS, DFS,
MUX_SELECT,
SHARED_REF
VIN+_A, VIN–_A,
VIN+_B, VIN–_B
Figure 31. Equivalent Digital Input Circuit
Figure 29. Equivalent Analog Input Circuit
04446-029
DRVDD
Figure 30. Equivalent Digital Output Circuit
Rev. B | Page 16 of 48
AD9248
THEORY OF OPERATION
The AD9248 consists of two high performance ADCs that are
based on the AD9235 converter core. The dual ADC paths are
independent, except for a shared internal band gap reference
source, VREF. Each of the ADC paths consists of a proprietary
front end SHA followed by a pipelined switched-capacitor ADC.
The pipelined ADC is divided into three sections, consisting
of a 4-bit first stage, followed by eight 1.5-bit stages, and a final
3-bit flash. Each stage provides sufficient overlap to correct for
flash errors in the preceding stages. The quantized outputs from
each stage are combined through the digital correction logic
block into a final 14-bit result. The pipelined architecture
permits the first stage to operate on a new input sample, while
the remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the
respective clock.
In IF under-sampling applications, any shunt capacitors
should be removed. In combination with the driving source
impedance, they limit the input bandwidth. For best dynamic
performance, the source impedances driving VIN+ and VIN−
should be matched such that common-mode settling errors are
symmetrical. These errors are reduced by the common-mode
rejection of the ADC.
H
T
T
5pF
VIN+
CPAR
T
5pF
The input stage contains a differential SHA that can be
configured as ac- or dc-coupled in differential or single-ended
modes. The output-staging block aligns the data, carries out the
error correction, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
VIN–
CPAR
T
H
04446-031
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the flash ADC
output to control a switched-capacitor digital-to-analog converter
(DAC) of the same resolution. The DAC output is subtracted from
the stage’s input signal and the residual is amplified (multiplied)
to drive the next pipeline stage. The residual multiplier stage is
also called a multiplying DAC (MDAC). One bit of redundancy
is used in each one of the stages to facilitate digital correction of
flash errors. The last stage simply consists of a flash ADC.
Figure 32. Switched-Capacitor Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as:
REFT = ½(AVDD + VREF)
REFB = ½(AVDD −VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
The equations above show that the REFT and REFB voltages are
symmetrical about the midsupply voltage and, by definition, the
input span is twice the value of the VREF voltage.
ANALOG INPUT
The analog input to the AD9248 is a differential, switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA
input accepts inputs over a wide common-mode range. An
input common-mode voltage of midsupply is recommended
to maintain optimal performance.
The SHA input is a differential switched-capacitor circuit. In
Figure 32, the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC input;
therefore, the precise values are dependent on the application.
The internal voltage reference can be pin-strapped to fixed values
of 0.5 V or 1.0 V or adjusted within the same range as discussed
in the Internal Reference Connection section. Maximum SNR
performance is achieved with the AD9248 set to the largest
input span of 2 V p-p. The relative SNR degradation is 3 dB
when changing from 2 V p-p mode to 1 V p-p mode.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as:
Rev. B | Page 17 of 48
VCMMIN = VREF/2
VCMMAX = (AVDD + VREF)/2
AD9248
The minimum common-mode input level allows the AD9248 to
accommodate ground-referenced inputs. Although optimum
performance is achieved with a differential input, a single-ended
source may be driven into VIN+ or VIN−. In this configuration,
one input accepts the signal, while the opposite input should be
set to midscale by connecting it to an appropriate reference. For
example, a 2 V p-p signal may be applied to VIN+, while a 1 V
reference is applied to VIN−. The AD9248 then accepts an
input signal varying between 2 V and 0 V. In the single-ended
configuration, distortion performance may degrade significantly
as compared to the differential case. However, the effect is less
noticeable at lower input frequencies and in the lower speed grade
models (AD9248-40 and AD9248-20).
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9248 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9248. This is especially true in IF
under-sampling applications where frequencies in the 70 MHz
to 200 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 33.
50Ω
10pF
49.9Ω
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive
to the clock duty cycle. Commonly, a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance
characteristics.
The AD9248 provides separate clock inputs for each channel. The
optimum performance is achieved with the clocks operated at the
same frequency and phase. Clocking the channels asynchronously
may degrade performance significantly. In some applications, it
is desirable to skew the clock timing of adjacent channels. The
AD9248’s separate clock inputs allow for clock timing skew
(typically ±1 ns) between the channels without significant
performance degradation.
The AD9248-65 contains two clock duty cycle stabilizers, one
for each converter, that retime the nonsampling edge, providing
an internal clock with a nominal 50% duty cycle. When proper
track-and-hold times for the converter are required to maintain
high performance, maintaining a 50% duty cycle clock is
particularly important in high speed applications. It may be
difficult to maintain a tightly controlled duty cycle on the input
clock on the PCB (see Figure 24). DCS can be enabled by tying
the DCS pin high.
The duty cycle stabilizer uses a delay-locked loop to create the
nonsampling edge. As a result, any changes to the sampling
frequency require approximately 2 μs to 3 μs to allow the DLL
to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated as
AVDD
VINA
2V p-p
CLOCK INPUT AND CONSIDERATIONS
AD9248
50Ω
⎤
⎡
1
SNR = 20 × log ⎢
⎥
(
)
2
π
f
t
×
×
×
j ⎦
INPUT
⎣
VINB
0.1μF
AGND
1kΩ
04446-032
10pF
1kΩ
Figure 33. Differential Transformer Coupling
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance.
In the equation, the rms aperture jitter, tJ , represents the rootsum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification.
Under-sampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aperture
jitter may affect the dynamic range of the AD9248, it is important
to minimize input clock jitter. The clock input circuitry should
use stable references; for example, use analog power and ground
planes to generate the valid high and low digital levels for the
AD9248 clock input. Power supplies for clock drivers should be
separated from the ADC output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods), it
should be retimed by the original clock at the last step.
Rev. B | Page 18 of 48
AD9248
A single channel can be powered down for moderate power
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered on. Because the buffer and voltage reference
remain powered on, the wake-up time is reduced to several
clock cycles.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9248 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The digital drive current can be
calculated by
DIGITAL OUTPUTS
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
The AD9248 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
where N is the number of bits changing, and CLOAD is the average
load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases with clock frequency.
Either channel of the AD9248 can be placed into standby mode
independently by asserting the PDWN_A or PDWN_B pins.
The data format can be selected for either offset binary or twos
complement. See the Data Format section for more information.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
results in a typical power consumption of 1 mW for the ADC.
Note that if DCS is enabled, it is mandatory to disable the clock
of an independently powered-down channel. Otherwise,
significant distortion results on the active channel. If the clock
inputs remain active while in total standby mode, typical power
dissipation of 12 mW results.
TIMING
The AD9248 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer
to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the AD9248
using the DCS pin. This provides a stable 50% duty cycle to
internal circuits.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B =
HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled
after a power-down, the wake-up time is directly related to the
recharging of the REFT and REFB decoupling capacitors and to
the duration of the power-down. Typically, it takes approximately
5 ms to restore full operation with fully discharged 0.1 μF and
10 μF decoupling capacitors on REFT and REFB.
A–1
A1
A0
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9248.
These transients can detract from the converter’s dynamic
performance. The lowest typical conversion rate of the AD9248
is 1 MSPS. At clock rates below 1 MSPS, dynamic performance
may degrade.
A7
A3
A4
B1
B0
A6
A5
B8
B2
ANALOG INPUT
ADC B
B7
B3
B4
B6
B5
CLK_A = CLK_B =
MUX_SELECT
A–7
B–8
tPD
B–7
A–6
B–6
A–5
B–5
A–4
B–4
A–3
B–3
A–2
B–2
A–1
B–1
A0
B0
A1
D0_A TO
D11_A
04446-033
B–1
ANALOG INPUT
ADC A
A8
A2
tPD
Figure 34. Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
Rev. B | Page 19 of 48
AD9248
The AD9248 data output format can be configured for either
twos complement or offset binary. This is controlled by the data
format select pin (DFS). Connecting DFS to AGND produces
offset binary output data. Conversely, connecting DFS to AVDD
formats the output data as twos complement.
The output data from the dual ADCs can be multiplexed onto a
single 14-bit output bus. The multiplexing is accomplished by
toggling the MUX_SELECT bit, which directs channel data to
the same or opposite channel data port. When MUX_SELECT
is logic high, the Channel A data is directed to the Channel A
output bus, and the Channel B data is directed to the Channel B
output bus. When MUX_SELECT is logic low, the channel data
is reversed, that is, the Channel A data is directed to the
Channel B output bus, and the Channel B data is directed to the
Channel A output bus. By toggling the MUX_SELECT bit,
multiplexed data is available on either of the output data ports.
If the ADCs run with synchronized timing, this same clock can
be applied to the MUX_SELECT pin. Any skew between
CLK_A, CLK_B, and MUX_SELECT can degrade AC
performance. It is recommended to keep the clock skew
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