14-Bit, 125 MSPS/105 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9255
Data Sheet
FEATURES
APPLICATIONS
SNR = 78.3 dBFS at 70 MHz and 125 MSPS
SFDR = 93 dBc at 70 MHz and 125 MSPS
Low power: 371 mW at 125 MSPS
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−153.4 dBm/Hz small signal input noise with 200 Ω input
impedance at 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Communications
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and
TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
PRODUCT HIGHLIGHTS
1.
On-chip dither option for improved SFDR performance
with low power analog input.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
Pin compatibility with the AD9265, allowing a simple
migration up to 16 bits.
2.
3.
4.
5.
FUNCTIONAL BLOCK DIAGRAM
SENSE RBIAS
VREF
PDWN
AGND
AVDD (1.8V)
REFERENCE
LVDS LVDS_RS
AD9255
VCM
VIN+
VIN–
DRVDD (1.8V)
TRACK-AND-HOLD
ADC
14-BIT
CORE
DITHER
CLK+
CLK–
OUTPUT
STAGING 14
CMOS OR
LVDS
(DDR)
14
CLOCK
MANAGEMENT
D13 TO D0
OR
OEB
SYNC
SERIAL PORT
SVDD SCLK/ SDIO/ CSB
DFS DCS
08505-001
DCO
Figure 1.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9255
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage Reference ...................................................................... 28
Applications ...................................................................................... 1
Clock Input Considerations ..................................................... 29
Product Highlights ........................................................................... 1
Power Dissipation and Standby Mode .................................... 31
Functional Block Diagram .............................................................. 1
Digital Outputs ........................................................................... 32
Revision History ............................................................................... 2
Timing ......................................................................................... 32
General Description ......................................................................... 3
Built-In Self-Test (BIST) and Output Test ................................. 33
Specifications .................................................................................... 4
Built-In Self-Test (BIST) ........................................................... 33
ADC DC Specifications ................................................................. 4
Output Test Modes .................................................................... 33
ADC AC Specifications ................................................................. 5
Serial Port Interface (SPI) ............................................................. 34
Digital Specifications ................................................................... 6
Configuration Using the SPI .................................................... 34
Switching Specifications ................................................................ 8
Hardware Interface .................................................................... 34
Timing Specifications .................................................................. 9
Configuration Without the SPI ................................................ 35
Absolute Maximum Ratings ......................................................... 10
SPI Accessible Features ............................................................. 35
Thermal Characteristics ............................................................ 10
Memory Map .................................................................................. 36
ESD Caution................................................................................ 10
Reading the Memory Map Register Table .............................. 36
Pin Configurations and Function Descriptions ......................... 11
Memory Map Register Table .................................................... 37
Typical Performance Characteristics ........................................... 15
Memory Map Register Descriptions ....................................... 39
Equivalent Circuits ......................................................................... 23
Applications Information ............................................................. 40
Theory of Operation ...................................................................... 25
Design Guidelines ...................................................................... 40
ADC Architecture ...................................................................... 25
Outline Dimensions ....................................................................... 41
Analog Input Considerations ................................................... 25
Ordering Guide .......................................................................... 41
REVISION HISTORY
9/2020—Rev. C to Rev. D
Changed CP-48-8 to CP-48-9 ...................................... Throughout
Changes to Figure 4........................................................................ 11
Updated Outline Dimensions ....................................................... 61
Changes to Ordering Guide .......................................................... 61
7/2013—Rev. B to Rev. C
Changes to Data Clock Output (DCO) Section ......................... 32
3/2013—Rev. A to Rev. B
Changes to Table 17 ......................................................................... 1
Updated Outline Dimensions ....................................................... 41
1/2010—Rev. 0 to Rev. A
Changes to Worst Other (Harmonic or Spur) Parameter,
Table 2 ................................................................................................ 6
Changes to Figure 77 ..................................................................... 29
Changes to Input Clock Divider Section .................................... 30
Changes to Table 17 ....................................................................... 37
Updated Outline Dimensions ....................................................... 41
10/2009—Revision 0: Initial Version
Rev. D | Page 2 of 44
Data Sheet
AD9255
GENERAL DESCRIPTION
The AD9255 is a 14-bit, 125 MSPS analog-to-digital converter
(ADC). The AD9255 is designed to support communications
applications where high performance combined with low cost,
small size, and versatility is desired.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic to
provide 14-bit accuracy at 125 MSPS data rates and guarantees
no missing codes over the full operating temperature range.
The ADC features a wide bandwidth differential sample-andhold analog input amplifier supporting a variety of user-selectable
input ranges. It is suitable for multiplexed systems that switch fullscale voltage levels in successive channels and for sampling singlechannel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9255 is suitable for applications in communications,
instrumentation, and medical imaging.
A differential clock input controls all internal conversion cycles. A
duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to
maintain excellent performance over a wide range of input
clock duty cycles. An integrated voltage reference eases design
considerations.
The ADC output data format is either parallel 1.8 V CMOS or
LVDS (DDR). A data output clock is provided to ensure proper
latch timing with receiving logic.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface. Flexible power-down options
allow significant power savings, when desired. An optional onchip dither function is available to improve SFDR performance
with low power analog input signals.
The AD9255 is available in a Pb-free, 48-lead LFCSP and is
specified over the industrial temperature range of −40°C to +85°C.
Rev. D | Page 3 of 44
AD9255
Data Sheet
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation at 1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance3
Input Common-Mode Voltage
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
SVDD
Supply Current
IAVDD2
IDRVDD2 (1.8 V CMOS)
IDRVDD2 (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input2
CMOS Output Mode
LVDS Output Mode
Standby Power4
Power-Down Power
Temp
Full
AD9255BCPZ-801
Min Typ
Max
14
Full
Full
Full
Full
25°C
Full
25°C
AD9255BCPZ-1051
Min Typ
Max
14
Guaranteed
±0.05 ±0.25
±0.2
±2.5
±0.4
±0.2
±0.9
±0.35
AD9255BCPZ-1251
Min Typ
Max
14
Guaranteed
±0.05
±0.25
±0.2
±2.5
±0.4
±0.2
±0.9
±0.45
Guaranteed
±0.05
±0.25
±0.4
±2.5
±0.45
±0.25
±1.2
±0.7
±2
±15
Full
Full
+8
3
25°C
0.62
0.63
0.61
LSB rms
Full
Full
Full
Full
2
8
0.9
6
2
8
0.9
6
2
8
0.9
6
V p-p
pF
V
kΩ
1.7
1.7
Full
1.7
1.8
1.8
±12
+8
3
1.9
1.9
1.7
1.7
3.5
1.7
1.8
1.8
±2
±15
% FSR
% FSR
LSB
LSB
LSB
LSB
Full
Full
Full
Full
±2
±15
Unit
Bits
±12
+8
3
1.9
1.9
1.7
1.7
3.5
1.7
1.8
1.8
ppm/°C
ppm/°C
±12
mV
mV
1.9
1.9
V
V
3.5
V
Full
Full
Full
126
13
39
131
169
19
42
176
194
23
44
202
mA
mA
mA
Full
239
248
321
332
371
382
mW
Full
Full
Full
Full
252
306
54
0.05
0.15
338
384
54
0.05
0.15
391
437
54
0.05
0.15
mW
mW
mW
mW
1
The suffix following the part number refers to the model found in the Ordering Guide section.
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Standby power is measured with a dc input, the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND).
2
Rev. D | Page 4 of 44
Data Sheet
AD9255
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 2.
1
Parameter
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
Without Dither (AIN at −23 dBFS)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
With On-Chip Dither (AIN at −23 dBFS)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
Temp
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
AD9255BCPZ-802
Min
Typ
Max
AD9255BCPZ-1052
Min
Typ
Max
79.2
78.9
AD9255BCPZ-1252
Min
Typ
Max
78.9
78.5
78.1
78.3
78.3
77.6
dBFS
dBFS
dBFS
dBFS
dBFS
76.9
78.0
76.9
77.7
76.4
77.1
75.5
78.7
78.7
78.6
78.0
78.0
78.0
Unit
76.8
75.8
77.0
75.3
76.7
74.3
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
12.8
12.8
12.5
12.3
12.8
12.7
12.5
12.2
12.7
12.7
12.4
12.0
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
−88
−94
−90
−89
−88
−93
−82
−81
−86
−81
−89
−80
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
88
94
90
89
88
93
77.9
77.3
76.7
−91
−88
−85
82
81
86
81
89
80
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
102
103
104
102
99
97
97
101
96
99
98
97
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
110
110
110
110
109
108
108
109
108
109
109
109
dBFS
dBFS
dBFS
dBFS
91
88
Rev. D | Page 5 of 44
85
AD9255
1
Parameter
WORST OTHER (HARMONIC OR SPUR)
Without Dither
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
With On-Chip Dither
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
TWO-TONE SFDR
Without Dither
fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS )
fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS )
ANALOG INPUT BANDWIDTH
1
2
Data Sheet
AD9255BCPZ-802
Min
Typ
Max
AD9255BCPZ-1052
Min
Typ
Max
AD9255BCPZ-1252
Min
Typ
Max
25°C
25°C
Full
25°C
25°C
−106
−106
−105
−104
−101
−104
−104
−102
−104
−103
−103
−100
25°C
25°C
Full
25°C
25°C
−105
−106
−106
−105
−101
−104
−103
−100
−103
−101
25°C
25°C
25°C
93
80
650
90
78
650
Temp
−94
−91
dBc
dBc
dBc
dBc
dBc
−98
−103
−100
dBc
dBc
dBc
dBc
dBc
95
79
650
dBc
dBc
MHz
−95
−97
Unit
−99
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
The suffix following the part number refers to the model found in the Ordering Guide section.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS
enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Rev. D | Page 6 of 44
Min
0.3
AGND
0.9
−100
−100
8
Typ
Max
CMOS/LVDS/LVPECL
0.9
3.6
AVDD
1.4
+100
+100
4
10
12
CMOS
0.9
AGND
1.2
AGND
−100
−100
12
AVDD
AVDD
0.6
+100
+100
1
16
20
Unit
V
V p-p
V
V
μA
μA
pF
kΩ
V
V
V
V
μA
μA
pF
kΩ
Data Sheet
Parameter
LOGIC INPUT (CSB)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT/OUTPUT (SDIO/DCS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
High Level Output Voltage
Low Level Output Voltage
LOGIC INPUTS (OEB, PDWN, DITHER, LVDS, LVDS_RS)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS (DRVDD = 1.8 V)
CMOS Mode
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
LVDS Mode
ANSI Mode
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Reduced Swing Mode
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
1
2
AD9255
Temperature
Min
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
Full
Full
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
Full
Full
Full
Full
Full
Full
1.22
0
−90
−10
Full
Full
1.79
1.75
Typ
Max
Unit
SVDD
0.6
+10
132
V
V
μA
μA
kΩ
pF
SVDD
0.6
−135
+10
V
V
μA
μA
kΩ
pF
SVDD
0.6
+10
128
V
V
μA
μA
kΩ
pF
V
V
26
2
26
2
26
5
1.70
0.2
2.1
0.6
−134
+10
26
5
V
V
μA
μA
kΩ
pF
V
V
Full
Full
0.2
0.05
V
V
Full
Full
290
1.15
345
1.25
400
1.35
mV
V
Full
Full
160
1.15
200
1.25
230
1.35
mV
V
Pull-up.
Pull-down.
Rev. D | Page 7 of 44
AD9255
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and
DCS enabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate2
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode
DCS Enabled
DCS Disabled
Divide-by-3 Mode, Divide-by-5 Mode, and
Divide-by-7 Mode, DCS Enabled3
Divide-by-2 Mode, Divide-by-4 Mode, Divideby-6 Mode, and Divide-by-8 Mode, DCS
Enabled or DCS Disabled3
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
CMOS Mode
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)4
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
LVDS Mode
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)4
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
Wake-Up Time5
OUT-OF-RANGE RECOVERY TIME
Temp
AD9255BCPZ-801
Min Typ Max
Full
AD9255BCPZ-1051
Min Typ
Max
625
Full
Full
Full
20
10
12.5
Full
Full
3.75
5.9
0.8
Full
0.8
Full
Full
6.25
6.25
AD9255BCPZ-1251
Min Typ Max
625
80
80
20
10
9.5
8.75
6.6
2.85
4.5
0.8
4.75
4.75
105
105
20
10
8
6.65
5.0
2.4
3.8
0.8
0.8
1.0
0.07
4
4
625
MHz
125
125
MSPS
MSPS
ns
5.6
4.2
ns
ns
ns
0.8
1.0
0.07
Unit
ns
1.0
0.07
ns
ps rms
Full
Full
Full
Full
2.4
2.7
0.3
2.8
3.4
0.6
12
3.4
4.2
0.9
2.4
2.7
0.3
2.8
3.4
0.6
12
3.4
4.2
0.9
2.4
2.7
0.3
2.8
3.4
0.6
12
3.4
4.2
0.9
ns
ns
ns
Cycles
Full
Full
2.6
3.3
−0.3
3.4
3.8
+0.4
12.5
500
2
4.2
4.3
+1.2
2.6
3.3
−0.3
3.4
3.8
+0.4
12.5
500
2
4.2
4.3
+1.2
2.6
3.3
−0.3
3.4
3.8
+0.4
12.5
500
2
4.2
4.3
+1.2
ns
ns
Full
Full
Full
1
The suffix following the part number refers to the model found in the Ordering Guide section.
Conversion rate is the clock rate after the divider.
3
See the Input Clock Divider section for additional information on using the DCS with the input clock divider.
4
Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).
5
Wake-up time is defined as the time required to return to normal operation from power-down mode.
2
Rev. D | Page 8 of 44
Cycles
μs
Cycles
Data Sheet
AD9255
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS1
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
1
Conditions
Min
Typ
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Max
0.30
0.40
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
ns
ns
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
Refer to Figure 84 for a detailed timing diagram.
Timing Diagrams
N–1
N+4
tA
N+5
N
N+3
VIN
N+1
tCH
tCL
N+2
tCLK
CLK+
CLK–
tDCO
DCO/DCO+
DCO–
LVDS (DDR) MODE
tPD
D0/1+ TO D12/D13+
tSKEW
DEx
– 12
D0/1– TO D12/D13–
DOx
– 12
DEx
– 11
DOx
– 11
DEx
– 10
DOx
– 10
DEx
–9
DOx
–9
DEx
–8
DOx
–8
CMOS MODE
D0 TO D13
Dx – 12
Dx – 11
Dx – 10
Dx – 9
Dx – 8
08505-002
NOTES
1. DEx DENOTES EVEN BIT.
2. DOx DENOTES ODD BIT.
Figure 2. LVDS (DDR) and CMOS Output Mode Data Output Timing
CLK+
tHSYNC
08505-104
tSSYNC
SYNC
Figure 3. SYNC Input Timing Requirements
Rev. D | Page 9 of 44
Unit
AD9255
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
SVDD to AGND
VIN+, VIN− to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/DCS to AGND
OEB to AGND
PDWN to AGND
LVDS to AGND
LVDS_RS to AGND
DITHER to AGND
D0 through D13 to AGND
DCO to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0V
−0.3 V to +3.6 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to SVDD +0.3 V
−0.3 V to SVDD +0.3 V
−0.3V to SVDD + 0.3 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints and maximizes
the thermal capability of the package.
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown, airflow improves heat dissipation, which
reduces θJA. In addition, metal in direct contact with the package
leads from metal traces, through holes, ground, and power
planes, reduces the θJA.
Table 7. Thermal Resistance
Package Type
48-Lead LFCSP
(CP-48-8)
−40°C to +85°C
1
150°C
θJA1, 2
24.5
21.4
19.2
θJC1, 3
1.3
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
3
−65°C to +150°C
Airflow
Velocity
(m/s)
0
1.0
2.5
ESD CAUTION
Rev. D | Page 10 of 44
θJB1, 4
12.7
Unit
°C/W
°C/W
°C/W
Data Sheet
AD9255
38 VREF
37 SENSE
39 DNC
41 LVDS_RS
40 DNC
42 VIN+
43 VIN–
45 AVDD
44 LVDS
46 VCM
48 PDWN
47 RBIAS
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SYNC
1
36 AVDD
CLK+
CLK–
2
3
35 DITHER
34 AVDD
AVDD
4
AVDD
OEB
5
6
DNC
7
DCO
DNC
8
9
33 SVDD
AD9255
32 CSB
31 SCLK/DFS
30 SDIO/DCS
PARALLEL
CMOS
TOP VIEW
(Not to Scale)
29 DRVDD
28 DNC
27 OR
26 D13 (MSB)
DNC 10
D0 (LSB) 11
25 D12
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE INPUT. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
08505-003
D9 22
D10 23
D11 24
DRVDD 20
D8 21
D6 18
D7 19
D4 16
D5 17
D2 14
D3 15
DRVDD 13
D1 12
Figure 4. LFCSP Parallel CMOS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
Mnemonic
ADC Power Supplies
13, 20, 29
DRVDD
4, 5, 34, 36, 45
AVDD
33
SVDD
7, 9, 10, 28, 39, 40 DNC
0
AGND
ADC Analog
42
43
38
37
47
46
2
3
Digital Input
1
Digital Outputs
11
12
14
15
16
17
18
19
21
Type
Description
Supply
Supply
Supply
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
SPI Input/Output Voltage
Do Not Connect.
Analog Ground. The exposed thermal pad on the bottom of the package provides
the analog ground for the input. This exposed pad must be connected to ground for
proper operation.
Ground
VIN+
VIN−
VREF
SENSE
RBIAS
VCM
CLK+
CLK−
Input
Input
Input/output
Input
Input/output
Output
Input
Input
Differential Analog Input Pin (+).
Differential Analog Input Pin (−).
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
SYNC
Input
Digital Synchronization Pin. Slave mode only.
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
Output
Output
Output
Output
Output
Output
Output
Output
Output
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
Rev. D | Page 11 of 44
AD9255
Data Sheet
Pin No.
22
23
24
25
26
27
8
SPI Control
31
30
32
ADC Configuration
6
35
Mnemonic
D9
D10
D11
D12
D13 (MSB)
OR
DCO
Type
Output
Output
Output
Output
Output
Output
Output
Description
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
CMOS Output Data.
Overrange Output.
Data Clock Output.
SCLK/DFS
SDIO/DCS
CSB
Input
Input/output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
OEB
DITHER
Input
Input
41
LVDS_RS
Input
44
LVDS
Input
48
PDWN
Input
Output Enable Input (Active Low).
In external pin mode, this pin sets dither to on (active high). Pull low for control via
SPI in SPI mode.
In external pin mode, this pin sets LVDS reduced swing output mode (active high).
Pull low for control via SPI in SPI mode.
In external pin mode, this pin sets LVDS output mode (active high). Pull low for
control via SPI in SPI mode.
Power-down input in external pin mode. In SPI mode, this input can be configured
as power-down or standby.
Rev. D | Page 12 of 44
AD9255
48
47
46
45
44
43
42
41
40
39
38
37
PDWN
RBIAS
VCM
AVDD
LVDS
VIN–
VIN+
LVDS_RS
DNC
DNC
VREF
SENSE
Data Sheet
SYNC
CLK+
1
2
AD9255
INTERLEAVED
LVDS
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
AVDD
DITHER
AVDD
SVDD
CSB
SCLK/DFS
SDIO/DCS
DRVDD
OR+
OR–
D12/13+
D12/13–
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD
MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
08505-004
DRVDD
D2/3–
D2/3+
D4/5–
D4/5+
D6/7–
D6/7+
DRVDD
D8/9–
D8/9+
D10/11–
D10/11+
13
14
15
16
17
18
19
20
21
22
23
24
CLK– 3
AVDD 4
AVDD 5
OEB 6
DCO– 7
DCO+ 8
DNC 9
DNC 10
D0/1– 11
D0/1+ 12
PIN 1
INDICATOR
Figure 5. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
ADC Power Supplies
13, 20, 29
DRVDD
4, 5, 34, 36, 45 AVDD
33
SVDD
9, 10, 39, 40
DNC
0
AGND
ADC Analog
42
43
38
37
47
46
2
3
Digital Input
1
Digital Outputs
12
11
15
14
17
16
19
18
22
21
Type
Description
Supply
Supply
Supply
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
SPI Input/Output Voltage.
Do Not Connect.
Analog Ground. The exposed thermal pad on the bottom of the package provides the
analog ground for the input. This exposed pad must be connected to ground for
proper operation.
Ground
VIN+
VIN−
VREF
SENSE
RBIAS
VCM
CLK+
CLK−
Input
Input
Input/output
Input
Input/output
Output
Input
Input
Differential Analog Input Pin (+).
Differential Analog Input Pin (−).
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
SYNC
Input
Digital Synchronization Pin. Slave mode only.
D0/1+
D0/1−
D2/3+
D2/3−
D4/5+
D4/5−
D6/7+
D6/7−
D8/9+
D8/9−
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
LVDS Output Data Bit 0/Bit 1 (LSB)—True.
LVDS Output Data Bit 0/Bit 1 (LSB)—Complement.
LVDS Output Data Bit 2/Bit 3—True.
LVDS Output Data Bit 2/Bit 3—Complement.
LVDS Output Data Bit 4/Bit 5—True.
LVDS Output Data Bit 4/Bit 5—Complement.
LVDS Output Data Bit 6/Bit 7—True.
LVDS Output Data Bit 6/Bit 7—Complement.
LVDS Output Data Bit 8/Bit 9 —True.
LVDS Output Data Bit 8/Bit 9—Complement.
Rev. D | Page 13 of 44
AD9255
Data Sheet
Pin No.
Mnemonic
24
D10/11+
23
D10/11−
26
D12/13+ (MSB)
25
D12/13− (MSB)
28
OR+
27
OR−
8
DCO+
7
DCO−
SPI Control
31
SCLK/DFS
30
SDIO/DCS
32
CSB
ADC Configuration
6
OEB
35
DITHER
Type
Output
Output
Output
Output
Output
Output
Output
Output
Description
LVDS Output Data Bit 10/Bit 11—True.
LVDS Output Data Bit 10/Bit 11—Complement.
LVDS Output Data Bit 12/Bit 13—True.
LVDS Output Data Bit 12/Bit 13—Complement.
LVDS Overrange Output—True.
LVDS Overrange Output—Complement.
LVDS Data Clock Output—True.
LVDS Data Clock Output—Complement.
Input
Input/output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
Input
Input
41
LVDS_RS
Input
44
LVDS
Input
48
PDWN
Input
Output Enable Input (Active Low).
In external pin mode, this pin sets dither to on (active high). Pull low for control via SPI
in the SPI mode.
In external pin mode, this pin sets LVDS reduced swing output mode (active high). Pull
low for control via SPI in the SPI mode.
In external pin mode, this pin sets LVDS output mode (active high). Pull low for control
via SPI in the SPI mode.
Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as
power-down or standby.
Rev. D | Page 14 of 44
Data Sheet
AD9255
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, SVDD = 1.8 V, sample rate = 125 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential input,
VIN = −1.0 dBFS, and 32k sample, TA = 25°C, unless otherwise noted.
0
–20
–40
–60
SECOND
HARMONIC
–80
THIRD
HARMONIC
–100
10
20
30
40
THIRD
HARMONIC
–80
SECOND
HARMONIC
–100
–140
08505-106
0
FREQUENCY (MHz)
0
AMPLITUDE (dBFS)
–100
THIRD
HARMONIC
40
–40
–60
–80
THIRD
SECOND HARMONIC
HARMONIC
–100
–120
10
20
30
40
FREQUENCY (MHz)
Figure 7. AD9255-80 Single-Tone FFT with fIN = 70.1 MHz
0
–140
08505-107
0
30
40
120
SFDR (dBFS)
SNR/SFDR (dBc AND dBFS)
100
THIRD
HARMONIC
SECOND
HARMONIC
–80
20
Figure 10. AD9255-80 Single-Tone FFT with fIN = 70.1 MHz at −6 dBFS with
Dither Enabled
–40
–60
10
FREQUENCY (MHz)
80MSPS
140.1MHz @ –1dBFS
SNR = 77.0dB (78.0dBFS)
SFDR = 82.1dBc
–20
0
08505-110
–120
–100
SNR (dBFS)
80
60
SFDR (dBc)
40
SNR (dBc)
20
–120
10
20
30
FREQUENCY (MHz)
Figure 8. AD9255-80 Single-Tone FFT with fIN = 140.1 MHz
40
0
–100
08505-108
0
–90
–80
–70
–60
–50
–40
–30
INPUT AMPLITUDE (dBFS)
–20
–10
0
08505-111
–140
30
80MSPS
70.1MHz @ –6dBFS
SNR = 73.2dB (79.2dBFS)
SFDR = 99dBc
–20
–60
SECOND
HARMONIC
20
0
–40
–80
10
Figure 9. AD9255-80 Single-Tone FFT with fIN = 200.3 MHz
80MSPS
70.1MHz @ –1dBFS
SNR = 77.8dB (78.8dBFS)
SFDR = 93.6dBc
–20
0
FREQUENCY (MHz)
Figure 6. AD9255-80 Single-Tone FFT with fIN = 2.4 MHz
AMPLITUDE (dBFS)
–60
–120
–140
AMPLITUDE (dBFS)
–40
08505-109
–120
–140
80MSPS
200.3MHz @ –1dBFS
SNR = 75.9dB (76.9dBFS)
SFDR = 81dBc
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
80MSPS
2.4MHz @ –1dBFS
SNR = 78.2dB (79.2dBFS)
SFDR = 89dBc
Figure 11. AD9255-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 98.12 MHz
Rev. D | Page 15 of 44
AD9255
Data Sheet
120
1.6M
0.62 LSB RMS
SFDRFS (DITHER ON)
1.4M
110
NUMBER OF HITS
SNR/SFDR (dBFS)
1.2M
100
SFDRFS (DITHER OFF)
90
1.0M
800k
600k
SNRFS (DITHER OFF)
400k
SNRFS (DITHER ON)
200k
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
0
08505-112
70
–100
N–3
1.0
95
SFDR @ +85°C
INL ERROR (LSB)
N+3
85
SNR @ –40°C
80
SNR @ +85°C
0.4
0.2
0
–0.2
–0.4
–0.6
70
–0.8
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
–1.0
08505-113
0
0
2000
4000
6000
8000
10,000 12,000 14,000 16,000
OUTPUT CODE
Figure 13. AD9255-80 Single-Tone SNR/SFDR vs.
Input Frequency (fIN) and Temperature with 2 V p-p Full Scale
08505-116
SNR/SFDR (dBFS/dBc)
N+2
0.6
SFDR @ +25°C
90
65
N+1
INL WITHOUT DITHER
INL WITH DITHER
0.8
SNR @ +25°C
N
Figure 15. AD9255-80 Grounded Input Histogram
SFDR @ –40°C
75
N–1
OUTPUT CODE
Figure 12. AD9255-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 30 MHz with and without Dither Enabled
100
N–2
08505-115
80
Figure 16. AD9255-80 INL with fIN = 12.5 MHz
105
0.50
100
DNL ERROR (LSB)
90
SFDR
85
0
–0.25
80
30
35
40
45
50
55
60
65
70
75
80
SAMPLE RATE (MSPS)
Figure 14. AD9255-80 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 70.1 MHz
–0.50
0
2000
4000
6000
8000
10,000 12,000 14,000 16,000
OUTPUT CODE
Figure 17. AD9255-80 DNL with fIN = 12.5 MHz
Rev. D | Page 16 of 44
08505-117
SNR
75
25
08505-114
SNR/SFDR (dBFS/dBc)
0.25
95
Data Sheet
AD9255
0
–20
–40
–60
SECOND
HARMONIC
–80
THIRD
HARMONIC
–100
10
20
30
40
50
–100
0
10
20
50
0
–40
–40
AMPLITUDE (dBFS)
105MSPS
70.1MHz @ –6dBFS
–20 SNR = 72.9dB (78.9dBFS)
SFDR = 91dBc
–60
SECOND
HARMONIC
–80
THIRD
HARMONIC
–60
–80
SECOND
HARMONIC
THIRD
HARMONIC
–100
–120
10
20
30
40
50
FREQUENCY (MHz)
–140
08505-119
0
Figure 19. AD9255-105 Single-Tone FFT with fIN = 70.1 MHz
20
30
40
50
Figure 22. AD9255-105 Single-Tone FFT with fIN = 70.1 MHz at −6 dBFS with
Dither Enabled
120
105MSPS
140.1MHz @ –1dBFS
–20 SNR = 76.7dB (77.7dBFS)
SFDR = 86.4dBc
SFDR (dBFS)
SNR/SFDR (dBc AND dBFS)
100
–40
THIRD
HARMONIC
10
FREQUENCY (MHz)
0
–60
0
08505-122
–120
SECOND
HARMONIC
–80
–100
SNR (dBFS)
80
60
SFDR (dBc)
40
SNR (dBc)
10
20
30
40
50
FREQUENCY (MHz)
Figure 20. AD9255-105 Single-Tone FFT with fIN = 140.1 MHz
0
–100
08505-120
0
–90
–80
–70
–60
–50
–40
–30
INPUT AMPLITUDE (dBFS)
–20
–10
0
08505-123
20
–120
–140
40
Figure 21. AD9255-105 Single-Tone FFT with fIN = 200.3 MHz
105MSPS
70.1MHz @ –1dBFS
–20 SNR = 77.4dB (78.4dBFS)
SFDR = 88.7dBc
–100
30
FREQUENCY (MHz)
0
–140
THIRD
HARMONIC
SECOND
HARMONIC
–80
–140
08505-118
0
Figure 18. AD9255-105 Single-Tone FFT with fIN = 2.4 MHz
AMPLITUDE (dBFS)
–60
–120
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–40
08505-121
–120
–140
105MSPS
200.3MHz @ –1dBFS
SNR = 75.4dB (76.4dBFS)
SFDR = 81.6dBc
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
105MSPS
2.4MHz @ –1dBFS
SNR = 77.9dB (78.9dBFS)
SFDR = 91dBc
Figure 23. AD9255-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 98.12 MHz
Rev. D | Page 17 of 44
AD9255
Data Sheet
120
1.4M
0.63 LSB RMS
SFDRFS (DITHER ON)
1.2M
110
NUMBER OF HITS
SNR/SFDR (dBFS)
1.0M
100
SFDRFS (DITHER OFF)
90
800k
600k
400k
SNRFS (DITHER OFF)
80
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
0
08505-124
70
–100
N–3
1.0
SFDR @ +25°C
INL ERROR (LSB)
N+3
85
SNR @ –40°C
80
SNR @ +85°C
0.4
0.2
0
–0.2
–0.4
–0.6
70
–0.8
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
–1.0
08505-125
0
0
2000
4000
6000
8000
10,000 12,000 14,000 16,000
OUTPUT CODE
08505-128
SNR/SFDR (dBFS/dBc)
N+2
0.6
SFDR @ +85°C
90
65
N+1
INL WITHOUT DITHER
INL WITH DITHER
0.8
95
SNR @ +25°C
N
Figure 27. AD9255-105 Grounded Input Histogram
SFDR @ –40°C
75
N–1
OUTPUT CODE
Figure 24. AD9255-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 30 MHz with and without Dither Enabled
100
N–2
08505-127
200k
SNRFS (DITHER ON)
Figure 28. AD9255-105 INL with fIN = 12.5 MHz
Figure 25. AD9255-105 Single-Tone SNR/SFDR vs.
Input Frequency (fIN) and Temperature with 2 V p-p Full Scale
0.50
105
0.25
SFDR
DNL ERROR (LSB)
95
90
85
0
–0.25
80
SAMPLE RATE (MSPS)
–0.50
0
2000
4000
6000
8000
10,000 12,000 14,000 16,000
OUTPUT CODE
Figure 29. AD9255-105 DNL with fIN = 12.5 MHz
Figure 26. AD9255-105 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 70.1 MHz
Rev. D | Page 18 of 44
08505-129
SNR
75
25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105
08505-126
SNR/SFDR (dBFS/dBc)
100
Data Sheet
AD9255
0
–20
–40
–60
SECOND
HARMONIC
–80
THIRD
HARMONIC
–100
10
20
30
40
50
60
0
–100
20
30
40
50
60
125MSPS
200.3MHz @ –1dBFS
–20 SNR = 74.5dB (75.5dBFS)
SFDR = 80.0dBc
AMPLITUDE (dBFS)
–80
10
0
–60
THIRD
HARMONIC
0
Figure 33. AD9255-125 Single-Tone FFT with fIN = 140.1 MHz
–40
SECOND
HARMONIC
–100
–40
–60
THIRD
HARMONIC
–80
SECOND
HARMONIC
–100
–120
10
20
30
40
50
60
FREQUENCY (MHz)
–140
08505-131
0
0
10
20
30
Figure 31. AD9255-125 Single-Tone FFT with fIN = 30.3 MHz
60
0
125MSPS
220.1MHz @ –1dBFS
–20 SNR = 74.2dB (75.2dBFS)
SFDR = 79.8dBc
–40
–40
AMPLITUDE (dBFS)
125MSPS
70.1MHz @ –1dBFS
–20 SNR = 77.3dB (78.3dBFS)
SFDR = 93.9dBc
–60
SECOND
HARMONIC
50
Figure 34. AD9255-125 Single-Tone FFT with fIN = 200.3 MHz
0
–80
40
FREQUENCY (MHz)
08505-134
–120
THIRD
HARMONIC
–100
–60
THIRD
HARMONIC
–80
SECOND
HARMONIC
–100
0
10
20
30
40
50
60
FREQUENCY (MHz)
Figure 32. AD9255-125 Single-Tone FFT with fIN = 70.1 MHz
–140
0
10
20
30
40
50
60
FREQUENCY (MHz)
Figure 35. AD9255-125 Single-Tone FFT with fIN = 220.1 MHz
Rev. D | Page 19 of 44
08505-135
–120
08505-132
–120
–140
THIRD
HARMONIC
FREQUENCY (MHz)
125MSPS
30.3MHz @ –1dBFS
SNR = 77.7dB (78.7dBFS)
SFDR = 95dBc
–20
AMPLITUDE (dBFS)
SECOND
HARMONIC
–80
–140
08505-130
0
Figure 30. AD9255-125 Single-Tone FFT with fIN = 2.4 MHz
AMPLITUDE (dBFS)
–60
–120
FREQUENCY (MHz)
–140
–40
08505-133
–120
–140
125MSPS
140.1MHz @ –1dBFS
SNR = 76.2dB (77.2dBFS)
SFDR = 88.9dBc
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
125MSPS
2.4MHz @ –1dBFS
SNR = 77.2dB (78.2dBFS)
SFDR = 88dBc
AD9255
Data Sheet
0
120
SFDR (dBFS)
100
SNR/SFDR (dBc AND dBFS)
–40
–60
–80
SECOND
HARMONIC
THIRD
HARMONIC
–100
10
20
30
40
50
60
Figure 36. AD9255-125 Single-Tone FFT with fIN = 70.1 MHz at −6 dBFS with
Dither Enabled
–15
40
SNR (dBc)
–50
–40
–30
–20
–10
0
Figure 39. AD9255-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 2.4 MHz
SNR/SFDR (dBc AND dBFS)
5
3
+
4
–120
–60
100
–75
–105
–70
SFDR (dBFS)
–60
2
–80
120
–45
–90
–90
INPUT AMPLITUDE (dBFS)
125MSPS
70.1MHz @ –23dBFS
SNR = 56.4dBc (79.4dBFS)
SFDR = 75.8dBc
–30
AMPLITUDE (dBFS)
SFDR (dBc)
0
–100
08505-136
0
FREQUENCY (MHz)
0
60
20
–120
–140
SNR (dBFS)
80
08505-139
AMPLITUDE (dBFS)
125MSPS
70.1MHz @ –6dBFS
–20 SNR = 72.6dB (78.6dBFS)
SFDR = 99.7dBc
6
SNR (dBFS)
80
60
SFDR (dBc)
40
SNR (dBc)
20
12
18
24
30
36
42
48
54
60
FREQUENCY (MHz)
Figure 37. AD9255-125 Single-Tone FFT with fIN = 70.1 MHz at −23 dBFS with
Dither Disabled, 1M Sample
–15
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
–40
–30
–20
–10
0
110
–75
–90
5
–50
SFDRFS (DITHER ON)
–60
2
–60
120
–45
+
–70
Figure 40. AD9255-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 98.12 MHz
125MSPS
70.1MHz @ –23dBFS
SNR = 55.9dBc (78.9dBFS)
SFDR = 86.6dBc
–120
–80
INPUT AMPLITUDE (dBFS)
–30
–105
–90
4
3
100
SFDRFS (DITHER OFF)
90
SNRFS (DITHER OFF)
6
80
SNRFS (DITHER ON)
–135
12
18
24
30
36
42
FREQUENCY (MHz)
48
54
60
70
–100
08505-138
6
Figure 38. AD9255-125 Single-Tone FFT with fIN = 70.1 MHz at −23 dBFS with
Dither Enabled, 1M Sample
–90
–80
–70
–60
–50
–40
–30
INPUT AMPLITUDE (dBFS)
–20
–10
0
08505-141
0
0
–100
08505-137
6
08505-140
–135
Figure 41. AD9255-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 30 MHz With and Without Dither Enabled
Rev. D | Page 20 of 44
Data Sheet
100
AD9255
0
SFDR @ –40°C
–20
SFDR/IMD3 (dBc AND dBFS)
SFDR @ +25°C
90
SFDR @ +85°C
85
SNR @ –40°C
80
75
SNR @ +25°C
SNR @ +85°C
0
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
Figure 42. AD9255-125 Single-Tone SNR/SFDR vs.
Input Frequency (fIN) and Temperature with 2 V p-p Full Scale
SFDR (dBFS)
IMD3 (dBFS)
–78
–66
–54
–42
–30
–18
–6
Figure 45. AD9255-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 125 MSPS
0
125MSPS
29.1MHz @ –7dBFS
32.1MHz @ –7dBFS
SFDR = 94.4dBc
(101.4dBFS)
–20
AMPLITUDE (dBFS)
85
SFDR
80
75
SNR
70
–40
–60
–80
–100
–120
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
–140
08505-143
0
Figure 43. AD9255-125 Single-Tone SNR/SFDR vs.
Input Frequency (fIN) with 1 V p-p Full Scale
SFDR (dBc)
AMPLITUDE (dBFS)
IMD3 (dBc)
–60
–80
SFDR (dBFS)
–100
–54
–42
–30
INPUT AMPLITUDE (dBFS)
–18
–6
08505-144
–66
40
50
60
–40
–60
–80
–100
–120
IMD3 (dBFS)
–78
30
125MSPS
169.1MHz @ –7dBFS
172.1MHz @ –7dBFS
SFDR = 79.5dBc (86.5dBFS)
–20
–40
–140
–90
20
Figure 46. AD9255-125 Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz
0
–120
10
FREQUENCY (MHz)
0
–20
0
08505-146
SNR/SFDR (dBFS/dBc)
–100
INPUT AMPLITUDE (dBFS)
90
SFDR/IMD3 (dBc AND dBFS)
–80
–140
–90
95
65
IMD3 (dBc)
–120
08505-142
65
–60
08505-145
70
SFDR (dBc)
–40
Figure 44. AD9255-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 125 MSPS
Rev. D | Page 21 of 44
–140
0
10
20
30
40
50
60
FREQUENCY (MHz)
Figure 47. AD9255-125 Two-Tone FFT with fIN1 = 169.1 MHz and
fIN2 = 172.1 MHz
08505-147
SNR/SFDR (dBFS/dBc)
95
AD9255
Data Sheet
105
0.50
100
SNR/SFDR (dBFS/dBc)
0.25
90
DNL ERROR (LSB)
95
SFDR
85
0
–0.25
80
45
55
65
75
85
95
105
115
–0.50
08505-148
35
125
SAMPLE RATE (MSPS)
0
SNR/SFDR (dBFS AND dBc)
400k
SFDR (dBFS)
70
60
50
0
N–3
N–2
N–1
N
N+1
N+2
N+3
OUTPUT CODE
08505-149
200k
INL WITHOUT DITHER
INL WITH DITHER
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
4000
6000
8000
10,000 12,000 14,000 16,000
OUTPUT CODE
08505-150
–0.8
2000
40
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
INPUT COMMON-MODE VOLTAGE (V)
Figure 52. AD9255-125 SNR/SFDR vs. Input Common Mode (VCM)
with fIN = 30 MHz
Figure 49. AD9255-125 Grounded Input Histogram
INL ERROR (LSB)
80
Figure 50. AD9255-125 INL with fIN = 12.5 MHz
Rev. D | Page 22 of 44
08505-152
NUMBER OF HITS
600k
0
10,000 12,000 14,000 16,000
SFDR (dBc)
90
800k
–1.0
8000
100
0.63 LSB RMS
1.0M
0.8
6000
Figure 51. AD9255-125 DNL with fIN = 12.5 MHz
1.2M
1.0
4000
OUTPUT CODE
Figure 48. AD9255-125 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 70.1 MHz
1.4M
2000
08505-151
SNR
75
25
Data Sheet
AD9255
EQUIVALENT CIRCUITS
DRVDD
VIN+ OR
VIN–
08505-005
08505-007
PAD
Figure 57. Digital Output
Figure 53. Equivalent Analog Input Circuit
AVDD
SVDD
0.9V
CLK–
350Ω
SDIO/DCS
08505-006
CLK+
26kΩ
10kΩ
08505-008
10kΩ
Figure 58. Equivalent SDIO/DCS Circuit
Figure 54. Equivalent Clock Input Circuit
AVDD
SVDD
350Ω
SCLK/DFS
VREF
6kΩ
08505-009
08505-012
26kΩ
Figure 55. Equivalent VREF Circuit
Figure 59. Equivalent SCLK/DFS Input Circuit
AVDD
SVDD
26kΩ
350Ω
CSB
350Ω
08505-011
08505-010
SENSE
Figure 56. Equivalent SENSE Circuit
Figure 60. Equivalent CSB Input Circuit
Rev. D | Page 23 of 44
AD9255
Data Sheet
AVDD
DITHER,
LVDS OR
LVDS_RS
350Ω
PDWN
26kΩ
08505-063
08505-061
26kΩ
Figure 61. Equivalent PDWN Circuit
Figure 63. Equivalent DITHER, LVDS, and LVDS_RS Input Circuit
DRVDD
26kΩ
350Ω
08505-062
OEB
350Ω
Figure 62. Equivalent OEB Input Circuit
Rev. D | Page 24 of 44
Data Sheet
AD9255
THEORY OF OPERATION
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9255 are accomplished
using a 3-wire SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9255 architecture consists of a front-end sample-andhold input network, followed by a pipelined, switchedcapacitor ADC. The quantized outputs from each stage are
combined into a final 14-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate on
a new input sample and the remaining stages to operate on the
preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier.
The residue amplifier magnifies the difference between the
reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage can be ac- or dc-coupled in differential or
single-ended modes. The output staging block aligns the data,
corrects errors, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
adjustment of the output voltage swing. During power-down,
the output buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9255 is a differential switchedcapacitor network that has been designed for optimum
performance while processing a differential input signal.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, any
shunt capacitors should be reduced. In combination with the
driving source impedance, the shunt capacitors limit the input
bandwidth. Refer to AN-742 Application Note, Frequency
Domain Response of Switched-Capacitor ADCs; AN-827
Application Note, A Resonant Approach to Interfacing Amplifiers
to Switched-Capacitor ADCs; and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D
Converters,” for more information on this subject (see
www.analog.com).
BIAS
S
S
CFB
CS
VIN+
CPAR1
CPAR2
H
S
S
CS
VIN–
CPAR1
CPAR2
S
S
CFB
BIAS
08505-037
With the AD9255, the user can sample any fS/2 frequency
segment from dc to 200 MHz, using appropriate low-pass or
band-pass filtering at the ADC inputs with little loss in ADC
performance. Operation to 300 MHz analog input is permitted,
but occurs at the expense of increased ADC noise and distortion.
Figure 64. Switched-Capacitor Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched, and the inputs should be
differentially balanced.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by this buffer to 2 × VREF.
Input Common Mode
The clock signal alternatively switches between sample mode
and hold mode (see Figure 64). When the input is switched into
sample mode, the signal source must be capable of charging the
sample capacitors and settling within 1/2 of a clock cycle.
The analog inputs of the AD9255 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD is
recommended for optimum performance, but the device
functions over a wider range with reasonable performance (see
Figure 52). An on-board common-mode voltage reference is
included in the design and is available from the VCM pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the VCM pin voltage
(typically 0.5 × AVDD). The VCM pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Applications
Information section.
Rev. D | Page 25 of 44
AD9255
Data Sheet
Dither
Static Linearity
The AD9255 has an optional dither mode that can be selected
either using the DITHER pin or using the SPI bus. Dithering is
the act of injecting a known but random amount of white noise,
commonly referred to as dither, into the input of the ADC.
Dithering has the effect of improving the local linearity at various
points along the ADC transfer function. Dithering can
significantly improve the SFDR when quantizing small signal
inputs, typically when the input level is below −6 dBFS.
Dithering also removes sharp local discontinuities in the INL
transfer function of the ADC and reduces the overall peak-topeak INL.
As shown in Figure 65, the dither that is added to the input of
the ADC through the dither DAC is precisely subtracted out
digitally to minimize SNR degradation. When dithering is
enabled, the dither DAC is driven by a pseudorandom number
generator (PN gen). In the AD9255, the dither DAC is precisely
calibrated to result in only a very small degradation in SNR and
SINAD. The typical SNR and SINAD degradation values, with
dithering enabled, are only 1 dB and 0.8 dB, respectively.
Differential Input Configurations
VIN
ADC CORE
In receiver applications, utilizing dither helps to reduce DNL errors
that cause small signal gain errors. Often, this issue is overcome
by setting the input noise at 5 dB to 10 dB above the converter
noise. By utilizing dither within the converter to correct the
DNL errors, the input noise requirement can be reduced.
Optimum performance is achieved while driving the AD9255 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-2, and ADA4938-2 differential drivers provide
excellent performance and a flexible interface to the ADC.
The output common-mode voltage of the ADA4938-2 is easily
set with the VCM pin of the AD9255 (see Figure 66), and the
driver can be configured in the filter topology shown to provide
band limiting of the input signal.
DOUT
15pF
200Ω
DITHER
DAC
76.8Ω
VIN
33Ω
90Ω
15Ω
VIN–
ADA4938-2
ADC
33Ω
15Ω
120Ω
200Ω
Large Signal FFT
08505-039
Figure 65. Dither Block Diagram
VCM
VIN+
15pF
Figure 66. Differential Input Configuration Using the ADA4938-2
In most cases, dithering does not improve SFDR for large signal
inputs close to full scale, for example, with a −1 dBFS input. For
large signal inputs, the SFDR is typically limited by front-end
sampling distortion, which dithering cannot improve.
However, even for such large signal inputs, dithering may be
useful for certain applications because it makes the noise floor
whiter. As is common in pipeline ADCs, the AD9255 contains
small DNL errors caused by random component mismatches
that produce spurs or tones that make the noise floor somewhat
randomly colored part-to-part. Although these tones are typically
at very low levels and do not limit SFDR when the ADC is quantizing large-signal inputs, dithering converts these tones to
noise and produces a whiter noise floor.
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 67. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
C2
R2
VIN+
R1
2V p-p
49.9Ω
C1
R1
0.1µF
ADC
R2
VIN–
VCM
C2
08505-040
DITHER ENABLE
0.1µF
08505-038
PN GEN
AVDD
5pF
Figure 67. Differential Transformer-Coupled Configuration
Small Signal FFT
For small signal inputs, the front-end sampling circuit typically
contributes very little distortion, and, therefore, the SFDR is likely
to be limited by tones caused by DNL errors due to random component mismatches. Therefore, for small signal inputs (typically,
those below −6 dBFS), dithering can significantly improve SFDR
by converting these DNL tones to white noise.
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9255. For applications in
Rev. D | Page 26 of 44
Data Sheet
AD9255
which SNR is a key parameter, differential double balun coupling
is the recommended input configuration (see Figure 68). In this
configuration, the input is ac-coupled and the CML is provided
to each input through a 33 Ω resistor. These resistors compensate
for losses in the input baluns to provide a 50 Ω impedance to
the driver.
Table 10. Example RC Network
In the double balun and transformer configurations, the value of
the input capacitors and resistors is dependent on the input frequency and source impedance and may need to be reduced or
removed. Table 10 displays recommended values to set the RC
network. However, these values are dependent on the input
signal and should be used only as a starting guide.
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone and higher is to use the ADL5562
differential driver. The ADL5562 provides three selectable gain
options up to 15.5 dB. An example circuit is shown in Figure
69; additional filtering between the ADL5562 output and the
AD9255 input may be required to reduce out-of-band noise. See
the ADL5562 data sheet for more information.
Frequency
Range
(MHz)
0 to 100
100 to 300
R1 Series
(Ω Each)
15
10
C1 Differential
(pF)
18
10
C2
0.1µF
0.1µF
2V p-p
R1
R2
VIN+
33Ω
S
S
P
0.1µF
33Ω
C1
0.1µF
R1
ADC
R2
VCM
VIN–
08505-041
PA
C2
Figure 68. Differential Double Balun Input Configuration
VCC
0.1µF
ANALOG INPUT
0Ω 2
1
5, 6, 7, 8
0.1µF
11 20Ω
0.1µF
10pF
15Ω
15Ω
VIN+
100Ω
ANALOG INPUT
3
0.1µF 0Ω
0.1µF
10
100Ω
15Ω
15Ω
0.1µF
10pF
20Ω
9
0.1µF
Figure 69. Differential Input Configuration Using the ADL5562
Rev. D | Page 27 of 44
VIN–
VCM
08505-042
4
AD9255
5pF
ADL5562
R2 Series
(Ω Each)
15
10
C2 Shunt
(pF Each)
Open
10
AD9255
Data Sheet
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9255.
The input range can be adjusted by varying the reference voltage
applied to the AD9255, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the sections that follow. The Reference
Decoupling section describes the best practices PCB layout of
the reference.
the reference amplifier in a noninverting mode with the VREF
output defined as follows:
R2
VREF 0.5 1
R1
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
VIN+
VIN–
Internal Reference Connection
ADC
CORE
A comparator within the AD9255 detects the potential at the
SENSE pin and configures the reference into four possible modes,
which are summarized in Table 11. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 70), setting VREF to 1.0 V for a 2.0 V p-p fullscale input. In this mode, with SENSE grounded, the full scale can
also be adjusted through the SPI port by adjusting Bit 6 and Bit 7 of
Register 0x18. These bits can be used to change the full scale to
1.25 V p-p, 1.5 V p-p, 1.75 V p-p, or to the default of 2.0 V p-p,
as shown in Table 17.
Connecting the SENSE pin to the VREF pin switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output for a 1 V p-p full-scale
input.
VIN+
VREF
SELECT
LOGIC
0.5V
R1
ADC
Figure 71. Programmable Reference Configuration
If the internal reference of the AD9255 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 72 shows
how the internal reference voltage is affected by loading.
0
VREF
SELECT
LOGIC
SENSE
ADC
08505-043
0.5V
–0.5
VREF = 0.5V
–1.0
VREF = 1V
–1.5
–2.0
–2.5
–3.0
0.2
Figure 70. Internal Reference Configuration
If a resistor divider is connected external to the chip, as shown
in Figure 71, the switch again sets to the SENSE pin. This puts
0.4
0.6
0.8
1.0
1.2
1.4
LOAD CURRENT (mA)
1.6
1.8
2.0
Figure 72. VREF Accuracy vs. Load
Table 11. Reference Configuration Summary
Selected Mode
External Reference
SENSE Voltage
AVDD
Resulting VREF (V)
N/A
Resulting Differential Span (V p-p)
2 × external reference
Internal Fixed Reference
VREF
0.5
1.0
Programmable Reference
0.2 V to VREF
Internal Fixed Reference
AGND to 0.2 V
R2
0.5 1
(see Figure 71)
R1
1.0
Rev. D | Page 28 of 44
2 × VREF
2.0
08505-045
REFERENCE VOLTAGE ERROR (%)
ADC
CORE
0.1µF
R2
SENSE
VIN–
1.0µF
0.1µF
08505-044
1.0µF
Data Sheet
AD9255
External Reference Operation
Clock Input Options
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. Figure 73 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
The AD9255 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless
of the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 75 and Figure 76 show two preferred methods for clocking
the AD9255. A low jitter clock source is converted from a singleended signal to a differential signal using either an RF
transformer or an RF balun.
1.5
VREF = 1.0V
1.0
0.5
The RF balun configuration is recommended for clock frequencies
at 625 MHz and the RF transformer is recommended for clock
frequencies from 10 MHz to 200 MHz. The back-to-back
Schottky diodes across the transformer/balun secondary limit
clock excursions into the AD9255 to approximately 0.8 V p-p
differential.
0
–0.5
–1.0
–1.5
0
20
40
TEMPERATURE (°C)
60
80
Figure 73. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 55). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a
maximum of 1.0 V.
CLOCK
INPUT
Mini-Circuits®
ADT1-1WT, 1:1Z
0.1µF
XFMR
0.1µF
ADC
AD9255
CLK+
100Ω
50Ω
0.1µF
CLK–
SCHOTTKY
DIODES:
HSMS2822
0.1µF
CLOCK INPUT CONSIDERATIONS
08505-048
–20
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9255 while
preserving the fast rise and fall times of the signal that are critical
to low jitter performance.
Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz)
For optimum performance, the AD9255 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK−
pins via a transformer or capacitors. These pins are biased
internally (see Figure 74) and require no external bias.
ADC
1nF
CLOCK
INPUT
AD9255
0.1µF
CLK+
50Ω
0.1µF
1nF
CLK–
AVDD
SCHOTTKY
DIODES:
HSMS2822
08505-049
–2.0
–40
08505-046
Figure 76. Balun-Coupled Differential Clock (625 MHz)
0.9V
CLK+
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 77. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/AD9520/
AD9522 clock drivers offer excellent jitter performance.
CLK–
4pF
08505-047
4pF
Figure 74. Equivalent Clock Input Circuit
0.1µF
CLOCK
INPUT
0.1µF
CLK+
AD95xx
CLOCK
INPUT
0.1µF
PECL DRIVER
100Ω
0.1µF
ADC
AD9255
CLK–
50kΩ
50kΩ
240Ω
240Ω
Figure 77. Differential PECL Sample Clock (Up to Rated Sample Rate)
Rev. D | Page 29 of 44
08505-050
REFERENCE VOLTAGE ERROR (mV)
2.0
AD9255
Data Sheet
0.1µF
0.1µF
CLOCK
INPUT
CLK+
AD95xx
0.1µF
0.1µF
ADC
AD9255
CLK–
50kΩ
08505-051
CLOCK
INPUT
100Ω
LVDS DRIVER
50kΩ
Figure 78. Differential LVDS Sample Clock (Up to the Rated Sample Rate)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 78. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/
AD9518/AD9520/AD9522 clock drivers offer excellent jitter
performance.
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass
the CLK− pin to ground with a 0.1 μF capacitor (see Figure 79).
VCC
CLOCK
INPUT
0.1µF
1kΩ
AD95xx
OPTIONAL
0.1µF
100Ω
CMOS DRIVER
50Ω1
CLK+
ADC
1kΩ
AD9255
CLK–
08505-052
0.1µF
150Ω RESISTOR IS OPTIONAL.
Figure 79. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9255 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9255. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS
enabled. Jitter in the rising edge of the input is still of paramount
concern and is not easily reduced by the internal stabilization
circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered in applications in
which the clock rate can change dynamically. A wait time of
1.5 μs to 5 μs is required after a dynamic clock frequency increase
or decrease before the DCS loop is relocked to the input signal.
During the time period that the loop is not locked, the DCS
loop is bypassed, and the internal device timing is dependent on
the duty cycle of the input clock signal. In such applications, it
may be appropriate to disable the duty cycle stabilizer. The
DCS can also be disabled in some cases when using the input
clock divider circuit, see the Input Clock Divider section for
additional information. In all other applications, enabling the
DCS circuit is recommended to maximize ac performance.
The DCS is enabled by setting the SDIO/DCS pin high when
operating in the external pin mode (see Table 12). If the SPI
mode is enabled, the DCS is enabled by default and can be
disabled by writing a 0x00 to Address 0x09.
Input Clock Divider
The AD9255 contains an input clock divider with the ability to
divide the input clock by integer values between 2 and 8. For
clock divide ratios of 2, 4, 6, or 8, the duty cycle stabilizer (DCS)
is not required because the output of the divider inherently
produces a 50% duty cycle. Enabling the DCS with the clock
divider in these divide modes may cause a slight degradation in
SNR so disabling the DCS is recommended. For other divide
ratios, divide-by-3, divide-by-5, and divide-by-7 the duty cycle
output from the clock divider is related to the input clock’s duty
cycle. In these modes, if the input clock has a 50% duty cycle, the
DCS is again not required. However, if a 50% duty cycle input
clock is not available the DCS must be enabled for proper part
operation.
To synchronize the AD9255 clock divider, use an external sync
signal applied to the SYNC pin. Bit 1 and Bit 2 of Register 0x100
allow the clock divider to be resynchronized on every SYNC
signal or only on the first SYNC signal after the register is written.
A valid signal at the SYNC pin causes the clock divider to reset
to its initial state. This synchronization feature allows multiple
parts to have their clock dividers aligned to guarantee simultaneous input sampling. If the SYNC pin is not used, it should be
tied to AGND.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to
jitter (tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( SNRLF /10) ]
In this equation, the rms aperture jitter represents the clock
input jitter specification. IF undersampling applications are
particularly sensitive to jitter, as illustrated in Figure 80.
Rev. D | Page 30 of 44
Data Sheet
AD9255
80
0.20
0.5
0.05ps
75
IAVDD
0.16
0.4
SNR (dBc)
70
0.20ps
65
60
0.50ps
55
1.00ps
0.3
0.12
TOTAL
POWER
0.2
0.08
0.1
0.04
SUPPLY CURRENT (A)
TOTAL POWER (W)
MEASURED
IDRVDD
75
0
125
100
08505-179
50
CLOCK FREQUENCY (MSPS)
Figure 80. SNR vs. Input Frequency and Jitter
Refer to AN-501 Application Note, Aperture Uncertainty and ADC
System Performance, and AN-756 Application Note, Sampled
Systems and the Effects of Clock Phase Noise and Jitter (see
www.analog.com) for more information about jitter performance
as it relates to ADCs.
0.20
0.4
0.16
IAVDD
TOTAL POWER (W)
Treat the clock input as an analog signal in cases in which
aperture jitter may affect the dynamic range of the AD9255. To
avoid modulating the clock signal with digital noise, separate
power supplies for clock drivers from the ADC output driver
supplies. Low jitter, crystal controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), the output clock should
be retimed by the original clock at the last step.
0.12
0.3
TOTAL
POWER
0.08
0.2
SUPPLY CURRENT (A)
Figure 81. AD9255-125 Power and Current vs. Sample Rate
0.5
0.04
0.1
IDRVDD
0
25
35
45
55
65
75
85
95
0
105
08505-180
1k
CLOCK FREQUENCY (MSPS)
POWER DISSIPATION AND STANDBY MODE
Figure 82. AD9255-105 Power and Current vs. Sample Rate
The maximum DRVDD current (IDRVDD) can be approximately
calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (14 output bits plus
one DCO).
TOTAL POWER (W)
As shown in Figure 81, the power dissipated by the AD9255 is
proportional to its sample rate. In CMOS output mode, the digital
power dissipation is determined primarily by the strength of the
digital drivers and the load on each output bit.
0.5
0.15
0.4
0.12
IAVDD
0.09
0.3
TOTAL
POWER
0.06
0.2
0.03
0.1
This maximum current occurs when every output bit switches on
every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is established
by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog
input signal.
Reducing the capacitive load presented to the output drivers
can minimize digital power consumption. The data in Figure 81,
Figure 82, and Figure 83 was taken using a 70 MHz analog input
signal, with a 5 pF load on each output driver.
SUPPLY CURRENT (A)
10
100
INPUT FREQUENCY (MHz)
IDRVDD
0
25
35
45
55
65
75
0
ENCODE FREQUENCY (MSPS)
08505-181
1
0
25
08505-053
50
1.50ps
Figure 83. AD9255-80 Power and Current vs. Sample Rate
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9255 is placed in power-down
mode. In this state, the ADC typically dissipates 0.05 mW.
During power-down, the output drivers are placed in a high
impedance state; asserting the PDWN pin low returns the
AD9255 to its normal operating mode.
Rev. D | Page 31 of 44
AD9255
Data Sheet
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to
normal operation.
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. In addition, when using the SPI
mode, the user can change the function of the external PDWN pin
to either place the part in power-down or standby mode. See the
Memory Map Register Descriptions section for more details.
Digital Output Enable Function (OEB)
DIGITAL OUTPUTS
The AD9255 output drivers can be configured to interface with
1.8 V CMOS logic families. The AD9255 can also be configured
for LVDS outputs using a DRVDD supply voltage of 1.8 V. The
AD9255 defaults to CMOS output mode but can be placed into
LVDS mode either by setting the LVDS pin high or by using the
SPI port to place the part into LVDS mode. Because most users do
not toggle between CMOS and LVDS mode during operation, use
of the LVDS pin is recommended to avoid any power-up loading
issues on the CMOS configured outputs.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies, which may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
In LVDS output mode, two output drive levels can be selected,
either ANSI LVDS or reduced swing LVDS mode. Using the
reduced swing LVDS mode lowers the DRVDD current and
reduces power consumption. The reduced swing LVDS mode
can be selected by asserting the LVDS_RS pin or by selecting
this mode via the SPI port.
The output data format is selected for either offset binary or
twos complement by setting the SCLK/DFS pin when operating in
the external pin mode (see Table 12).
As detailed in AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Voltage
at Pin
AGND
SVDD
SCLK/DFS
Offset binary (default)
Twos complement
SDIO/DCS
DCS disabled
DCS enabled (default)
The AD9255 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the OEB pin or
through the SPI interface. If the OEB pin is low, the output data
drivers and DCOs are enabled. If the OEB pin is high, the output
data drivers and DCOs are placed in a high impedance state. This
OEB function is not intended for rapid access to the data bus.
Note that OEB is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
When using the SPI interface, the data and DCO outputs can be
three-stated by using the output enable bar bit in Register 0x14.
TIMING
The AD9255 provides latched data with a pipeline delay of
12 clock cycles (12.5 clock cycles in LVDS mode). Data outputs
are available one propagation delay (tPD) after the rising edge of
the clock signal.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9255. These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9255 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9255 provides a single data clock output (DCO) pin in
CMOS output mode and two differential data clock output (DCO)
pins in LVDS mode intended for capturing the data in an
external register. In CMOS output mode, the data outputs are
valid on the rising edge of DCO, unless the DCO clock polarity
has been changed via the SPI. In LVDS output mode, data is
output as double data rate with the odd numbered output bits
transitioning near the rising edge of DCO and the even numbered
output bits transitioning near the falling edge of DCO. See
Figure 2 for a graphical timing description.
Table 13. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −VREF − 0.5 LSB
= −VREF
=0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Rev. D | Page 32 of 44
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
OR
1
0
0
0
1
Data Sheet
AD9255
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9255 includes built-in self-test features designed to
enable verification of the integrity of the part as well as facilitate
board level debugging. A built-in self-test (BIST) feature is
included that verifies the integrity of the digital datapath of the
AD9255. Various output test options are also provided to place
predictable values on the outputs of the AD9255.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9255 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs for
512 cycles and stops. The BIST signature value is placed in
Register 0x24 and Register 0x25.
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the part configuration.
OUTPUT TEST MODES
The output test options are shown in Table 17. When an output
test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting, and some are not. The seed value for
the PN sequence tests can be forced if the PN reset bits are used to
hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored), but
they do require an encode clock. For more information, see
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
Rev. D | Page 33 of 44
AD9255
Data Sheet
SERIAL PORT INTERFACE (SPI)
The AD9255 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
gives the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and can
be written to, or read from, via the port. Memory is organized into
bytes that can be further divided into fields, which are documented
in the Memory Map section. For detailed operational
information, see AN-877Application Note, Interfacing to High
Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK/DFS pin, the
SDIO/DCS pin, and the CSB pin (see Table 14). The SCLK/DFS
(a serial clock) is used to synchronize the read and write data
presented from and to the ADC. The SDIO/DCS (serial data
input/output) is a dual-purpose pin that allows data to be sent
and read from the internal ADC memory map registers. The
CSB (chip select bar) is an active low control that enables or
disables the read and write cycles.
Table 14. Serial Port Interface Pins
Pin Mnemonic
SCLK/DFS
SDIO/DCS
CSB
Function
Serial clock. The SCLK function of the pin is for
the serial shift clock input, which is used to
synchronize serial interface reads and writes.
SDIO is the serial data input/output function of
the pin. A dual-purpose pin that typically
serves as an input or an output, depending on
the instruction being sent and the relative
position in the timing frame.
Chip select bar. An active low control that
gates the read and write cycles.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. See Figure 84
and Table 5 for an example of the serial timing and its definitions.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes
to allow for additional external timing. When CSB is tied high
at power-up, SPI functions are placed in high impedance mode.
This mode turns on any SPI pin secondary functions. When
CSB is toggled low after power-up, the part remains in SPI
mode and does not revert back to pin mode.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
All data is composed of 8-bit words. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. This allows the serial
data input/output (SDIO) pin to change direction from an
input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a
readback operation, performing a readback causes the serial
data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 14 comprise the physical interface
between the user programming device and the serial port of the
AD9255. When using the SPI interface, the SCLK pin and the
CSB pin function as inputs. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The AD9255 has a separate supply pin for the SPI interface,
SVDD. The SVDD pin can be set at any level between 1.8 V and
3.3 V to enable operation with a SPI bus at these voltages
without requiring level translation. If the SPI port is not used,
SVDD
can be tied to the DRVDD voltage.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in AN-812 Application Note, MicrocontrollerBased Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9255 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are tied to AVDD or ground during
device power-on, they are associated with a specific function.
The Digital Outputs section describes the alternate functions
that are supported on the AD9255.
Rev. D | Page 34 of 44
Data Sheet
AD9255
CONFIGURATION WITHOUT THE SPI
SPI ACCESSIBLE FEATURES
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin and the SCLK/DFS pin serve as standalone
CMOS-compatible control pins. When the device is powered
up, it is assumed that the user intends to use the pins as static
control lines for the duty cycle stabilizer and output data
format feature control. In this mode, connect the CSB chip
select to AVDD, which disables the serial port interface.
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in AN-877 Application Note, Interfacing to High Speed ADCs via
SPI. The AD9255 part-specific features are described in detail
following Table 17, the external memory map register table.
Table 16. Features Accessible Using the SPI
Feature Name
Mode
The OEB pin, the DITHER pin, the LVDS pin, the LVDS_RS
pin, and the PDWN pin are active control lines in both external
pin mode and SPI mode. The input from these pins or the SPI
register setting (the logical OR of the SPI bit and the pin function)
is used to determine the mode of operation for the part.
Clock
Offset
Table 15. Mode Selection
External
Voltage
SVDD (default)
AGND
SVDD
AGND (default)
DRVDD
AGND (default)
AVDD
Pin
SDIO/DCS
SCLK/DFS
OEB
PDWN
AGND (default)
AGND (default)
AVDD
AGND (default)
AVDD
LVDS
LVDS_RS
DITHER
AGND (default)
AVDD
Test I/O
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Chip in power-down or
standby mode
Normal operation
CMOS output mode
LVDS output mode
ANSI LVDS output levels
Reduced swing LVDS
output levels
Dither disabled
Dither enabled
tHIGH
tDS
tS
tDH
Output Mode
Output Phase
Output Delay
VREF
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS, set the
clock divider, set the clock divider phase, and
enable the SYNC input
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set the output mode
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
tCLK
tH
tLOW
CSB
SCLK DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
08505-055
SDIO DON’T CARE
DON’T CARE
Figure 84. Serial Port Interface Timing Diagram
Rev. D | Page 35 of 44
AD9255
Data Sheet
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into four sections: the chip
configuration registers (Address 0x00 to Address 0x02); the
transfer register (Address 0xFF); the ADC functions registers,
including setup, control, and test (Address 0x08 to Address 0x30);
and the digital feature control registers (Address 0x100).
The memory map register table (see Table 17) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading, Bit 7 (MSB), is the start of the
default hexadecimal value given. For example, Address 0x18, the
VREF select register, has a hexadecimal default value of 0xC0. This
means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This
setting is the default reference selection setting. The default value
uses a 2.0 V p-p reference. For more information on this function
and others, see AN-877 Application Note, Interfacing to High
Speed ADCs via SPI. This document details the functions
controlled by Register 0x00 to Register 0x30. The remaining
register, at Register 0x100, is documented in the Memory Map
Register Descriptions section.
Open Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is open
(for example, Address 0x18). If the entire address location is
open (for example, Address 0x13), this address location should not
be written.
Default Values
After the AD9255 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 17.
Logic Levels
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and the bit autoclears.
Rev. D | Page 36 of 44
Data Sheet
AD9255
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Addr. Register
(Hex)
Name
Bit 7 (MSB)
Chip Configuration Registers
0x00
SPI port
0
configuration
0x01
0x02
Chip ID
Chip grade
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value
(Hex)
LSB first
Soft reset
1
1
Soft reset
LSB
first
0
0x18
Open
Open
Open
Transfer
8-Bit Chip ID[7:0], AD9255 = 0x65 (default)
Speed grade ID
Open Open
01 = 125 MSPS
10 = 105 MSPS
11 = 80 MSPS
Open
Open
Open
Open
Open
Open
Open
Open
ADC Functions Registers
0x08
Power
1
modes
Open
External powerdown pin
function
0 = powerdown
1 = standby
Open
Open
Open
0x09
Global clock
Open
Open
Open
Open
Open
0x0B
Clock divide
(global)
Open
Open
Open
Open
Open
0x0D
Test mode
Open
Open
Reset PN23
generator
Reset PN9
generator
Open
0x0E
BIST enable
Open
Open
Open
Open
Open
Transfer Register
0xFF
Transfer
Rev. D | Page 37 of 44
0x65
Internal
power-down
mode
00 = normal
operation
01 = full powerdown
10 = standby
11 = normal
operation
Open
Open
Duty
cycle
stabilizer
(default)
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating checkerboard
101 = PN 23 sequence
110 = PN 9 sequence
111 = one/zero word toggle
Reset BIST Open
BIST
sequence
enable
Default Notes/
Comments
The nibbles are
mirrored so
LSB-first mode
or MSB-first
mode registers
correctly,
regardless of
shift mode
Read only
Speed grade ID
used to
differentiate
devices; read
only
0x00
Synchronously
transfers data
from the
master shift
register to the
slave
0x80
Determines
various generic
modes of chip
operation
0x01
0x00
Clock divide
values other
than 000
automatically
cause the duty
stabilizer to
become active.
0x00
When this
register is set,
the test data is
placed on the
output pins in
place of normal
data
0x04
AD9255
Addr.
(Hex)
0x14
Register
Name
Output
mode
0x16
Data Sheet
Bit 7 (MSB)
Drive
strength
0 = ANSI
LVDS
1 = reduced
LVDS
Bit 6
Output
type
0=
CMOS
1 = LVDS
Bit 5
Open
Bit 4
Output
enable
bar
Bit 3
Open
Clock phase
control
Invert DCO
clock
Open
Open
Open
Open
0x17
DCO output
delay
Open
Open
Open
0x18
VREF select
Reference voltage
selection
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p (default)
BIST
signature LSB
0x25
BIST
signature
MSB
0x30
Dither
Open
enable
Digital Feature Control Register
0x100 Sync control
Open
Open
0x24
Open
Open
Open
Open
Open
Bit 2
Output
invert
Bit 1
Bit 0 (LSB)
Output
format
00 = offset
binary
01 = twos
complement
01 = gray code
11 = offset binary
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO clock delay
(delay = 2500 ps × register value/31)
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
Open Open
Open
Open
Default
Value
(Hex)
0x00
0x00
Default Notes/
Comments
Configures the
outputs and
the format of
the data
Allows
selection of
clock delays
into the input
clock divider
0x00
0xC0
BIST Signature[7:0]
0x00
Read only
BIST Signature[15:8]
0x00
Read only
Dither
enable
Open
Open
Open
Open
Open
0x00
Open
Clock
divider
next sync
only
Clock
divider
sync
enable
Master
sync
enable
0x00
Rev. D | Page 38 of 44
Data Sheet
AD9255
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
and to ignore the rest. The clock divider sync enable bit
(Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bits[7:3]—Reserved
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
These bits are reserved.
Bit 0—Master Sync Enable
Bit 2—Clock Divider Next Sync Only
Bit 0 must be high to enable any of the sync functions. If the
sync capability is not used, this bit should remain low to
conserve power.
Sync Control (Register 0x100)
If the master sync enable bit (Address 0x100, Bit 0) and the
clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2
allows the clock divider to sync to the first sync pulse it receives
Rev. D | Page 39 of 44
AD9255
Data Sheet
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9255 as a system, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements that are needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9255, it is recommended
that two separate 1.8 V supplies be used. Use one supply for analog
(AVDD); use a separate supply for the digital outputs (DRVDD).
Several different decoupling capacitors can be used to cover
both high and low frequencies. Locate these capacitors close to
the point of entry at the PCB level and close to the pins of the
part, with minimal trace length. The power supply for the SPI
port, SVDD, should not contain excessive noise and should also be
bypassed close to the part.
A single PCB ground plane should be sufficient when using the
AD9255. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
LVDS Operation
should have several vias to achieve the lowest possible resistive
thermal path for heat dissipation to flow through the bottom of
the PCB. Fill or plug these vias with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, overlay a silkscreen to partition the continuous plane on
the PCB into several uniform sections. This provides several tie
points between the ADC and the PCB during the reflow process.
Using one continuous plane with no partitions guarantees only
one tie point between the ADC and the PCB. For detailed
information about packaging and PCB layout of chip scale
packages, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), at www.analog.com.
VCM
Decouple the VCM pin to ground with a 0.1 μF capacitor, as
shown in Figure 67.
RBIAS
The AD9255 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
The AD9255 can be configured for CMOS or LVDS output mode
on power-up using the LVDS pin, Pin 44. If LVDS operation is
desired, connect Pin 44 to AVDD. LVDS operation can also be
enabled through the SPI port. If CMOS operation is desired,
connect Pin 44 to AGND.
Reference Decoupling
Exposed Paddle Thermal Heat Slug Recommendations
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9255 to keep these signals from transitioning at the converter
inputs during critical sampling periods.
It is mandatory that the exposed paddle on the underside of the
ADC be connected to the analog ground (AGND) to achieve
the best electrical and thermal performance. A continuous,
exposed (no solder mask) copper plane on the PCB should
mate to the AD9255 exposed paddle, Pin 0. The copper plane
Decouple the VREF pin externally to ground with a low ESR,
1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic
capacitor.
SPI Port
Rev. D | Page 40 of 44
Data Sheet
AD9255
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
7.10
7.00 SQ
6.90
37
36
48
1
0.50
BSC
5.65
5.50 SQ
5.35
EXPOSED
PAD
TOP VIEW
PKG-003641/004499
0.80
0.75
0.70
END VIEW
SEATING
PLANE
0.45
0.40
0.35
24
P IN 1
IN D IC ATO R AR E A OP T I O N S
(SEE DETAIL A)
13
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.20 MIN
5.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD
10-10-2018-B
PIN 1
INDICATOR
AREA
0.30
0.23
0.18
Figure 85. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9255BCPZ-125
AD9255BCPZRL7-125
AD9255BCPZ-105
AD9255BCPZRL7-105
AD9255BCPZ-80
AD9255BCPZRL7-80
AD9255-125EBZ
AD9255-105EBZ
AD9255-80EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Rev. D | Page 41 of 44
Package Option
CP-48-9
CP-48-9
CP-48-9
CP-48-9
CP-48-9
CP-48-9
AD9255
Data Sheet
NOTES
Rev. D | Page 42 of 44
Data Sheet
AD9255
NOTES
Rev. D | Page 43 of 44
AD9255
Data Sheet
NOTES
©2009–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08505-9/20(D)
Rev. D | Page 44 of 44
工商网监
湘ICP备2023018690号
