AD9260AS

High Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate AD9260 STAGE 1:2X 16-BIT: DECIMATION 10MHz FILTER REFERENCE BUFFER DRVDD DRVSS DIGITAL DEMODULATOR 12-BIT: 20MHz AD9260 STAGE 2:2X 16-BIT: DECIMATION 5MHz FILTER OTR 16-BIT: STAGE 3:2X 2.5MHz DECIMATION FILTER VREF SENSE REFCOM BANDGAP REFERENCE DAV BIAS CIRCUIT CLOCK BUFFER MODE REGISTER BIAS ADJUST CLK MODE READ PRODUCT DESCRIPTION The AD9260 is a 16-bit, high-speed oversampled analog-todigital converter (ADC) that offers exceptional dynamic range over a wide bandwidth. The AD9260 is manufactured on an advanced CMOS process. High dynamic range is achieved with an oversampling ratio of 8× through the use of a proprietary technique that combines the advantages of sigma-delta and pipeline converter technologies. The AD9260 is a switchedcapacitor ADC with a nominal full-scale input range of 4 V. It offers a differential input with 60 dB of common-mode rejection of common-mode signals. The signal range of each differential input is ±1 V centered on a 2.0 V common-mode level. The on-chip decimation filter is configured for maximum performance and flexibility. A series of three half-band FIR filter stages provide 8× decimation filtering with 85 dB of stopband attenuation and 0.004 dB of pass-band ripple. An onboard digital multiplexer allows the user to access data from the various stages of the decimation filter. The on-chip programmable reference and reference buffer amplifier are configured for maximum accuracy and flexibility. An external reference can also be chosen to suit the user’s specific dc accuracy and drift requirements. The AD9260 operates on a single +5 V supply, typically consuming 585 mW of power. A power scaling circuit is provided allowing the AD9260 to operate at power consump- BIT1– BIT16 CS 00581-C-001 REF TOP REF BOTTOM COMMON MODE AVSS AVDD AVSS MULTIBIT SIGMA-DELTA MODULATOR OUTPUT REGISTER VINB RESET/ SYNC DVSS DVDD OUTPUT MODE MULTIPLEXER VINA AVSS AVDD Monolithic 16-bit, oversampled A/D converter 8× oversampling mode, 20 MSPS clock 2.5 MHz output word rate 1.01 MHz signal passband with 0.004 dB ripple Signal-to-noise ratio: 88.5 dB Total harmonic distortion: –96 dB Spurious-free dynamic range: 100 dB Input referred noise: 0.6 LSB Selectable oversampling ratio: 1×, 2×, 4×, 8× Selectable power dissipation: 150 mW to 585 mW 85 dB stop-band attenuation 0.004 dB pass-band ripple Linear phase Single 5 V analog supply, 5 V/3 V digital supply Synchronize capability for parallel ADC interface Twos complement output data 44-lead MQFP AVDD FUNCTIONAL BLOCK DIAGRAM FEATURES Figure 1. tion levels as low as 150 mW at reduced clock and data rates. The AD9260 is available in a 44-lead MQFP package and is specified to operate over the industrial temperature range. PRODUCT HIGHLIGHTS The AD9260 is fabricated on a very cost effective CMOS process. High speed, precision, mixed-signal analog circuits are combined with high density digital filter circuits. The AD9260 offers a complete single-chip 16-bit sampling ADC with a 2.5 MHz output data rate in a 44-lead MQFP. Selectable Internal Decimation Filtering—The AD9260 provides a high performance decimation filter with 0.004 dB pass-band ripple and 85 dB of stop-band attenuation. The filter is configurable with options for 1×, 2×, 4×, and 8× decimation. Power Scaling—The AD9260 consumes a low 585 mW of power at 16-bit resolution and 2.5 MHz output data rate. Its power can be scaled down to as low as 150 mW at reduced clock rates. Single Supply—Both the analog and digital portions of the AD9260 can operate off of a single +5 V supply, simplifying system power supply design. The digital logic will also accommodate a single +3 V supply for reduced power. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD9260 TABLE OF CONTENTS Specifications..................................................................................... 3 Theory of Operation ...................................................................... 23 Clock Input Frequency Range .................................................... 3 Analog Input and Reference Overview ....................................... 24 DC Specifications ......................................................................... 3 Input Span ................................................................................... 24 AC Specifications.......................................................................... 4 Input Compliance Range........................................................... 24 Digital Filter Characteristics ....................................................... 6 Analog Input Operation ............................................................ 24 Digital Filter Characteristics ....................................................... 7 Driving the Input........................................................................ 25 Digital Specifications ................................................................... 9 Reference Operation ...................................................................... 28 Switching Specifications ............................................................ 10 Digital Inputs and Outputs ........................................................... 30 Absolute Maximum Ratings.......................................................... 11 Digital Outputs ........................................................................... 30 Thermal Characteristics ............................................................ 11 Mode Operation ......................................................................... 31 ESD Caution................................................................................ 11 Bias Pin Operation ..................................................................... 32 Terminology .................................................................................... 12 Power Dissipation Considerations ............................................... 33 Pin Configuration and Function Descriptions........................... 13 Digital Output Driver Considerations (DRVDD) ................. 33 Typical Performance Characteristics ........................................... 14 Grounding and Decoupling...................................................... 34 Typical AC Characterization Curves vs. Decimation Mode ................................................................. 15 Evaluation Board General Description ....................................... 36 Typical AC Characterization Curves for 8× Mode ................ 16 Typical AC Characterization Curves for 4× Mode ................ 17 Typical AC Characterization Curves for 2× Mode ................ 18 Typical AC Characterization Curves for 1× Mode ................ 19 Typical AC Characterization Curves ....................................... 20 Features and User Controls....................................................... 36 Shipment Configuration............................................................ 37 Quick Setup................................................................................. 37 Application Information ........................................................... 38 Outline Dimensions ....................................................................... 43 Ordering Guide .......................................................................... 43 Additional AC Characterization Curves ................................. 21 REVISION HISTORY 7/04—Changed from Rev. B to Rev. C Changed “trimpot” to “variable resistor” ..................... Universal Updated Format................................................................ Universal Updated Outline Dimensions ......................................................43 Changes to Ordering Guide .........................................................43 5/00—Changed from Rev. A to Rev. B. 1/98—Changed from Rev. 0 to Rev. A. Rev. C | Page 2 of 44 AD9260 SPECIFICATIONS CLOCK INPUT FREQUENCY RANGE Table 1. Parameter—Decimation Factor (N) CLOCK INPUT (Modulator Sample Rate, fCLOCK) OUTPUT WORD RATE (FS = fCLOCK/N) AD9260 (8) 1 20 0.125 2.5 AD9260 (4) 1 20 0.250 5 AD9260 (2) 1 20 0.500 10 AD9260 (1) 1 20 1 20 Unit kHz min MHz max kHz min MHz max DC SPECIFICATIONS AVDD = +5 V, DVDD = +3 V, DRVDD = +3 V, fCLOCK = 20 MSPS, VREF = +2.5 V, Input CML = 2.0 V TMIN to TMAX unless otherwise noted, RBIAS = 2 kΩ. Table 2. Parameter—Decimation Factor (N) RESOLUTION INPUT REFERRED NOISE (TYP) 1.0 V Reference 2.5 V Reference1 ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) No Missing Codes Offset Error Gain Error2 Gain Error3 TEMPERATURE DRIFT Offset Error Gain Error2 Gain Error3 POWER SUPPLY REJECTION AVDD, DVDD, DRVDD (+5 V ±0.25 V) ANALOG INPUT Input Span VREF= 1.0 V VREF= 2.5 V Input (VINA or VINB) Range Input Capacitance INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Output Voltage Error (1 V Mode) Output Voltage (2.5 V Mode) Output Voltage Error (2.5 V Mode) Load Regulation4 1 V REF 2.5 V REF REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD AD9260 (8) 16 AD9260 (4) 16 AD9260 (2) 16 AD9260 (1) 12 Unit Bits min 1.40 0.68 (90.6) 2.4 1.2 (86) 6.0 3.7 (76) 1.3 1.0 (63.2) LSB rms typ LSB rms typ (dB typ) ± 0.75 ± 0.50 16 0.9 (0.5) 2.75 (0.66) 1.35 (0.7) ± 0.75 ± 0.50 16 (0.5) (0.66) (0.7) ± 0.75 ± 0.50 16 (0.5) (0.66) (0.7) ± 0.3 ± 0.25 12 (0.5) (0.66) (0.7) LSB typ LSB typ Bits Guaranteed % FSR max (typ @ +25°C) % FSR max (typ @ +25°C) % FSR max (typ @ +25°C) 2.5 22 7.0 2.5 22 7.0 2.5 22 7.0 2.5 22 7.0 ppm/°C typ ppm/°C typ ppm/°C typ 0.06 0.06 0.06 0.06 % FSR max 1.6 4.0 +0.5 +AVDD –0.5 10.2 1.6 4.0 +0.5 +AVDD –0.5 10.2 1.6 4.0 +0.5 +AVDD –0.5 10.2 1.6 4.0 +0.5 +AVDD –0.5 10.2 V p p Diff. max V p p Diff. max V min V max pF typ 1 ± 14 2.5 ± 35 1 ± 14 2.5 ± 35 1 ± 14 2.5 ± 35 1 ± 14 2.5 ± 35 V typ mV max V typ mV max 0.5 2.0 8 0.5 2.0 8 0.5 2.0 8 0.5 2.0 8 mV max mV max kΩ +5 +5 +5 +5 V (± 5%) Rev. C | Page 3 of 44 AD9260 Parameter—Decimation Factor (N) DVDD and DRVDD Supply Current IAVDD IDVDD IDRVDD POWER CONSUMPTION AD9260 (8) +5.5 +2.7 AD9260 (4) +5.5 +2.7 AD9260 (2) +5.5 +2.7 AD9260 (1) +5.5 +2.7 Unit V max V min 115 115 115 12.5 10.3 6.5 0.450 613 0.850 608 1.7 600 115 134 2.4 3.5 2.6 585 630 mA typ mA max mA typ mA max mA typ mW typ mW max 1 VINA and VINB connect to DUT CML. Including Internal 2.5 V reference. 3 Excluding Internal 2.5 V reference. 4 Load regulation with 1 mA load current (in addition to that required by AD9260). 2 AC SPECIFICATIONS AVDD = +5 V, DVDD = +3 V, DRVDD = +3 V, fCLOCK = 20 MSPS, VREF = +2.5 V, Input CML = 2.0 V TMIN to TMAX unless otherwise noted, RBIAS = 2 kΩ. Table 3. Parameter—Decimation Factor (N) DYNAMIC PERFORMANCE INPUT TEST FREQUENCY: 100 kHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS INPUT TEST FREQUENCY: 500 kHz Signal to Noise Ratio (SNR) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS AD9260(8) AD9260(4) AD9260(2) AD9260(1) Unit 88.5 82.5 82 78 74 68 63 58 dB typ dB typ 87.5 82 82 77.5 74 69 63 58 dB typ dB typ –96 –93 –96 –98 –97 –96 –98 –98 dB typ dB typ 100 94 98 100 98 94 88 84 dB typ dB typ 86.5 80.5 82.5 82 74 63 77 68 58 dB typ dB min dB typ 86.0 80.0 82.0 81 74 63 77 68 58 –97.0 –90.0 –95.5 –92 –89 –86 –96 –89 –86 99.0 90.0 92 91 88 Rev. C | Page 4 of 44 dB typ dB min dB typ dB typ dB max dB typ dB typ dB max AD9260 Parameter—Decimation Factor (N) Input Amplitude = –6.0 dBFS INPUT TEST FREQUENCY: 1.0 MHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS INPUT TEST FREQUENCY: 2.0 MHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS INPUT TEST FREQUENCY: 5.0 MHz (typ) Signal-to-Noise Ratio (SNR) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS SNR and Distortion (SINAD) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS Total Harmonic Distortion (THD) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS Spurious-Free Dynamic Range (SFDR) Input Amplitude = –0.5 dBFS Input Amplitude = –6.0 dBFS INTERMODULATION DISTORTION fIN1 = 475 kHz, fIN2 = 525 kHz fIN1 = 950 kHz, fIN2 = 1.050 MHz DYNAMIC CHARACTERISTICS Full Power Bandwidth Small Signal Bandwidth (AIN = –20 dBFS) Aperture Jitter AD9260(8) 98 AD9260(4) 100 AD9260(2) 91 AD9260(1) 82 Unit dB typ 85 80 82 76 74 68 63 58 dB typ dB typ 84.5 80 81 76 74 69 63 58 dB typ dB typ –102 –96 –96 –94 –82 –84 –79 –77 dB typ dB typ 105 98 98 96 83 87 80 80 dB typ dB typ 82 76 74 68 63 58 dB typ dB typ 81 76 73 69 62 58 dB typ dB typ –101 –95 –80 –80 –75 –76 dB typ dB typ 104 100 80 83 78 79 dB typ dB typ 59 57 dB typ dB typ 58 57 dB typ dB typ –58 –67 dB typ dB typ 59 70 dB typ dB typ –93 –95 –91 –86 –91 –85 –83 –83 dBFS typ dBFS typ 75 75 2 75 75 2 75 75 2 75 75 2 MHz typ MHz typ ps rms typ Rev. C | Page 5 of 44 AD9260 DIGITAL FILTER CHARACTERISTICS Table 4. Parameter 8× DECIMATION (N = 8) Pass-Band Ripple Stop-Band Attenuation Pass-Band Stop-Band Pass-Band/Transition Band Frequency (–0.1 dB Point) (–3.0 dB Point) Absolute Group Delay1 Group Delay Variation Settling Time (to ± 0.0007%)1 4× DECIMATION (N = 4) Pass-Band Ripple Stop-Band Attenuation Pass-Band Stop-Band Pass-Band/Transition Band Frequency (–0.1 dB Point) (–3.0 dB Point) Absolute Group Delay1 Group Delay Variation Settling Time (to ± 0.0007%)1 2× DECIMATION (N = 2) Pass-Band Ripple Stop-Band Attenuation Pass-Band Stop-Band Pass-Band/Transition Band Frequency (–0.1 dB Point) (–3.0 dB Point) Absolute Group Delay1 Group Delay Variation Settling Time (to ± 0.0007%)1 1× DECIMATION (N = 1) Propagation Delay: tPROP Absolute Group Delay 1 AD9260 Unit 0.00125 82.5 0 0.605 × (fCLOCK/20 MHz) 1.870 × (fCLOCK/20 MHz) 18.130 × (fCLOCK/20 MHz) dB max dB min MHz min MHz max MHz min MHz max 0.807 × (fCLOCK/20 MHz) 1.136 × (fCLOCK/20 MHz) 13.55 × (20 MHz/fCLOCK) 0 24.2 × (20 MHz/fCLOCK) MHz max MHz max µs max µs max µs max 0.001 82.5 0 1.24 × (fCLOCK/20 MHz) 3.75 × (fCLOCK/20 MHz) 16.25 × (fCLOCK/20 MHz) dB max dB min MHz min MHz max MHz min MHz max 1.61 × (fCLOCK/20 MHz) 2.272 × (fCLOCK/20 MHz) 2.90 × (20 MHz/fCLOCK) 0 5.05 × (20 MHz/fCLOCK) MHz max MHz max µs max µs max µs max 0.0005 85.5 0 2.491 × (fCLOCK/20 MHz) 7.519 × (fCLOCK/20 MHz) 12.481 × (fCLOCK/20 MHz) dB max dB min MHz min MHz max MHz min MHz max 3.231 × (fCLOCK/20 MHz) 4.535 × (fCLOCK/20 MHz) 0.80 × (20 MHz/fCLOCK) 0 1.40 × (20 MHz/fCLOCK) MHz max MHz max µs max µs max µs max 13 (225 × (20 MHz/fCLOCK)) + tPROP ns max ns max To determine overall Absolute Group Delay and/or Settling Time inclusive of delay from the sigma-delta modulator, add Absolute Group Delay and/or Settling Time pertaining to specific decimation mode to the Absolute Group Delay specified in 1 ×decimation. Rev. C | Page 6 of 44 AD9260 DIGITAL FILTER CHARACTERISTICS 0 –40 –60 –80 –120 0 0.2 0.4 0.6 0.8 1.0 1.2 FREQUENCY (NORMALIZED TO π) 0.6 0.4 0.2 0 –0.2 –0.4 00581-C-002 –100 0.8 0 100 Figure 2. 8x FIR Filter Frequency Response 400 500 600 –40 –60 –80 –120 0 0.2 0.4 0.6 0.8 1.0 1.2 FREQUENCY (NORMALIZED TO π) 0.6 0.4 0.2 0 –0.2 00581-C-003 –100 0.8 0 10 20 30 40 50 60 70 80 90 100 110 CLOCK PERIODS (RELATIVE TO CLK) Figure 3. 4x FIR Filter Frequency Response 00581-C-006 NORMALIZED OUTPUT RESPONSE 1.0 –20 MAGNITUDE (dB) 300 Figure 5. 8x FIR Filter Impulse Response 0 Figure 6. 4x FIR Filter Impulse Response 1.0 NORMALIZED OUTPUT RESPONSE 0 –20 –40 –60 –80 –100 –120 0 0.2 0.4 0.6 0.8 1.0 FREQUENCY (NORMALIZED TO π) 1.2 00581-C-004 MAGNITUDE (dB) 200 CLOCK PERIODS (RELATIVE TO CLK) Figure 4. 2x FIR Filter Frequency Response 0.8 0.6 0.4 0.2 0 –0.2 0 5 10 15 20 CLOCK PERIODS (RELATIVE TO CLK) Figure 7. 2x FIR Filter Impulse Response Rev. C | Page 7 of 44 25 00581-C-007 MAGNITUDE (dB) –20 00581-C-005 NORMALIZED OUTPUT RESPONSE 1.0 AD9260 Table 5. Integer Filter Coefficients for First Stage Decimation Filter (23-Tap Half-Band FIR Filter) Table 7. Integer Filter Coefficients for Third Stage Decimation Filter (107-Tap Half-Band FIR Filter) Lower Coefficient Upper Coefficient Integer Value Lower Coefficient Upper Coefficient Integer Value H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(23) H(22) H(21) H(20) H(19) H(18) H(17) H(16) H(15) H(14) H(13) –1 0 13 0 –66 0 224 0 –642 0 2496 4048 H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(23) H(24) H(25) H(26) H(27) H(28) H(29) H(30) H(31) H(32) H(33) H(34) H(35) H(36) H(37) H(38) H(39) H(40) H(41) H(42) H(43) H(44) H(45) H(46) H(47) H(48) H(49) H(50) H(51) H(52) H(53) H(54) H(107) H(106) H(105) H(104) H(103) H(102) H(101) H(100) H(99) H(98) H(97) H(96) H(95) H(94) H(93) H(92) H(91) H(90) H(89) H(88) H(87) H(86) H(85) H(84) H(83) H(82) H(81) H(80) H(79) H(78) H(77) H(76) H(75) H(74) H(73) H(72) H(71) H(70) H(69) H(68) H(67) H(66) H(65) H(64) H(63) H(62) H(61) H(60) H(59) H(58) H(57) H(56) H(55) –1 0 2 0 –2 0 3 0 –3 0 1 0 3 0 –12 0 27 0 –50 0 85 0 –135 0 204 0 –297 0 420 0 –579 0 784 0 –1044 0 1376 0 –1797 0 2344 0 –3072 0 4089 0 –5624 0 8280 0 –14268 0 43520 68508 Table 6. Integer Filter Coefficients for Second Stage Decimation Filter (43-Tap Half-Band FIR Filter) Lower Coefficient Upper Coefficient Integer Value H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) H(28) H(27) H(26) H(25) H(24) H(23) 3 0 –12 0 35 0 –83 0 172 0 –324 0 572 0 –976 0 1680 0 –3204 0 10274 16274 NOTE: The composite filter undecimated coefficients (i.e., impulse response) in the 4× decimation mode can be determined by convolving the first stage filter taps with a “zero stuffed” version of the second stage filter taps (i.e., insert one zero between samples). Similarly, the composite filter coefficients in the 8× decimation mode can be determined by convolving the taps of the composite 4× decimation mode (as previously determined) with a “zero stuffed” version of the third stage filter taps (i.e., insert three zeros between samples). Rev. C | Page 8 of 44 AD9260 DIGITAL SPECIFICATIONS AVDD = +5 V, DVDD = +5 V, TMIN to TMAX unless otherwise noted. Table 8. Parameter CLOCK1 AND LOGIC INPUTS High Level Input Voltage (DVDD = +5 V) (DVDD = +3 V) Low Level Input Voltage (DVDD = +5 V) (DVDD = +3 V) High Level Input Current (VIN = DVDD) Low Level Input Current (VIN = 0 V) Input Capacitance LOGIC OUTPUTS (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage2 (IOL = 0.3 mA) Low Level Output Voltage (IOL = 50 µA) Output Capacitance LOGIC OUTPUTS (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) Low Level Output Voltage (IOL = 50 µA) 2 Unit +3.5 +2.1 V min V max +1.0 +0.9 ± 10 ± 10 5 V min V max µA max µA max pF typ +4.5 +2.4 +0.4 +0.1 5 V min V min V max V max pF typ +2.4 +0.7 V min V max Since CLK is referenced to AVDD, +5 V logic input levels only apply. The AD9260 is not guaranteed to meet VOL = 0.4 V max for standard TTL load of IOL = 1.6 mA. S2 S1 tC ANALOG INPUT tCL tCH INPUT CLOCK tDI tDS DATA OUTPUT tOE tH DAV tDAV tOD READ 00581-C-008 1 AD9260 CS Figure 8. Timing Diagram Rev. C | Page 9 of 44 AD9260 tRES-DAV tCLK-DAV INPUT CLOCK 00581-C-009 RESET DAV Figure 9. RESET Timing Diagram SWITCHING SPECIFICATIONS AVDD = +5 V, DVDD = +5 V, CL = 20 pF, TMIN to TMAX unless otherwise noted. Table 9. Parameters Clock Period Data Available (DAV) Period Data Invalid Data Set-Up Time Clock Pulse-Width High Clock Pulse-Width Low Data Hold Time RESET to DAV Delay CLOCK to DAV Delay Three-State Output Disable Time Three-State Output Enable Time Symbol tC tDAV tDI tDS tCH tCL tH tRES–DAV tCLK–DAV tOD tOE Rev. C | Page 10 of 44 AD9260 50 tC ×Mode 40% tDAV tDAV –tH –tDI 22.5 22.5 3.5 10 15 8 45 Unit ns min ns min ns max ns min ns min ns min ns min ns typ ns typ ns typ ns typ AD9260 ABSOLUTE MAXIMUM RATINGS Table 10. Parameter AVDD to AVSS DVDD to DVSS AVSS to DVSS AVDD to DVDD DRVDD to DRVSS DRVSS to AVSS REFCOM to AVSS CLK, MODE, READ, CS, and RESET to DVSS Digital Outputs to DRVSS VINA, VINB, CML, and BIAS to AVSS VREF to AVSS SENSE to AVSS CAPB and CAPT to AVSS Junction Temperature Storage Temperature Lead Temperature (10 s) Rating –0.3 V to +6.5 V –0.3 V to +6.5 V –0.3 V to +0.3 V –6.5 V to +6.5 V –0.3 V to +6.5 V –0.3 V to +0.3 V –0.3 V to +0.3 V –0.3 V to DVDD + 0.3 V –0.3 V to DRVDD + 0.3 V –0.3 V to AVDD + 0.3 V –0.3 V to AVDD + 0.3 V –0.3 V to AVDD + 0.3 V –0.3 V to AVDD + 0.3 V 150°C –65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 44-Lead MQFP θJA = 53.2°C/W θJC = 19°C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 11 of 44 AD9260 TERMINOLOGY Integral Nonlinearity (INL) INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 14-bit resolution indicates that all 16384 codes, respectively, must be present over all operating ranges. NOTE: Conventional INL and DNL measurements don’t really apply to ∑∆ converters: the DNL looks continually better if longer data records are taken. For the AD9260, INL and DNL numbers are given as representative. Zero Error The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference and the ideal difference between first and last code transitions. Aperture Jitter Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, it is possible to get a measure of performance expressed as N, the effective number of bits: N = (SINAD − 1.76)/6.02 Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Temperature Drift The temperature drift for zero error and gain error specifies the maximum change from the initial (+25°C) value to the value at TMIN or TMAX. Spurious-Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. Power Supply Rejection The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). Rev. C | Page 12 of 44 AD9260 BIAS 38 MODE 39 CAPT 40 CAPB 41 AVSS 42 NC VINA 43 CML NC 44 VINB AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 37 36 35 34 DVSS 1 AVSS 2 33 REFCOM PIN 1 IDENTIFIER 32 VREF DVDD 3 31 SENSE AVDD 4 30 RESET DRVSS 5 AD9260 29 AVSS DRVDD 6 TOP VIEW (Not to Scale) 28 AVDD CLK 7 27 CS 8 26 DAV (LSB) BIT16 9 25 OTR READ 17 18 19 20 BIT8 BIT7 BIT6 BIT5 21 22 NC = NO CONNECT Figure 10. Pin Configuration Table 11. Pin Function Descriptions Pin No. 1 2, 29, 38 3 4, 28, 44 5 6 7 8 9 10–23 24 25 26 27 30 31 32 33 34 35 36 37 39 40, 43 41 42 Mnemonic DVSS AVSS DVDD AVDD DRVSS DRVDD CLK READ BIT16 BIT15–BIT2 BIT1 OTR DAV CS RESET SENSE VREF REFCOM MODE BIAS CAPB CAPT CML NC VINA VINB Description Digital Ground. Analog Ground. +3 V to +5 V Digital Supply. +5 V Analog Supply. Digital Output Driver Ground. +3 V to +5 V Digital Output Driver Supply. Clock Input. Part of DSP Interface—Pull Low to Disable Output Bits. Least Significant Data Bit (LSB). Data Output Bit. Most Significant Data Bit (MSB). Out of Range—Set When Converter or Filter Overflows. Data Available. Chip Select (CS): Active LOW. RESET: Active LOW. Reference Amplifier SENSE: Selects REF Level. Input Span Select Reference I/O. Reference Common. Mode Select—Selects Decimation Mode. Power Bias. Noise Reduction Pin—Decouples Reference Level. Noise Reduction Pin—Decouples Reference Level. Common-Mode Level (AVDD/2.5). No Connect (Ground for Shielding Purposes). Analog Input Pin (+). Analog Input Pin (–). Rev. C | Page 13 of 44 00581-C-010 16 BIT3 15 BIT4 14 BIT9 13 BIT10 12 BIT11 23 BIT2 BIT12 24 BIT1 (MSB) BIT14 11 BIT13 BIT15 10 AD9260 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = DRVDD = +5.0 V, 4 V Input Span, Differential DC Coupled Input with CML = 2.0 V, fCLOCK = 20 MSPS, Full Bias. 0 100kHz INPUT 20MHz CLOCK 8 × DECIMATION THD: –96dB dB BELOW FULL SCALE –40 –60 –80 –60 –80 –100 –120 –120 0.2 0.4 0.6 0.8 1.0 1.2 FREQUENCY (MHz) 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (MHz) Figure 11. Spectral Plot of the AD9260 at 100 kHz Input, 20 MHz Clock, 8x OSR (2.5 MHz Output Data Rate) Figure 14. Spectral Plot of the AD9260 at 100 kHz Input, 20 MHz Clock, Undecimated (20 MHz Output Data Rate) 0 110 100kHz INPUT 20MHz CLOCK 4 × DECIMATION THD: –98dB –12dBFS/TONE WORST CASE SPUR (dBFS) –20 dB BELOW FULL SCALE –40 –100 0 100kHz INPUT 20MHz CLOCK 1 × DECIMATION THD: –98dB –20 00581-C-011 dB BELOW FULL SCALE –20 00581-C-014 0 –40 –60 –80 –100 106 102 –6.5dBFS/TONE 98 –26dBFS/TONE –46dBFS/TONE 94 0.5 1.0 1.5 2.0 2.5 FREQUENCY (MHz) 90 00581-C-012 0 Figure 12. Spectral Plot of the AD9260 at 100 kHz Input, 20 MHz Clock, 4x OSR (5 MHz Output Data Rate) 0 0.4 0.6 0.8 1.0 FREQUENCY (MHz) Figure 15. Dual-Tone SFDR vs. Input Frequency (F1 = F2, Span = 10% Center Frequency, Mode = 8x) 0 100kHz INPUT 20MHz CLOCK 2 × DECIMATION THD: –98dB –40 –60 –80 –40 –60 –80 –100 –120 –120 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) 00581-C-013 –100 0 DUAL-TONE TEST f1 = 1.0MHz f2 = 975kHz 20MHz CLOCK 8 × DECIMATION IM3: –94dB –20 dB BELOW FULL SCALE –20 Figure 13. Spectral Plot of the AD9260 at 100 kHz Input, 20 MHz Clock, 2x OSR (10 MHz Output Data Rate) Rev. C | Page 14 of 44 0 0.2 0.4 0.6 0.8 FREQUENCY (MHz) 1.0 1.2 00581-C-016 0 dB BELOW FULL SCALE 0.2 00581-C-015 –120 Figure 16. Two-Tone Spectral Performance of the AD9260 Given Inputs at 975 kHz and 1.0 MHz, 20 MHz Clock, 8x Decimation AD9260 TYPICAL AC CHARACTERIZATION CURVES VS. DECIMATION MODE AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, AIN = 0.5 dBFS Full Bias. 90 90 8 × MODE 75 80 2 × MODE 70 65 75 2 × MODE 70 65 1 × MODE 60 60 1 × MODE 10.0 INPUT FREQUENCY (MHz) 50 0.1 1.0 10.0 INPUT FREQUENCY (MHz) Figure 17. SINAD vs. Input Frequency (fCLOCK = 20 MSPS) 8x SINAD performance limited by noise contribution of input differential op amp driver 00581-C-020 1.0 55 00581-C-017 55 50 0.1 8 × MODE 4 × MODE 4 × MODE 80 SINAD (dBFS) 85 SINAD (dBFS) 85 Figure 20. SINAD vs. Input Frequency (fCLOCK = 10 MSPS) –50 –70 1 × MODE 1 × MODE –75 –60 –80 –85 THD (dBFS) THD (dBFS) –70 –80 2 × MODE –90 2 × MODE –95 –100 –90 8 × MODE 4 × MODE –105 4 × MODE –110 8 × MODE 1.0 10.0 INPUT FREQUENCY (MHz) –120 0.1 00581-C-018 –110 0.1 –115 1.0 10.0 INPUT FREQUENCY (MHz) Figure 18. THD vs. Input Frequency (fCLOCK = 20 MSPS) 00581-C-021 –100 Figure 21. THD vs. Input Frequency (fCLOCK = 10 MSPS) –50 –70 1 × MODE –75 1 × MODE –60 –80 –85 SFDR (dBFS) –80 2 × MODE –90 2 × MODE –95 4 × MODE –100 8 × MODE –90 –105 –110 –100 4 × MODE 1.0 10.0 INPUT FREQUENCY (MHz) Figure 19. SFDR vs. Input Frequency (fCLOCK = 20 MSPS) –120 0.1 1.0 10.0 INPUT FREQUENCY (MHz) Figure 22. SFDR vs. Input Frequency (fCLOCK = 10 MSPS) Rev. C | Page 15 of 44 00581-C-022 –115 8 × MODE –110 0.1 00581-C-019 SFDR (dBFS) –70 AD9260 TYPICAL AC CHARACTERIZATION CURVES FOR 8× MODE AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias. 90 85 –0.5dBFS 85 –0.5dBFS 80 –6.0dBFS 80 –6.0dBFS SINAD (dB) 75 70 75 70 –20dBFS –20dBFS 65 65 1.0 INPUT FREQUENCY (MHz) 60 0.1 00581-C-023 60 0.1 1.0 INPUT FREQUENCY (MHz) Figure 23. SINAD vs. Input Frequency (fCLOCK = 20 MSPS) SINAD performance limited by noise contribution of input differential op amp driver. 00581-C-026 SINAD (dB) 90 Figure 26. SINAD vs. Input Frequency (fCLOCk- = 10 MSPS) –70 –70 –75 –75 –20dBFS –80 –80 –20dBFS –90 –100 –95 –6.0dBFS –105 –100 –0.5dBFS –110 0.1 1.0 INPUT FREQUENCY (MHz) –105 0.1 Figure 24. THD vs. Input Frequency (fCLOCK = 20 MSPS) Figure 27. THD vs. Input Frequency (fCLOCK = 10 MSPS) 105 105 100 100 –6.0dBFS –6.0dBFS SFDR (dBc) 95 –0.5dBFS 90 85 80 0.1 –0.5dBFS 90 –20dBFS 1.0 INPUT FREQUENCY (MHz) 95 85 –20dBFS 00581-C-025 SFDR (dBc) 1.0 INPUT FREQUENCY (MHz) 00581-C-027 –6.0dBFS –85 Figure 25. SFDR vs. Input Frequency (fCLOCK = 20 MSPS) 80 0.1 1.0 INPUT FREQUENCY (MHz) Figure 28. SFDR vs. Input Frequency (fCLOCK = 10 MSPS) Rev. C | Page 16 of 44 00581-C-028 –95 THD (dB) –0.5dBFS –90 00581-C-024 THD (dB) –85 AD9260 TYPICAL AC CHARACTERIZATION CURVES FOR 4× MODE AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias. 90 90 85 85 –0.5dBFS 80 –0.5dBFS 80 75 SINAD (dB) SINAD (dB) –6.0dBFS 70 65 –20dBFS –6.0dBFS 75 70 60 65 55 10.0 INPUT FREQUENCY (MHz) 60 0.1 00581-C-029 1.0 1.0 INPUT FREQUENCY (MHz) Figure 29. SINAD vs. Input Frequency (fCLOCK = 20 MSPS) 00581-C-032 –20dBFS 50 0.1 Figure 32. SINAD vs. Input Frequency (fCLOCK = 10 MSPS) –70 –70 –75 –75 –20dBFS –80 –80 –0.5dBFS –85 –0.5dBFS THD (dB) –90 –95 –100 –105 –105 1.0 10.0 INPUT FREQUENCY (MHz) –110 0.1 00581-C-030 –110 0.1 1.0 INPUT FREQUENCY (MHz) Figure 30. THD vs. Input Frequency (fCLOCK = 20 MSPS) Figure 33. THD vs. Input Frequency (fCLOCK = 10 MSPS) 110 110 105 105 –0.5dBFS 100 100 SFDR (dBc) –6.0dBFS 95 90 –6.0dBFS 95 –20dBFS 90 85 85 –0.5dBFS –20dBFS 80 0.1 1.0 10.0 INPUT FREQUENCY (MHz) 00581-C-031 SFDR (dBc) –6.0dBFS 00581-C-033 –100 –95 –6.0dBFS –20dBFS –90 Figure 31. SFDR vs. Input Frequency (fCLOCK = 20 MSPS) 80 0.1 1.0 INPUT FREQUENCY (MHz) Figure 34. SFDR vs. Input Frequency (fCLOCK = 10 MSPS) Rev. C | Page 17 of 44 00581-C-034 THD (dB) –85 AD9260 TYPICAL AC CHARACTERIZATION CURVES FOR 2× MODE AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias. 80 80 75 75 –0.5dBFS –0.5dBFS 70 –6.0dBFS SINAD (dB) 65 65 60 55 1.0 10.0 INPUT FREQUENCY (MHz) 50 0.1 00581-C-035 50 0.1 –60 –65 –65 –75 –0.5dBFS THD (dB) THD (dB) –70 –20dBFS –80 –80 –20dBFS –85 –85 –90 –90 –0.5dBFS –100 0.1 –6.0dBFS –6.0dBFS –95 1.0 10.0 INPUT FREQUENCY (MHz) –100 0.1 00581-C-036 –95 10.0 Figure 38. SINAD vs. Input Frequency (fCLOCK = 10 MSPS) –60 –75 1.0 INPUT FREQUENCY (MHz) Figure 35. SINAD vs. Input Frequency (fCLOCK = 20 MSPS) –70 –20dBFS 55 –20dBFS 00581-C-038 60 –6.0dBFS 1.0 10.0 INPUT FREQUENCY (MHz) Figure 36. THD vs. Input Frequency (fCLOCK = 20 MSPS) 00581-C-039 SINAD (dB) 70 Figure 39. THD vs. Input Frequency (fCLOCK = 10 MSPS) 100 100 95 95 –6.0dBFS SFDR (dBc) 90 –6.0dBFS 85 –0.5dBFS 80 –0.5dBFS 85 –20dBFS 80 75 75 70 0.1 1.0 10.0 INPUT FREQUENCY (MHz) Figure 37. SFDR vs. Input Frequency (fCLOCK = 20 MSPS) 70 0.1 1.0 10.0 INPUT FREQUENCY (MHz) Figure 40. SFDR vs. Input Frequency (fCLOCK = 10 MSPS) Rev. C | Page 18 of 44 00581-C-040 –20dBFS 00581-C-037 SFDR (dBc) 90 AD9260 TYPICAL AC CHARACTERIZATION CURVES FOR 1× MODE AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias. 70 70 65 65 –0.5dBFS –0.5dBFS 60 SINAD (dB) SINAD (dB) 60 –6.0dBFS 55 50 –6.0dBFS 55 50 45 45 –20dBFS 1.0 10.0 INPUT FREQUENCY (MHz) 40 0.1 00581-C-041 40 0.1 1.0 10.0 INPUT FREQUENCY (MHz) Figure 41. SINAD vs. Input Frequency (fCLOCK = 20 MSPS) 00581-C-044 –20dBFS Figure 44. SINAD vs. Input Frequency (fCLOCK = 10 MSPS) –55 –55 –0.5dBFS –60 –60 –20dBFS –65 –65 –20dBFS –70 –70 THD (dBc) THD (dB) –6.0dBFS –75 –80 –75 –80 –85 –85 –90 –90 –95 –95 –0.5dBFS 1.0 10.0 INPUT FREQUENCY (MHz) –100 0.1 00581-C-042 –100 0.1 Figure 42. THD vs. Input Frequency (fCLOCK = 20 MSPS) 100 95 95 –0.5dBFS 90 –0.5dBFS 85 –6.0dBFS SDFR (dBc) –6.0dBFS 75 70 65 80 75 70 65 –20dBFS 60 60 55 55 50 0.1 1.0 10.0 INPUT FREQUENCY (MHz) Figure 43. SFDR vs. Input Frequency (fCLOCK = 20 MSPS) 50 0.1 1.0 10.0 INPUT FREQUENCY (MHz) Figure 46. SFDR vs. Input Frequency (fCLOCK = 10 MSPS) Rev. C | Page 19 of 44 00581-C-046 –20dBFS 00581-C-043 SDFR (dBc) 85 80 10.0 Figure 45. THD vs. Input Frequency (fCLOCK = 10 MSPS) 100 90 1.0 INPUT FREQUENCY (MHz) 00581-C-045 –6.0dBFS AD9260 TYPICAL AC CHARACTERIZATION CURVES AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, AIN = –0.5 dBFS, Differential DC Coupled Input with CML = 2 V. –60 100 95 FULL BIAS –65 90 –70 80 HALF BIAS THD (dBc) SFDR (dBFS) 85 75 70 QUARTER BIAS –75 FIN = 1MHz, 2 × MODE –80 –85 65 FIN = 100kHz, 8 × MODE –90 60 0 5 10 15 20 CLOCK FREQUENCY (MHz) –100 1.0 00581-C-047 50 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 COMMON MODE INPUT LEVEL (V) 00581-C-050 –95 55 Figure 50. THD vs. Common-Mode Input Level (CML) Figure 47. SFDR vs. Clock Rate (fIN = 100 kHz in 8x Mode) –40 100 FULL BIAS –50 80 CMR (dB) SFDR (dBFS) HALF BIAS 60 QUARTER BIAS 40 FS = 20MHz –60 FS = 10MHz –70 FS = 5MHz 5 10 15 25 20 CLOCK FREQUENCY (MHz) 00581-C-048 0 –90 1k 10k 100k 1M 10M 100M INPUT FREQUENCY (Hz) Figure 48. SFDR vs. Clock Rate (fIN = 500 kHz in 4x Mode) 00581-C-051 –80 20 Figure 51. CMR vs. Input Frequency (VCML = 2 V p-p, 1x Mode) 100 100 FULL BIAS 95 4V SPAN SFDR-2 × MODE SFDR (dBFS) 60 HALF BIAS 40 90 4V SPAN SNR-8 × MODE 85 1.6V SPAN SNR-8 × MODE QUARTER BIAS 20 80 5 10 15 20 25 CLOCK FREQUENCY (MHz) 75 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 FREQUENCY (MHz) Figure 52. 4 V vs. 1.6 V Span SNR/SFDR (fCLOCK = 20 MSPS) Figure 49. SFDR vs. Clock Rate (fIN = 1.0 MHz in 2x Mode) Rev. C | Page 20 of 44 00581-C-052 1.6V SPAN SFDR-2 × MODE 0 00581-C-049 SFDR (dBFS) 80 AD9260 ADDITIONAL AC CHARACTERIZATION CURVES AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, AIN = –0.5 dBFS, Differential DC Coupled Input with CML = 2 V, Full Bias, unless otherwise noted. 120 120 20 MSPS (dBFS) FULL BIAS 20 MSPS FULL BIAS SFDR (dBFS) 110 WORST SPUR (dBc AND dBFS) 110 10 MSPS FULL BIAS 105 100 20 MSPS HALF BIAS 95 90 10 MSPS HALF BIAS 80 –50 –45 –40 –35 –30 –25 –20 –15 –10 20 MSPS (dBc) FULL BIAS 90 80 10 MSPS (dBc) HALF BIAS 70 60 –5 50 –60 00581-C-053 85 10 MSPS (dBFS) HALF BIAS 100 0 AIN (dBFS) –50 –40 –30 –20 –10 0 AIN (dBFS) Figure 53. Single-Tone SFDR vs. Amplitude (fIN = 100 kHz, 8x Mode) 00581-C-056 115 Figure 56. Two-Tone SFDR (F1 = 475 kHz, F2 = 525 MHz, 8x Mode) 110 120 FULL BIAS (dBFS) 105 110 WORST SPUR (dBc AND dBFS) 10 MSPS FULL BIAS 95 10 MSPS HALF BIAS 20 MSPS FULL BIAS 90 85 HALF BIAS (dBFS) 90 FULL BIAS (dBc) 80 70 HALF BIAS (dBc) –40 –35 –30 –25 –20 –15 –10 –5 50 –60 00581-C-054 –45 0 AIN (dBFS) Figure 54. Single-Tone SFDR vs. Amplitude (fIN = 1.0 MHz) –40 –30 –20 –10 0 AIN (dBFS) Figure 57. Two-Tone SFDR (F1 = 0.95 kHz, F2 = 1.05 MHz, 8x Mode, 20 MSPS) 110 120 10 MSPS HALF BIAS 100 110 WORST SPUR (dBc AND dBFS) 105 20 MSPS FULL BIAS 95 10 MSPS FULL BIAS 90 85 dBFS 100 dBc 90 80 70 60 –45 –40 –35 –30 –25 –20 –15 –10 –5 00581-C-055 80 –50 –50 00581-C-057 60 80 –50 SFDR (dBFS) 100 0 AIN (dBFS) Figure 55. Single-Tone SFDR vs. Amplitude (fIN = 500 kHz, 2x Mode) Rev. C | Page 21 of 44 50 –60 –50 –40 –30 AIN (dBFS) –20 –10 0 00581-C-058 SFDR (dBFS) 100 Figure 58. Two-Tone SFDR (F1 = 1.9 MHz, F2 = 2.1 MHz, 4x Mode 20 MSPS) AD9260 + – + – 5B DAC1 INT1 + – INT2 5B ADC 3B ADC 5B DAC + – 4 3B ADC 3B DAC 3B DAC 4 4B ADC PIPELINE CORRECTION LOGIC 5B DAC2 8 LSBs SHUFFLE MOUT Z–D ++ LSB DIFFERENTIATOR COUT CONTROL/TEST LOGIC HALF-BAND DECIMATION FILTER STAGE 1 BANDGAP REFERENCE HALF-BAND DECIMATION FILTER STAGE 2 REFERENCE BUFFER HALF-BAND DECIMATION FILTER STAGE 3 OUTPUT BITS Figure 59. Simplified Block Diagram Rev. C | Page 22 of 44 00581-C-059 VIN + – 16 AD9260 THEORY OF OPERATION The AD9260 utilizes a new analog-to-digital converter architecture to combine sigma-delta techniques with a high speed, pipelined A/D converter. This topology allows the AD9260 to offer the high dynamic range associated with sigmadelta converters while maintaining very wide input signal bandwidth (1.25 MHz) at a very modest 8 oversampling ratio. Figure 59 provides a block diagram of the AD9260. The differential analog input is fed into a second order, multibit sigma-delta modulator. This modulator features a 5-bit flash quantizer and 5-bit feedback. In addition, a 12-bit pipelined A/D quantizes the input to the 5-bit flash to greater accuracy. A special digital modulation loop combines the output of the 12bit pipelined A/D with the delayed output of the 5-bit flash to produce the equivalent response of a second order loop with a 12-bit quantizer and 12-bit feedback. The combination of a second order loop and multibit feedback provides inherent stability: the AD9260 is not prone to the idle tones or full-scale idiosyncrasies sometimes associated with higher order single bit sigma-delta modulators. The output of this 12-bit modulator is fed into the digital decimation filter. The voltage level on the MODE pin establishes the configuration for the digital filter. The user may bring the data out undecimated (at the clock rate), or at a decimation factor of 2×, 4×, or a full 8×. The spectra for these four cases are shown in Figure 11, Figure 12, Figure 13, and Figure 14, all for a 100 kHz full-scale input and 20 MHz clock. The spectra of the undecimated output clearly shows the second order shaping characteristic of the quantization noise as it rises at frequencies above 1.25 MHz. The on-chip decimation filter provides excellent stopband rejection to suppress any stray input signal between 1.25 MHz and 18.75 MHz, substantially easing the requirements on any antialiasing filter for the analog input path. The decimation filters are integrated with symmetric FIR filter structures, providing a linear phase response and excellent passband flatness. The digital output driver register of the AD9260 features both READ and CHIP SELECT pins to allow easy interfacing. The digital supply of the AD9260 is designed to operate over a 2.7 V to 5.25 V supply range, though 3 V supplies are recommended to minimize digital noise on the board. A DATA AVAILABLE pin allows the user to easily synchronize to the converter’s decimated output data rate. OUT-OF-RANGE (OTR) indication is given for an overflow in the pipelined A/D converter or digital filters. A RESETB function is provided to synchronize the converter’s decimated data and clear any overflow condition in the analog integrators. An on-chip reference and reference buffer are included on the AD9260. The reference can be configured in either a 2.5 V mode (providing a 4 V p-p differential input full scale), a 1 V mode (providing a 1.6 V p-p differential input full scale), or programmed with an external resistor divider to provide any voltage level between 1 V and 2.5 V. However, optimum noise and distortion performance for the AD9260 can only be achieved with a 2.5 V reference, as shown in Figure 52. For users who want to operate the part at reduced clock frequencies, the bias current of the AD9260 is designed to be scalable. This scaling is accomplished through use of the proper external resistor tied to the BIAS pin: the power can be reduced roughly proportionately to clock frequency by as much as 75% (for clock rates of 5 MHz). Refer to Figure 47 to Figure 49 and Figure 53 to Figure 57 for characterization curves showing performance tradeoffs. Rev. C | Page 23 of 44 AD9260 ANALOG INPUT AND REFERENCE OVERVIEW Figure 60, a simplified model of the AD9260, highlights the relationship between the analog inputs, VINA, VINB and the reference voltage VREF. Like the voltage applied to the top of the resistor ladder in a flash A/D converter, the value VREF defines the maximum input voltage to the A/D converter. An internal reference buffer in the AD9260 scales the reference voltage VREF before it is applied internally to the AD9260 A/D core. The scale factor of this reference buffer is 0.8. Consequently, the maximum input voltage to the A/D core is +0.8 × VREF. The minimum input voltage to the A/D core is automatically defined to be –0.8 × VREF. With this scale factor, the maximum differential input span of 4 V p-p is obtained with a VREF voltage of 2.5 V. A smaller differential input span may be obtained by using a VREF voltage of less than 2.5 V at the expense of ac performance (refer to Figure 52). VINA Σ 16 A/D CORE VINB –0.8 × VREF 00581-C-060 – Figure 60. Simplified Input Model INPUT SPAN The AD9260 is implemented with a differential input structure. This structure allows the common-mode level (average voltage of the two input pins) of the input signal to be varied independently of the input span of the converter over a wide range, as shown in Figure 50. Specifically, the input to the A/D core is the difference of the voltages applied at the VINA and VINB input pins. Therefore, the equation, VCORE = VINA − VINB (1) defines the output of the differential input stage and provides the input to the A/D core. The voltage, VCORE, must satisfy the condition, −0.8 × VREF ≤ VCORE ≤ +0.8 × VREF AVSS + 0.5V < VINB < AVDD + 0.5V (3) where AVSS is nominally 0 V and AVDD is nominally +5 V, defines this requirement. Thus the valid inputs for VINA and VINB are any combination that satisfies both Equations 2 and 3. Note that the clock clamping method used in the differential driver circuit shown in Figure 63 is sufficient for protecting the AD9260 in an undervoltage condition. For additional information showing the relationships between VINA, VINB, VREF, and the digital output of the AD9260, see Table 13. Refer to Table 12 for a summary of the various analog input and reference configurations. ANALOG INPUT OPERATION +0.8 × VREF + AVSS + 0.5V < VINA < AVDD − 0.5V (2) where VREF is the voltage at the VREF pin. INPUT COMPLIANCE RANGE The analog input structure of the AD9260 is optimized to meet the performance requirements for some of the most demanding communication and data acquisition applications. This input structure is composed of a switched-capacitor network that samples the input signal applied to pins VINA and VINB on every rising edge of the CLK pin. The input switched capacitors are charged to the input voltage during each period of CLK. The resulting charge, q, on these capacitors is equal to C × VIN, where C is the input capacitor. The change in charge on these capacitors, delta q, as the capacitors are charged from a previous sample of the input signal to the next sample, is approximated in the following equation, delta q ~ C × deltaVN = C × (VN − VN −2 ) (4) where VN represents the present sample of the input signal and VN–2 represents the sample taken two clock cycles earlier. The average current flow into the input (provided from an external source) is given in the following equation, I = delta q / T ~ C × (VN − VN −2 )× f CLOCK (5) where T represents the period of CLK and fCLOCK represents the frequency of CLK. Equations 4 and 5 provide simplifying approximations of the operation of the analog input structure of the AD9260. A more exact, detailed description and analysis of the input operation follows. In addition to the limitations on the differential span of the input signal indicated in Equation 2, an additional limitation is placed on the inputs by the analog input structure of the AD9260. The analog input structure bounds the valid operating range for VINA and VINB. The condition, Rev. C | Page 24 of 44 AD9260 circuitry must provide additional charge, qdelta, to capacitors CS1 and CS2, which is the difference between the precharged value, Q(n–1), and the new value, Q(n), as given in the following equation, SS3 SS1 CS1 SH1 VINA CPA1 CPB1 SS2 SS4 CS2 ANALOG MODULATOR SH2 VINB CPB2 00581-C-061 SH3 SH4 Figure 61. Detailed Analog Input Structure Figure 61 illustrates the analog input structure of the AD9260. For the moment, ignore the presence of the parasitic capacitors CPA and CPB. The effects of these parasitic capacitors will be discussed near the end of this section. The switched capacitors, CS1 and CS2, sample the input voltages applied on pins VINA and VINB. These capacitors are connected to input pins VINA and VINB when CLK is low. When CLK rises, a sample of the input signal is taken on capacitors CS1 and CS2. When CLK is high, capacitors CS1 and CS2 are connected to the Analog Modulator. The modulator precharges capacitors CS1 and CS2 to minimize the amount of charge required from any circuit used in combination with the AD9260 to drive input pins VINA and VINB. This reduces the input drive requirements of the analog circuitry driving pins VINA and VINB. The Analog Modulator precharges the voltages across capacitors CS1 and CS2, approximately equal to a delayed version of the input signal. When capacitors CS1 and CS2 are connected to input pins VINA and VINB, the differential charge, Q(n), on these capacitors is given in the following equation, Q(n) = q1 − q2 = CS × VCORE (6) where q1 and q2 are the individual charges stored on capacitors CS1 and CS2 respectively, and CS is the capacitance value of CS1 and CS2. When capacitors CS1 and CS2 are connected to the Analog Modulator during the preceding precharge clock phase, the capacitors are precharged equal to an approximation of a previous sample of the input signal. Consequently the differential charge on these capacitors while CLK is high is given in the following equation, Q(n − 1) = CS × VCORE (delay ) + CS × Vdelta (7) where VCORE(delay) is the value of VCORE sampled during a previous period of CLK, and Vdelta is the sigma-delta error voltage left on the capacitors. Vdelta is a natural artifact of the sigma-delta feedback techniques utilized in the Analog Modulator of the AD9260. It is a small random voltage term that changes every clock period and varies from 0 to ±0.05 ×VREF. The analog circuitry used to drive the input pins of the AD9260 must respond to the charge glitch that occurs when capacitors CS1 and CS2 are connected to input pins VINA and VINB. This (8) Qdelta = CS × [VCORE − VCORE (delay ) + Vdelta ] (9) DRIVING THE INPUT Transient Response The charge glitch occurs once at the beginning of every period of the input CLK (falling edge), and the sample is taken on capacitors CS1 and CS2 exactly one-half period later (rising edge). Figure 62 presents a typical input waveform applied to input Pins VINA and VINB of the AD9260. TRACK SAMPLE TRACK SAMPLE TRACK SAMPLE TRACK SAMPLE CLOCK VINA-VINB 00581-C-062 CPA2 Qdelta = Q(n) − Q(n − 1) Figure 62. Typical Input Waveform Figure 62 illustrates the effect of the charge glitch when a source with nonzero output impedance is used to drive the input pins. This source must be capable of settling from the charge glitch in one-half period of the CLK. Unfortunately, the MOS switches used in any CMOS-switched capacitor circuit (including those in the AD9260) include nonlinear parasitic junction capacitances connected to their terminals. Figure 61 also illustrates the parasitic capacitances, Cpa1, Cpb1, Cpa2, and Cpb2, associated with the input switches. Parasitic capacitor Cpa1 and Cpa2 are always connected to Pins VINA and VINB and therefore do not contribute to the glitch energy. Parasitic capacitors Cpb1 and Cpb2, on the other hand, cause a charge glitch that adds to that of input capacitors CS1 and CS2 when they are connected to input Pins VINA and VINB. The nonlinear junction capacitance of Cpb1 and Cpb2 cause charge glitch energy that is nonlinearily related to the input signal. Therefore, linear settling is difficult to achieve unless the input source completely settles during one-half period of CLK. A portion of the glitch impulse energy kicked back at the source is not linearly related to the input signal. Therefore, the best way to ensure that the input signal settles linearly is to use wide bandwidth circuitry, which settles as completely as possible from the glitch during one-half period of the CLK. The AD9260 utilizes a proprietary clock-boosted bootstrapping technique to reduce the nonlinear parasitic Rev. C | Page 25 of 44 AD9260 capacitances of the internal CMOS switches. This technique improves the linearity of the input switches and reduces the nonlinear parasitic capacitance. Thus, this technique reduces the nonlinear glitch energy. The capacitance values for the input capacitors and parasitic capacitors for the input structure of the AD9260, as illustrated in Figure 61, are listed as follows. 499Ω 499Ω 50Ω VIN VINA +5V CS 100pF AD9260 AD8138 50Ω VINB CS = 3.2 pF, Cpa = 6 pF, Cpb = 1 pF (where CS is the capacitance value of capacitors CS1 and CS2, Cpa is the value of capacitors Cpa1 and Cpa2, and Cpb is the value of capacitors Cpb1 and Cpb2). The total capacitance at each input pin is CIN = CS + Cpa + Cpb = 10.2 pF. 499Ω 499Ω CS 100pF 10µF 0.1µF 00581-C-063 VREF Figure 63. AD8138 Single-Ended Differential ADC Driver Input Driver Considerations The optimum noise and distortion performance of the AD9260 can ONLY be achieved when the AD9260 is driven differentially with a 4 V input span. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversion. In the case of the AD9260, a single-ended-to-differential conversion is best realized using a differential op amp driver. Although a transformer will perform a similar function for ac signals, its usefulness is precluded by its inability to directly drive the AD9260 and thus the additional requirement of an active low noise, low distortion buffer stage. Single-Ended-to-Differential Op Amp Driver There are two single-ended-to-differential op amp driver circuits useful for driving the AD9260. The first circuit, shown in Figure 63, uses the AD8138 and represents the best choice in most applications. The AD8138 is a low distortion differential ADC driver designed to convert a ground-referenced singleended input signal to a differential output signal with a specified common-mode level for dc-coupling applications. It is capable of maintaining the typical THD and SFDR performance of the AD9260 with only a slight degradation in its noise performance in the 8 mode (i.e., SNR of 85 dB–86 dB). In this application, the AD8138 is configured for unity gain and its common-mode output level is set to 2.5 V, functioning like the VREF of the AD9260, to maximize its output headroom while operating from a single supply. Note that the singlesupply operation has the benefit of not requiring an input protection network for the AD9260 in dc-coupled applications. A simple R-C network at the output is used to filter out high frequency noise from the AD8138. Recall, the AD9260’s small signal bandwidth is 75 MHz. Therefore, any noise falling within the baseband bandwidth of the AD9260 defined by its sample and decimation rate, as well as images of its baseband response occurring at multiples of the sample rate, will degrade its overall noise performance. The second driver circuit, shown in Figure 64, can provide slightly enhanced noise performance relative to the AD8138, assuming low noise, high speed op amps are used. This differential op amp driver circuit is configured to convert and level-shift a 2 V p-p single-ended, ground-referenced signal to a 4 V p-p differential signal centered at the common-mode level of the AD9260. The circuit is based on two op amps that are configured as matched unity gain difference amplifiers. The single-ended input signal is applied to opposing inputs of the difference amplifiers, thus providing differential outputs. The common-mode offset voltage is applied to the noninverting resistor leg of each difference amplifier providing the required offset voltage. This offset voltage is derived from the commonmode level (CML) pin of the AD9260 via a low output impedance buffer amplifier capable of driving a 1 µF capacitive load. The common-mode offset can be varied over a 1.8 V to 2.5 V span without any serious degradation in distortion performance as shown in Figure 50, thus providing some flexibility in improving output compression distortion from some ±5 op amps with limited positive voltage swing. To protect the AD9260 from an undervoltage fault condition from op amps specified for ±5 V operation, two 50 Ω series resistors and a diode to AGND are inserted between each op amp output and the AD9260 inputs. The AD9260 will inherently be protected against any overvoltage condition if the op amps share the same positive power supply (AVDD) as the AD9260. Note, the gain accuracy and common-mode rejection of each difference amplifier in this driver circuit can be enhanced by using a matched thin-film resistor network (Ohmtek ORNA5000F) for the op amps. Resistor values should be 500 Ω or less to maintain the lowest possible noise. The noise performance of each unity gain differential driver circuit is limited by its inherent noise gain of two. For unity gain op amps only, the noise gain can be reduced from two to one Rev. C | Page 26 of 44 AD9260 R (1 dB–2 dB) when compared to the OPA642. Note that the majority of the AD9260 test and characterization data presented in this data sheet was taken using the AD9632 op amp in this dc-coupled driver circuit. This driver circuit is also provided on the AD9260 evaluation board since the AD8138 was unreleased at that time. R 50Ω 50Ω VINA R R VIN CF CC 100pF VCML-VIN R CF AD9260 CD 100pF 50Ω 50Ω VINB R CC 100pF R R CML 0.1µF 1.0µF Figure 64. DC-Coupled Differential Driver with Level-Shifting beyond the input signals passband by adding a shunt capacitor, CF, across the feedback resistor of each op amp. This will essentially establish a low-pass filter which reduces the noise gain to one beyond the filter’s f–3 dB while simultaneously bandlimiting the input signal to f–3 dB. Note that the pole established by this filter can also be used as the real pole of an antialiasing filter. Since the noise contribution of two op amps from the same product family are typically equal but uncorrelated, the total output-referred noise of each op amp will add root-sum square leading to a further 3 dB degradation in the circuit’s noise performance. Further out-of-band noise reduction can be realized with the addition of single-ended and differential capacitors, CS and CD. The distortion and noise performance of the two op amps within the signal path are critical in achieving optimum performance in the AD9260. Low noise op amps capable of providing greater than 85 dB THD at 1 MHz while swinging over a 1 V to 3 V range are a rare commodity, yet these parts are the only ones that should be considered. The AD9632 op amp was found to provide superb distortion performance in this circuit due to its ability to maintain excellent distortion performance over a wide bandwidth while swinging over a 1 V to 3 V range. Since the AD9632 is gain-of-two or greater stable, the use of the noise reduction shunt capacitors discussed above was prohibited, thus degrading its noise performance slightly 00581-C-064 AD817 The outputs of each op amp are ac coupled via a small series resistor and capacitor (i.e., 50 Ω and 0.1 µF) to the respective inputs of the AD9260. Similar to the dc coupled driver, further out-of-band noise reduction can be realized with the addition of 100 pF single-ended and differential capacitors, CS and CD. The lower cutoff frequency of this ac-coupled circuit is determined by RC and CC in which RC is tied to the common-mode level pin, CML, of the AD9260 for proper biasing of the inputs. Although the OPA642 was found to provide the lowest overall noise and distortion performance (88.8 dB and 96 dB THD @ 100 kHz), the AD8055, or dual AD8056, suffered only a 0.5 dB to 1.5 dB degradation in overall performance. It is worth noting that given the high level of performance attainable by the AD9260, special consideration must be given to both the quality of the test equipment and test set-up in its evaluation. Common-Mode Level The CML pin is an internal analog bias point used internally by the AD9260. This pin must be decoupled to analog ground with at least a 0.1 µF capacitor as shown in Figure 65. The dc level of CML is approximately AVDD/2.5. This voltage should be buffered if it is to be used for any external biasing. Note: the common-mode voltage of the input signal applied to the AD9260 need not be at the exact same level as CML. While this level is recommended for optimal performance, the AD9260 is tolerant of a range of input common-mode voltages around AVDD/2.5. Rev. C | Page 27 of 44 CML 0.1µF AD9260 Figure 65. CML Decoupling 00581-C-065 VCML-VIN AD9260 REFERENCE OPERATION The AD9260 contains an on-board band gap reference and internal reference buffer amplifier. The onboard reference provides a pin-strappable option to generate either a 1 V or 2.5 V output. With the addition of two external resistors, the user can generate reference voltages other than 1 V and 2.5 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. See Table 12 for a summary of the pin-strapping options for the AD9260 reference configurations. Note, the optimum noise and distortion can only be achieved with a 2.5 V reference. SENSE and another resistor (R2) connected between SENSE and REFCOM. The other comparator controls internal circuitry that will disable the reference amplifier if the SENSE pin is tied to AVDD. Disabling the reference amplifier allows the VREF pin to be driven by an external voltage reference. TO A/D 5kΩ CAPT 6.25kΩ 6.25kΩ Figure 66 shows a simplified model of the internal voltage reference of the AD9260. A pin-strappable reference amplifier buffers a 1 V fixed reference. The output from the reference amplifier, A1, appears on the VREF pin and must be decoupled with 0.1 µF and 10 µF capacitor to REFCOM. The voltage on the VREF pin determines the full-scale input span of the A/D. This input span equals: A2 5kΩ DISABLE A2 CAPB LOGIC – + 1V VREF A1 7.5kΩ 7.5k Full - Scale Input Span = 1.6 × VREF AD9260 SENSE DISABLE A1 LOGIC 5kΩ REFCOM 00581-C-066 The voltage appearing at the VREF pin, as well as the state of the internal reference amplifier, A1, is determined by the voltage appearing at the SENSE pin. The logic circuitry contains two comparators that monitor the voltage at the SENSE pin. The comparator with the lowest set point (approximately 0.3 V) controls the position of the switch within the feedback path of A1. If the SENSE pin is tied to REFCOM, the switch is connected to the internal resistor network, thus providing a VREF of 2.5 V. If the SENSE pin is tied to the VREF pin via a short or resistor, the switch is connected to the SENSE pin. A short will provide a VREF of 1.0 V while an external resistor network will provide an alternative VREF SPAN between 1.0 V and 2.5 V. The external resistor network, for example, may be implemented as a resistor divider circuit. This divider circuit could consist of a resistor (R1) connected between VREF and Figure 66. Simplified Reference The reference buffer circuit level shifts the reference to an appropriate common-mode voltage for use by the internal circuitry. The on-chip buffer provides the low impedance necessary for driving the internal switched capacitor circuits and eliminates the need for an external buffer op amp. Table 12. Reference Configuration Summary Reference Operating Mode INTERNAL INTERNAL INTERNAL EXTERNAL Input Span (VINA–VINB) (V p-p) 1.6 4.0 1.6 ≤ SPAN ≤ 4.0 and SPAN = 1.6 × VREF 1.6 ≤ SPAN ≤4.0 Required VREF (V) 1 2.5 1 ≤ VREF ≤ 2.5 and VREF = (1+R1/R2) 1 ≤ VREF ≤2.5 Rev. C | Page 28 of 44 Connect SENSE SENSE R1 R2 SENSE VREF To VREF REFCOM VREF and SENSE SENSE and REFCOM AVDD EXT. REF. AD9260 bandlimits the noise contribution from the reference. The turnon time of the reference voltage appearing between CAPT and CAPB is approximately 15 ms and should be evaluated in any power-down mode of operation. Rev. C | Page 29 of 44 AD9260 VREF 0.1µF + 10µF SENSE REFCOM 0.1µF CAPT 0.1µF + 10µF CAPB 0.1µF Figure 67. Recommended Reference Decoupling Network 00581-C-067 The actual reference voltages used by the internal circuitry of the AD9260 appear on the CAPT and CAPB pins. If VREF is configured for 2.5 V, thus providing a 4 V full-scale input span, the voltages appear at CAPT and CAPB are 3.0 V and 1.0 V respectively. For proper operation when using the internal or an external reference, it is necessary to add a capacitor network to decouple the CAPT and CAPB pins. Figure 67 shows the recommended decoupling network. This capacitive network performs the following three functions: (1) along with the reference amplifier, A2, it provides a low source impedance over a large frequency range to drive the A/D internal circuitry; (2) it provides the necessary compensation for A2; and (3) it AD9260 DIGITAL INPUTS AND OUTPUTS Table 14. CS and READ Pin Functionality DIGITAL OUTPUTS The AD9260 output data is presented in a twos complement format. Table 13 indicates the output data formats for various input ranges and decimation modes. A straight binary output data format can be created by inverting the MSB. Table 13. Output Data Format Input (V) Condition (V) 8× Decimation Mode VINA–VINB < –0.8 ×VREF VINA–VINB = –0.8 ×VREF VINA–VINB =0 VINA–VINB = +0.8 ×VREF – 1 LSB VINA–VINB >= + 0.8 ×VREF 4× Decimation Mode VINA–VINB < –0.825 ×VREF VINA–VINB = –0.825 ×VREF VINA–VINB =0 VINA–VINB = +0.825 ×VREF –1 LSB VINA–VINB >= + 0.825 ×VREF 2× Decimation Mode VINA–VINB < –0.825 ×VREF VINA–VINB = –0.825 ×VREF VINA–VINB =0 VINA–VINB = +0.825 ×VREF –1 LSB VINA–VINB >= + 0.825 ×VREF CS Low Low High High READ Low High Low High Condition of Data Output Pins Data Output Pins in Hi-Z State ADC Data on Output Pins Data Output Pins in Hi-Z State Data Output Pins in Hi-Z State Digital Output DAV Pin 1000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1111 1000 0001 0001 1100 1000 0001 0000 1100 0000 0000 0000 0000 0111 1110 1110 0011 0111 1110 1110 0011 1000 0000 0100 0001 1000 0000 0100 0001 0000 0000 0000 0000 0111 1111 1011 1110 0111 1111 1011 1110 The slightly different ± full-scale input voltage conditions and their corresponding digital output code for the 4× and 2× decimation modes can be attributed to the different digital scaling factors applied to each AD9260 FIR decimation stage for filter optimization purposes. Thus, a + full-scale reading of 0111 1111 1111 1111 and – full-scale reading of 1000 0000 0000 0000 is unachievable in the 2× and 4× decimation modes. As a result, a digital overrange condition can never exist in the 2× or the 4× decimation mode and thus OTR being set high indicates an overrange condition in the analog modulator. The output data format in 1× decimation differs from that in 2×, 4× and 8× decimation modes. In 1× decimation mode the output data remains in a twos complement format, but the digital numbers are scaled by a factor of 7/128. This factor of 7/128 is the product of an internal scale factor of 7/8 in the analog modulator and a 1/16 scale factor caused by LSB justification of the 12-bit modulator data. CS and Read Pins The CS and READ pins control the state of the output data pins (BIT1–BIT16) on the AD9260. The CS pin is active low and the READ pin is active high. When CS and READ are both active the ADC data is driven on the output data pins, otherwise the output data pins are in a high-impedance (Hi-Z) state. Table 14 indicates the relationship between the CS and READ pins and the state of Pins Bit 1 to Bit 16. The DAV pin indicates when the output data of the AD9260 is valid. Digital output data is updated on the rising edge of DAV. The data hold time (tH) is dependent on the external loading of DAV and the digital data output pins (BIT1–BIT16) as well as the particular decimation mode. The internal DAV driver is sized to be larger than the drivers pertaining to the digital data outputs to ensure that rising edge of DAV occurs before the data transitions under similar loading conditions (i.e., fanout) regardless of mode. Note that minimum data hold (tH) of 3.5 ns is specified in the Figure 4 timing diagram from the 50% point of DAV’s rising edge to the 50% of data transition using a capacitive load of 20 pF for DAV and BIT1–BIT16. Applications interfacing to TTL logic and/or having larger capacitive loading for DAV than BIT1–BIT16 should consider latching data on the falling edge of DAV since the falling edge of DAV occurs well after the data has transitioned in the case of the 2×, 4×, and 8× modes. The duty cycle of DAV is approximately 50% and it remains active independent of CS and READ. RESET Pin The RESET pin is an asynchronous digital input that is active low. Upon asserting RESET low, the clocks in the digital decimation filters are disabled, the DAV pin goes low and the data on the digital output data pins (Bit 1–Bit 16) is invalid. In addition, the analog modulator in the AD9260 and internal clock dividers used in the decimation filters are reset and will remain reset as long as RESET is maintained low. In the 2×, 4×, or 8× mode, the RESET must remain low for at least a clock period to ensure all the clock dividers and analog modulator are reset. Upon bringing RESET high, the internal clock dividers will begin to count again on the next falling edge of CLK and DAV will go high approximately 15 ns after this falling edge, resuming normal operation. Refer to Figure 9 for a timing diagram. The state of the internal decimation filters in the AD9260 remains unchanged when RESET is asserted low. Consequently, when RESET is pulsed low, this resets the analog modulator but does not clear all the data in the digital filters. The data in the filters is corrupted by the effect of resetting the analog modulator (this causes an abrupt change at the input of the digital filter and this change is unrelated to the signal at the input of the A/D converter). Similarly, in multiplexed Rev. C | Page 30 of 44 AD9260 applications in which the input of the A/D converters sees an abrupt change, the data in the analog modulator and digital filter will be corrupted. For this reason, following a pulse on the RESET pin, or change in channels (i.e., multiplexed applications only), the decimation filters must be flushed of their data. These filters have a memory length, hence delay, equal to the number of filter taps times the clock rate of the converter. This memory length may be interpreted in terms of a number of samples stored in the decimation filter. For example, if the part is in 8× decimation mode, the delay is 321/fCLOCK. This corresponds to 321 samples stored in the decimation filter. These 321 samples must be flushed from the AD9260 after RESET is pulsed high prior to reusing the data from the AD9260. That is, the AD9260 should be allowed to clock for 321 samples as the corrupted data is flushed from the filters. If the part is in 4× or 2× decimation mode, then the relatively smaller group delays of the 4× and 2× decimation filters result fewer samples that must be flushed from the filters (108 samples and 23 samples respectively). In 2×, 4×, or 8× mode, RESET may be used to synchronize multiple AD9260s clocked with the same clock. The decimation filters in the AD9260 are clocked with an internal clock divider. The state of this clock divider determines when the output data becomes available (relative to CLK). In order to synchronize multiple AD9260s clocked with the same clock, it is necessary that the clock dividers in each of the individual AD9260s are all reset to the same state. When RESET is asserted low, these clock dividers are cleared. On the next falling edge of CLK following the rising edge of RESET, the clock dividers begin counting and the clock is applied to the digital decimation filters. OTR Pin The OTR pin is a synchronous output that is updated each CLK period. It indicates that an overrange condition has occurred within the AD9260. Ideally, OTR should be latched on the falling edge of CLK to ensure proper setup-and-hold time. However, since an overrange condition typically extends well beyond one clock cycle (i.e., does not toggle at the CLK rate). OTR typically remains high for more than a clock cycle, allowing it to be successfully detected on the rising edge of CLK or monitored asynchronously. An overrange condition must be carefully handled because of the group delays in the low-pass digital decimation filters in the output stages of the AD9260. When the input signal exceeds the full-scale range of the converter, this can have a variety of effects upon the operation of the AD9260, depending on the duration and amplitude of this overrange condition. A short duration overrange condition (