AD9269-80EBZ

16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9269 FEATURES 1.8 V analog supply operation 1.8 V to 3.3 V output supply Integrated quadrature error correction (QEC) SNR 77.6 dBFS at 9.7 MHz input 71 dBFS at 200 MHz input SFDR 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input Low power 44 mW per channel at 20 MSPS 100 mW per channel at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = −0.5/+1.1 LSB Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer (DCS) Integer 1-to-6 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock output (DCO) with programmable clock and data alignment FUNCTIONAL BLOCK DIAGRAM AVDD GND SDIO SCLK CSB SPI AD9269 VIN+A ADC VIN–A PROGRAMMING DATA CMOS OUTPUT BUFFER ORA D15A D0A DCOA VREF SENSE VCM RBIAS VIN–B ADC VIN+B REF SELECT QUADRATURE ERROR CORRECTION MUX OPTION DRVDD CMOS OUTPUT BUFFER ORB D15B D0B DCOB DIVIDE 1 TO 6 DUTY CYCLE STABILIZER MODE CONTROLS 08538-001 CLK+ CLK– SYNC DCS PDWN DFS OEB Figure 1. PRODUCT HIGHLIGHTS 1. The AD9269 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. An optional SPI selectable dc correction and quadrature error correction (QEC) feature corrects for dc offset, gain, and phase mismatches between the two channels. A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments, and voltage reference modes. The AD9269 is packaged in a 64-lead RoHS-compliant LFCSP that is pin compatible with the AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC the AD9231 12-bit ADC, the AD6659 12-bit baseband diversity receiver, and the AD9204 10-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR 2. 3. 4. 5. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. AD9269 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Functional Block Diagram .............................................................. 1  Product Highlights ........................................................................... 1  Revision History ............................................................................... 2  General Description ......................................................................... 3  Specifications..................................................................................... 4  DC Specifications ......................................................................... 4  AC Specifications.......................................................................... 6  Digital Specifications ................................................................... 7  Switching Specifications .............................................................. 8  Timing Specifications .................................................................. 9  Absolute Maximum Ratings.......................................................... 10  Thermal Characteristics ............................................................ 10  ESD Caution ................................................................................ 10  Pin Configuration and Function Descriptions ........................... 11  Typical Performance Characteristics ........................................... 13  AD9269-80 .................................................................................. 13  AD9269-65 .................................................................................. 15  AD9269-40 .................................................................................. 16  AD9269-20 .................................................................................. 17  Equivalent Circuits ......................................................................... 18  Theory of Operation ...................................................................... 19  ADC Architecture ...................................................................... 19  Analog Input Considerations.................................................... 19  Voltage Reference ....................................................................... 21  Clock Input Considerations ...................................................... 22  Power Dissipation and Standby Mode .................................... 24  Digital Outputs ........................................................................... 25  Timing ......................................................................................... 25  Built-In Self-Test (BIST) and Output Test .................................. 26  Built-In Self-Test (BIST) ............................................................ 26  Output Test Modes ..................................................................... 26  Channel/Chip Synchronization .................................................... 27  DC and Quadrature Error Correction (QEC) ............................ 28  Serial Port Interface (SPI) .............................................................. 29  Configuration Using the SPI ..................................................... 29  Hardware Interface..................................................................... 29  Configuration Without the SPI ................................................ 30  SPI Accessible Features .............................................................. 30  Memory Map .................................................................................. 31  Reading the Memory Map Register Table............................... 31  Open Locations .......................................................................... 31  Default Values ............................................................................. 31  Memory Map Register Table ..................................................... 32  Memory Map Register Descriptions ........................................ 34  Applications Information .............................................................. 36  Design Guidelines ...................................................................... 36  Outline Dimensions ....................................................................... 37  Ordering Guide .......................................................................... 37  REVISION HISTORY 1/10—Revision 0: Initial Version Rev. 0 | Page 2 of 40 AD9269 GENERAL DESCRIPTION The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The AD9269 incorporates an optional integrated dc correction and quadrature error correction block (QEC) that corrects for dc offset, gain, and phase mismatch between the two channels. This functional block can be very beneficial to complex signal processing applications such as direct conversion receivers. The ADC also contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus. The AD9269 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C). Rev. 0 | Page 3 of 40 AD9269 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error 1 Differential Nonlinearity (DNL) 2 Integral Nonlinearity (INL)2 MATCHING CHARACTERISTICS Offset Error Gain Error1 TEMPERATURE DRIFT Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation Error at 1.0 mA INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 3 Input CommonMode Voltage Input CommonMode Range REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD2 IDRVDD2 (1.8 V) IDRVDD2 (3.3 V) Temp Full Full Full Full Full Min 16 AD9269-20/AD9269-40 Typ Max Min 16 AD9269-65 Typ Max Min 16 AD9269-80 Typ Max Unit Bits Guaranteed ±0.05 ±0.40 −2.0 −0.9/+1.2 Guaranteed ±0.05 ±0.50 −2.0 −0.9/+1.4 Guaranteed ±0.05 ±0.50 −2.0 −0.9/+1.65 % FSR % FSR LSB 25°C Full 25°C −0.5/+0.6 ±5.50 ±2.0 −0.5/+1.1 ±6.50 ±2.2 −0.5/+1.1 ±6.50 ±3.3 LSB LSB LSB 25°C 25°C Full ±0.0 ±0.2 ±2 ±0.50 ±0.0 ±0.2 ±2 ±0.55 ±0.0 ±0.2 ±2 ±0.65 % FSR % FSR ppm/°C Full Full 0.981 0.993 2 1.005 0.981 0.993 2 1.005 0.981 0.993 2 1.005 V mV 25°C 2.8 2.8 2.8 LSB rms V p-p pF V 1.3 V kΩ Full Full Full Full Full 0.5 2 6.5 0.9 1.3 7.5 0.5 2 6.5 0.9 1.3 7.5 0.5 2 6.5 0.9 7.5 Full Full Full Full Full 1.7 1.7 1.8 1.9 3.6 52.5/72.6 1.7 1.7 1.8 1.9 3.6 101.2 1.7 1.7 1.8 1.9 3.6 119 V V mA mA mA 50.0/69.3 3.9/6.4 7.4/12.4 96.6 9.6 18.7 113 11.8 23 Rev. 0 | Page 4 of 40 AD9269 Parameter POWER CONSUMPTION DC Input Sine Wave Input2 (DRVDD = 1.8 V) Sine Wave Input2 (DRVDD = 3.3 V) Standby Power 4 Power-Down Power 1 2 Temp Min AD9269-20/AD9269-40 Typ Max Min AD9269-65 Typ Max Min AD9269-80 Typ Max Unit Full Full Full Full Full 87.7/121.7 96.9/136.3 114.4/165.7 37/37 1.0 102.0/142.3 170.7 191.2 235.6 37 1.0 199.8 200 224.6 279 37 1.0 240 mW mW mW mW mW Measured with a 1.0 V external reference. Measured with a 10 MHz input frequency at a rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 4 Standby power is measured with a dc input and the CLK+, CLK− active. Rev. 0 | Page 5 of 40 AD9269 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 200 MHz T WO-TONE SFDR fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) CROSSTALK 2 ANALOG INPUT BANDWIDTH 1 2 Temp 25°C 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full 25°C 25°C 25°C Full 25°C Full 25°C 25°C Full 25°C AD9269-20/AD9269-40 Min Typ Max 78.0 77.5 76.5 76.5 Min AD9269-65 Typ Max 77.5 77.5 Min AD9269-80 Typ Max 77.6 77.2 76.3 Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc MHz 76.5 76.5 75.5 71.0 77.9 77.2 77.4 77.2 76.0 76.4 76.4 75.0 69.4 12.6 12.5 12.4 12.6 12.5 12.4 12.6 12.5 12.3 11.2 −93 −92 −80 −97 −90 −80 −80 95 90 95 91 80 89 95 80 80 −99 −100 −90 −99 −100 −89 −100 −91 −97 −89 −86 90 −110 700 90 −110 700 90 −110 700 −99 −99 90 93 92 76.1 77.4 76.9 76.0 −95 −90 −80 −89 −97 −93 80 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. Rev. 0 | Page 6 of 40 AD9269 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SCLK/DFS, SYNC, PDWN) 1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (CSB) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SDIO/DCS)2 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS DRVDD = 3.3 V High Level Output Voltage, IOH = 50 μA High Level Output Voltage, IOH = 0.5 mA Low Level Output Voltage, IOL = 1.6 mA Low Level Output Voltage, IOL = 50 μA DRVDD = 1.8 V High Level Output Voltage, IOH = 50 μA High Level Output Voltage, IOH = 0.5 mA Low Level Output Voltage, IOL = 1.6 mA Low Level Output Voltage, IOL = 50 μA 1 2 Temp Min AD9269-20/AD9269-40/AD9269-65/AD9269-80 Typ Max CMOS/LVDS/LVPECL 0.9 Unit Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 0.2 GND − 0.3 −10 −10 8 10 4 3.6 AVDD + 0.2 +10 +10 12 V V p-p V μA μA kΩ pF V V μA μA kΩ pF V V μA μA kΩ pF V V μA μA kΩ pF 1.2 0 −50 −10 30 2 1.2 0 −10 40 26 2 1.2 0 −10 40 26 5 DRVDD + 0.3 0.8 −75 +10 DRVDD + 0.3 0.8 +10 135 DRVDD + 0.3 0.8 +10 130 Full Full Full Full Full Full Full Full 3.29 3.25 0.2 0.05 1.79 1.75 0.2 0.05 V V V V V V V V Internal 30 kΩ pull-down. Internal 30 kΩ pull-up. Rev. 0 | Page 7 of 40 AD9269 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate 1 CLK Period—Divide-by-1 Mode (tCLK) CLK Pulse Width High (tCH) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) DCO Propagation Delay (tDCO) DCO to Data Skew (tSKEW) Pipeline Delay (Latency) With QEC Active Wake-Up Time 2 Standby OUT-OF-RANGE RECOVERY TIME 1 2 Temp Full Full Full Full Full Full Full Full Full Full Full Full Full AD9269-20/AD9269-40 Min Typ Max 480 20/40 25.0/12.5 1.0 0.1 3 3 0.1 9 11 350 600/400 2 Min AD9269-65 Typ Max 480 65 7.69 1.0 0.1 3 3 0.1 9 11 350 300 2 Min AD9269-80 Typ Max 480 80 6.25 1.0 0.1 3 3 0.1 9 11 350 260 2 Unit MHz MSPS ns ns ns ps rms ns ns ns Cycles Cycles μs ns Cycles 3 50/25 3 15.38 3 12.5 Conversion rate is the clock rate after the CLK divider. Wake-up time is dependent on the value of the decoupling capacitors. N–1 N VIN N+1 N+2 tA N+3 N+4 N+5 tCH CLK+ CLK– tCLK tDCO DCOA/DCOB tSKEW 08538-002 08538-003 CH A/CH B DATA N–9 N–8 N–7 N–6 N–5 tPD Figure 2. CMOS Output Data Timing N–1 N VIN tA N+3 N+1 N+4 N+5 N+2 tCH CLK+ CLK– tCLK tDCO DCOA/DCOB tSKEW CH A/CH B DATA CH A N–9 CH B N–9 CH A N–8 CH B N–8 CH A N–7 CH B N–7 CH A N–6 CH B N–6 CH A N–5 tPD Figure 3. CMOS Interleaved Output Timing Rev. 0 | Page 8 of 40 AD9269 TIMING SPECIFICATIONS Table 5. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Conditions SYNC to rising edge of CLK setup time SYNC to rising edge of CLK hold time Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 2 40 2 2 10 10 10 10 Min Typ 0.24 0.40 Max Unit ns ns ns ns ns ns ns ns ns ns ns CLK+ tSSYNC SYNC tHSYNC 08538-004 Figure 4. SYNC Input Timing Requirements Rev. 0 | Page 9 of 40 AD9269 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to AGND DRVDD to AGND VIN+A, VIN+B, VIN−A, VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB to AGND PDWN to AGND D0x through D15x to AGND DCOx to AGND Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −40°C to +85°C 150°C −65°C to +150°C THERMAL CHARACTERISTICS The exposed paddle is the only ground connection for the chip. The exposed paddle must be soldered to the AGND plane of the user’s PCB. Soldering the exposed paddle to the user’s board also increases the reliability of the solder joints and maximizes the thermal capability of the package. Table 7. Thermal Resistance Airflow Velocity (m/sec) 0 1.0 2.5 Package Type 64-Lead LFCSP 9 mm × 9 mm (CP-64-4) 1 2 3 θJA1, 2 23 20 18 θJC1, 3 2.0 θJB1, 4 12 Unit °C/W °C/W °C/W Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θJA. ESD CAUTION Rev. 0 | Page 10 of 40 AD9269 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD CLK+ CLK– SYNC D0B (LSB) D1B D2B D3B D4B D5B DRVDD D6B D7B D8B D9B D10B D11B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9269 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS ORA D15A (MSB) D14A D13A D12A D11A DRVDD D10A D9A D8A D7A NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. D12B D13B DRVDD D14B D15B (MSB) ORB DCOB DCOA D0A (LSB) D1A D2A DRVDD D3A D4A D5A D6A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. 0, EP 1, 2 3 4 to 9, 11 to 18, 20, 21 10, 19, 28, 37 22 23 24 25 to 27, 29 to 36, 38 to 42 43 44 Mnemonic AGND CLK+, CLK− SYNC D0B (LSB) to D15B (MSB) DRVDD ORB DCOB DCOA D0A (LSB) to D15A (MSB) ORA SDIO/DCS Description The exposed paddle is the only ground connection. It must be soldered to the PCB analog ground to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down. Channel B Digital Outputs. D0B is the LSB; D15B is the MSB. Digital Output Driver Supply (1.8 V to 3.3 V). Channel B Out-of-Range Digital Output. Channel B Data Clock Digital Output. Channel A Data Clock Digital Output. Channel A Digital Outputs. D0A is the LSB; D15A is the MSB. Channel A Out-of-Range Digital Output. SPI Data Input/Output (SDIO). Bidirectional SPI data I/O in SPI mode. 30 kΩ internal pull-down in SPI mode. Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal pull-up in non-SPI (DCS) mode. SPI Clock (SCLK). Input in SPI mode. 30 kΩ internal pull-down. Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down. DFS high: twos complement output. DFS low: offset binary output. SPI Chip Select. Active low enable; 30 kΩ internal pull-up. Digital Input. 30 kΩ internal pull-down. Low: enable Channel A and Channel B digital outputs. High: three-state outputs. Digital Input. 30 kΩ internal pull-down. High: power down device. Low: run device, normal operation. 45 SCLK/DFS 46 47 CSB OEB 48 PDWN Rev. 0 | Page 11 of 40 08538-005 AD9269 Pin No. 49, 50, 53, 54, 59, 60, 63, 64 51, 52 55 56 57 58 61, 62 Mnemonic AVDD VIN+A, VIN−A VREF SENSE VCM RBIAS VIN−B, VIN+B Description 1.8 V Analog Supply Pins. Channel A Analog Inputs. Voltage Reference Input/Output. Reference Mode Selection. Analog Output Voltage at Midsupply. Sets the common mode of the analog inputs. Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. Channel B Analog Inputs. Rev. 0 | Page 12 of 40 AD9269 TYPICAL PERFORMANCE CHARACTERISTICS AD9269-80 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 –20 80MSPS 9.7MHz @ –1dBFS SNR = 76.8dB (77.8dBFS) SFDR = 94.3dBc AMPLITUDE (dBFS) 0 –20 80MSPS 30.6MHz @ –1dBFS SNR = 76.5dB (77.5dBFS) SFDR = 85.7dBc –40 AMPLITUDE (dBFS) –40 –60 –60 –80 –80 –100 –100 –120 08538-033 –120 08538-034 08538-054 –140 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) –140 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) Figure 6. AD9269-80 Single-Tone FFT with fIN = 9.7 MHz 0 –20 80MSPS 69MHz @ –1dBFS SNR = 75.1dB (76.1dBFS) SFDR = 89.5dBc AMPLITUDE (dBFS) Figure 9. AD9269-80 Single-Tone FFT with fIN = 30.6 MHz 0 –20 80MSPS 210MHz @ –1dBFS SNR = 70dB (71dBFS) SFDR = 79.7dBc –40 AMPLITUDE (dBFS) –40 –60 –60 –80 –80 –100 –100 –120 08538-035 –120 08538-036 –140 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) –140 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) Figure 7. AD9269-80 Single-Tone FFT with fIN = 69 MHz 0 –15 –30 80MSPS 28.3MHz @ –7dBFS 30.6MHz @ –7dBFS SFDR = 89.5dBc (96.5dBFS) Figure 10. AD9269-80 Single-Tone FFT with fIN = 210 MHz 10 –10 SFDR (dBc) –45 –60 –75 –90 SFDR/IMD3 (dBc/dBFS) –30 IMD3 (dBc) –50 AMPLITUDE (dBFS) –70 SFDR (dBFS) 2F1 + F2 2F2 + F1 F2 – F1 –105 –120 F1 + F2 2F2 – F1 2F1 – F2 –90 –110 IMD3 (dBFS) 08538-053 –135 4 8 12 16 20 24 28 FREQUENCY (MHz) 32 36 –130 –95 –85 –75 –65 –55 –45 –35 INPUT AMPLITUDE (dBFS) –25 –15 Figure 8. AD9269-80 Two-Tone FFT with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz Figure 11. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz Rev. 0 | Page 13 of 40 AD9269 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 100 90 80 SFDR (dBc) 100 120 SFDRFS SNR/SFDR (dBFS/dBc) 70 60 50 40 30 20 10 SNR (dBFS) SNR/SFDR (dBc/dBFS) 80 SNRFS SFDR 60 SNR 40 20 08538-057 0 50 100 150 INPUT FREQUENCY (MHz) 200 –50 –40 –30 –20 INPUT AMPLITUDE (dBFS) –10 0 Figure 12. AD9269-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale 100 90 80 SFDR (dBc) Figure 15. AD9269-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 4.0M 3.5M 3.0M 2.8 LSB RMS SNR/SFDR (dBFS/dBc) 70 60 50 40 30 NUMBER OF HITS SNR (dBFS) 2.5M 2.0M 1.5M 1.0M 20 10 08538-055 500k 0 N – 12 N – 11 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 08538-048 0 10 20 30 40 50 60 SAMPLE RATE (MSPS) 70 80 OUTPUT CODE Figure 13. AD9269-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz 1.5 6 Figure 16. Grounded Input Histogram 1.0 4 DNL ERROR (LSB) INL ERROR (LSB) 0.5 2 0 0 –0.5 –2 –1.0 –4 08538-038 0 16,384 32,768 OUTPUT CODE 49,152 65,536 0 16,384 32,768 OUTPUT CODE 49,152 65,536 Figure 14. DNL Error with fIN = 9.7 MHz Figure 17. INL with fIN = 9.7 MHz Rev. 0 | Page 14 of 40 08538-037 –1.5 –6 08538-061 0 0 –65 –60 AD9269 AD9269-65 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 –20 65MSPS 9.7MHz @ –1dBFS SNR = 76.9dB (77.9dBFS) SFDR = 95.9dBc 120 SFDRFS 100 SNR/SFDR (dBc/dBFS) AMPLITUDE (dBFS) –40 80 SNRFS SFDR 60 SNR 40 –60 –80 –100 –120 08538-030 20 0 5 10 15 20 25 30 –50 FREQUENCY (MHz) –40 –30 –20 INPUT AMPLITUDE (dBFS) –10 0 Figure 18. AD9269-65 Single-Tone FFT with fIN = 9.7 MHz 0 –20 –40 65MSPS 69MHz @ –1dBFS SNR = 75.5dB (76.5dBFS) SFDR = 87.4dBc Figure 21. AD9269-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz 100 SFDR (dBc) 90 80 SNR/SFDR (dBFS/dBc) AMPLITUDE (dBFS) 70 60 50 40 30 20 SNR (dBFS) –60 –80 –100 –120 10 0 5 10 15 20 25 30 0 50 FREQUENCY (MHz) 100 150 INPUT FREQUENCY (MHz) 200 Figure 19. AD9269-65 Single-Tone FFT with fIN = 69 MHz 0 –20 65MSPS 30.6MHz @ –1dBFS SNR = 76.6dB (77.6dBFS) SFDR = 89.9dBc Figure 22. AD9269-65 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale AMPLITUDE (dBFS) –40 –60 –80 –100 –120 –140 0 5 10 15 20 25 30 FREQUENCY (MHz) 08538-031 Figure 20. AD9269-65 Single-Tone FFT with fIN = 30.6 MHz Rev. 0 | Page 15 of 40 08539-056 –140 08538-032 0 08538-060 –140 0 –65 –60 AD9269 AD9269-40 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 –20 40MSPS 9.7MHz @ –1dBFS SNR = 76.9dB (77.9dBFS) SFDR = 95.1dBc 120 SFDRFS 100 AMPLITUDE (dBFS) –40 –60 –80 –100 –120 08538-028 SNR/SFDR (dBFS/dBFS) 80 SNRFS SFDR 60 SNR 40 20 0 2 4 6 8 10 12 14 16 18 20 –50 FREQUENCY (MHz) –40 –30 –20 INPUT AMPLITUDE (dBFS) –10 0 Figure 23. AD9269-40 Single-Tone FFT with fIN = 9.7 MHz 0 –20 40MSPS 30.6MHz @ –1dBFS SNR = 76.6dB (77.6dBFS) SFDR = 88.8dBc Figure 25. AD9269-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz AMPLITUDE (dBFS) –40 –60 –80 –100 –120 08538-029 –140 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) Figure 24. AD9269-40 Single-Tone FFT with fIN = 30.6 MHz Rev. 0 | Page 16 of 40 08538-059 –140 0 –65 –60 AD9269 AD9269-20 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled, unless otherwise noted. 0 –20 20MSPS 9.7MHz @ –1dBFS SNR = 76.9dB (77.9dBFS) SFDR = 95.6dBc 120 SFDRFS 100 SNR/SFDR (dBc/dBFS) AMPLITUDE (dBFS) –40 –60 –80 –100 –120 08538-024 SNRFS 80 60 SFDR (dBc) 40 SNR (dBc) 20 0 1 2 3 4 5 6 7 8 9 10 –80 –70 FREQUENCY (MHz) –60 –50 –40 –30 –20 INPUT AMPLITUDE (dBFS) –10 0 Figure 26. AD9269-20 Single-Tone FFT with fIN = 9.7 MHz 0 –20 20MSPS 30.6MHz @ –1dBFS SNR = 76.7dB (77.7dBFS) SFDR = 90.7dBc Figure 28. AD9269-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz AMPLITUDE (dBFS) –40 –60 –80 –100 –120 08538-026 –140 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (MHz) Figure 27. AD9269-20 Single-Tone FFT with fIN = 30.6 MHz Rev. 0 | Page 17 of 40 08538-058 –140 0 –90 AD9269 EQUIVALENT CIRCUITS AVDD DRVDD VIN±x 08538-039 Figure 29. Equivalent Analog Input Circuit AVDD Figure 34. Equivalent Digital Output Circuit AVDD DRVDD 30kΩ 350Ω SDIO/DCS 30kΩ RBIAS AND VCM 08538-041 375Ω 08538-042 Figure 30. Equivalent SDIO/DCS Input Circuit DRVDD Figure 35. Equivalent RBIAS, VCM Circuit DRVDD AVDD SCLK/DFS, SYNC, OEB, AND PDWN 350Ω 30kΩ 08538-043 350Ω CSB 30kΩ Figure 31. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit Figure 36. Equivalent CSB Input Circuit AVDD AVDD 375Ω 375Ω VREF 08538-047 SENSE Figure 32. Equivalent VREF Circuit AVDD 5Ω Figure 37. Equivalent SENSE Circuit CLK+ 15kΩ 0.9V AVDD 5Ω CLK– 08538-040 15kΩ Figure 33. Equivalent Clock Input Circuit Rev. 0 | Page 18 of 40 08538-046 7.5kΩ 08538-045 08538-044 AD9269 THEORY OF OPERATION The AD9269 dual-channel ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 200 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 300 MHz analog input is permitted, but it occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD9269 can be used as a baseband or direct downconversion receiver, in which one ADC is used for I input data and the other is used for Q input data. The AD9269 incorporates an optional, integrated dc correction and quadrature error correction block (QEC) that can correct for dc offset, gain, and phase mismatch between the two channels. This functional block can be very beneficial to complex signal processing applications such as direct conversion receivers. Synchronization capability is provided to allow synchronized timing between multiple channels or multiple devices. Programming and control of the AD9269 are accomplished using a 3-wire SPI-compatible serial interface. ANALOG INPUT CONSIDERATIONS The analog input to the AD9269 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance. The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 38). When the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. Refer to the AN-742 Application Note, Frequency Domain Response of SwitchedCapacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (see www.analog.com); and the Analog Dialogue article, “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. ADC ARCHITECTURE The AD9269 architecture consists of a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the CMOS output buffers. The output buffers are powered from a separate (DRVDD) supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. H CPAR VIN+x H CSAMPLE S S S S CSAMPLE VIN–x CPAR H H 08538-006 Figure 38. Switched-Capacitor Input Circuit Rev. 0 | Page 19 of 40 AD9269 Input Common Mode The analog inputs of the AD9269 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 39. 100 95 SFDR (dBc) 90 SNR/SFDR (dBFS/dBc) driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 200Ω VIN 76.8Ω 33Ω 90Ω VIN–x AVDD ADA4938-2 0.1µF 120Ω 200Ω 10pF 33Ω ADC 08538-007 08538-008 VIN+x VCM Figure 40. Differential Input Configuration Using the ADA4938-2 85 80 75 SNR (dBFS) For baseband applications below ~10 MHz where SNR is a key parameter, differential transformer-coupling is the recommended input configuration (see Figure 41). To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. VIN+x R 70 65 60 0.5 08538-049 2V p-p 49.9Ω R C ADC VIN–x VCM 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 0.1µF INPUT COMMON-MODE VOLTAGE (V) Figure 39. SNR/SFDR vs. Input Common-Mode Voltage, fIN = 32.5 MHz, fS = 80 MSPS Figure 41. Differential Transformer-Coupled Configuration An on-board, common-mode voltage reference is included in the design and is available from the VCM pin. The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9269. For applications above ~10 MHz where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 42). An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver (see Figure 43). Refer to the AD8352 data sheet for more information. R VIN+x 25Ω Differential Input Configurations Optimum performance is achieved while driving the AD9269 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9269 (see Figure 40), and the 0.1µF 2V p-p PA S S P 0.1µF 25Ω 0.1µF C 0.1µF R VIN–x ADC VCM 08538-010 Figure 42. Differential Double Balun Input Configuration VCC 0.1µF ANALOG INPUT 0Ω 16 1 2 CD RD RG 3 4 ANALOG INPUT 5 0.1µF 0Ω 14 0.1µF 0.1µF 8, 13 11 0.1µF 0.1µF R 200Ω VIN+x C 0.1µF 200Ω R VIN–x VCM 08538-011 AD8352 10 ADC Figure 43. Differential Input Configuration Using the AD8352 Rev. 0 | Page 20 of 40 AD9269 In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 9 displays the suggested values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. Table 9. Example RC Network Frequency Range (MHz) 0 to 70 70 to 200 R Series (Ω Each) 33 125 C Differential (pF) 22 Open Internal Reference Connection A comparator within the AD9269 detects the potential at the SENSE pin and configures the reference into two possible modes, which are summarized in Table 10. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 45), setting VREF to 1.0 V. VIN+A/VIN+B VIN–A/VIN–B ADC CORE Single-Ended Input Configuration A single-ended input can provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 44 shows a typical single-ended input configuration. 10µF AVDD 1kΩ 1V p-p 49.9Ω 0.1µF 1kΩ C R 08538-009 VREF 1.0µF 0.1µF SELECT LOGIC SENSE 0.5V 08538-012 ADC R VIN+x Figure 45. Internal Reference Configuration AVDD 1kΩ 10µF 0.1µF 1kΩ ADC VIN–x If the internal reference of the AD9269 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 46 shows how the internal reference voltage is affected by loading. 0 Figure 44. Single-Ended Input Configuration REFERENCE VOLTAGE ERROR (%) VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9269. VREF can be configured using either the internal 1.0 V reference or an externally applied 1.0 V reference voltage. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the bestpractices PCB layout of the reference. –0.5 –1.0 INTERNAL VREF = 0.993V –1.5 –2.0 –2.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (mA) Figure 46. VREF Accuracy vs. Load Current Table 10. Reference Configuration Summary Selected Mode Fixed Internal Reference Fixed External Reference SENSE Voltage (V) AGND to 0.2 AVDD Resulting VREF ( V) 1.0 internal 1.0 applied to external VREF pin Resulting Differential Span (V p-p) 2.0 2.0 Rev. 0 | Page 21 of 40 08538-014 –3.0 AD9269 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 47 shows the typical drift characteristics of the internal reference in 1.0 V mode. 4 3 2 VREF ERROR (mV) 1 VREF ERROR (mV) Clock Input Options The AD9269 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 49 and Figure 50 show two preferred methods for clocking the AD9269 (at rates up to 6× the specified sample rate when using the internal clock divider function). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer. The RF balun configuration is recommended for clock frequencies between 125 MHz and 480 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9269 to approximately 0.8 V p-p differential. 0 –1 –2 –3 –4 –5 08538-052 –6 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 47. Typical VREF Drift When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7.5 kΩ load (see Figure 32). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9269 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. 1nF CLOCK INPUT 50Ω 0.1µF CLK+ 0.1µF ADC CLK– 08538-018 1nF SCHOTTKY DIODES: HSMS2822 CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9269 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 48) and require no external bias. AVDD Figure 49. Balun-Coupled Differential Clock (Up to 480 MHz) Mini-Circuits® ADT1-1WT, 1:1 Z 0.1µF CLOCK INPUT 50Ω 100Ω 0.1µF XFMR 0.1µF CLK+ ADC CLK– 08538-017 0.9V CLK+ CLK– 0.1µF SCHOTTKY DIODES: HSMS2822 2pF 2pF 08538-016 Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz) Figure 48. Equivalent Clock Input Circuit Rev. 0 | Page 22 of 40 AD9269 If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 51. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. The AD9269 clock divider can be synchronized using the external SYNC input. Bits[2:1] in Register 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. 0.1µF CLOCK INPUT 0.1µF CLOCK INPUT 50kΩ 50kΩ AD951x PECL DRIVER 240Ω 240Ω 0.1µF CLK+ 100Ω 0.1µF CLK– 08538-019 Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9269 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9269. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 54. 80 79 DCS OFF DCS ON ADC Figure 51. Differential PECL Sample Clock (Up to 480 MHz) A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 52. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. 0.1µF CLOCK INPUT 0.1µF CLOCK INPUT 50kΩ 50kΩ AD951x LVDS DRIVER 0.1µF CLK+ 100Ω 0.1µF CLK– 08538-020 ADC 78 77 In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 53). VCC 0.1µF CLOCK INPUT 50Ω 1 1kΩ 1kΩ AD951x CMOS DRIVER OPTIONAL 0.1µF 100Ω CLK+ SNR (dBFS) Figure 52. Differential LVDS Sample Clock (Up to 480 MHz) 76 75 74 73 72 71 70 30 08538-064 35 40 45 50 55 60 65 70 POSITIVE DUTY CYCLE (%) ADC CLK– 0.1µF 08538-021 Figure 54. SNR vs. Duty Cycle Stabilizer On/Off 150Ω RESISTOR IS OPTIONAL. Figure 53. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Input Clock Divider The AD9269 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 6. Optimum performance is obtained by enabling the internal duty cycle stabilizer (DCS) when using divide ratios other than 1, 2, or 4. Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 20 MHz nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after the dynamic clock frequency increases or decreases before the DCS loop is relocked to the input signal. Rev. 0 | Page 23 of 40 AD9269 Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( − SNRLF /10) ] In the previous equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 55. 80 75 POWER DISSIPATION AND STANDBY MODE As shown in Figure 56, the analog core power dissipated by the AD9269 is proportional to its sample rate. The digital power dissipation of the CMOS outputs is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD current (IDRVDD) can be calculated as IDRVDD = VDRVDD × CLOAD × fCLK × N where N is the number of output bits (34, in the case of the AD9269). 210 0.05ps 190 AD9269-80 70 0.2ps ANALOG CORE POWER (mW) 170 SNR (dBFS) 65 150 AD9269-65 60 55 50 3.0ps 1 10 100 0.5ps 130 110 1.0ps 1.5ps 2.0ps 2.5ps 1k 07938-022 AD9269-40 90 AD9269-20 70 10 20 30 40 50 60 70 80 08538-051 45 FREQUENCY (MHz) CLOCK RATE (MSPS) Figure 55. SNR vs. Input Frequency and Jitter Figure 56. Analog Core Power vs. Clock Rate The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9269. To avoid modulating the clock signal with digital noise, keep power supplies for clock drivers separate from the ADC output driver supplies. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. For more information, see the AN-501 Application Note and the AN-756 Application Note, available on www.analog.com. This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 56 was taken using the same operating conditions as those used for the Typical Performance Characteristics, with a 5 pF load on each output driver. Rev. 0 | Page 24 of 40 AD9269 The AD9269 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates 1 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9269 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map section for more details. Table 11. SCLK/DFS Mode Selection (External Pin Mode) Voltage at Pin AGND DRVDD SCLK/DFS Offset binary (default) Twos complement SDIO/DCS DCS disabled DCS enabled (default) As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. Digital Output Enable Function (OEB) The AD9269 provides a flexible three-state ability for the digital output pins. The three-state mode is enabled by the OEB pin or through the SPI interface. If the OEB pin is low, the output data drivers and DCOs are enabled. If the OEB pin is high, the output data drivers and DCOs are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. When using the SPI interface, the data outputs and DCO of each channel can be independently three-stated by using the output disable (OEB) bit, Bit 4 in Register 0x14. DIGITAL OUTPUTS The AD9269 output drivers can be configured to interface with 1.8 V to 3.3 V CMOS logic families. Output data can also be multiplexed onto a single output bus to reduce the total number of traces required. The CMOS output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies and may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. The output data format can be selected to be either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 11). TIMING The AD9269 provides latched data with a pipeline delay of nine clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9269. These transients may degrade converter dynamic performance. The lowest typical conversion rate of the AD9269 is 3 MSPS. At clock rates below 3 MSPS, dynamic performance may degrade. Data Clock Output (DCO) The AD9269 provides two data clock output (DCO) signals that are designed to capture the data in an external register. The CMOS data outputs are valid on the rising edge of DCO unless the DCO clock polarity has been changed via the SPI. See Figure 2 and Figure 3 for a graphical timing description. Table 12. Output Data Format Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− Condition (V) < −VREF − 0.5 LSB = −VREF =0 = +VREF − 1.0 LSB > +VREF − 0.5 LSB Offset Binary Output Mode 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 Twos Complement Mode 1000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1111 OR 1 0 0 0 1 Rev. 0 | Page 25 of 40 AD9269 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9269 includes a built-in test feature that is designed to enable verification of the integrity of each channel as well as to facilitate board-level debugging. A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9269 is included. Various output test options are also provided to place predictable values on the outputs of the AD9269. This enables Bit 0 (BIST enable) in Register 0x0E and resets the PN sequence generator, Bit 2 (BIST init) in Register 0x0E. At the completion of the BIST, Bit 0 in Register 0x24 is automatically cleared. The PN sequence can be continued from its last value by writing a 0 in Bit 2 in Register 0x0E. However, if the PN sequence is not reset, the signature calculation does not equal the predetermined value at the end of the test. At that point, the user must rely on verifying the output data. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9269 signal path. Perform the BIST test after a reset to ensure that the part is in a known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output. At the datapath output, CRC logic calculates a signature from the data. The BIST sequence runs for 512 cycles and then stops. When the sequence is complete, the BIST compares the signature results with a predetermined value. If the signatures match, the BIST sets Bit 0 in Register 0x24, signifying that the test passed. If the BIST test failed, Bit 0 in Register 0x24 is cleared. The outputs are connected during this test, so the PN sequence can be observed as it runs. Writing the value 0x05 to Register 0x0E runs the BIST. OUTPUT TEST MODES The output test options are described in Table 17 at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks, and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 in Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. 0 | Page 26 of 40 AD9269 CHANNEL/CHIP SYNCHRONIZATION The AD9269 has a SYNC input that offers the user flexible synchronization options for synchronizing sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock; however, to ensure that there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times that are shown in Table 5. Drive the SYNC input using a single-ended CMOS-type signal. Rev. 0 | Page 27 of 40 AD9269 DC AND QUADRATURE ERROR CORRECTION (QEC) In direct conversion or other quadrature systems, mismatches between the real (I) and imaginary (Q) signal paths cause frequencies in the positive spectrum to image into the negative spectrum, and vice versa. From an RF point of view, this is equivalent to information above the local oscillator (LO) frequency interfering with information below the LO frequency, and vice versa. These mismatches may occur from gain and/or phase mismatches in the analog quadrature demodulator or in any other mismatches between the I and Q signal chains. In a single-carrier zero-IF system where the carrier has been placed symmetrically around dc, this causes self-distortion of the carrier as the two sidebands fold onto one another and degrade the error vector magnitude (EVM) of the signal. In a multicarrier communication system, this can be even more problematic because carriers of widely different power levels can interfere with one another. For example, a large carrier centered at +f1 can have an image appear at −f1 that may be much larger than the desired carrier at −f1. The integrated quadrature error correction (QEC) algorithm of the AD9269 attempts to measure and correct the amplitude and phase imbalances of the I and Q signal paths to achieve higher levels of image suppression than is achievable by analog means alone. These errors can be corrected in an adapted manner, in which the I and Q gain and quadrature phase mismatches are constantly estimated and corrected, allowing for constant tracking of slow changes in mismatches that are due to supply and temperature. The quadrature errors are corrected in a frequency independent manner on the AD9269; therefore, systems with significant mismatch in the baseband I and Q signal chains may have reduced image suppression. The AD9269 QEC still corrects the systematic imbalances. The convergence time of the QEC algorithm is dependent on the statistics of the input signal. For large signals and large imbalance errors, this convergence time is typically less than 2 million samples of the AD9269 data rate. The default configuration on the AD9269 has the QEC and dc correction blocks disabled, and Bits[2:0] in Register 0x110 must be pulled high to enable the correction blocks. The quadrature gain, quadrature phase, and dc correction algorithms can also be disabled independently for system debugging or to save power by pulling Bits[2:0] low in Register 0x110. When the QEC is enabled and a correction value has been calculated, the value remains active as long as any of the QEC functions (DC, gain, or phase correction) are being used. QEC and DC Correction Range Table 13 gives the minimum and maximum correction ranges of the algorithms. If the mismatches are greater than these ranges, an imperfect correction results. Table 13. QEC and DC Correction Range Parameter Gain Phase DC 0 –15 –30 AMPLITUDE (dBFS) Minimum −1.1 dB −1.79 degrees −6 % Maximum +1.0 dB +1.79 degrees +6% –45 –60 –75 –90 –105 –120 –135 3 2 DC OFFSET IMAGE 5 6 4 0M –7.5M 7.5M 15M 22.5M 30M –37.5M –30.0M –22.5M –15.0M 37.5M FREQUENCY (MHz) Figure 57. QEC Mode Off 0 –15 –30 AMPLITUDE (dBFS) LO Leakage (DC) Correction In a direct conversion receiver subsystem, LO to RF leakage of the quadrature modulator shows up as dc offsets at baseband. These offsets are added to dc offsets in the baseband signal paths, and both contribute to a carrier at dc. In a zero-IF receiver, this dc energy can cause problems because it appears in band of a desired channel. As part of the QEC function, the dc offset is suppressed by applying a low frequency notch filter to form a null around dc. In applications where constant tracking of the dc offsets and quadrature errors are not needed, the algorithms can be independently frozen to save power. When frozen, the image and LO leakage (dc) correction are still performed, but changes are no longer tracked. Bits[5:3] in Register 0x110 disable the respective correction when frozen. Rev. 0 | Page 28 of 40 –45 –60 –75 –90 –105 –120 –135 0M –7.5M 7.5M 15M 22.5M 30M –37.5M –30.0M –22.5M –15.0M 37.5M 08538-066 2 3 DC OFFSET IMAGE 6 5 4 FREQUENCY (MHz) Figure 58. QEC Mode On 08538-065 AD9269 SERIAL PORT INTERFACE (SPI) The AD9269 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI provides added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. SPI functions are placed in high impedance mode. This mode turns on any secondary functions of the SPI function pins. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and the length of the data stream is determined by the W1 and W0 bits, as shown in Figure 59. All data is composed of 8-bit words. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. This allows the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/ output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK, the SDIO, and the CSB (see Table 14). The SCLK (a serial clock) is used to synchronize the read and write data presented from and to the ADC. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an activelow control that enables or disables the read and write cycles. Table 14. Serial Port Interface Pins Pin SCLK SDIO Function Serial clock. A serial shift clock input that is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active-low control that gates the read and write cycles. HARDWARE INTERFACE The pins described in Table 14 constitute the physical interface between the programming device of the user and the serial port of the AD9269. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. CSB The falling edge of the CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 59 and Table 5. Other modes involving the CSB are available. The CSB can be held low indefinitely, permanently enabling the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When the CSB is tied high, the tHIGH tDH tLOW tDS tS CSB tCLK tH SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 59. Serial Port Interface Timing Diagram Rev. 0 | Page 29 of 40 08538-023 AD9269 The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9269 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SDIO/DCS and SCLK/DFS serve a dual function when the SPI interface is not being used. When the pins are strapped to DRVDD or ground during device power-on, they are associated with a specific function. The Digital Outputs section describes the strappable functions supported on the AD9269. SPI ACCESSIBLE FEATURES Table 16 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9269 part-specific features are described in detail in Table 17. Table 16. Features Accessible Using the SPI Feature Mode Clock Offset Test I/O Output Mode Output Phase Output Delay VREF Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS via the SPI Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the reference voltage CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control. In this mode, connect the CSB chip select to DRVDD, which disables the serial port interface. Table 15. Mode Selection Pin SDIO/DCS SCLK/DFS OEB PDWN External Voltage DRVDD (default) AGND DRVDD AGND (default) DRVDD AGND (default) DRVDD AGND (default) Configuration Duty cycle stabilizer enabled Duty cycle stabilizer disabled Twos complement enabled Offset binary enabled Outputs in high impedance Outputs enabled Chip in power-down or standby Normal operation Rev. 0 | Page 30 of 40 AD9269 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table (see Table 17) contains eight bit locations. The memory map is divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the device index and transfer registers (Address 0x05 and Address 0xFF); the program registers, including setup, control, and test (Address 0x08 to Address 0x2E); and the digital feature control registers (Address 0x100 to Address 0x11D). Table 17 documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x05, the channel index register, has a hexadecimal default value of 0x03. This means that in Address 0x05, Bits[7:2] = 0, and the remaining Bits[1:0] = 1. This setting is the default channel index setting. The default value results in both ADC channels receiving the next write command. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This document details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers, Register 0x100 to Register 0x11D, are documented in the Memory Map Register Descriptions section following Table 17. DEFAULT VALUES After the AD9269 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 17). Logic Levels An explanation of logic level terminology follows: • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Transfer Register Map Address 0x08 to Address 0x18 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and then the bit autoclears. Channel-Specific Registers Some channel setup functions can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in the memory map register table as local. These local registers and bits can be accessed by setting the appropriate Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, set only Channel A or Channel B to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in the memory map register table affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. OPEN LOCATIONS All address and bit locations that are not included in the SPI map are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x05). If the entire address location is open, it is omitted from the SPI map (for example, Address 0x13) and should not be written. Rev. 0 | Page 31 of 40 AD9269 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Addr. Register (Hex) Name Chip configuration registers 0x00 SPI port configuration (global) (MSB) Bit 7 0 Bit 6 LSB first Bit 5 Soft reset Bit 4 1 Bit 3 1 Bit 2 Soft reset Bit 1 LSB first (LSB) Bit 0 0 Default Value (Hex) 0x18 Comments The nibbles are mirrored so that LSB- or MSB-first mode registers correctly, regardless of shift mode Unique chip ID used to differentiate devices; read only Unique speed grade ID used to differentiate devices; read only Bits are set to determine which device on chip receives the next write command; the default is all devices on chip Synchronously transfers data from the master shift register to the slave Determines various generic modes of chip operation 0x01 Chip ID (global) 8-bit chip ID, Bits[7:0] AD9269 = 0x75 0x75 0x02 Chip grade (global) Open Speed grade ID, Bits[6:4] 20 MSPS = 000 40 MSPS = 001 65 MSPS = 010 80 MSPS = 011 Open Open Open Open Open Open N/A Device index and transfer registers 0x05 Channel index Open ADC B default ADC A default 0x03 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Program registers (may or may not be indexed by device index) External pin function 0x08 Modes External 0x00 = powerfull power-down down 0x01 = standby enable (local) (local) Open Open 0x09 Clock (global) Open Open Open Open 0x0B Clock divider (global) Open 00 = chip run 01 = full powerdown 10 = standby 11 = chip-wide digital reset (local) Open Duty cycle stabilize Clock divider, Bits[2:0] Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 0x80 0x00 0x00 The divide ratio is the value plus 1 Rev. 0 | Page 32 of 40 AD9269 Addr. (Hex) 0x0D Register Name Test mode (local) (MSB) Bit 7 Bit 6 User test mode (local) 00 = single 01 = alternate 10 = single once 11 = alternate once Bit 5 Reset PN long gen Bit 4 Reset PN short gen (LSB) Bit 3 Bit 2 Bit 1 Bit 0 Output test mode [3:0] (local) 0000 = off (default) 0001 = midscale short 0010 = positive FS 0011 = negative FS 0100 = alternating checkerboard 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency Open BIST init Open BIST enable Default Value (Hex) 0x00 Comments When set, the test data is placed on the output pins in place of normal data 0x0E BIST enable Open Open Open Open 0x00 0x10 0x14 Offset adjust (local) Output mode 8-bit device offset adjustment [7:0] (local) Offset adjust in LSBs from +127 to −128 (twos complement format) Output Open Output 00 = 3.3 V CMOS Output mux disable invert 10 = 1.8 V CMOS enable (local) (interleaved) (OEB) (local) 0x00 0x00 When Bit 0 is set, the BIST function is initiated Device offset trim Configures the outputs and the format of the data 0x15 OUTPUT_ADJUST 0x16 OUTPUT_PHASE 3.3 V DCO drive strength 00 = 1 stripe (default) 01 = 2 stripes 10 = 3 stripes 11 = 4 stripes Open DCO output polarity 0= normal 1= inverted (local) 1.8 V DCO drive strength 00 = 1 stripe 01 = 2 stripes 10 = 3 stripes (default) 11 = 4 stripes Open Open 0x17 OUTPUT_DELAY Enable DCO delay Open Enable data delay Open 0x19 0x1A 0x1B 0x1C 0x24 USER_PATT1_LSB USER_PATT1_MSB USER_PATT2_LSB USER_PATT2_MSB MISR_LSB B7 B15 B7 B15 Open B6 B14 B6 B14 Open B5 B13 B5 B13 Open B4 B12 B4 B12 Open 00 = offset binary 01 = twos complement 10 = gray code 11 = offset binary (local) 1.8 V data 3.3 V data drive strength drive strength 00 = 1 stripe 00 = 1 stripe 01 = 2 stripes (default) 10 = 3 stripes 01 = 2 stripes (default) 10 = 3 stripes 11 = 4 stripes 11 = 4 stripes Open Input clock phase adjust, Bits[2:0] (Value is number of input clock cycles of phase delay) 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles Open DCO/data delay, Bits[2:0] 000 = 0.56 ns 001 = 1.12 ns 010 = 1.68 ns 011 = 2.24 ns 100 = 2.80 ns 101 = 3.36 ns 110 = 3.92 ns 111 = 4.48 ns B3 B2 B1 B0 B11 B3 B11 B10 B2 B10 Open B9 B1 B9 Open B8 B0 B8 B0 0x22 Determines CMOS output drive strength properties 0x00 On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock; internal latching is unaffected This sets the fine output delay of the output clock but does not change internal timing 0x00 0x00 0x00 0x00 0x00 0x00 Open User-Defined Pattern 1, LSB User-defined Pattern 1, MSB User-Defined Pattern 2, LSB User-Defined Pattern 2, MSB Least significant byte of MISR; read only Rev. 0 | Page 33 of 40 AD9269 Addr. (Hex) 0x2A Register Name Features (MSB) Bit 7 Open Bit 6 Open Bit 5 Open Bit 4 Open Bit 3 Open Bit 2 Open Bit 1 Open (LSB) Bit 0 OR OE (local) 0= ADC A 1= ADC B (local) Master sync enable Default Value (Hex) 0x01 Comments Disable the OR pin for the indexed channel Assign an ADC to an output channel 0x2E Output assign Open Open Open Open Open Open Open Ch A = 0x00 Ch B = 0x01 Digital feature control 0x100 Sync control (global) Open Open Open Open Open 0x101 USR2 0x110 0x111 0x112 0x113 0x114 0x116 0x117 0x118 0x119 0x11A 0x11B 0x11C 0x11D QEC Control 0 QEC Control 1 QEC gain bandwidth control QEC phase bandwidth control QEC DC bandwidth control QEC Initial Gain 0 QEC Initial Gain 1 QEC Initial Phase 0 QEC Initial Phase 1 QEC Initial DC I 0 QEC Initial DC I 1 QEC Initial DC Q 0 QEC Initial DC Q 1 Enable OEB (Pin 47) (local) Open Open Enable GCLK detect Freeze phase Open Freeze gain Open Clock divider next sync only Run GCLK Clock divider sync enable Open 0x01 Open Open Open Open Open Freeze DC DC enable Force DC KEXP_GAIN KEXP_PHASE KEXP_DC Phase enable Force phase Disable SDIO pulldown Gain enable Force gain 0x88 Enables internal oscillator for clock rates of