AD9283BRSZ-RL80

a 8-Bit, 50 MSPS/80 MSPS/100 MSPS 3 V A/D Converter AD9283 FEATURES 8-Bit, 50, 80, and 100 MSPS ADC Low Power: 90 mW at 100 MSPS On-Chip Reference and Track/Hold 475 MHz Analog Bandwidth SNR = 46.5 dB @ 41 MHz at 100 MSPS 1 V p-p Analog Input Range Single 3.0 V Supply Operation (2.7 V–3.6 V) Power-Down Mode: 4.2 mW APPLICATIONS Battery Powered Instruments Hand-Held Scopemeters Low Cost Digital Oscilloscopes GENERAL DESCRIPTION The AD9283 is an 8-bit monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and is optimized for low cost, low power, small size and ease of use. The product operates at a 100 MSPS conversion rate, with outstanding dynamic performance over its full operating range. The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and an encode clock for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic. FUNCTIONAL BLOCK DIAGRAM VD PWRDWN VDD AD9283 A IN T/H ADC A IN ENCODE TIMING REF GND REF REF OUT IN OUTPUT STAGING 8 D7–D0 The encoder input is TTL/CMOS compatible. A power-down function may be exercised to bring total consumption to 4.2 mW. In power-down mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced CMOS process, the AD9283 is available in a 20-lead surface mount plastic package (SSOP) specified over the industrial temperature range (–40°C to +85°C). REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD9283–SPECIFICATIONS (V DD = 3.0 V, VD = 3.0 V; single-ended input; external Parameter Temp Test Level AD9283BRS-100 Min Typ Max RESOLUTION DC ACCURACY Differential Nonlinearity AD9283BRS-80 Min Typ Max 8 ± 0.5 reference, unless otherwise noted) AD9283BRS-50 Min Typ Max 8 ± 0.5 ± 0.5 I VI I VI VI I VI VI Analog Bandwidth, Full Power Full Full 25°C Full Full Full 25°C Full 25°C Full 25°C V V I VI VI VI I VI V VI V SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth Low (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 Full 25°C 25°C 25°C 25°C 25°C Full Full VI IV IV IV V V VI VI DIGITAL INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance Full Full Full Full 25°C VI VI VI VI V 2.0 Full Full VI VI 2.95 2.95 2.95 0.05 Offset Binary Code 0.05 Offset Binary Code 0.05 Offset Binary Code Full Full VI VI 90 4.2 90 4.2 80 4.2 25°C I No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (With Respect to AIN) Common-Mode Voltage Input Offset Voltage Reference Voltage Reference Tempco Input Resistance Input Capacitance DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage Output Coding POWER SUPPLY Power Dissipation3, 4 Power-Down Dissipation Power Supply Rejection Ratio (PSRR) –1.25 ± 0.75 Guaranteed –6 ± 2.5 –8 80 –35 1.2 7 5 ± 512 ± 200 ± 10 ± 40 1.25 ± 130 10 +6 +8 –6 –8 ± 0.75 Guaranteed ± 2.5 +35 –35 1.3 1.2 13 16 7 5 +6 +8 –1.25 –6 –8 ± 0.75 Guaranteed ± 2.5 80 80 ± 512 ± 200 ± 10 ± 40 1.25 ± 130 10 ± 512 ± 200 ± 10 ± 40 1.25 ± 130 10 +35 –35 1.3 1.2 13 16 7 5 2 2 2 475 475 475 100 80 1 1000 1000 4.3 4.3 2.0 –1.25 +1.25 +1.50 +1.25 +1.50 Bits 25°C Full 25°C Full Full 25°C Full Full Integral Nonlinearity +1.25 +1.50 +1.25 +2.25 8 0 5 3.0 4.5 5.0 5.0 2.0 7.0 0 5 3.0 4.5 2.0 18 –2– +6 +8 % FS % FS ppm/°C +35 1.3 13 16 0 5 3.0 4.5 7.0 2.0 0.8 ±1 ±1 0.8 ±1 ±1 2.0 120 7 LSB LSB LSB LSB 1 1000 1000 8.0 8.0 7.0 2.0 0.8 ±1 ±1 2.0 +1.25 +1.50 +1.25 +1.50 50 1 1000 1000 2.0 115 7 18 Unit mV p-p mV mV mV V ppm/°C kΩ kΩ pF µA MHz MSPS MSPS ns ns ns ps rms ns ns V V µA µA pF V V 100 7 mW mW 18 mV/V REV. C AD9283 Parameter Temp Test Level AD9283BRS-100 Min Typ Max 25°C 25°C V V 25°C 25°C 25°C 25°C I I I V 46.5 46.5 43.5 46.5 46.0 25°C 25°C 25°C 25°C I I I V 45 45.5 42.5 45 42.5 25°C 25°C 25°C 25°C I I I V 7.3 7.4 7.3 6.9 25°C 25°C 25°C 25°C I I I V 57 60 58 46 25°C 25°C 25°C 25°C I I I V 25°C V AD9283BRS-80 Min Typ Max AD9283BRS-50 Min Typ Max Unit 5 DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz Effective Number of Bits fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz 2nd Harmonic Distortion fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz 3rd Harmonic Distortion fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz Two-Tone Intermod Distortion (IMD) fIN = 10.3 MHz 2 2 50 47 2 2 44 47 47 47 44 47 43.5 46.5 42 52 ns ns 47 47 dB dB dB dB 43.5 46.5 46 7.5 7.5 7.5 54.5 55 52.5 53 2 2 dB dB dB dB 7.6 7.5 Bits Bits Bits Bits 60 60 55 55 55 60 56 dBc dBc dBc dBc 70 62.5 60 55 55 70 60 dBc dBc dBc dBc 52 dBc 52 NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference). 2 tV and tPD are measured from the 1.5 V level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of ± 40 µA. 3 Power dissipation measured with encode at rated speed and a dc analog input. 4 Typical thermal impedance for the RS style (SSOP) 20-lead package: θJC = 46°C/W, θCA = 80°C/W, θJA = 126°C/W. 5 SNR/harmonics based on an analog input voltage of –0.7 dBFS referenced to a 1.024 V full-scale input range. Specifications subject to change without notice. *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V VREF IN . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C ORDERING GUIDE Model Temperature Ranges Package Options AD9283BRS -50, -80, -100 –40°C to +85°C 20-Lead SSOP RS-20 AD9283/PCB 25°C Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9283 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C Package Descriptions –3– WARNING! ESD SENSITIVE DEVICE AD9283 EXPLANATION OF TEST LEVELS Table I. Output Coding (VREF = 1.25 V) Test Level I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. Step AIN–AIN Digital Output 255 • • 128 127 • • 0 0.512 • • 0.002 –0.002 • • –0.512 1111 1111 • • 1000 0000 0111 1111 • • 0000 0000 PIN CONFIGURATION PWRDWN 1 20 D0 (LSB) VREF OUT 2 19 D1 VREF IN 3 18 D2 GND 4 17 D3 VD 5 16 GND AD9283 TOP VIEW 15 V DD (Not to Scale) 14 D4 A IN 7 A IN 6 VD 8 13 D5 GND 9 12 D6 11 D7 (MSB) ENCODE 10 PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic Function 1 PWRDWN 2 3 4, 9, 16 5, 8 6 VREF OUT VREF IN GND VD AIN 7 10 11–14, 17–20 15 AIN ENCODE D7–D4, D3–D0 VDD Power-Down Function Select; Logic HIGH for Power-Down Mode (Digital Outputs Go to High Impedance State) Internal Reference Output (1.25 V typ); Bypass with 0.1 µF to Ground Reference Input for ADC (1.25 V typ) Ground Analog 3 V Power Supply Analog Input for ADC (Can Be Left Open if Operating in Single-Ended Mode, but Recommend Connection to a 0.1 µF Capacitor and a 25 Ω Resistor in Series to Ground for Better Input Matching) Analog Input for ADC Encode Clock for ADC (ADC Samples on Rising Edge of ENCODE) Digital Outputs of ADC Digital output power supply. Nominally 2.5 V to 3.6 V –4– REV. C AD9283 SAMPLE N SAMPLE N+4 SAMPLE N+1 SAMPLE N+5 AIN SAMPLE N+2 tA tEH tEL SAMPLE N+3 1/fS ENCODE t PD D7–D0 DATA N–4 DATA N–3 DATA N–2 DATA N–1 tV DATA N DATA N+1 Figure 1. Timing Diagram VDD VDD 33.3k⍀ 33.3k⍀ OUT AIN A IN 14.3k⍀ 14.3k⍀ Figure 2. Equivalent Analog Input Circuit Figure 5. Equivalent Digital Output Circuit VD VD VBIAS OUT REF IN Figure 3. Equivalent Reference Input Circuit Figure 6. Equivalent Reference Output Circuit VD ENCODE Figure 4. Equivalent Encode Input Circuit REV. C –5– AD9283 – Typical Performance Characteristics 70 0 ENCODE = 100MSPS 2ND 65 ENCODE = 100MSPS AIN = 10.3MHz SNR = 46.5dB SINAD = 45dB 2nd = 57dBc 3rd = 54.5dBc –10 –20 –30 60 55 3RD dB dB –40 –50 50 45 –60 –70 40 –80 35 –90 30 –100 10 20 FREQUENCY TPC 1. Spectrum: fS = 100 MSPS, fIN = 10.3 MHz –20 –30 60 80 100 TPC 4. Harmonic Distortion vs. AIN Frequency 0 –10 30 40 50 FREQUENCY – A IN 0 ENCODE = 100MSPS AIN = 41MHz SNR = 46.5dB SINAD = 45dB 2nd = 58dBc 3rd = 52.5dBc ENCODE = 100MSPS AIN1 = 9MHz AIN2 = 10MHz IMD = 52dBc –10 –20 –30 –40 dB dB –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 FREQUENCY FREQUENCY TPC 2. Spectrum: fS = 100 MSPS, fIN = 40 MHz TPC 5. Two-Tone Intermodulation Distortion 0 –10 –20 –30 55 ENCODE = 100MSPS AIN = 76MHz SNR = 46dB SINAD = 42.5dB 2nd = 46dBc 3rd = 53dBc ENCODE = 100MSPS 50 SNR 45 dB dB –40 –50 SINAD 40 –60 –70 35 –80 –90 30 FREQUENCY TPC 3. Spectrum: fS = 100 MSPS, fIN = 76 MHz 10 20 30 40 50 FREQUENCY 60 80 90 100 TPC 6. SINAD/SNR vs. AIN Frequency –6– REV. C AD9283 120 49 AIN = 10.3MHz SNR A IN = 10.3MHz 100 48 SINAD 80 POWER – mW dB 47 46 60 45 40 44 20 43 10 20 30 40 50 60 ENCODE RATE 70 80 90 0 100 TPC 7. SINAD/SNR vs. Encode Rate 10 20 30 40 50 60 ENCODE RATE 70 90 80 100 TPC 10. Analog Power Dissipation vs. Encode Rate 49 60 ENCODE = 100MSPS A IN = 10.3MHz 50 48 SNR SNR 40 47 dB dB SINAD 30 SINAD 46 20 45 10 44 –60 0 7.0 6.5 6.0 4.5 4.0 5.5 5.0 ENCODE PULSEWIDTH HIGH – ns 3.5 3.0 TPC 8. SINAD/SNR vs. Encode Pulsewidth High –40 –20 0 20 40 TEMPERATURE – ⴗC 60 80 TPC 11. SINAD/SNR vs. Temperature 1.00 0.5 0.0 0.75 –0.5 –1.0 0.50 –1.5 0.25 LSB dB –2.0 –2.5 –3.0 0.00 –0.25 –3.5 –0.50 –4.0 –4.5 –0.75 –5.0 –5.5 0 –1.00 100 200 300 400 BANDWIDTH – MHz 500 600 CODE TPC 9. ADC Frequency Response: fS = 100 MSPS REV. C TPC 12. Differential Nonlinearity –7– 100 AD9283 Digital Outputs 2.0 The digital outputs are TTL/CMOS compatible. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing to ease interfacing with 2.5 V or 3.3 V logic. The AD9283 goes into a low power state within two clock cycles following the assertion of the PWRDWN input. PWRDWN is asserted with a logic high. During power-down the outputs transition to a high impedance state. The time it takes to achieve optimal performance after disabling the powerdown mode is approximately 15 clock cycles. Care should be taken when loading the digital outputs of any high speed ADC. Large output loads create current transients on the chip that can degrade the converter’s performance. 1.5 1.0 LSB 0.5 0.0 –0.5 –1.0 –1.5 Voltage Reference –2.0 CODE A stable and accurate 1.25 V voltage reference is built into the AD9283 (VREF OUT). In normal operation, the internal reference is used by strapping Pins 2 and 3 of the AD9283 together. The input range can be adjusted by varying the reference voltage applied to the AD9283. No degradation in performance occurs when the reference is adjusted ± 5%. The full-scale range of the ADC tracks reference voltage changes linearly. Whether used or not, the internal reference (Pin 2) should be bypassed with a 0.1 µF capacitor to ground. TPC 13. Integral Nonlinearity APPLICATIONS Theory of Operation The analog signal is applied differentially or single-endedly to the inputs of the AD9283. The signal is buffered and fed forward to an on-chip sample-and-hold circuit. The ADC core architecture is a bit-per-stage pipeline type converter utilizing switch capacitor techniques. The bit-per-stage blocks determine the 5 MSBs and drive a FLASH converter to encode the 3 LSBs. Each of the 5 MSB stages provides sufficient overlap and error correction to allow optimization of performance with respect to comparator accuracy. The output staging block aligns the data, carries out the error correction and feeds the data to the eight output buffers. The AD9283 includes an on-chip reference (nominally 1.25 V) and generates all clocking signals from one externally applied encode command. This makes the ADC easy to interface with and requires very few external components for operation. Timing The AD9283 provides latched data outputs with four pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (Figure 1. Timing Diagram). The minimum guaranteed conversion rate to the ADC is 1 MSPS. The dynamic performance of the converter will degrade at encode rates below this sample rate. Evaluation Board The AD9283 evaluation board offers an easy way to test the AD9283. It only requires a 3 V supply, an analog input and encode clock to test the AD9283. The board is shipped with the 100 MSPS grade ADC. ENCODE Input The ENCODE input is fully TTL/CMOS compatible with a nominal threshold of 1.5 V. Care was taken on the chip to match clock line delays and maintain sharp clock logic transitions. Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. This ADC uses an on-chip sample-and-hold circuit which is essentially a mixer. Any timing jitter on the ENCODE will be combined with the desired signal and degrade the high frequency performance of the ADC. The user is advised to give commensurate thought to the clock source. The analog input to the board accepts a 1 V p-p signal centered at ground. J1 should be used (Jump E3–E4, E18–E19) to drive the ADC through Transformer T1. J2 should be used for singleended input drive (Jump E19–E21). Both J1 and J2 are terminated to 50 Ω on the PCB. Each analog path is ac-coupled to an on-chip resistor divider which provides the required dc bias. A (TTL/CMOS Level) sample clock is applied to connector J3 which is terminated through 50 Ω on the PCB. This clock is buffered by U5 which also provides the clocks for the 574 latches, DAC, and the off-card latch clock CLKCON. (Timing can be modified at E17.) Analog Input The analog input to the ADC is fully differential and both inputs are internally biased. This allows the most flexible use of ac or dc and differential or single-ended input modes. For peak performance the inputs are biased at 0.3 × VD. See the specification table for allowable common-mode range when dc coupling the input. The inputs are also buffered to reduce the load the user needs to drive. For best dynamic performance, the impedances at AIN and AIN should be matched. The importance of this increases with sampling rate and analog input frequency. The nominal input range is 1.024 V p-p. There is a reconstruction DAC (AD9760) on the PCB. The DAC is on the board to assist in debug only—the outputs should not be used to measure performance of the ADC. –8– REV. C AD9283 Figure 7. Printed Circuit Board Top Side Silkscreen Figure 9. Printed Circuit Board Top Side Copper Figure 8. Printed Circuit Board Bottom Side Silkscreen Figure 10. Printed Circuit Board “Split” Power Layer REV. C –9– AD9283 Figure 12. Printed Circuit Board Bottom Side Copper Figure 11. Printed Circuit Board Ground Layer EVALUATION BOARD BILL OF MATERIALS — GS01717 # Qty REFDES Device Package Value 1 2 3 15 4 24 Ceramic Cap Tantalum Cap 0603 BCAPTAJD 0.1 µF 10 µF 4 5 4 1 C1, C4–C17 C18–C21 E1–E6, E8–E10, E12–E19, E21, E34–E39 J1, J2, J3, J5 P1 W-HOLE Connector 5-Pin Connector SMB 6 7 8 9 10 11 12 13 14 1 5 1 1 1 1 1 1 1 P2 R4, R9, R10, R21, R22 R7 R23 T1 U1 U3 U4 U5 37-Pin Connector Resistor Resistor Resistor Transformer AD9283 AD9760 74ACQ574 SN74LVC86 –10– 1206 1206 1206 Wieland Connector (P/N #25.602.2553.0 Top P/N #Z5.530.0525.0 Bottom) AMP-747462-2 50 Ω 25 Ω 2 kΩ Mini-Circuits T1-1T-KK81 SSOP-20 SOIC-28 SOIC-20 SO14 REV. C REV. C J3 J1 –11– E4 R10 50⍀ J2 R4 50⍀ E3 Figure 13. Printed Circuit Board S chematic 3 4 5 1 2 3 E21 E18 T1 R9 50⍀ 6 5 4 E19 R7 25⍀ C8 0.1␮F C1 0.1␮F VA 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y U5 SN74LVC86 C7 0.1␮F C6 0.1␮F C17 0.1␮F VA VD GND VDL VDAC 2 1 1A 2 1B 3 1Y ENC 4 2A E15 E17 5 2B VDL CLKCON 6 E16 2Y 7 GND VA 1 P1 CLKDAC E14 GND VA1 AIN AIN VA GND REFIN E13 VDL REFOUT PWDN D3 D2 D1 D0 11 12 13 14 15 16 17 18 19 20 DA3 DA2 DA1 DA0 DA5 DA4 DA7 DA6 D7 D6 D5 D4 VDD GND U1 AD9283 PWDN C13 0.1␮F 10 E12 ENC 9 8 7 6 5 4 3 2 1 VDL E1 E2 VA E5 E8 CLKLAT C4 0.1␮F C5 0.1␮F E6 E10 E9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VD NC4 DB1 DB0 NC1 NC2 NC3 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 C9 0.1␮F C18 10␮F 9 8 7 6 5 4 3 2 1 E35 E34 C14 0.1␮F C15 0.1␮F C12 0.1␮F VDAC VDAC E39 E38 11 R22 50⍀ C11 0.1␮F R21 50⍀ VDAC CLKLAT DA7 DA5 DA4 DA3 DA2 DA1 DA0 DA6 VDL 12 C16 0.1␮F 13 14 15 16 17 18 19 20 R23 2k⍀ CLOCK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC C10 0.1␮F E37 E36 CLKDAC GND D7 D6 D5 D4 D3 D2 D1 D0 OUT_EN U4 74ACQ574 C21 10␮F VDAC C20 10␮F VDL C19 10␮F 10 VD 28 CLK 27 DVDD 26 DCOM 25 NC5 24 AVDD 23 COMP2 22 IOUTA 21 IOUTB 20 ACOM 19 COMP1 18 FSADJ 17 REFIO 16 REFLO 15 SLEEP U3 AD9760 VA J5 CLKCON P2 C37DRPF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 AD9283 AD9283 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C00584b–0–10/01(C) 20-Lead Shrink Small Outline Package (SSOP) (RS-20) 20 11 1 10 0.07 (1.78) 0.066 (1.67) 0.078 (1.98) PIN 1 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) 0.212 (5.38) 0.205 (5.21) 0.311 (7.9) 0.301 (7.64) 0.295 (7.50) 0.271 (6.90) 0.0256 (0.65) BSC 8° SEATING 0.009 (0.229) 0° PLANE 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) Revision History Location Page Data Sheet changed from REV. B to REV. C. PRINTED IN U.S.A. Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 –12– REV. C