AD9398

HDMI™ Display Interface AD9398 FEATURES HDMI interface Supports high bandwidth digital content protection RGB to YCbCr 2-way color conversion 1.8 V/3.3 V power supply 100-lead, Pb-free LQFP RGB and YCbCr output formats Digital video interface HDMI 1.1, DVI 1.0 150 MHz HDMI receiver Supports high bandwidth digital content protection (HDCP 1.1) Digital audio interface HDMI 1.1-compatible audio interface SPDIF (IEC90658-compatible) digital audio output Multichannel I2S audio output (up to 8 channels) SCL SDA FUNCTIONAL BLOCK DIAGRAM R/G/B 8 × 3 SERIAL REGISTER AND POWER MANAGEMENT YCbCr (4:2:2 OR 4:4:4) RGB ↔YCbCr COLORSPACE CONVERTER 2 DATACK HSOUT VSOUT Rx0+ Rx0– Rx1+ Rx1– Rx2+ Rx2– RxC+ RxC– RTERM HDMI RECEIVER 2 R/G/B 8 × 3 OR YCbCr DATACK HSYNC VSYNC DE DE S/PDIF OUT 8-CHANNEL I2S MCLK LRCLK APPLICATIONS Advanced TVs HDTVs Projectors LCD monitors MCL MDA HDCP 05678-001 DDCSCL DDCSDA AD9398 Figure 1. GENERAL DESCRIPTION The AD9398 offers a high definition multimedia interface (HDMI) receiver integrated on a single chip. Also included is support for high bandwidth digital content protection (HDCP). The AD9398 contains a HDMI 1.0-compatible receiver and supports all HDTV formats (up to 1080p) and display resolutions up to SXGA (1280 × 1024 @ 75 Hz). The receiver features an intrapair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays can now receive encrypted video content. The AD9398 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP 1.1 protocol. Fabricated in an advanced CMOS process, the AD9398 is provided in a space-saving 100-lead, surface-mount, Pb-free, plastic LQFP and is specified over the 0°C to 70°C temperature range. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD9398 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Digital Interface Electrical Characteristics ............................... 3 Absolute Maximum Ratings............................................................ 5 Explanation of Test Levels ........................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Design Guide..................................................................................... 9 General Description..................................................................... 9 Digital Inputs ................................................................................ 9 Serial Control Port ....................................................................... 9 Output Signal Handling............................................................... 9 Power Management...................................................................... 9 Timing.......................................................................................... 10 VSYNC Filter and Odd/Even Fields ........................................ 10 HDMI Receiver........................................................................... 10 DE Generator .............................................................................. 10 4:4:4 to 4:2:2 Filter ...................................................................... 11 Audio PLL Setup......................................................................... 12 Audio Board Level Muting........................................................ 13 Output Data Formats................................................................. 13 2-Wire Serial Register Map ........................................................... 14 2-Wire Serial Control Register Details ........................................ 25 Chip Identification ..................................................................... 25 BT656 Generation ...................................................................... 27 Macrovision................................................................................. 28 Color Space Conversion ............................................................ 29 2-Wire Serial Control Port ............................................................ 36 Data Transfer via Serial Interface............................................. 36 Serial Interface Read/Write Examples ..................................... 37 PCB Layout Recommendations.................................................... 38 Power Supply Bypassing ............................................................ 38 Outputs (Both Data and Clocks).............................................. 38 Digital Inputs .............................................................................. 38 Color Space Converter (CSC) Common Settings...................... 39 Outline Dimensions ....................................................................... 41 Ordering Guide .......................................................................... 41 REVISION HISTORY 10/05—Revision 0: Initial Version Rev. 0 | Page 2 of 44 AD9398 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD, VD = 3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum. Table 1. Parameter DIGITAL INPUTS (5 V TOLERANT) Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Current, High (IIH) Input Current, Low (IIL) Input Capacitance DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, Low (VOL) Duty Cycle, DATACK Output Coding THERMAL CHARACTERISTICS θJA Junction-to-Ambient Temp Full Full Full Full 25°C Full Full Full Test Level VI VI V V V VI VI V Min 2.6 0.8 −82 82 3 VDD − 0.1 45 50 Binary 35 0.4 55 VDD − 0.1 45 50 Binary 35 0.4 55 −82 82 3 AD9398KSTZ-100 Typ Max Min 2.6 0.8 AD9398KSTZ-150 Typ Max Unit V V μA μA pF V V % V °C/W DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS VDD = VD =3.3 V, DVDD = PVDD = 1.8 V, ADC clock = maximum. Table 2. Parameter RESOLUTION DC DIGITAL I/O SPECIFICATIONS High-Level Input Voltage (VIH) Low-Level Input Voltage (VIL) High-Level Output Voltage (VOH) Low-Level Output Voltage (VOL) DC SPECIFICATIONS Output High Level (IOHD) (VOUT = VOH) Output Low Level IOLD, (VOUT = VOL) DATACK High Level VOHC, (VOUT = VOH) DATACK Low Level VOLC, (VOUT = VOL) Differential Input Voltage, SingleEnded Amplitude Test Level Conditions AD9398KSTZ-100 Min Typ Max 8 2.5 0.8 VDD − 0.1 VDD − 0.1 Output drive = high Output drive = low Output drive = high Output drive = low Output drive = high Output drive = low Output drive = high Output drive = low 75 36 24 12 8 40 20 30 15 700 75 0.1 36 24 12 8 40 20 30 15 700 AD9398KSTZ-150 Min Typ Max 8 2.5 0.8 0.1 Unit Bit V V V V mA mA mA mA mA mA mA mA mV VI VI VI VI IV IV IV IV IV IV IV IV IV Rev. 0 | Page 3 of 44 AD9398 Parameter POWER SUPPLY VD Supply Voltage VDD Supply Voltage DVDD Supply Voltage PVDD Supply Voltage IVD Supply Current (Typical Pattern) 1 IVDD Supply Current (Typical Pattern) 2 IDVDD Supply Current (Typical Pattern)1, 4 Test Level IV IV IV IV V V V V VI IV IV IV IV Conditions AD9398KSTZ-100 Min Typ Max 3.15 1.7 1.7 1.7 3.3 3.3 1.8 1.8 80 40 88 26 130 3.47 347 1.9 1.9 100 100 3 110 35 AD9398KSTZ-150 Min Typ Max 3.15 1.7 1.7 1.7 3.3 3.3 1.8 1.8 80 55 110 30 130 3.47 347 1.9 1.9 110 1751 145 40 Unit V V V V mA mA mA mA mA ps Clock period ps ps ps ps ps ps ps ps ns % MHz IPVDD Supply Current (Typical Pattern) Power-Down Supply Current (IPD) AC SPECIFICATIONS Intrapair (+ to −) Differential Input Skew (TDPS) Channel to Channel Differential Input Skew (TCCS) Low-to-High Transition Time for Data and Controls (DLHT) 360 6 Output drive = high; CL = 10 pF Output drive = low; CL = 5 pF Output drive = high; CL = 10 pF Output drive = low; CL = 5 pF Output drive = high; CL = 10 pF Output drive = low; CL = 5 pF Output drive = high; CL = 10 pF Output drive = low; CL = 5 pF −0.5 45 20 2.0 50 −0.5 900 1300 650 1200 850 1250 800 1200 2.0 55 150 Low-to-High Transition Time for DATACK (DLHT) IV IV High-to-Low Transition Time for Data and Controls (DHLT) IV IV High-to-Low Transition Time for DATACK (DHLT) IV IV Clock-to-Data Skew 5 ( TSKEW) Duty Cycle, DATACK DATACK Frequency (FCIP) 1 2 IV IV VI The typical pattern contains a gray scale area, output drive = high. Worst-case pattern is alternating black and white pixels. The typical pattern contains a gray scale area, output drive = high. 3 Specified current and power values with a worst-case pattern (on/off). 4 DATACK load = 10 pF, data load = 5 pF. 5 Drive strength = high. Rev. 0 | Page 4 of 44 AD9398 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VD VDD DVDD PVDD Analog Inputs Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating 3.6 V 3.6 V 1.98 V 1.98 V VD to 0.0 V 5 V to 0.0 V 20 mA −25°C to +85°C −65°C to +150°C 150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EXPLANATION OF TEST LEVELS Table 4. Level I II III IV V VI Test 100% production tested. 100% production tested at 25°C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C; guaranteed by design and characterization testing. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 44 AD9398 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS O/E FIELD DATACK PWRDN HSOUT VSOUT RED 0 RED 1 RED 2 RED 3 RED 4 RED 5 RED 6 RED 7 GND GND 78 SDA SCL VDD VDD NC NC NC 77 DE VD 100 99 95 89 88 87 84 93 92 82 97 96 91 90 86 85 81 80 98 94 83 79 76 VD GND GREEN 7 GREEN 6 GREEN 5 GREEN 4 GREEN 3 GREEN 2 GREEN 1 GREEN 0 VDD GND BLUE 7 BLUE 6 BLUE 5 BLUE 4 BLUE 3 BLUE 2 BLUE 1 BLUE 0 MCLKIN MCLKOUT SCLK LRCLK I2S3 I2S2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIN 1 75 74 73 72 71 70 69 68 67 GND NC NC VD NC NC GND NC VD NC GND GND GND GND GND GND PVDD GND FILT PVDD GND PVDD GND MDA MCL AD9398 TOP VIEW (Not to Scale) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 27 31 37 38 39 42 48 49 26 33 34 44 29 30 35 36 40 41 45 46 28 32 S/PDIF I2S1 I2S0 Rx0+ Rx1+ Rx2+ RxC+ 43 RTERM GND GND GND GND GND DVDD DVDD GND VD VD 47 DVDD Rx0– Rx1– Rx2– RxC– Figure 2. Pin Configuration Table 5. Complete Pinout List Pin Type INPUTS DIGITAL VIDEO DATA INPUTS Pin No. 81 35 34 38 37 41 40 43 44 92 to 99 2 to 9 12 to 19 89 87 85 84 57 Mnemonic PWRDN Rx0+ Rx0− Rx1+ Rx1− Rx2+ Rx2− RxC+ RxC− RED [7:0] GREEN [7:0] BLUE [7:0] DATACK HSOUT VSOUT FIELD FILT Function Power-Down Control Digital Input Channel 0 True Digital Input Channel 0 Complement Digital Input Channel 1 True Digital Input Channel 1 Complement Digital Input Channel 2 True Digital Input Channel 2 Complement Digital Data Clock True Digital Data Clock Complement Outputs of Red Converter, Bit 7 is MSB Outputs of Green Converter, Bit 7 is MSB Outputs of Blue Converter, Bit 7 is MSB Data Output Clock HSYNC Output Clock (Phase-Aligned with DATACK) VSYNC Output Clock (Phase-Aligned with DATACK) Odd/Even Field Output Connection for External Filter Components For audio PLL Value 3.3 V CMOS TMDS TMDS TMDS TMDS TMDS TMDS TMDS TMDS VDD VDD VDD VDD VDD VDD VDD PVDD DIGITAL VIDEO CLOCK INPUTS OUTPUTS REFERENCES Rev. 0 | Page 6 of 44 05678-002 NC = NO CONNECT DDCSDA DDCSCL 50 AD9398 Pin Type POWER SUPPLY Pin No. 80, 76, 72, 67, 45, 33 100, 90, 10 59, 56, 54 48, 32, 30 83 82 49 50 51 52 28 27 26 25 24 20 21 22 23 88 46 Mnemonic VD VDD PVDD DVDD GND SDA SCL DDCSCL DDCSDA MCL MDA S/PDIF I2S0 I2S1 I2S2 I2S3 MCLKIN MCLKOUT SCLK LRCLK DE RTERM Function Analog Power Supply and DVI Terminators Output Power Supply PLL Power Supply Digital Logic Power Supply Ground Serial Port Data I/O Serial Port Data Clock HDCP Slave Serial Port Data Clock HDCP Slave Serial Port Data I/O HDCP Master Serial Port Data Clock HDCP Master Serial Port Data I/O S/PDIF Digital Audio Output I2S Audio (Channel 1, Channel 2) I2S Audio (Channel 3, Channel 4) I2S Audio (Channel 5, Channel 6) I2S Audio (Channel 7, Channel 8) External Reference Audio Clock In Audio Master Clock Output Audio Serial Clock Output Data Output Clock for Left and Right Audio Channels Data Enable Sets Internal Termination Resistance Value 3.3 V 1.8 V to 3.3 V 1.8 V 1.8 V 0V 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS VDD VDD VDD VDD VDD VDD VDD VDD VDD 3.3 V CMOS 500 Ω CONTROL HDCP AUDIO DATA OUTPUTS DATA ENABLE RTERM Table 6. Pin Function Descriptions Mnemonic INPUTS Rx0+ Rx0− Rx1+ Rx1− Rx2+ Rx2− Description Digital Input Channel 0 True. Digital Input Channel 0 Complement. Digital Input Channel 1 True. Digital Input Channel 1 Complement. Digital Input Channel 2 True. Digital input Channel 2 Complement. These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel rate) from a digital graphics transmitter. Digital Data Clock True. Digital Data Clock Complement. This clock pair receives a TMDS clock at 1× pixel data rate. External Filter Connection. For proper operation, the audio-clock generator PLL requires an external filter. Connect the filter shown in Figure 8 to this pin. For optimal performance, minimize noise and parasitics on this node. For more information see the PCB Layout Recommendations section . Power-Down Control/Three-State Control. The function of this pin is programmable via Register 0x26 [2:1]. Horizontal Sync Output. A reconstructed and phase-aligned version of the HSYNC input. Both the polarity and duration of this output can be programmed via serial bus registers. By maintaining alignment with DATACK and DATA, data timing with respect to horizontal sync can always be determined. Vertical Sync Output. The separated VSYNC from a composite signal or a direct pass through of the VSYNC signal. The polarity of this output can be controlled via the serial bus bit (Register 0x24 [6]). Odd/Even Field Bit for Interlaced Video. This output identifies whether the current field (in an interlaced signal) is odd or even. The polarity of this signal is programmable via Register 0x24[4]. Data Enable that defines valid video. Can be received in the signal or generated by the AD9398. Rev. 0 | Page 7 of 44 RxC+ RxC− FILT PWRDN OUTPUTS HSOUT VSOUT O/E FIELD DE AD9398 Mnemonic RTERM AUDIO DATA OUTPUT S/PDIF I2S0 to I2S3 MCLKIN MCLKOUT SCLK LRCLK SERIAL PORT SDA SCL DDCSDA DDCSCL MDA MCL DATA OUTPUTS RED [7:0] GREEN [7:0] BLUE [7:0] Description RTERM is the termination resistor used to drive the AD9398 internally to a precise 50 Ω termination for TMDS lines. This should be a 500 Ω 1% tolerance resistor. Sony/Philips Digital Interface. Supports digital audio from 32 kbps to 192 kbps. Inter-IC Sound Channel 0 through Channel 3. Each line supports two channels of digital audio. Master Audio Clock External. Used if internal MCLK is not generated. Master Audio Clock Output to Drive Audio DACs. Serial Clock Out to support Digital Audio. Data Output Clock for Left and Right Audio Channels. Serial Port Data I/O for Programming AD9398 Registers—I2C Address is 0x98. Serial Port Data Clock for Programming AD9398 Registers. Serial Port Data I/O for HDCP Communications to Transmitter—I2C Address is 0x74 or 0x76. Serial Port Data Clock for HDCP Communications to Transmitter. Serial Port Data I/O to EEPROM with HDCP Keys—I2C Address is 0xA0. Serial Port Data Clock to EEPROM with HDCP Keys. Data Output, Red Channel. Data Output, Green Channel. Data Output, Blue Channel. The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed, but is different if the color space converter is used. When the sampling time is changed by adjusting the phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is maintained. Data Clock Output. This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible output clocks can be selected with Register 0x25 [7:6]. These are related to the pixel clock (1/2× pixel clock, 1× pixel clock, 2× frequency pixel clock, and a 90° phase shifted pixel clock). They are produced either by the internal PLL clock generator or EXTCLK and are synchronous with the pixel sampling clock. The polarity of DATACK can also be inverted via Register 0x24 [0]. The sampling time of the internal pixel clock can be changed by adjusting the phase register. When this is changed, the pixel-related DATACK timing is shifted as well. The DATA, DATACK, and HSOUT outputs are all moved, so the timing relationship among the signals is maintained. Analog Power Supply. These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible. Digital Output Power Supply. A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply transients (noise). These supply pins are identified separately from the VD pins, so output noise transferred into the sensitive analog circuitry can be minimized. If the AD9398 is interfacing with lower voltage logic, VDD may be connected to a lower supply voltage (as low as 1.8 V) for compatibility. Clock Generator Power Supply. The most sensitive portion of the AD9398 is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins. Digital Input Power Supply. This supplies power to the digital logic. Ground. The ground return for all circuitry on chip. It is recommended that the AD9398 be assembled on a single solid ground plane, with careful attention to ground current paths. DATA CLOCK OUTPUT DATACK POWER SUPPLY 1 VD (3.3 V) VDD (1.8 V to 3.3 V) PVDD (1.8 V) DVDD (1.8 V) GND 1 The supplies should be sequenced such that VD and VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VD or VDD. Rev. 0 | Page 8 of 44 AD9398 DESIGN GUIDE GENERAL DESCRIPTION The AD9398 is a fully integrated solution for receiving DVI/HDMI signals and is capable of decoding HDCPencrypted signals through connections to an external EEPROM. The circuit is ideal for providing an interface for HDTV monitors or as the front end to high performance video scan converters. Implemented in a high performance CMOS process, the interface can capture signals with pixel rates of up to 150 MHz. The AD9398 includes all necessary circuitry for decoding TMDS signaling including those encrypted with HDCP. Included in the output formatting is a color space converter (CSC), which accommodates any input color space and can output any color space. All controls are programmable via a 2wire serial interface. Full integration of these sensitive mixed signal functions makes system design straight-forward and less sensitive to the physical and electrical environments. SERIAL CONTROL PORT The serial control port is designed for 3.3 V logic. However, it is tolerant of 5 V logic signals. OUTPUT SIGNAL HANDLING The digital outputs operate from 1.8 V to 3.3 V (VDD). POWER MANAGEMENT The AD9398 uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, the power-down bit, and the power-down pin to determine the correct power state. There are four power states: full power, seek mode, auto power-down, and power-down. Table 7 summarizes how the AD9398 determines the power mode to use and which circuitry is powered on/off in each of these modes. The powerdown command has priority and then the automatic circuitry. The power-down pin (Pin 81—polarity set by Register 0x26[3]) can drive the chip into four power-down options. Bit 2 and Bit 1 of Register 0x26 control these four options. Bit 0 controls whether the chip is powered down or the outputs are placed in high impedance mode (with the exception of SOG). Bit 7 to Bit 4 of Register 0x26 control whether the outputs, SOG, Sony Philips digital interface (SPDIF ) or Inter-IC sound bus (I2S or IIS) outputs are in high impedance mode. See the 2-Wire Serial Control Register Detail section for the details. DIGITAL INPUTS The digital control inputs (I2C) on the AD9398 operate to 3.3 V CMOS levels. In addition, all digital inputs, except the TMDS (HDMI/DVI) inputs, are 5 V tolerant (applying 5 V to them does not cause damage.) The TMDS input pairs (Rx0+/Rx0−, Rx1+/Rx1−, Rx2+/Rx2−, and RxC+/RxC−) must maintain a 100 Ω differential impedance (through proper PCB layout) from the connector to the input where they are internally terminated (50 Ω to 3.3 V). If additional ESD protection is desired, use of a California Micro Devices (CMD) CM1213 (among others) series low capacitance ESD protection offers 8 kV of protection to the HDMI TMDS lines. Table 7. Power-Down Mode Descriptions Mode Full Power Seek Mode Seek Mode Power-Down 1 2 Power-Down 1 1 1 1 0 Inputs Sync Detect 2 1 0 0 X Auto PD Enable 3 X 0 1 Power-On or Comments Everything Everything Serial bus, sync activity detect, SOG, band gap reference Serial bus, sync activity detect, SOG, band gap reference Power-down is controlled via Bit 0 in Serial Bus Register 0x26. Sync detect is determined by OR’ing Bit 7 to Bit 2 in Serial Bus Register 0x15. 3 Auto power-down is controlled via Bit 7 in Serial Bus Register 0x27. Rev. 0 | Page 9 of 44 AD9398 TIMING The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. Figure 3 shows the timing operation of the AD9398. tPER tDCYCLE DATACK SYNC SEPARATOR THRESHOLD FIELD 1 QUADRANT HSIN VSIN VSOUT O/E FIELD 2 3 FIELD 0 4 1 FIELD 1 2 3 FIELD 0 4 1 ODD FIELD Figure 5. VSYNC Filter—Odd tSKEW 05678-003 HDMI RECEIVER The HDMI receiver section of the AD9398 allows the reception of a digital video stream, which is backward compatible with DVI and able to accommodate not only video of various formats (RGB, YCrCb 4:4:4, 4:2:2), but also up to eight channels of audio. Infoframes are transmitted carrying information about the video format, audio clocks, and many other items necessary for a monitor to use fully the information stream available. The earlier digital visual interface (DVI) format was restricted to an RGB 24-bit color space only. Embedded in this data stream were HSYNCs, VSYNCs, and display enable (DE) signals, but no audio information. The HDMI specification allows transmission of all the DVI capabilities, but adds several YCrCb formats that make the inclusion of a programmable color space converter (CSC) a very desirable feature. With this, the scaler following the AD9398 can specify that it always wishes to receive a particular format—for instance, 4:2:2 YCrCb— regardless of the transmitted mode. If RGB is sent, the CSC can easily convert that to 4:2:2 YCrCb while relieving the scaler of this task. In addition, the HDMI specification supports the transmission of up to eight channels of S/PDIF or I2S audio. The audio information is packetized and transmitted during the video blanking periods along with specific information about the clock frequency. Part of this audio information (audio infoframe) tells the user how many channels of audio are being transmitted, where they should be placed, information regarding the source (make, model), and other data. 05678-004 DATA HSOUT Figure 3. Output Timing VSYNC FILTER AND ODD/EVEN FIELDS The VSYNC filter is used to eliminate spurious VSYNCs, maintain a consistent timing relationship between the VSYNC and HSYNC output signals, and generate the odd/even field output. The filter works by examining the placement of VSYNC with respect to HSYNC and, if necessary, slightly shifting it in time at the VSOUT output. The goal is to keep the VSYNC and HSYNC leading edges from switching at the same time, eliminating confusion as to when the first line of a frame occurs. Enabling the VSYNC filter is done with Register 0x21[5]. Use of the VSYNC filter is recommended for all cases, including interlaced video, and is required when using the HSYNC per VSYNC counter. Figure 4 and Figure 5 illustrate even/odd field determination in two situations. SYNC SEPARATOR THRESHOLD FIELD 1 QUADRANT HSIN VSIN VSOUT O/E FIELD 2 3 FIELD 0 4 1 FIELD 1 2 3 FIELD 0 4 1 EVEN FIELD DE GENERATOR The AD9398 has an on-board generator for DE, for start of active video (SAV), and for end of active video (EAV), all of which are necessary for describing the complete data stream for a BT656-compatible output. In addition to this particular output, it is possible to generate the DE for cases in which a scaler is not used. This signal alerts the following circuitry as to which are displayable video pixels. Figure 4. VSYNC Filter—Even Rev. 0 | Page 10 of 44 05678-005 AD9398 4:4:4 TO 4:2:2 FILTER The AD9398 contains a filter that allows it to convert a signal from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the maximum accuracy and fidelity of the original signal. One of the three channels is represented in Figure 6. In each processing channel, the three inputs are multiplied by three separate coefficients marked a1, a2, and a3. These coefficients are divided by 4096 to obtain nominal values ranging from −0.9998 to +0.9998. The variable labeled a4 is used as an offset control. The CSC_Mode setting is the same for all three processing channels. This multiplies all coefficients and offsets by a factor of 2CSC_Mode. The functional diagram for a single channel of the CSC, as shown in Figure 6, is repeated for the remaining G and B channels. The coefficients for these channels are b1, b2, b3, b4, c1, c2, c3, and c4. CSC_Mode[1:0] a1[12:0] 1 4096 a4[12:0] ×4 RIN [11:0] × a2[12:0] 0 GIN [11:0] × a3[12:0] 05678-006 Input Color Space to Output Color Space The AD9398 can accept a wide variety of input formats and either retain that format or convert to another. Input formats supported are: • • • 4:4:4 YCrCb 8-bit 4:2:2 YCrCb 8-, 10-, and 12-bit RGB 8-bit Output modes supported are: • • • 4:4:4 YCrCb 8-bit 4:2:2 YCrCb 8-, 10-, and 12-bit Dual 4:2:2 YCrCb 8-bit 2 ROUT [11:0] 1 × + + + ×2 Color Space Conversion (CSC) Matrix The CSC matrix in the AD9398 consists of three identical processing channels. In each channel, three input values are multiplied by three separate coefficients. Also included are an offset value for each row of the matrix and a scaling multiple for all values. Each value has a 13-bit, twos complement resolution to ensure the signal integrity is maintained. The CSC is designed to run at speeds up to 150 MHz, supporting resolutions up to 1080p at 60 Hz. With any-to-any color space support, formats such as RGB, YUV, YCbCr, and others are supported by the CSC. The main inputs, RIN, GIN, and BIN come from the 8- to 12-bit inputs from each channel. These inputs are based on the input format detailed in Table 10. The mapping of these inputs to the CSC inputs is shown in Table 8. Table 8. CSC Port Mapping Input Channel R/CR Gr/Y B/CB CSC Input Channel RIN GIN BIN B × 1 4096 BIN [11:0] × × 1 4096 Figure 6. Single CSC Channel A programming example and register settings for several common conversions are listed in the Color Space Converter (CSC) Common Settings section. For a detailed functional description and more programming examples, refer to Application Note AN-795, AD9880 Color Space Converter User's Guide. Rev. 0 | Page 11 of 44 AD9398 AUDIO PLL SETUP Data contained in the audio infoframes, among other registers, define for the AD9398 HDMI receiver not only the type of audio, but the sampling frequency (fS). The audio infoframe also contains information about the N and CTS values used to recreate the clock. With this information, it is possible to regenerate the audio sampling frequency. The audio clock is regenerated by dividing the 20-bit CTS value into the TMDS clock, then multiplying by the 20-bit N value. This yields a multiple of the sampling frequency of either 128 × fS or 256 × fS. It is possible for this to be specified up to 1024 × fS. SOURCE DEVICE DIVIDE BY N CYCLE TIME COUNTER CTS1 SINK DEVICE In order to provide the most flexibility in configuring the audio sampling clock, an additional PLL is employed. The PLL characteristics are determined by the loop filter design, the PLL charge pump current, and the VCO range setting. The loop filter design is shown in Figure 8. CP 8nF RZ 1.5kΩ 05678-010 CZ 80nF PVD FILT Figure 8. PLL Loop Filter Detail 128 × fS VIDEO CLOCK N 1N TMDS CLOCK N1 DIVIDE BY CTS MULTIPLY 128 × fS BY N To fully support all audio modes for all video resolutions up to 1080p, it is necessary to adjust certain audio-related registers from their power-on default values. Table 9 describes these registers and gives the recommended settings. REGISTER N AND CTS VALUES ARE TRANSMITTED USING THE AUDIO CLOCK REGENERATION PACKET. VIDEO CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL. Figure 7. N and CTS for Audio Clock Table 9. AD9398 Audio Register Settings Register 0x01 0x02 0x03 Bits 7:0 7:4 7:6 5:3 2 4 7 6:4 3 2:0 Recommended Setting 0x00 0x40 01 010 1 0 1 011 0 0** Function PLL Divisor (MSBs) PLL Divisor (LSBs) VCO Range Charge Pump Current PLL Enable Audio Frequency Mode Override PLL Enable MCLK PLL Divisor N/CTS Disable MCLK Sampling Frequency Comments The analog video PLL is also used for the audio clock circuit when in HDMI mode. This is done automatically. 05678-007 0x34 0x58 In HDMI mode, this bit enables a lower frequency to be used for audio MCLK generation. Allows the chip to determine the low frequency mode of the audio PLL. This enables the analog PLL to be used for audio MCLK generation. When the analog PLL is enabled for MCLK generation, another frequency divider is provided. These bits set the divisor to 4. The N and CTS values should always be enabled. 000 = 128 × fS 001 = 256 × fS 010 = 384 × fS 011 = 512 × fS Rev. 0 | Page 12 of 44 AD9398 AUDIO BOARD LEVEL MUTING The audio can be muted through the infoframes or locally via the serial bus registers. This can be controlled with Register R0x57, Bits [7:4]. This information is the fundamental difference between DVI and HDMI transmissions and is located in read-only registers R0x5A to R0xEE. In addition to this information, registers are provided to indicate that new information has been received. Registers with addresses ending in 0xX7 or 0xXF beginning at R0x87 contain the new data flag (NDF) information. These registers contain the same information and all are reset once any of them are read. Although there is no external interrupt signal, it is very easy for the user to read any of these registers to see if there is new information to be processed. AVI Infoframes The HDMI TMDS transmission contains infoframes with specific information for the monitor such as: • • • • • • • • Audio information 2 channels to 8 channels of audio identified Audio coding Audio sampling frequency Speaker placement N and CTS values (for reconstruction of the audio) Muting Source information • • • • CD SACD DVD OUTPUT DATA FORMATS The AD9398 supports 4:4:4, 4:2:2, double data rate (DDR), and BT656 output formats. Register 0x25[3:0] controls the output mode. These modes and the pin mapping are listed in Table 10. Video information • • • • • Video ID code (per CEA861B) Color space Aspect ratio Horizontal and vertical bar information MPEG frame information (I, B, or P frame) • Vendor (transmitter source) name and product model Table 10. Port Bit 4:4:4 4:2:2 4:4:4 DDR 4:2:2 to 12 1 Red 7 6 5 4 Red/Cr [7:0] CbCr [7:0] DDR ↑ 1 G [3:0] DDR ↓ R [7:0] CbCr [11:0] 3 2 1 0 DDR ↑ B [7:4] Green 7 6 5 4 Green/Y [7:0] Y [7:0] DDR ↑ B [3:0] DDR ↓ G [7:4] 3 Blue 7 6 5 4 3 Blue/Cb [7:0] DDR 4:2:2 ↑ CbCr ↓ Y, Y DDR 4:2:2 ↑ CbCr [11:0] DDR 4:2:2 ↓ Y,Y [11:0] Y [11:0] 2 1 0 2 1 0 Arrows in the table indicate clock edge. Rising edge of clock = ↑, falling edge = ↓. Rev. 0 | Page 13 of 44 AD9398 2-WIRE SERIAL REGISTER MAP The AD9398 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 11. Control Register Map Read/Write or Read Only Read Read/Write Read/Write Read/Write Default Value 00000000 01101001 1101**** 01****** **001*** *****0** 0******* *0****** Hex Address 0x00 0x001 0x02 0x03 Bits [7:0] [7:0] [7:4] [7:6] [5:3] [2] [7] [6] Register Name Chip Revision PLL Divider MSB PLL Divider VCO Range Charge Pump PLL Enable HSYNC Source HSYNC Source Override VSYNC Source VSYNC Source Override Channel Select Channel Select Override Interface Select Interface Override Input HSYNC Polarity HSYNC Polarity Override Input VSYNC Polarity VSYNC Polarity Override HSYNCs per VSYNC MSB HSYNCs per VSYNC VSYNC Duration HSYNC Duration HSYNC Output Polarity 0x11 Read/Write Description Chip revision ID. Revision is read [7:4]. [3:0]. PLL feedback divider value MSB. PLL feedback divider value. VCO range. Charge pump current control for PLL. This bit enables a lower frequency to be used for audio MCLK generation. 0 = HSYNC. 1 = SOG. 0 = auto HSYNC source. 1 = manual HSYNC source. 0 = VSYNC. 1 = VSYNC from SOG. 0 = auto HSYNC source. 1 = manual HSYNC source. 0 = Channel 0. 1 = Channel 1. 0 = auto-channel select. 1 = manual channel select. 0 = analog interface. 1 = digital interface. 0 = auto-interface select. 1 = manual interface select. 0 = active low. 1 = active high. 0 = auto HSYNC polarity. 1 = manual HSYNC polarity. 0 = active low. 1 = active high. 0 = auto VSYNC polarity. 1 = manual VSYNC polarity. MSB of HSYNCs per VSYNC. HSYNCs per VSYNC count. VSYNC duration. HSYNC duration. Sets the duration of the output HSYNC in pixel clocks. Output HSYNC polarity. 0 = active low out. 1 = active high out. Output VSYNC polarity 0 = active low out. 1 = active high out. [5] [4] [3] [2] **0***** ***0**** ****0*** *****0** [1] [0] 0x12 Read/Write [7] [6] ******0* *******0 1******* *0****** [5] [4] **1***** ***0**** 0x17 0x18 0x22 0x23 0x24 Read Read Read/Write Read/Write Read/Write [3:0] [7:0] [7:0] [7:0] [7] ****0000 00000000 4 32 1******* [6] *1****** VSYNC Output Polarity Rev. 0 | Page 14 of 44 AD9398 Hex Address Read/Write or Read Only Bits [5] Default Value **1***** Register Name DE Output Polarity Description Output DE polarity. 0 = active low out. 1 = active high out. Output field polarity. 0 = active low out. 1 = active high out. 0 = don’t invert clock out. 1 = invert clock out. Select which clock to use on output pin. 1× CLK is divided down from TMDS clock input when pixel repetition is in use. 00 = ½× CLK. 01 = 1× CLK. 10 = 2× CLK. 11 = 90° phase 1× CLK. Set the drive strength of the outputs. 00 = lowest, 11 = highest. Selects the data output mapping. 00 = 4:4:4 mode (normal). 01 = 4:2:2 + DDR 4:2:2 on blue. 10 = DDR 4:4:4 + DDR 4:2:2 on blue. 11 = 12-bit 4:2:2 (HDMI option only) Enables primary output. Enables secondary output (DDR 4:2:2 in Output Mode 1 and Mode 2). Three-state the outputs. Three-state the SPDIF output. Three-state the I2S output and the MCLK out. Sets polarity of power-down pin. 0 = active low. 1 = active high. Selects the function of the power-down pin. 00 = power-down. 01 = power-down and three-state SOG. 10 = three-state outputs only. 11 = three-state outputs and SOG. 0 = normal. 1 = power-down. 0 = disable auto low power state. 1 = enable auto low power state. Sets the LSB of the address of the HDCP I2C. Set to 1 only for a second receiver in a dual-link configuration. 0 = use internally generated MCLK. 1 = use external MCLK input. If an external MCLK is used, it must be locked to the video clock according to the CTS and N available in the I2C. Any mismatch between the internal MCLK and the input MCLK results in dropped or repeated audio samples. [4] ***1**** Field Output Polarity [0] 0x25 Read/Write [7:6] *******0 01****** Output CLK Invert Output CLK Select [5:4] [3:2] **11**** ****00** Output Drive Strength Output Mode [1] [0] 0x26 Read/Write [7] [5] [4] [3] ******1* *******0 0******* **0***** ***0**** ****1*** Primary Output Enable Secondary Output Enable Output Three-State SPDIF Three-State I2S Three-State Power-Down Pin Polarity [2:1] *****00* Power-Down Pin Function [0] 0x27 Read/Write [7] *******0 1******* Power-Down Auto Power-Down Enable HDCP A0 [6] *0****** [5] **0***** MCLK External Enable Rev. 0 | Page 15 of 44 AD9398 Hex Address Read/Write or Read Only Bits [4] [3] [2:0] 0x28 Read/Write [7:2] [1:0] [7:0] [3:0] [7:0] [3:0] [7:0] [7] [6:5] Default Value ***0**** ****0*** *****000 011000** ******01 00000100 ****0101 00000000 ****0010 11010000 0******* *00***** Register Name BT656 EN Force DE Generation Interlace Offset VS Delay HS Delay MSB HS Delay Line Width MSB Line Width Screen Height MSB Screen Height Ctrl EN I2S Out Mode Description Enables EAV/SAV codes to be inserted into the video output data. Allows use of the internal DE generator in DVI mode. Sets the difference (in HSYNCs) in field length between Field 0 and Field 1. Sets the delay (in lines) from the VSYNC leading edge to the start of active video. MSB, Register 0x29. Sets the delay (in pixels) from the HSYNC leading edge to the start of active video. MSB, Register 0x2B. Sets the width of the active video line in pixels. MSB, Register 0x2D. Sets the height of the active screen in lines. Allows Ctrl [3:0] to be output on the I2S data pins. 00 = I2S mode. 01 = right-justified. 10 = left-justified. 11 = raw IEC60958 mode. Sets the desired bit width for right-justified mode. Detects a TMDS DE. Detects a TMDS clock. Gives the status of AV mute based on general control packets. Returns 1 when read of EEPROM keys is successful. Returns quality number based on DE edges. This bit is high when HDCP decryption is in use (content is protected). The signal goes low when HDCP is not being used. Use this bit to allow copying of the content. The bit should be sampled at regular intervals because it can change on a frame-by-frame basis. Returns DVI HSYNC polarity. Returns DVI VSYNC polarity. Returns current HDMI pixel repetition amount. 0 = 1×, 1 = 2×, ... The clock and data outputs automatically de-repeat by this value. Sets the maximum pseudo sync pulse width for Macrovision detection. Sets the minimum pseudo sync pulse width for Macrovision detection. Tells the Macrovision detection engine whether oversampling occurs. Tells the Macrovision detection engine to enter PAL mode. Sets the start line for Macrovision detection. 0 = standard definition. 1 = progressive scan mode. 0 = use hard-coded settings for line counts and pulse widths. 1 = use I2C values for these settings. Sets the end line for Macrovision detection. Sets the number of pulses required in the last 3 lines (SD mode only). 0x29 0x2A 0x2B 0x2C 0x2D 0x2E Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 0x2F Read [4:0] [6] [5] [4] [3] [2:0] [6] ***11000 *0****** **0***** ***0**** ****0*** *****000 *0****** I2S Bit Width TMDS Sync Detect TMDS Active AV Mute HDCP Keys Read HDMI Quality HDMI Content Encrypted 0x30 Read [5] [4] [3:0] **0***** ***0**** ****0000 DVI HSYNC Polarity DVI VSYNC Polarity HDMI Pixel Repetition 0x31 Read/Write [7:4] [3:0] 1001**** ****0110 0******* *0****** **001101 1******* *0****** MV Pulse Max MV Pulse Min MV Oversample En MV Pal En MV Line Count Start MV Detect Mode MV Settings Override 0x32 Read/Write [7] [6] [5:0] [7] [6] 0x33 Read/Write 0x34 Read/Write [5:0] [7:6] **010101 10****** MV Line Count End MV Pulse Limit Set Rev. 0 | Page 16 of 44 AD9398 Hex Address Read/Write or Read Only Bits [5] [4] [3] [2] [1] Default Value **0***** ***0**** ****0*** *****0** ******0* Register Name Low Freq Mode Low Freq Override Up Conversion Mode CrCb Filter Enable CSC_Enable Description Sets audio PLL to low frequency mode. Low frequency mode should only be set for pixel clocks